new file: verilog/rtl/alu_xor_4.v
new file: verilog/rtl/macro_10.v
new file: verilog/rtl/macro_15.v
new file: verilog/rtl/macro_7.v
new file: verilog/rtl/macro_decap_12.v
new file: verilog/rtl/macro_decap_3.v
new file: verilog/rtl/macro_golden.v
new file: verilog/rtl/macro_nodecap.v
new file: verilog/rtl/macro_nofill.v
def/macro_10.def
def/macro_15.def
def/macro_7.def
def/macro_decap_12.def
def/macro_decap_3.def
def/macro_golden.def
def/macro_nodecap.def
def/macro_nofill.def
gds/
lef/macro_10.lef
lef/macro_15.lef
lef/macro_7.lef
lef/macro_decap_12.lef
lef/macro_decap_3.lef
lef/macro_golden.lef
lef/macro_nodecap.lef
lef/macro_nofill.lef
lib/
mag/macro_10.mag
mag/macro_15.mag
mag/macro_7.mag
mag/macro_decap_12.mag
mag/macro_decap_3.mag
mag/macro_golden.mag
mag/macro_nodecap.mag
mag/macro_nofill.mag
maglef/macro_10.mag
maglef/macro_15.mag
maglef/macro_7.mag
maglef/macro_decap_12.mag
maglef/macro_decap_3.mag
maglef/macro_golden.mag
maglef/macro_nodecap.mag
maglef/macro_nofill.mag
openlane/user_proj_example/config_15.json
openlane/user_proj_example/config_7.json
openlane/user_proj_example/config_decap_12.json
openlane/user_proj_example/config_decap_3
openlane/user_proj_example/config_golden.json
openlane/user_proj_example/config_nodecap.json
openlane/user_proj_example/config_nofill.json
openlane/user_project_wrapper/macro_1.cfg
sdc/
sdf/
signoff/user_proj_example/metrics.csv
signoff/user_project_wrapper/metrics.csv
spef/
spi/lvs/macro_10.spice
spi/lvs/macro_15.spice
spi/lvs/macro_7.spice
spi/lvs/macro_decap_12.spice
spi/lvs/macro_decap_3.spice
spi/lvs/macro_golden.spice
spi/lvs/macro_nodecap.spice
spi/lvs/macro_nofill.spice
verilog/dv/macro_10/
verilog/dv/macro_15/
verilog/dv/macro_7/
verilog/dv/macro_decap12/
verilog/dv/macro_decap3/
verilog/dv/macro_golden/
verilog/dv/macro_no_decap/
verilog/dv/macro_no_fill/
verilog/gl/macro_10.nl.v
verilog/gl/macro_10.v
verilog/gl/macro_15.nl.v
verilog/gl/macro_15.v
verilog/gl/macro_7.nl.v
verilog/gl/macro_7.v
verilog/gl/macro_decap_12.nl.v
verilog/gl/macro_decap_12.v
verilog/gl/macro_decap_3.nl.v
verilog/gl/macro_decap_3.v
verilog/gl/macro_golden.nl.v
verilog/gl/macro_golden.v
verilog/gl/macro_nodecap.nl.v
verilog/gl/macro_nodecap.v
verilog/gl/macro_nofill.nl.v
verilog/gl/macro_nofill.v
verilog/gl/user_project_wrapper.nl.v
diff --git a/verilog/rtl/1 b/verilog/rtl/1
new file mode 100644
index 0000000..13ceea9
--- /dev/null
+++ b/verilog/rtl/1
@@ -0,0 +1,128 @@
+`default_nettype none
+
+`ifdef FORMAL
+ `define MPRJ_IO_PADS 38
+`endif
+
+`define USE_LA 1
+`define USE_IO 1
+
+module macro_10 (
+ `ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+ `endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // // Logic Analyzer Signals
+ `ifdef USE_LA
+ input wire [127:0] la_data_in,
+ output wire [127:0] la_data_out,
+ input wire [127:0] la_oenb,
+ `endif
+ // // IOs
+ `ifdef USE_IO
+ input wire [`MPRJ_IO_PADS-1:0] io_in,
+ output wire [`MPRJ_IO_PADS-1:0] io_out,
+ output wire [`MPRJ_IO_PADS-1:0] io_oeb,
+ `endif
+ // // Analog (direct connection to GPIO pad---use with
+ // caution)
+ // // Note that analog I/O is not available on the
+ // 7 lowest-numbered
+ // // GPIO pads, and so the analog_io indexing is offset from
+ // the
+ // // GPIO indexing by 7 (also upper 2 GPIOs do not have
+ // analog_io).
+// inout [`MPRJ_IO_PADS-10:0] analog_io,
+
+ // // Independent clock (on independent integer divider)
+// input wire user_clock2,
+
+// // // User maskable interrupt signals
+// output wire [2:0] user_irq,
+
+ input wire io_active
+ );
+ //
+ // /*--------------------------------------*/
+ // /* User project is instantiated here */
+ // /*--------------------------------------*/
+ //
+ reg [3:0] A0, B0, A1, B1; //Inputs
+ reg [1:0] ALU_Sel1, ALU_Sel2; //Select Signals
+ wire [3:0] ALU_Out1,ALU_Out2; // ALU 4-bit Output
+ wire CarryOut1,CarryOut2; // Carry Out Flag
+ wire [3:0] x; //Compares ALU outputs
+ wire y; //Compares Carry Outputs
+ wire clk;
+ wire [31:0] la1_data_out;
+ assign la1_data_out = la_data_out[63:32];
+ wire [31:0] buf_la1_data_out; //Tri-stated
+ wire [`MPRJ_IO_PADS-1:0] buf_io_out; //Tri-stated
+ wire [`MPRJ_IO_PADS-1:0] buf_io_oeb; //Tri-stated
+
+ `ifdef FORMAL
+ `ifdef USE_LA
+ assign la1_data_out = io_active ? buf_la1_data_out : 32'b0; // formal verification
+ `endif
+ `ifdef USE_IO
+ assign io_oeb = io_active ? buf_io_oeb : {`MPRJ_IO_PADS{1'b0}}; //If active, the outputs are enabled at io_oeb
+ assign io_out = io_active ? buf_io_out : {`MPRJ_IO_PADS{1'b0}}; //If active, the outputs are passed to io_out
+ `endif
+ `include "properties.v" //Checks for the tri-state buffer
+
+ `else
+ `ifdef USE_LA
+ assign la1_data_out = io_active ? buf_la1_data_out : 32'bz;
+ `endif
+ `ifdef USE_IO
+ assign io_oeb = io_active ? buf_io_oeb : {`MPRJ_IO_PADS{1'b0}};
+ assign io_out = io_active ? buf_io_out : {`MPRJ_IO_PADS{1'b0}};
+ `endif
+ //$display("outputs and active is",io_out,active);
+ `endif
+
+ assign buf_io_oeb = {`MPRJ_IO_PADS{1'b0}}; //enabled
+
+ //ALU_XOR instantiated
+
+ alu_xor_4 u_alu_xor_4(
+`ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+`endif
+ .clk(wb_clk_i),
+ .A0(io_in[21:18]),
+ .B0(io_in[25:22]),
+ .A1(io_in[29:26]),
+ .B1(io_in[33:30]),
+ .ALU_Sel1(io_in[35:34]),
+ .ALU_Sel2(io_in[37:36]),
+ .ALU_Out1(buf_io_out[17:14]),
+ .ALU_Out2(buf_io_out[13:10]),
+ .CarryOut1(buf_io_out[5]),
+ .CarryOut2(buf_io_out[4]),
+ .x(buf_io_out[9:6]),
+ .y(buf_io_out[0])
+);
+ endmodule // user_project_wrapper
+
+ `default_nettype wire
diff --git a/verilog/rtl/alu_xor_4.v b/verilog/rtl/alu_xor_4.v
new file mode 100644
index 0000000..aacb883
--- /dev/null
+++ b/verilog/rtl/alu_xor_4.v
@@ -0,0 +1,94 @@
+// Code your design here
+module alu_xor_4(
+`ifdef USE_POWER_PINS
+ inout vccd1, // User area 1 1.8V supply
+ inout vssd1, // User area 1 digital ground
+`endif
+input clk,
+ input [3:0] A0,B0,A1,B1, // ALU 8-bit Inputs
+input [1:0] ALU_Sel1,ALU_Sel2,// ALU Selection
+ output [3:0] ALU_Out1,ALU_Out2, // ALU 8-bit Output
+output CarryOut1,CarryOut2, // Carry Out Flag
+ output [3:0] x,
+output y,
+input [1:0] active
+);
+
+alu_4 alu_4_1(
+.A (A0),
+.B (B0),
+.ALU_Sel (ALU_Sel1),
+.ALU_Out (ALU_Out1),
+.CarryOut (CarryOut1)
+);
+
+alu_4 alu_4_2(
+.A (A1),
+.B (B1),
+.ALU_Sel (ALU_Sel2),
+.ALU_Out (ALU_Out2),
+.CarryOut (CarryOut2)
+);
+
+
+ assign x[3:0] = ALU_Out1[3:0] ^ ALU_Out2[3:0];
+assign y = CarryOut1 ^ CarryOut2;
+ always @(*)
+begin
+
+ $display("A0", A0[3:0]);
+ $display("B0", B0[3:0]);
+ $display("A1", A1[3:0]);
+ $display("B1", B1[3:0]);
+ $display("ALU_Sel1", ALU_Sel1[1:0]);
+ $display("ALU_Sel2", ALU_Sel2[1:0]);
+ #1000;
+ $display("ALU_Out1", ALU_Out1[3:0]);
+ $display("ALU_Out2", ALU_Out2[3:0]);
+ $display("CarryOut1", CarryOut1);
+ $display("CarryOut2", CarryOut2);
+ $display("x", x[3:0]);
+ $display("y", y);
+
+#1000;
+if (x!=0)
+$display ("Faulty ALU");
+else
+$display ("ALU is right");
+if (y!=0)
+$display ("Faulty Carry");
+else
+$display ("Carry is right");
+end
+
+
+endmodule
+
+module alu_4(
+ input [3:0] A,B, // ALU 8-bit Inputs
+input [1:0] ALU_Sel,// ALU Selection
+ output [3:0] ALU_Out, // ALU 8-bit Output
+output CarryOut // Carry Out Flag
+);
+ reg [4:0] ALU_Result;
+
+ assign ALU_Out = ALU_Result[3:0]; // ALU out
+ assign CarryOut = ALU_Result[4];
+
+always @(*)
+begin
+case(ALU_Sel)
+2'b00: // Addition
+ALU_Result = A + B ;
+2'b01: // Subtraction
+ALU_Result = A - B ;
+2'b10: // and
+ALU_Result = A & B;
+2'b11: // or
+ALU_Result = A | B;
+
+default: ALU_Result = A + B ;
+endcase
+end
+
+endmodule
diff --git a/verilog/rtl/macro_10.v b/verilog/rtl/macro_10.v
new file mode 100644
index 0000000..13ceea9
--- /dev/null
+++ b/verilog/rtl/macro_10.v
@@ -0,0 +1,128 @@
+`default_nettype none
+
+`ifdef FORMAL
+ `define MPRJ_IO_PADS 38
+`endif
+
+`define USE_LA 1
+`define USE_IO 1
+
+module macro_10 (
+ `ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+ `endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // // Logic Analyzer Signals
+ `ifdef USE_LA
+ input wire [127:0] la_data_in,
+ output wire [127:0] la_data_out,
+ input wire [127:0] la_oenb,
+ `endif
+ // // IOs
+ `ifdef USE_IO
+ input wire [`MPRJ_IO_PADS-1:0] io_in,
+ output wire [`MPRJ_IO_PADS-1:0] io_out,
+ output wire [`MPRJ_IO_PADS-1:0] io_oeb,
+ `endif
+ // // Analog (direct connection to GPIO pad---use with
+ // caution)
+ // // Note that analog I/O is not available on the
+ // 7 lowest-numbered
+ // // GPIO pads, and so the analog_io indexing is offset from
+ // the
+ // // GPIO indexing by 7 (also upper 2 GPIOs do not have
+ // analog_io).
+// inout [`MPRJ_IO_PADS-10:0] analog_io,
+
+ // // Independent clock (on independent integer divider)
+// input wire user_clock2,
+
+// // // User maskable interrupt signals
+// output wire [2:0] user_irq,
+
+ input wire io_active
+ );
+ //
+ // /*--------------------------------------*/
+ // /* User project is instantiated here */
+ // /*--------------------------------------*/
+ //
+ reg [3:0] A0, B0, A1, B1; //Inputs
+ reg [1:0] ALU_Sel1, ALU_Sel2; //Select Signals
+ wire [3:0] ALU_Out1,ALU_Out2; // ALU 4-bit Output
+ wire CarryOut1,CarryOut2; // Carry Out Flag
+ wire [3:0] x; //Compares ALU outputs
+ wire y; //Compares Carry Outputs
+ wire clk;
+ wire [31:0] la1_data_out;
+ assign la1_data_out = la_data_out[63:32];
+ wire [31:0] buf_la1_data_out; //Tri-stated
+ wire [`MPRJ_IO_PADS-1:0] buf_io_out; //Tri-stated
+ wire [`MPRJ_IO_PADS-1:0] buf_io_oeb; //Tri-stated
+
+ `ifdef FORMAL
+ `ifdef USE_LA
+ assign la1_data_out = io_active ? buf_la1_data_out : 32'b0; // formal verification
+ `endif
+ `ifdef USE_IO
+ assign io_oeb = io_active ? buf_io_oeb : {`MPRJ_IO_PADS{1'b0}}; //If active, the outputs are enabled at io_oeb
+ assign io_out = io_active ? buf_io_out : {`MPRJ_IO_PADS{1'b0}}; //If active, the outputs are passed to io_out
+ `endif
+ `include "properties.v" //Checks for the tri-state buffer
+
+ `else
+ `ifdef USE_LA
+ assign la1_data_out = io_active ? buf_la1_data_out : 32'bz;
+ `endif
+ `ifdef USE_IO
+ assign io_oeb = io_active ? buf_io_oeb : {`MPRJ_IO_PADS{1'b0}};
+ assign io_out = io_active ? buf_io_out : {`MPRJ_IO_PADS{1'b0}};
+ `endif
+ //$display("outputs and active is",io_out,active);
+ `endif
+
+ assign buf_io_oeb = {`MPRJ_IO_PADS{1'b0}}; //enabled
+
+ //ALU_XOR instantiated
+
+ alu_xor_4 u_alu_xor_4(
+`ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+`endif
+ .clk(wb_clk_i),
+ .A0(io_in[21:18]),
+ .B0(io_in[25:22]),
+ .A1(io_in[29:26]),
+ .B1(io_in[33:30]),
+ .ALU_Sel1(io_in[35:34]),
+ .ALU_Sel2(io_in[37:36]),
+ .ALU_Out1(buf_io_out[17:14]),
+ .ALU_Out2(buf_io_out[13:10]),
+ .CarryOut1(buf_io_out[5]),
+ .CarryOut2(buf_io_out[4]),
+ .x(buf_io_out[9:6]),
+ .y(buf_io_out[0])
+);
+ endmodule // user_project_wrapper
+
+ `default_nettype wire
diff --git a/verilog/rtl/macro_15.v b/verilog/rtl/macro_15.v
new file mode 100644
index 0000000..9f1b092
--- /dev/null
+++ b/verilog/rtl/macro_15.v
@@ -0,0 +1,128 @@
+`default_nettype none
+
+`ifdef FORMAL
+ `define MPRJ_IO_PADS 38
+`endif
+
+`define USE_LA 1
+`define USE_IO 1
+
+module macro_15 (
+ `ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+ `endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // // Logic Analyzer Signals
+ `ifdef USE_LA
+ input wire [127:0] la_data_in,
+ output wire [127:0] la_data_out,
+ input wire [127:0] la_oenb,
+ `endif
+ // // IOs
+ `ifdef USE_IO
+ input wire [`MPRJ_IO_PADS-1:0] io_in,
+ output wire [`MPRJ_IO_PADS-1:0] io_out,
+ output wire [`MPRJ_IO_PADS-1:0] io_oeb,
+ `endif
+ // // Analog (direct connection to GPIO pad---use with
+ // caution)
+ // // Note that analog I/O is not available on the
+ // 7 lowest-numbered
+ // // GPIO pads, and so the analog_io indexing is offset from
+ // the
+ // // GPIO indexing by 7 (also upper 2 GPIOs do not have
+ // analog_io).
+// inout [`MPRJ_IO_PADS-10:0] analog_io,
+
+ // // Independent clock (on independent integer divider)
+// input wire user_clock2,
+
+// // // User maskable interrupt signals
+// output wire [2:0] user_irq,
+
+ input wire io_active
+ );
+ //
+ // /*--------------------------------------*/
+ // /* User project is instantiated here */
+ // /*--------------------------------------*/
+ //
+ reg [3:0] A0, B0, A1, B1; //Inputs
+ reg [1:0] ALU_Sel1, ALU_Sel2; //Select Signals
+ wire [3:0] ALU_Out1,ALU_Out2; // ALU 4-bit Output
+ wire CarryOut1,CarryOut2; // Carry Out Flag
+ wire [3:0] x; //Compares ALU outputs
+ wire y; //Compares Carry Outputs
+ wire clk;
+ wire [31:0] la1_data_out;
+ assign la1_data_out = la_data_out[63:32];
+ wire [31:0] buf_la1_data_out; //Tri-stated
+ wire [`MPRJ_IO_PADS-1:0] buf_io_out; //Tri-stated
+ wire [`MPRJ_IO_PADS-1:0] buf_io_oeb; //Tri-stated
+
+ `ifdef FORMAL
+ `ifdef USE_LA
+ assign la1_data_out = io_active ? buf_la1_data_out : 32'b0; // formal verification
+ `endif
+ `ifdef USE_IO
+ assign io_oeb = io_active ? buf_io_oeb : {`MPRJ_IO_PADS{1'b0}}; //If active, the outputs are enabled at io_oeb
+ assign io_out = io_active ? buf_io_out : {`MPRJ_IO_PADS{1'b0}}; //If active, the outputs are passed to io_out
+ `endif
+ `include "properties.v" //Checks for the tri-state buffer
+
+ `else
+ `ifdef USE_LA
+ assign la1_data_out = io_active ? buf_la1_data_out : 32'bz;
+ `endif
+ `ifdef USE_IO
+ assign io_oeb = io_active ? buf_io_oeb : {`MPRJ_IO_PADS{1'b0}};
+ assign io_out = io_active ? buf_io_out : {`MPRJ_IO_PADS{1'b0}};
+ `endif
+ //$display("outputs and active is",io_out,active);
+ `endif
+
+ assign buf_io_oeb = {`MPRJ_IO_PADS{1'b0}}; //enabled
+
+ //ALU_XOR instantiated
+
+ alu_xor_4 u_alu_xor_4(
+`ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+`endif
+ .clk(wb_clk_i),
+ .A0(io_in[21:18]),
+ .B0(io_in[25:22]),
+ .A1(io_in[29:26]),
+ .B1(io_in[33:30]),
+ .ALU_Sel1(io_in[35:34]),
+ .ALU_Sel2(io_in[37:36]),
+ .ALU_Out1(buf_io_out[17:14]),
+ .ALU_Out2(buf_io_out[13:10]),
+ .CarryOut1(buf_io_out[5]),
+ .CarryOut2(buf_io_out[4]),
+ .x(buf_io_out[9:6]),
+ .y(buf_io_out[0])
+);
+ endmodule // user_project_wrapper
+
+ `default_nettype wire
diff --git a/verilog/rtl/macro_7.v b/verilog/rtl/macro_7.v
new file mode 100644
index 0000000..5a82508
--- /dev/null
+++ b/verilog/rtl/macro_7.v
@@ -0,0 +1,128 @@
+`default_nettype none
+
+`ifdef FORMAL
+ `define MPRJ_IO_PADS 38
+`endif
+
+`define USE_LA 1
+`define USE_IO 1
+
+module macro_7 (
+ `ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+ `endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // // Logic Analyzer Signals
+ `ifdef USE_LA
+ input wire [127:0] la_data_in,
+ output wire [127:0] la_data_out,
+ input wire [127:0] la_oenb,
+ `endif
+ // // IOs
+ `ifdef USE_IO
+ input wire [`MPRJ_IO_PADS-1:0] io_in,
+ output wire [`MPRJ_IO_PADS-1:0] io_out,
+ output wire [`MPRJ_IO_PADS-1:0] io_oeb,
+ `endif
+ // // Analog (direct connection to GPIO pad---use with
+ // caution)
+ // // Note that analog I/O is not available on the
+ // 7 lowest-numbered
+ // // GPIO pads, and so the analog_io indexing is offset from
+ // the
+ // // GPIO indexing by 7 (also upper 2 GPIOs do not have
+ // analog_io).
+// inout [`MPRJ_IO_PADS-10:0] analog_io,
+
+ // // Independent clock (on independent integer divider)
+// input wire user_clock2,
+
+// // // User maskable interrupt signals
+// output wire [2:0] user_irq,
+
+ input wire io_active
+ );
+ //
+ // /*--------------------------------------*/
+ // /* User project is instantiated here */
+ // /*--------------------------------------*/
+ //
+ reg [3:0] A0, B0, A1, B1; //Inputs
+ reg [1:0] ALU_Sel1, ALU_Sel2; //Select Signals
+ wire [3:0] ALU_Out1,ALU_Out2; // ALU 4-bit Output
+ wire CarryOut1,CarryOut2; // Carry Out Flag
+ wire [3:0] x; //Compares ALU outputs
+ wire y; //Compares Carry Outputs
+ wire clk;
+ wire [31:0] la1_data_out;
+ assign la1_data_out = la_data_out[63:32];
+ wire [31:0] buf_la1_data_out; //Tri-stated
+ wire [`MPRJ_IO_PADS-1:0] buf_io_out; //Tri-stated
+ wire [`MPRJ_IO_PADS-1:0] buf_io_oeb; //Tri-stated
+
+ `ifdef FORMAL
+ `ifdef USE_LA
+ assign la1_data_out = io_active ? buf_la1_data_out : 32'b0; // formal verification
+ `endif
+ `ifdef USE_IO
+ assign io_oeb = io_active ? buf_io_oeb : {`MPRJ_IO_PADS{1'b0}}; //If active, the outputs are enabled at io_oeb
+ assign io_out = io_active ? buf_io_out : {`MPRJ_IO_PADS{1'b0}}; //If active, the outputs are passed to io_out
+ `endif
+ `include "properties.v" //Checks for the tri-state buffer
+
+ `else
+ `ifdef USE_LA
+ assign la1_data_out = io_active ? buf_la1_data_out : 32'bz;
+ `endif
+ `ifdef USE_IO
+ assign io_oeb = io_active ? buf_io_oeb : {`MPRJ_IO_PADS{1'b0}};
+ assign io_out = io_active ? buf_io_out : {`MPRJ_IO_PADS{1'b0}};
+ `endif
+ //$display("outputs and active is",io_out,active);
+ `endif
+
+ assign buf_io_oeb = {`MPRJ_IO_PADS{1'b0}}; //enabled
+
+ //ALU_XOR instantiated
+
+ alu_xor_4 u_alu_xor_4(
+`ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+`endif
+ .clk(wb_clk_i),
+ .A0(io_in[21:18]),
+ .B0(io_in[25:22]),
+ .A1(io_in[29:26]),
+ .B1(io_in[33:30]),
+ .ALU_Sel1(io_in[35:34]),
+ .ALU_Sel2(io_in[37:36]),
+ .ALU_Out1(buf_io_out[17:14]),
+ .ALU_Out2(buf_io_out[13:10]),
+ .CarryOut1(buf_io_out[5]),
+ .CarryOut2(buf_io_out[4]),
+ .x(buf_io_out[9:6]),
+ .y(buf_io_out[0])
+);
+ endmodule // user_project_wrapper
+
+ `default_nettype wire
diff --git a/verilog/rtl/macro_decap_12.v b/verilog/rtl/macro_decap_12.v
new file mode 100644
index 0000000..2d53bef
--- /dev/null
+++ b/verilog/rtl/macro_decap_12.v
@@ -0,0 +1,128 @@
+`default_nettype none
+
+`ifdef FORMAL
+ `define MPRJ_IO_PADS 38
+`endif
+
+`define USE_LA 1
+`define USE_IO 1
+
+module macro_decap_12 (
+ `ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+ `endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // // Logic Analyzer Signals
+ `ifdef USE_LA
+ input wire [127:0] la_data_in,
+ output wire [127:0] la_data_out,
+ input wire [127:0] la_oenb,
+ `endif
+ // // IOs
+ `ifdef USE_IO
+ input wire [`MPRJ_IO_PADS-1:0] io_in,
+ output wire [`MPRJ_IO_PADS-1:0] io_out,
+ output wire [`MPRJ_IO_PADS-1:0] io_oeb,
+ `endif
+ // // Analog (direct connection to GPIO pad---use with
+ // caution)
+ // // Note that analog I/O is not available on the
+ // 7 lowest-numbered
+ // // GPIO pads, and so the analog_io indexing is offset from
+ // the
+ // // GPIO indexing by 7 (also upper 2 GPIOs do not have
+ // analog_io).
+// inout [`MPRJ_IO_PADS-10:0] analog_io,
+
+ // // Independent clock (on independent integer divider)
+// input wire user_clock2,
+
+// // // User maskable interrupt signals
+// output wire [2:0] user_irq,
+
+ input wire io_active
+ );
+ //
+ // /*--------------------------------------*/
+ // /* User project is instantiated here */
+ // /*--------------------------------------*/
+ //
+ reg [3:0] A0, B0, A1, B1; //Inputs
+ reg [1:0] ALU_Sel1, ALU_Sel2; //Select Signals
+ wire [3:0] ALU_Out1,ALU_Out2; // ALU 4-bit Output
+ wire CarryOut1,CarryOut2; // Carry Out Flag
+ wire [3:0] x; //Compares ALU outputs
+ wire y; //Compares Carry Outputs
+ wire clk;
+ wire [31:0] la1_data_out;
+ assign la1_data_out = la_data_out[63:32];
+ wire [31:0] buf_la1_data_out; //Tri-stated
+ wire [`MPRJ_IO_PADS-1:0] buf_io_out; //Tri-stated
+ wire [`MPRJ_IO_PADS-1:0] buf_io_oeb; //Tri-stated
+
+ `ifdef FORMAL
+ `ifdef USE_LA
+ assign la1_data_out = io_active ? buf_la1_data_out : 32'b0; // formal verification
+ `endif
+ `ifdef USE_IO
+ assign io_oeb = io_active ? buf_io_oeb : {`MPRJ_IO_PADS{1'b0}}; //If active, the outputs are enabled at io_oeb
+ assign io_out = io_active ? buf_io_out : {`MPRJ_IO_PADS{1'b0}}; //If active, the outputs are passed to io_out
+ `endif
+ `include "properties.v" //Checks for the tri-state buffer
+
+ `else
+ `ifdef USE_LA
+ assign la1_data_out = io_active ? buf_la1_data_out : 32'bz;
+ `endif
+ `ifdef USE_IO
+ assign io_oeb = io_active ? buf_io_oeb : {`MPRJ_IO_PADS{1'b0}};
+ assign io_out = io_active ? buf_io_out : {`MPRJ_IO_PADS{1'b0}};
+ `endif
+ //$display("outputs and active is",io_out,active);
+ `endif
+
+ assign buf_io_oeb = {`MPRJ_IO_PADS{1'b0}}; //enabled
+
+ //ALU_XOR instantiated
+
+ alu_xor_4 u_alu_xor_4(
+`ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+`endif
+ .clk(wb_clk_i),
+ .A0(io_in[21:18]),
+ .B0(io_in[25:22]),
+ .A1(io_in[29:26]),
+ .B1(io_in[33:30]),
+ .ALU_Sel1(io_in[35:34]),
+ .ALU_Sel2(io_in[37:36]),
+ .ALU_Out1(buf_io_out[17:14]),
+ .ALU_Out2(buf_io_out[13:10]),
+ .CarryOut1(buf_io_out[5]),
+ .CarryOut2(buf_io_out[4]),
+ .x(buf_io_out[9:6]),
+ .y(buf_io_out[0])
+);
+ endmodule // user_project_wrapper
+
+ `default_nettype wire
diff --git a/verilog/rtl/macro_decap_3.v b/verilog/rtl/macro_decap_3.v
new file mode 100644
index 0000000..3545c4e
--- /dev/null
+++ b/verilog/rtl/macro_decap_3.v
@@ -0,0 +1,128 @@
+`default_nettype none
+
+`ifdef FORMAL
+ `define MPRJ_IO_PADS 38
+`endif
+
+`define USE_LA 1
+`define USE_IO 1
+
+module macro_decap_3 (
+ `ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+ `endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // // Logic Analyzer Signals
+ `ifdef USE_LA
+ input wire [127:0] la_data_in,
+ output wire [127:0] la_data_out,
+ input wire [127:0] la_oenb,
+ `endif
+ // // IOs
+ `ifdef USE_IO
+ input wire [`MPRJ_IO_PADS-1:0] io_in,
+ output wire [`MPRJ_IO_PADS-1:0] io_out,
+ output wire [`MPRJ_IO_PADS-1:0] io_oeb,
+ `endif
+ // // Analog (direct connection to GPIO pad---use with
+ // caution)
+ // // Note that analog I/O is not available on the
+ // 7 lowest-numbered
+ // // GPIO pads, and so the analog_io indexing is offset from
+ // the
+ // // GPIO indexing by 7 (also upper 2 GPIOs do not have
+ // analog_io).
+// inout [`MPRJ_IO_PADS-10:0] analog_io,
+
+ // // Independent clock (on independent integer divider)
+// input wire user_clock2,
+
+// // // User maskable interrupt signals
+// output wire [2:0] user_irq,
+
+ input wire io_active
+ );
+ //
+ // /*--------------------------------------*/
+ // /* User project is instantiated here */
+ // /*--------------------------------------*/
+ //
+ reg [3:0] A0, B0, A1, B1; //Inputs
+ reg [1:0] ALU_Sel1, ALU_Sel2; //Select Signals
+ wire [3:0] ALU_Out1,ALU_Out2; // ALU 4-bit Output
+ wire CarryOut1,CarryOut2; // Carry Out Flag
+ wire [3:0] x; //Compares ALU outputs
+ wire y; //Compares Carry Outputs
+ wire clk;
+ wire [31:0] la1_data_out;
+ assign la1_data_out = la_data_out[63:32];
+ wire [31:0] buf_la1_data_out; //Tri-stated
+ wire [`MPRJ_IO_PADS-1:0] buf_io_out; //Tri-stated
+ wire [`MPRJ_IO_PADS-1:0] buf_io_oeb; //Tri-stated
+
+ `ifdef FORMAL
+ `ifdef USE_LA
+ assign la1_data_out = io_active ? buf_la1_data_out : 32'b0; // formal verification
+ `endif
+ `ifdef USE_IO
+ assign io_oeb = io_active ? buf_io_oeb : {`MPRJ_IO_PADS{1'b0}}; //If active, the outputs are enabled at io_oeb
+ assign io_out = io_active ? buf_io_out : {`MPRJ_IO_PADS{1'b0}}; //If active, the outputs are passed to io_out
+ `endif
+ `include "properties.v" //Checks for the tri-state buffer
+
+ `else
+ `ifdef USE_LA
+ assign la1_data_out = io_active ? buf_la1_data_out : 32'bz;
+ `endif
+ `ifdef USE_IO
+ assign io_oeb = io_active ? buf_io_oeb : {`MPRJ_IO_PADS{1'b0}};
+ assign io_out = io_active ? buf_io_out : {`MPRJ_IO_PADS{1'b0}};
+ `endif
+ //$display("outputs and active is",io_out,active);
+ `endif
+
+ assign buf_io_oeb = {`MPRJ_IO_PADS{1'b0}}; //enabled
+
+ //ALU_XOR instantiated
+
+ alu_xor_4 u_alu_xor_4(
+`ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+`endif
+ .clk(wb_clk_i),
+ .A0(io_in[21:18]),
+ .B0(io_in[25:22]),
+ .A1(io_in[29:26]),
+ .B1(io_in[33:30]),
+ .ALU_Sel1(io_in[35:34]),
+ .ALU_Sel2(io_in[37:36]),
+ .ALU_Out1(buf_io_out[17:14]),
+ .ALU_Out2(buf_io_out[13:10]),
+ .CarryOut1(buf_io_out[5]),
+ .CarryOut2(buf_io_out[4]),
+ .x(buf_io_out[9:6]),
+ .y(buf_io_out[0])
+);
+ endmodule // user_project_wrapper
+
+ `default_nettype wire
diff --git a/verilog/rtl/macro_golden.v b/verilog/rtl/macro_golden.v
new file mode 100644
index 0000000..1f39689
--- /dev/null
+++ b/verilog/rtl/macro_golden.v
@@ -0,0 +1,128 @@
+`default_nettype none
+
+`ifdef FORMAL
+ `define MPRJ_IO_PADS 38
+`endif
+
+`define USE_LA 1
+`define USE_IO 1
+
+module macro_golden (
+ `ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+ `endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // // Logic Analyzer Signals
+ `ifdef USE_LA
+ input wire [127:0] la_data_in,
+ output wire [127:0] la_data_out,
+ input wire [127:0] la_oenb,
+ `endif
+ // // IOs
+ `ifdef USE_IO
+ input wire [`MPRJ_IO_PADS-1:0] io_in,
+ output wire [`MPRJ_IO_PADS-1:0] io_out,
+ output wire [`MPRJ_IO_PADS-1:0] io_oeb,
+ `endif
+ // // Analog (direct connection to GPIO pad---use with
+ // caution)
+ // // Note that analog I/O is not available on the
+ // 7 lowest-numbered
+ // // GPIO pads, and so the analog_io indexing is offset from
+ // the
+ // // GPIO indexing by 7 (also upper 2 GPIOs do not have
+ // analog_io).
+// inout [`MPRJ_IO_PADS-10:0] analog_io,
+
+ // // Independent clock (on independent integer divider)
+// input wire user_clock2,
+
+// // // User maskable interrupt signals
+// output wire [2:0] user_irq,
+
+ input wire io_active
+ );
+ //
+ // /*--------------------------------------*/
+ // /* User project is instantiated here */
+ // /*--------------------------------------*/
+ //
+ reg [3:0] A0, B0, A1, B1; //Inputs
+ reg [1:0] ALU_Sel1, ALU_Sel2; //Select Signals
+ wire [3:0] ALU_Out1,ALU_Out2; // ALU 4-bit Output
+ wire CarryOut1,CarryOut2; // Carry Out Flag
+ wire [3:0] x; //Compares ALU outputs
+ wire y; //Compares Carry Outputs
+ wire clk;
+ wire [31:0] la1_data_out;
+ assign la1_data_out = la_data_out[63:32];
+ wire [31:0] buf_la1_data_out; //Tri-stated
+ wire [`MPRJ_IO_PADS-1:0] buf_io_out; //Tri-stated
+ wire [`MPRJ_IO_PADS-1:0] buf_io_oeb; //Tri-stated
+
+ `ifdef FORMAL
+ `ifdef USE_LA
+ assign la1_data_out = io_active ? buf_la1_data_out : 32'b0; // formal verification
+ `endif
+ `ifdef USE_IO
+ assign io_oeb = io_active ? buf_io_oeb : {`MPRJ_IO_PADS{1'b0}}; //If active, the outputs are enabled at io_oeb
+ assign io_out = io_active ? buf_io_out : {`MPRJ_IO_PADS{1'b0}}; //If active, the outputs are passed to io_out
+ `endif
+ `include "properties.v" //Checks for the tri-state buffer
+
+ `else
+ `ifdef USE_LA
+ assign la1_data_out = io_active ? buf_la1_data_out : 32'bz;
+ `endif
+ `ifdef USE_IO
+ assign io_oeb = io_active ? buf_io_oeb : {`MPRJ_IO_PADS{1'b0}};
+ assign io_out = io_active ? buf_io_out : {`MPRJ_IO_PADS{1'b0}};
+ `endif
+ //$display("outputs and active is",io_out,active);
+ `endif
+
+ assign buf_io_oeb = {`MPRJ_IO_PADS{1'b0}}; //enabled
+
+ //ALU_XOR instantiated
+
+ alu_xor_4 u_alu_xor_4(
+`ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+`endif
+ .clk(wb_clk_i),
+ .A0(io_in[21:18]),
+ .B0(io_in[25:22]),
+ .A1(io_in[29:26]),
+ .B1(io_in[33:30]),
+ .ALU_Sel1(io_in[35:34]),
+ .ALU_Sel2(io_in[37:36]),
+ .ALU_Out1(buf_io_out[17:14]),
+ .ALU_Out2(buf_io_out[13:10]),
+ .CarryOut1(buf_io_out[5]),
+ .CarryOut2(buf_io_out[4]),
+ .x(buf_io_out[9:6]),
+ .y(buf_io_out[0])
+);
+ endmodule // user_project_wrapper
+
+ `default_nettype wire
diff --git a/verilog/rtl/macro_nodecap.v b/verilog/rtl/macro_nodecap.v
new file mode 100644
index 0000000..08d6559
--- /dev/null
+++ b/verilog/rtl/macro_nodecap.v
@@ -0,0 +1,128 @@
+`default_nettype none
+
+`ifdef FORMAL
+ `define MPRJ_IO_PADS 38
+`endif
+
+`define USE_LA 1
+`define USE_IO 1
+
+module macro_nodecap (
+ `ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+ `endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // // Logic Analyzer Signals
+ `ifdef USE_LA
+ input wire [127:0] la_data_in,
+ output wire [127:0] la_data_out,
+ input wire [127:0] la_oenb,
+ `endif
+ // // IOs
+ `ifdef USE_IO
+ input wire [`MPRJ_IO_PADS-1:0] io_in,
+ output wire [`MPRJ_IO_PADS-1:0] io_out,
+ output wire [`MPRJ_IO_PADS-1:0] io_oeb,
+ `endif
+ // // Analog (direct connection to GPIO pad---use with
+ // caution)
+ // // Note that analog I/O is not available on the
+ // 7 lowest-numbered
+ // // GPIO pads, and so the analog_io indexing is offset from
+ // the
+ // // GPIO indexing by 7 (also upper 2 GPIOs do not have
+ // analog_io).
+// inout [`MPRJ_IO_PADS-10:0] analog_io,
+
+ // // Independent clock (on independent integer divider)
+// input wire user_clock2,
+
+// // // User maskable interrupt signals
+// output wire [2:0] user_irq,
+
+ input wire io_active
+ );
+ //
+ // /*--------------------------------------*/
+ // /* User project is instantiated here */
+ // /*--------------------------------------*/
+ //
+ reg [3:0] A0, B0, A1, B1; //Inputs
+ reg [1:0] ALU_Sel1, ALU_Sel2; //Select Signals
+ wire [3:0] ALU_Out1,ALU_Out2; // ALU 4-bit Output
+ wire CarryOut1,CarryOut2; // Carry Out Flag
+ wire [3:0] x; //Compares ALU outputs
+ wire y; //Compares Carry Outputs
+ wire clk;
+ wire [31:0] la1_data_out;
+ assign la1_data_out = la_data_out[63:32];
+ wire [31:0] buf_la1_data_out; //Tri-stated
+ wire [`MPRJ_IO_PADS-1:0] buf_io_out; //Tri-stated
+ wire [`MPRJ_IO_PADS-1:0] buf_io_oeb; //Tri-stated
+
+ `ifdef FORMAL
+ `ifdef USE_LA
+ assign la1_data_out = io_active ? buf_la1_data_out : 32'b0; // formal verification
+ `endif
+ `ifdef USE_IO
+ assign io_oeb = io_active ? buf_io_oeb : {`MPRJ_IO_PADS{1'b0}}; //If active, the outputs are enabled at io_oeb
+ assign io_out = io_active ? buf_io_out : {`MPRJ_IO_PADS{1'b0}}; //If active, the outputs are passed to io_out
+ `endif
+ `include "properties.v" //Checks for the tri-state buffer
+
+ `else
+ `ifdef USE_LA
+ assign la1_data_out = io_active ? buf_la1_data_out : 32'bz;
+ `endif
+ `ifdef USE_IO
+ assign io_oeb = io_active ? buf_io_oeb : {`MPRJ_IO_PADS{1'b0}};
+ assign io_out = io_active ? buf_io_out : {`MPRJ_IO_PADS{1'b0}};
+ `endif
+ //$display("outputs and active is",io_out,active);
+ `endif
+
+ assign buf_io_oeb = {`MPRJ_IO_PADS{1'b0}}; //enabled
+
+ //ALU_XOR instantiated
+
+ alu_xor_4 u_alu_xor_4(
+`ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+`endif
+ .clk(wb_clk_i),
+ .A0(io_in[21:18]),
+ .B0(io_in[25:22]),
+ .A1(io_in[29:26]),
+ .B1(io_in[33:30]),
+ .ALU_Sel1(io_in[35:34]),
+ .ALU_Sel2(io_in[37:36]),
+ .ALU_Out1(buf_io_out[17:14]),
+ .ALU_Out2(buf_io_out[13:10]),
+ .CarryOut1(buf_io_out[5]),
+ .CarryOut2(buf_io_out[4]),
+ .x(buf_io_out[9:6]),
+ .y(buf_io_out[0])
+);
+ endmodule // user_project_wrapper
+
+ `default_nettype wire
diff --git a/verilog/rtl/macro_nofill.v b/verilog/rtl/macro_nofill.v
new file mode 100644
index 0000000..5e994df
--- /dev/null
+++ b/verilog/rtl/macro_nofill.v
@@ -0,0 +1,128 @@
+`default_nettype none
+
+`ifdef FORMAL
+ `define MPRJ_IO_PADS 38
+`endif
+
+`define USE_LA 1
+`define USE_IO 1
+
+module macro_nofill (
+ `ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+ `endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // // Logic Analyzer Signals
+ `ifdef USE_LA
+ input wire [127:0] la_data_in,
+ output wire [127:0] la_data_out,
+ input wire [127:0] la_oenb,
+ `endif
+ // // IOs
+ `ifdef USE_IO
+ input wire [`MPRJ_IO_PADS-1:0] io_in,
+ output wire [`MPRJ_IO_PADS-1:0] io_out,
+ output wire [`MPRJ_IO_PADS-1:0] io_oeb,
+ `endif
+ // // Analog (direct connection to GPIO pad---use with
+ // caution)
+ // // Note that analog I/O is not available on the
+ // 7 lowest-numbered
+ // // GPIO pads, and so the analog_io indexing is offset from
+ // the
+ // // GPIO indexing by 7 (also upper 2 GPIOs do not have
+ // analog_io).
+// inout [`MPRJ_IO_PADS-10:0] analog_io,
+
+ // // Independent clock (on independent integer divider)
+// input wire user_clock2,
+
+// // // User maskable interrupt signals
+// output wire [2:0] user_irq,
+
+ input wire io_active
+ );
+ //
+ // /*--------------------------------------*/
+ // /* User project is instantiated here */
+ // /*--------------------------------------*/
+ //
+ reg [3:0] A0, B0, A1, B1; //Inputs
+ reg [1:0] ALU_Sel1, ALU_Sel2; //Select Signals
+ wire [3:0] ALU_Out1,ALU_Out2; // ALU 4-bit Output
+ wire CarryOut1,CarryOut2; // Carry Out Flag
+ wire [3:0] x; //Compares ALU outputs
+ wire y; //Compares Carry Outputs
+ wire clk;
+ wire [31:0] la1_data_out;
+ assign la1_data_out = la_data_out[63:32];
+ wire [31:0] buf_la1_data_out; //Tri-stated
+ wire [`MPRJ_IO_PADS-1:0] buf_io_out; //Tri-stated
+ wire [`MPRJ_IO_PADS-1:0] buf_io_oeb; //Tri-stated
+
+ `ifdef FORMAL
+ `ifdef USE_LA
+ assign la1_data_out = io_active ? buf_la1_data_out : 32'b0; // formal verification
+ `endif
+ `ifdef USE_IO
+ assign io_oeb = io_active ? buf_io_oeb : {`MPRJ_IO_PADS{1'b0}}; //If active, the outputs are enabled at io_oeb
+ assign io_out = io_active ? buf_io_out : {`MPRJ_IO_PADS{1'b0}}; //If active, the outputs are passed to io_out
+ `endif
+ `include "properties.v" //Checks for the tri-state buffer
+
+ `else
+ `ifdef USE_LA
+ assign la1_data_out = io_active ? buf_la1_data_out : 32'bz;
+ `endif
+ `ifdef USE_IO
+ assign io_oeb = io_active ? buf_io_oeb : {`MPRJ_IO_PADS{1'b0}};
+ assign io_out = io_active ? buf_io_out : {`MPRJ_IO_PADS{1'b0}};
+ `endif
+ //$display("outputs and active is",io_out,active);
+ `endif
+
+ assign buf_io_oeb = {`MPRJ_IO_PADS{1'b0}}; //enabled
+
+ //ALU_XOR instantiated
+
+ alu_xor_4 u_alu_xor_4(
+`ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+`endif
+ .clk(wb_clk_i),
+ .A0(io_in[21:18]),
+ .B0(io_in[25:22]),
+ .A1(io_in[29:26]),
+ .B1(io_in[33:30]),
+ .ALU_Sel1(io_in[35:34]),
+ .ALU_Sel2(io_in[37:36]),
+ .ALU_Out1(buf_io_out[17:14]),
+ .ALU_Out2(buf_io_out[13:10]),
+ .CarryOut1(buf_io_out[5]),
+ .CarryOut2(buf_io_out[4]),
+ .x(buf_io_out[9:6]),
+ .y(buf_io_out[0])
+);
+ endmodule // user_project_wrapper
+
+ `default_nettype wire
