update config.json

openlane/user_proj_example/config.json

diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json
index 8ace564..3f616d0 100644
--- a/openlane/user_proj_example/config.json
+++ b/openlane/user_proj_example/config.json
@@ -1,17 +1,22 @@
 {
     "DESIGN_NAME": "user_proj_example",
-    "VERILOG_FILES": ["dir::verilog/rtl/defines.v","dir::verilog/rtl/user_proj_example.v"],
+    "DESIGN_IS_CORE": 0,
+    "VERILOG_FILES": "/home/jeffdi/caravel-gf180mcu/verilog/rtl/defines.v /home/jeffdi/caravel_user_project_gf/verilog/rtl/user_proj_example.v",
     "CLOCK_PERIOD": 10,
     "CLOCK_PORT": "wb_clk_i",
     "CLOCK_NET": "counter.clk",
     "FP_SIZING": "absolute",
     "DIE_AREA": "0 0 900 600",
-    "FP_PIN_ORDER_CFG": "pin_order.cfg",
+    "FP_PIN_ORDER_CFG": "/home/jeffdi/caravel_user_project_gf/openlane/user_proj_example/pin_order.cfg",
     "PL_BASIC_PLACEMENT": 0,
     "PL_TARGET_DENSITY": 0.55,
-    "RT_MAX_LAYER": "{met4}",
+    "VDD_NETS": ["vccd1"],
+    "GND_NETS": ["vssd1"],
+    "DIODE_INSERTION_STRATEGY": 4,
+    "RUN_CVC": 1,
     "pdk::sky130*": {
         "FP_CORE_UTIL": 45,
+        "RT_MAX_LAYER": "{met4}",
         "scl::sky130_fd_sc_hd": {
             "CLOCK_PERIOD": 10
         },
@@ -33,6 +38,7 @@
         "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
         "CLOCK_PERIOD": 24.0,
         "FP_CORE_UTIL": 40,
+        "RT_MAX_LAYER": "{Metal4}",
         "SYNTH_MAX_FANOUT": 4,
         "PL_TARGET_DENSITY": 0.45
     }