sdc/mbist_top2.sdc

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# Created by write_sdc
# Wed Dec 14 13:56:02 2022
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current_design mbist_top2
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# Timing Constraints
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create_clock -name wb_clk_i -period 10.0000 [get_ports {wb_clk_i}]
set_clock_transition 0.1500 [get_clocks {wb_clk_i}]
set_clock_uncertainty 0.2500 wb_clk_i
set_propagated_clock [get_clocks {wb_clk_i}]
create_generated_clock -name bist_mem_clk_a -add -source [get_ports {wb_clk_i}] -master_clock [get_clocks {wb_clk_i}] -divide_by 1 -comment {Mem Clock A} [get_ports {mem_clk_a}]
set_propagated_clock [get_clocks {bist_mem_clk_a}]
create_generated_clock -name bist_mem_clk_b -add -source [get_ports {wb_clk_i}] -master_clock [get_clocks {wb_clk_i}] -divide_by 1 -comment {Mem Clock B} [get_ports {mem_clk_b}]
set_propagated_clock [get_clocks {bist_mem_clk_b}]
set_clock_uncertainty 0.2500 [get_ports {mem_clk_a}]
set_clock_uncertainty 0.2500 [get_ports {mem_clk_b}]
set_clock_groups -name async_clock -asynchronous \
 -group [list [get_clocks {bist_mem_clk_a}]\
           [get_clocks {bist_mem_clk_b}]\
           [get_clocks {wb_clk_i}]] -comment {Async Clock group}
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -rise -min -add_delay [get_ports {bist_en}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -fall -min -add_delay [get_ports {bist_en}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {bist_load}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {bist_load}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {bist_run}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {bist_run}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {bist_sdi}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {bist_sdi}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {bist_shift}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {bist_shift}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[0]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[0]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[10]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[10]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[11]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[11]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[12]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[12]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[13]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[13]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[14]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[14]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[15]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[15]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[16]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[16]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[17]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[17]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[18]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[18]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[19]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[19]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[1]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[1]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[20]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[20]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[21]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[21]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[22]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[22]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[23]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[23]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[24]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[24]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[25]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[25]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[26]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[26]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[27]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[27]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[28]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[28]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[29]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[29]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[2]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[2]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[30]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[30]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[31]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[31]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[3]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[3]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[4]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[4]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[5]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[5]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[6]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[6]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[7]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[7]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[8]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[8]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_dout_a[9]}]
set_input_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_dout_a[9]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {rst_n}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {rst_n}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_adr_i[0]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_adr_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_adr_i[1]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_adr_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_adr_i[2]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_adr_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_adr_i[3]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_adr_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_adr_i[4]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_adr_i[4]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_adr_i[5]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_adr_i[5]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_adr_i[6]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_adr_i[6]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_adr_i[7]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_adr_i[7]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_cyc_i}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_cyc_i}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_sel_i[0]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_sel_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_sel_i[1]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_sel_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_sel_i[2]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_sel_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_sel_i[3]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_sel_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_stb_i}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_stb_i}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_we_i}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_we_i}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {bist_correct}]
set_output_delay 4.5000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {bist_correct}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {bist_done}]
set_output_delay 4.5000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {bist_done}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {bist_error}]
set_output_delay 4.5000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {bist_error}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {bist_error_cnt[0]}]
set_output_delay 4.5000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {bist_error_cnt[0]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {bist_error_cnt[1]}]
set_output_delay 4.5000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {bist_error_cnt[1]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {bist_error_cnt[2]}]
set_output_delay 4.5000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {bist_error_cnt[2]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {bist_error_cnt[3]}]
set_output_delay 4.5000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {bist_error_cnt[3]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {bist_sdo}]
set_output_delay 4.5000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {bist_sdo}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_addr_a[0]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_addr_a[0]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_addr_a[1]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_addr_a[1]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_addr_a[2]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_addr_a[2]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_addr_a[3]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_addr_a[3]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_addr_a[4]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_addr_a[4]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_addr_a[5]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_addr_a[5]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_addr_a[6]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_addr_a[6]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_addr_a[7]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_addr_a[7]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_addr_b[0]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_addr_b[0]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_addr_b[1]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_addr_b[1]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_addr_b[2]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_addr_b[2]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_addr_b[3]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_addr_b[3]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_addr_b[4]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_addr_b[4]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_addr_b[5]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_addr_b[5]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_addr_b[6]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_addr_b[6]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_addr_b[7]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_addr_b[7]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a}] -min -add_delay [get_ports {mem_cen_a}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a}] -max -add_delay [get_ports {mem_cen_a}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_cen_b}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_cen_b}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[0]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[0]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[10]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[10]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[11]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[11]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[12]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[12]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[13]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[13]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[14]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[14]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[15]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[15]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[16]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[16]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[17]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[17]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[18]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[18]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[19]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[19]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[1]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[1]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[20]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[20]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[21]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[21]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[22]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[22]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[23]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[23]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[24]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[24]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[25]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[25]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[26]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[26]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[27]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[27]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[28]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[28]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[29]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[29]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[2]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[2]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[30]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[30]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[31]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[31]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[3]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[3]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[4]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[4]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[5]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[5]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[6]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[6]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[7]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[7]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[8]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[8]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_din_b[9]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_din_b[9]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_mask_b[0]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_mask_b[0]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_mask_b[1]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_mask_b[1]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_mask_b[2]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_mask_b[2]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_mask_b[3]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_mask_b[3]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b}] -min -add_delay [get_ports {mem_web_b}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b}] -max -add_delay [get_ports {mem_web_b}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_ack_o}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_ack_o}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[0]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[10]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[10]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[11]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[11]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[12]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[12]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[13]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[13]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[14]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[14]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[15]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[15]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[16]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[16]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[17]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[17]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[18]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[18]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[19]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[19]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[1]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[20]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[20]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[21]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[21]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[22]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[22]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[23]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[23]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[24]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[24]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[25]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[25]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[26]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[26]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[27]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[27]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[28]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[28]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[29]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[29]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[2]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[30]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[30]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[31]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[31]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[3]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[4]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[4]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[5]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[5]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[6]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[6]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[7]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[7]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[8]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[8]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[9]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[9]}]
set_output_delay 1.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_err_o}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_err_o}]
set_max_delay\
    -from [get_ports {wbd_clk_int}] 3.5000
set_max_delay\
    -from [get_ports {wbd_clk_int}]\
    -to [get_ports {wbd_clk_mbist}] 3.5000
set_max_delay\
    -to [get_ports {wbd_clk_mbist}] 2.0000
set_false_path\
    -from [get_ports {bist_en}]
###############################################################################
# Environment
###############################################################################
set_load -pin_load 0.0334 [get_ports {bist_correct}]
set_load -pin_load 0.0334 [get_ports {bist_done}]
set_load -pin_load 0.0334 [get_ports {bist_error}]
set_load -pin_load 0.0334 [get_ports {bist_sdo}]
set_load -pin_load 0.0334 [get_ports {mem_cen_a}]
set_load -pin_load 0.0334 [get_ports {mem_cen_b}]
set_load -pin_load 0.0334 [get_ports {mem_clk_a}]
set_load -pin_load 0.0334 [get_ports {mem_clk_b}]
set_load -pin_load 0.0334 [get_ports {mem_web_b}]
set_load -pin_load 0.0334 [get_ports {wb_cyc_i}]
set_load -pin_load 0.0334 [get_ports {wb_stb_i}]
set_load -pin_load 0.0334 [get_ports {wb_we_i}]
set_load -pin_load 0.0334 [get_ports {bist_error_cnt[3]}]
set_load -pin_load 0.0334 [get_ports {bist_error_cnt[2]}]
set_load -pin_load 0.0334 [get_ports {bist_error_cnt[1]}]
set_load -pin_load 0.0334 [get_ports {bist_error_cnt[0]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a[7]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a[6]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a[5]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a[4]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a[3]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a[2]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a[1]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a[0]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b[7]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b[6]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b[5]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b[4]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b[3]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b[2]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b[1]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b[0]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[31]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[30]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[29]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[28]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[27]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[26]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[25]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[24]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[23]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[22]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[21]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[20]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[19]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[18]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[17]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[16]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[15]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[14]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[13]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[12]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[11]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[10]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[9]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[8]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[7]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[6]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[5]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[4]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[3]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[2]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[1]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[0]}]
set_load -pin_load 0.0334 [get_ports {mem_mask_b[3]}]
set_load -pin_load 0.0334 [get_ports {mem_mask_b[2]}]
set_load -pin_load 0.0334 [get_ports {mem_mask_b[1]}]
set_load -pin_load 0.0334 [get_ports {mem_mask_b[0]}]
set_load -pin_load 0.0334 [get_ports {wb_adr_i[7]}]
set_load -pin_load 0.0334 [get_ports {wb_adr_i[6]}]
set_load -pin_load 0.0334 [get_ports {wb_adr_i[5]}]
set_load -pin_load 0.0334 [get_ports {wb_adr_i[4]}]
set_load -pin_load 0.0334 [get_ports {wb_adr_i[3]}]
set_load -pin_load 0.0334 [get_ports {wb_adr_i[2]}]
set_load -pin_load 0.0334 [get_ports {wb_adr_i[1]}]
set_load -pin_load 0.0334 [get_ports {wb_adr_i[0]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[31]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[30]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[29]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[28]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[27]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[26]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[25]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[24]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[23]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[22]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[21]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[20]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[19]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[18]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[17]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[16]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[15]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[14]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[13]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[12]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[11]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[10]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[9]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[8]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[7]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[6]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[5]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[4]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[3]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[2]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[1]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_i[0]}]
set_load -pin_load 0.0334 [get_ports {wb_sel_i[3]}]
set_load -pin_load 0.0334 [get_ports {wb_sel_i[2]}]
set_load -pin_load 0.0334 [get_ports {wb_sel_i[1]}]
set_load -pin_load 0.0334 [get_ports {wb_sel_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_en}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_load}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_run}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_sdi}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_shift}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_cyc_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_we_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[0]}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
###############################################################################
# Design Rules
###############################################################################
set_max_fanout 4.0000 [current_design]