design clean-up
diff --git a/README.md b/README.md index 35078b9..3da7c25 100644 --- a/README.md +++ b/README.md
@@ -5,3 +5,7 @@ # Reference * turbo8051 <https://opencores.org/projects/turbo8051> * Julien OURY MPW Project <https://github.com/JulienOury/ChristmasTreeController.git> +* opengfx430 <https://github.com/olgirard/opengfx430> +* openMSP430 <https://opencores.org/websvn/filedetails?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2FopenMSP430.pdf> +* slau049f <https://www.ti.com/lit/ug/slau049f/slau049f.pdf> +* LT24 Card <http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=68&No=892&PartNo=2#heading>
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile new file mode 100644 index 0000000..dcd4196 --- /dev/null +++ b/verilog/dv/Makefile
@@ -0,0 +1,47 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + +# ---- Test patterns for project striVe ---- + +.SUFFIXES: +.SILENT: clean all + +PATTERNS = user_mbist_test1 + +all: ${PATTERNS} + echo "################# RTL Test case Summary #####################" > regression.rpt + xterm -e /usr/bin/watch -n 25 /bin/cat regression.rpt & + for i in ${PATTERNS}; do \ + ( cd $$i && make | tee run.rtl.log && grep Monitor run.rtl.log | grep $$i >> ../regression.rpt) ; \ + done + echo "################# GL Test case Summary #####################" >> regression.rpt + \rm -rf */*.vvp + for i in ${PATTERNS}; do \ + ( cd $$i && make SIM=GL | tee run.gl.log && grep Monitor run.gl.log | grep $$i >> ../regression.rpt) ; \ + done + echo "################# End of Test case Summary #####################" >> regression.rpt + +DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv)) +$(DV_PATTERNS): verify-% : + cd $* && make + +clean: ${PATTERNS} + for i in ${PATTERNS}; do \ + ( cd $$i && make clean ) ; \ + done + rm -rf *.log + +.PHONY: clean all
diff --git a/verilog/dv/user_mbist_test1/Makefile b/verilog/dv/user_mbist_test1/Makefile new file mode 100644 index 0000000..9224b8a --- /dev/null +++ b/verilog/dv/user_mbist_test1/Makefile
@@ -0,0 +1,85 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + + +# ---- Include Partitioned Makefiles ---- + +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### + +DESIGNS?=../../.. + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog + +export PDK_PATH ?= $(PDK_PATH) + +## Simulation mode: RTL/GL +SIM?=RTL +DUMP?=OFF + +### To Enable IVERILOG FST DUMP +export IVERILOG_DUMPER = fst + + +.SUFFIXES: + +PATTERN = user_mbist_test1 + +all: ${PATTERN:=.vcd} + + +vvp: ${PATTERN:=.vvp} + +%.vvp: %_tb.v +ifeq ($(SIM),RTL) + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ + $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ + $< -o $@ + endif +else + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ + $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ + $< -o $@ + endif +endif + +%.vcd: %.vvp + vvp $< | tee run.rtl.log + + +# ---- Clean ---- + +clean: + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump + +.PHONY: clean hex all
diff --git a/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v b/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v new file mode 100644 index 0000000..e6c5e53 --- /dev/null +++ b/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v
@@ -0,0 +1,660 @@ +//////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> +////////////////////////////////////////////////////////////////////// +//// //// +//// Standalone User validation Test bench //// +//// //// +//// //// +//// Description //// +//// This is a standalone test bench to validate the //// +//// Digital core MBIST logic through External WB i/F. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.1 - 18 Oct 2021, Dinesh A //// +//// //// +////////////////////////////////////////////////////////////////////// + +`default_nettype wire + +`timescale 1 ns / 1 ps + +`include "./sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" +`include "user_reg_map.v" + +`define NO_SRAM 4 // Number of SRAM connected to MBIST WRAPPER +`define SRAM_AD 9 // SRAM ADDRESS WIDTH + +`define TB_TOP user_mbist_test1_tb +module `TB_TOP; + + reg clock; + reg wb_rst_i; + reg power1, power2; + reg power3, power4; + + reg wbd_ext_cyc_i; // strobe/request + reg wbd_ext_stb_i; // strobe/request + reg [31:0] wbd_ext_adr_i; // address + reg wbd_ext_we_i; // write + reg [31:0] wbd_ext_dat_i; // data output + reg [3:0] wbd_ext_sel_i; // byte enable + + wire [31:0] wbd_ext_dat_o; // data input + wire wbd_ext_ack_o; // acknowlegement + wire wbd_ext_err_o; // error + + // User I/O + wire [37:0] io_oeb; + wire [37:0] io_out; + wire [37:0] io_in; + + wire gpio; + wire [37:0] mprj_io; + wire [7:0] mprj_io_0; + reg test_fail; + reg [31:0] read_data; + reg [31:0] writemem [0:511]; + reg [`SRAM_AD-1:0] faultaddr [0:7]; + integer i; + event error_insert; + + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 clock <= (clock === 1'b0); + + initial begin + clock = 0; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + end + + `ifdef WFDUMP + initial begin + $dumpfile("simx.vcd"); + $dumpvars(0, user_mbist_test1_tb); + end + `endif + + initial begin + wb_rst_i <= 1'b1; + #100; + wb_rst_i <= 1'b0; // Release reset + + #200; // Wait for reset removal + repeat (10) @(posedge clock); + $display("Monitor: Standalone User Test Started"); + + test_fail = 0; + // Remove Wb Reset + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + + + $display("###################################################"); + $display(" MBIST Test with Without Address Failure"); + $display("###################################################"); + + // Check Is there is any BIST Error + // [0] - Bist Done - 1 + // [1] - Bist Error - 0 + // [2] - Bist Correct - 0 + // [3] - Reserved - 0 + // [7:4] - Bist Error Cnt - 4'h0 + insert_fault(0,0,32'h01010101); + + if(test_fail == 0) begin + $display("Monitor: Step-1: BIST Test without any Memory Error insertion test Passed"); + end else begin + $display("Monitor: Step-1: BIST Test without any Memory Error insertion test Failed"); + end + $dumpon; + $display("###################################################"); + $display(" MBIST Test with Single Address Failure"); + $display("###################################################"); + // Check Is there is any BIST Error + // [0] - Bist Done - 1 + // [1] - Bist Error - 0 + // [2] - Bist Correct - 1 + // [3] - Reserved - 0 + // [7:4] - Bist Error Cnt - 4'h1 + //if(read_data[6:0] != 7'b0001101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x1 + faultaddr[0] = 9'h10; + insert_fault(1,1,32'h15151515); + + if(test_fail == 0) begin + $display("Monitor: Step-2: BIST Test with One Memory Error insertion test Passed"); + end else begin + $display("Monitor: Step-2: BIST Test with One Memory Error insertion test Failed"); + end + $display("###################################################"); + $display("###################################################"); + $display(" MBIST Test with Two Address Failure"); + $display("###################################################"); + // Check Is there is any BIST Error + // [0] - Bist Done - 1 + // [1] - Bist Error - 0 + // [2] - Bist Correct - 1 + // [3] - Reserved - 0 + // [7:4] - Bist Error Cnt - 4'h2 + //if(read_data[6:0] != 7'b0010101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x2 + faultaddr[0] = 9'h10; + faultaddr[1] = 9'h20; + insert_fault(2,0,32'h25252525); + + if(test_fail == 0) begin + $display("Monitor: Step-3: BIST Test with Two Memory Error insertion test Passed"); + end else begin + $display("Monitor: Step-3: BIST Test with Two Memory Error insertion test Failed"); + end + $display("###################################################"); + $display(" MBIST Test with Three Address Failure"); + $display("###################################################"); + + // Check Is there is any BIST Error + // [0] - Bist Done - 1 + // [1] - Bist Error - 0 + // [2] - Bist Correct - 1 + // [3] - Reserved - 0 + // [7:4] - Bist Error Cnt - 4'h3 + //if(read_data[6:0] != 7'b0011101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x3 + faultaddr[0] = 9'h10; + faultaddr[1] = 9'h20; + faultaddr[2] = 9'h30; + insert_fault(3,1,32'h35353535); + + if(test_fail == 0) begin + $display("Monitor: Step-4: BIST Test with Three Memory Error insertion test Passed"); + end else begin + $display("Monitor: Step-4: BIST Test with Three Memory Error insertion test Failed"); + end + $display("###################################################"); + $display(" MBIST Test with Fours Address Failure"); + $display("###################################################"); + // Check Is there is any BIST Error + // [0] - Bist Done - 1 + // [1] - Bist Error - 0 + // [2] - Bist Correct - 1 + // [3] - Reserved - 0 + // [7:4] - Bist Error Cnt - 4'h4 + //if(read_data[6:0] != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4 + faultaddr[0] = 9'h10; + faultaddr[1] = 9'h20; + faultaddr[2] = 9'h30; + faultaddr[3] = 9'h40; + insert_fault(4,0,32'h45454545); + + if(test_fail == 0) begin + $display("Monitor: Step-5: BIST Test with Four Memory Error insertion test Passed"); + end else begin + $display("Monitor: Step-5: BIST Test with Four Memory Error insertion test Failed"); + end + + $dumpon; + $display("###################################################"); + $display(" MBIST Test with Fours Address(Continous Starting Addrsess) Failure"); + $display("###################################################"); + // Check Is there is any BIST Error + // [0] - Bist Done - 1 + // [1] - Bist Error - 0 + // [2] - Bist Correct - 1 + // [3] - Reserved - 0 + // [7:4] - Bist Error Cnt - 4'h4 + //if(read_data[6:0] != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4 + faultaddr[0] = 9'h0; + faultaddr[1] = 9'h1; + faultaddr[2] = 9'h2; + faultaddr[3] = 9'h3; + insert_fault(4,0,32'h45454545); + + if(test_fail == 0) begin + $display("Monitor: Step-5.2: BIST Test with Four Memory Error insertion test Passed"); + end else begin + $display("Monitor: Step-5.2: BIST Test with Four Memory Error insertion test Failed"); + end + + $display("###################################################"); + $display(" MBIST Test with Fours Address(Last Addrsess) Failure"); + $display("###################################################"); + // Check Is there is any BIST Error + // [0] - Bist Done - 1 + // [1] - Bist Error - 0 + // [2] - Bist Correct - 1 + // [3] - Reserved - 0 + // [7:4] - Bist Error Cnt - 4'h4 + //if(read_data[6:0] != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4 + faultaddr[0] = 9'hF0; + faultaddr[1] = 9'hF1; + faultaddr[2] = 9'hF2; + faultaddr[3] = 9'hF3; + insert_fault(4,0,32'h45454545); + + if(test_fail == 0) begin + $display("Monitor: Step-5.3: BIST Test with Four Memory Error insertion test Passed"); + end else begin + $display("Monitor: Step-5.3: BIST Test with Four Memory Error insertion test Failed"); + end + $dumpon; + $display("###################################################"); + $display(" MBIST Test with Five Address Failure"); + $display("###################################################"); + // Check Is there is any BIST Error + // [0] - Bist Done - 1 + // [1] - Bist Error - 1 + // [2] - Bist Correct - 1 + // [3] - Reserved - 0 + // [7:4] - Bist Error Cnt - 4'h4 + //if(read_data[6:0] != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4 + faultaddr[0] = 9'h10; + faultaddr[1] = 9'h20; + faultaddr[2] = 9'h30; + faultaddr[3] = 9'h40; + faultaddr[4] = 9'h50; + insert_fault(5,1,32'h47474747); + + if(test_fail == 0) begin + $display("Monitor: Step-5: BIST Test with Five Memory Error insertion test Passed"); + end else begin + $display("Monitor: Step-5: BIST Test with Five Memory Error insertion test Failed"); + end + + $dumpon; + $display("###################################################"); + $display(" MBIST Test with Functional Access, continuation of previous MBIST Signature"); + $display("###################################################"); + $dumpon; + fork + begin + // Remove the Bist Enable and Bist Run + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_BIST_CTRL2,'h000); + + // Fill Random Data + for (i=0; i< 9'h1FC; i=i+1) begin + writemem[i] = $random; + wb_user_core_write(`ADDR_SPACE_SRAM0+(i*4),writemem[i]); + wb_user_core_write(`ADDR_SPACE_SRAM1+(i*4),writemem[i]); + wb_user_core_write(`ADDR_SPACE_SRAM2+(i*4),writemem[i]); + wb_user_core_write(`ADDR_SPACE_SRAM3+(i*4),writemem[i]); + end + // Read back data + for (i=0; i< 9'h1FC; i=i+1) begin + wb_user_core_read_check(`ADDR_SPACE_SRAM0+(i*4),read_data,writemem[i],32'hFFFFFFFF); + wb_user_core_read_check(`ADDR_SPACE_SRAM1+(i*4),read_data,writemem[i],32'hFFFFFFFF); + wb_user_core_read_check(`ADDR_SPACE_SRAM2+(i*4),read_data,writemem[i],32'hFFFFFFFF); + wb_user_core_read_check(`ADDR_SPACE_SRAM3+(i*4),read_data,writemem[i],32'hFFFFFFFF); + end + + // Cross-check Reducency address hold the failure address data + // Is last Error inserted address are 0x10,0x20,0x30,0x40 + // So Address 0x1FC = Data[0x10], 0x1FD = Data[0x20] + // Address 0x1FE = Data[0x30], 0x1FF = Data[0x40] + // Check 2kb SRAM1 + wb_user_core_read_check(`ADDR_SPACE_SRAM0 + (9'h1FC *4),read_data,writemem[9'h10],32'hFFFFFFFF); + wb_user_core_read_check(`ADDR_SPACE_SRAM0 + (9'h1FD *4),read_data,writemem[9'h20],32'hFFFFFFFF); + wb_user_core_read_check(`ADDR_SPACE_SRAM0 + (9'h1FE *4),read_data,writemem[9'h30],32'hFFFFFFFF); + wb_user_core_read_check(`ADDR_SPACE_SRAM0 + (9'h1FF *4),read_data,writemem[9'h40],32'hFFFFFFFF); + + // Check 2kb SRAM2 + wb_user_core_read_check(`ADDR_SPACE_SRAM1 + (9'h1FC *4),read_data,writemem[9'h11],32'hFFFFFFFF); + wb_user_core_read_check(`ADDR_SPACE_SRAM1 + (9'h1FD *4),read_data,writemem[9'h21],32'hFFFFFFFF); + wb_user_core_read_check(`ADDR_SPACE_SRAM1 + (9'h1FE *4),read_data,writemem[9'h31],32'hFFFFFFFF); + wb_user_core_read_check(`ADDR_SPACE_SRAM1 + (9'h1FF *4),read_data,writemem[9'h41],32'hFFFFFFFF); + + // Check 2kb SRAM3 + wb_user_core_read_check(`ADDR_SPACE_SRAM2 + (9'h1FC *4),read_data,writemem[9'h12],32'hFFFFFFFF); + wb_user_core_read_check(`ADDR_SPACE_SRAM2 + (9'h1FD *4),read_data,writemem[9'h22],32'hFFFFFFFF); + wb_user_core_read_check(`ADDR_SPACE_SRAM2 + (9'h1FE *4),read_data,writemem[9'h32],32'hFFFFFFFF); + wb_user_core_read_check(`ADDR_SPACE_SRAM2 + (9'h1FF *4),read_data,writemem[9'h42],32'hFFFFFFFF); + + // Check 2kb SRAM4 + wb_user_core_read_check(`ADDR_SPACE_SRAM3 + (9'h1FC *4),read_data,writemem[9'h13],32'hFFFFFFFF); + wb_user_core_read_check(`ADDR_SPACE_SRAM3 + (9'h1FD *4),read_data,writemem[9'h23],32'hFFFFFFFF); + wb_user_core_read_check(`ADDR_SPACE_SRAM3 + (9'h1FE *4),read_data,writemem[9'h33],32'hFFFFFFFF); + wb_user_core_read_check(`ADDR_SPACE_SRAM3 + (9'h1FF *4),read_data,writemem[9'h43],32'hFFFFFFFF); + + end + begin + // Loop for BIST TimeOut + repeat (200000) @(posedge clock); + // $display("+1000 cycles"); + test_fail = 1; + end + join_any + disable fork; //disable pending fork activity + if(test_fail == 0) begin + $display("Monitor: Step-5: BIST Test with Functional access test Passed"); + end else begin + $display("Monitor: Step-5: BIST Test with Functional access test failed"); + end + + $display("###################################################"); + $finish; + end + +wire USER_VDD1V8 = 1'b1; +wire VSS = 1'b0; + + +user_project_wrapper u_top( +`ifdef USE_POWER_PINS + .vccd1(USER_VDD1V8), // User area 1 1.8V supply + .vssd1(VSS), // User area 1 digital ground +`endif + .wb_clk_i (clock), // System clock + .user_clock2 (1'b1), // Real-time clock + .wb_rst_i (wb_rst_i), // Regular Reset signal + + .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request + .wbs_stb_i (wbd_ext_stb_i), // strobe/request + .wbs_adr_i (wbd_ext_adr_i), // address + .wbs_we_i (wbd_ext_we_i), // write + .wbs_dat_i (wbd_ext_dat_i), // data output + .wbs_sel_i (wbd_ext_sel_i), // byte enable + + .wbs_dat_o (wbd_ext_dat_o), // data input + .wbs_ack_o (wbd_ext_ack_o), // acknowlegement + + + // Logic Analyzer Signals + .la_data_in ('1) , + .la_data_out (), + .la_oenb ('0), + + + // IOs + .io_in (io_in) , + .io_out (io_out) , + .io_oeb (io_oeb) , + + .user_irq () + +); + +`ifndef GL // Drive Power for Hold Fix Buf + // All standard cell need power hook-up for functionality work + initial begin + + + end +`endif + + +//------------------------------------- +// Insert user defined number of fault +// ----------------------------------- + +task insert_fault; +input [3:0] num_fault; +input fault_type; // 0 -> struck at 0 and 1 -> struck at 1 +input [31:0] mbist_signature; +reg [31:0] datain; +reg [`SRAM_AD-1:0] fail_addr1; +reg [`SRAM_AD-1:0] fail_addr2; +reg [`SRAM_AD-1:0] fail_addr3; +reg [`SRAM_AD-1:0] fail_addr4; +integer j; +begin + repeat (2) @(posedge clock); + // Remove the Bist Enable and Bist Run + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_BIST_CTRL2,'h000); + // Remove WB and BIST RESET + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h001); + // Set the Bist Enable and Bist Run + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_BIST_CTRL2,'h00000003); + // Remove WB and BIST RESET + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h003); + fork + begin + // Check for MBIST Done + read_data = 'h0; + while (read_data[0] != 1'b1) begin + wb_user_core_read(`ADDR_SPACE_GLBL+`GLBL_BIST_STAT,read_data); + end + // wait for some time for all the BIST to complete + repeat (1000) @(posedge clock); + // Check Is there is any BIST Error + // [0] - Bist Done + // [1] - Bist Error + // [2] - Bist Correct + // [3] - Reserved + // [7:4] - Bist Error Cnt + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_BIST_STAT,read_data,mbist_signature[31:0],32'hFFFFFFFF); + end + // Insert Error Insertion + begin + while(1) begin + repeat (1) @(posedge clock); + #1; + + if(u_top.u_sram0_2kb.web0 == 1'b0 && + ((num_fault > 0 && u_top.u_sram0_2kb.addr0 == faultaddr[0]) || + (num_fault > 1 && u_top.u_sram0_2kb.addr0 == faultaddr[1]) || + (num_fault > 2 && u_top.u_sram0_2kb.addr0 == faultaddr[2]) || + (num_fault > 3 && u_top.u_sram0_2kb.addr0 == faultaddr[3]) || + (num_fault > 4 && u_top.u_sram0_2kb.addr0 == faultaddr[4]) || + (num_fault > 5 && u_top.u_sram0_2kb.addr0 == faultaddr[5]) || + (num_fault > 6 && u_top.u_sram0_2kb.addr0 == faultaddr[6]) || + (num_fault > 7 && u_top.u_sram0_2kb.addr0 == faultaddr[7]))) + begin + if(fault_type == 0) // Struck at 0 + force u_top.u_sram0_2kb.din0 = u_top.mem0_din_a & 32'hFFFF_FFFE; + else + force u_top.u_sram0_2kb.din0 = u_top.mem0_din_a | 32'h1; + -> error_insert; + end else begin + release u_top.u_sram0_2kb.din0; + end + + if(u_top.u_sram1_2kb.web0 == 1'b0 && + ((num_fault > 0 && u_top.u_sram1_2kb.addr0 == faultaddr[0]+1) || + (num_fault > 1 && u_top.u_sram1_2kb.addr0 == faultaddr[1]+1) || + (num_fault > 2 && u_top.u_sram1_2kb.addr0 == faultaddr[2]+1) || + (num_fault > 3 && u_top.u_sram1_2kb.addr0 == faultaddr[3]+1) || + (num_fault > 4 && u_top.u_sram1_2kb.addr0 == faultaddr[4]+1) || + (num_fault > 5 && u_top.u_sram1_2kb.addr0 == faultaddr[5]+1) || + (num_fault > 6 && u_top.u_sram1_2kb.addr0 == faultaddr[6]+1) || + (num_fault > 7 && u_top.u_sram1_2kb.addr0 == faultaddr[7]+1))) + begin + if(fault_type == 0) // Struck at 0 + force u_top.u_sram1_2kb.din0 = u_top.mem1_din_a & 32'hFFFF_FFFE; + else + force u_top.u_sram1_2kb.din0 = u_top.mem1_din_a | 32'h1; + -> error_insert; + end else begin + release u_top.u_sram1_2kb.din0; + end + + if(u_top.u_sram2_2kb.web0 == 1'b0 && + ((num_fault > 0 && u_top.u_sram2_2kb.addr0 == faultaddr[0]+2) || + (num_fault > 1 && u_top.u_sram2_2kb.addr0 == faultaddr[1]+2) || + (num_fault > 2 && u_top.u_sram2_2kb.addr0 == faultaddr[2]+2) || + (num_fault > 3 && u_top.u_sram2_2kb.addr0 == faultaddr[3]+2) || + (num_fault > 4 && u_top.u_sram2_2kb.addr0 == faultaddr[4]+2) || + (num_fault > 5 && u_top.u_sram2_2kb.addr0 == faultaddr[5]+2) || + (num_fault > 6 && u_top.u_sram2_2kb.addr0 == faultaddr[6]+2) || + (num_fault > 7 && u_top.u_sram2_2kb.addr0 == faultaddr[7]+2))) + begin + if(fault_type == 0) // Struck at 0 + force u_top.u_sram2_2kb.din0 = u_top.mem2_din_a & 32'hFFFF_FFFE; + else + force u_top.u_sram2_2kb.din0 = u_top.mem2_din_a | 32'h1; + -> error_insert; + end else begin + release u_top.u_sram2_2kb.din0; + end + + if(u_top.u_sram3_2kb.web0 == 1'b0 && + ((num_fault > 0 && u_top.u_sram3_2kb.addr0 == faultaddr[0]+3) || + (num_fault > 1 && u_top.u_sram3_2kb.addr0 == faultaddr[1]+3) || + (num_fault > 2 && u_top.u_sram3_2kb.addr0 == faultaddr[2]+3) || + (num_fault > 3 && u_top.u_sram3_2kb.addr0 == faultaddr[3]+3) || + (num_fault > 4 && u_top.u_sram3_2kb.addr0 == faultaddr[4]+3) || + (num_fault > 5 && u_top.u_sram3_2kb.addr0 == faultaddr[5]+3) || + (num_fault > 6 && u_top.u_sram3_2kb.addr0 == faultaddr[6]+3) || + (num_fault > 7 && u_top.u_sram3_2kb.addr0 == faultaddr[7]+3))) + begin + if(fault_type == 0) // Struck at 0 + force u_top.u_sram3_2kb.din0 = u_top.mem3_din_a & 32'hFFFF_FFFE; + else + force u_top.u_sram3_2kb.din0 = u_top.mem3_din_a | 32'h1; + -> error_insert; + end else begin + release u_top.u_sram3_2kb.din0; + end + + end + end + begin + // Loop for BIST TimeOut + repeat (200000) @(posedge clock); + // $display("+1000 cycles"); + test_fail = 1; + end + join_any + disable fork; //disable pending fork activity + + // Read Back the Failure Address and cross-check all the 4 MBIST + for(j=0; j < `NO_SRAM; j=j+1) begin + fail_addr1 = faultaddr[0]+j; + fail_addr2 = faultaddr[1]+j; + fail_addr3 = faultaddr[2]+j; + fail_addr4 = faultaddr[3]+j; + + // Select the Serial SDI/SDO interface + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_BIST_CTRL1,j); + if(num_fault == 1) + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_BIST_SRLDATA,read_data,{16'h0,7'h0,fail_addr1},32'h0000_FFFF); + if(num_fault == 2) + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_BIST_SRLDATA,read_data,{7'h0,fail_addr2,7'h0,fail_addr1},32'hFFFF_FFFF); + if(num_fault == 3) begin + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_BIST_SRLDATA,read_data,{7'h0,fail_addr2,7'h0,fail_addr1},32'hFFFF_FFFF); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_BIST_SRMDATA,read_data,{16'h0,7'h0,fail_addr3},32'h0000_FFFF); + end + if(num_fault >= 4) begin + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_BIST_SRLDATA,read_data,{7'h0,fail_addr2,7'h0,fail_addr1},32'hFFFF_FFFF); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_BIST_SRMDATA,read_data,{7'h0,faultaddr[3]+j,7'h0,fail_addr3},32'hFFFF_FFFF); + end + end +end +endtask + + +task wb_user_core_write; +input [31:0] address; +input [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h1; // write + wbd_ext_dat_i =data; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data); + repeat (2) @(posedge clock); +end +endtask + +task wb_user_core_read; +input [31:0] address; +output [31:0] data; +reg [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='0; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + #1; + data = wbd_ext_dat_o; + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + //$display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); + repeat (2) @(posedge clock); +end +endtask + +task wb_user_core_read_check; +input [31:0] address; +output [31:0] data; +input [31:0] cmp_data; +input [31:0] cmp_mask; +reg [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='0; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + #1; + data = wbd_ext_dat_o; + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + if((data & cmp_mask) !== (cmp_data & cmp_mask) ) begin + $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,(cmp_data & cmp_mask),(data & cmp_mask)); + test_fail = 1; + end else begin + $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,(data & cmp_mask)); + end + repeat (2) @(posedge clock); +end +endtask + + +endmodule +`default_nettype wire
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project new file mode 100644 index 0000000..1ddeecc --- /dev/null +++ b/verilog/includes/includes.gl.caravel_user_project
@@ -0,0 +1,231 @@ +# Caravel user project includes ++define+UNIT_DELAY=#0.2 ++incdir+$(USER_PROJECT_VERILOG)/rtl/ ++incdir+$(USER_PROJECT_VERILOG)/rtl/i2cm/src/includes ++incdir+$(USER_PROJECT_VERILOG)/rtl/usb1_host/src/includes ++incdir+$(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/includes ++incdir+$(USER_PROJECT_VERILOG)/dv/common/bfm ++incdir+$(USER_PROJECT_VERILOG)/dv/common/model ++incdir+$(USER_PROJECT_VERILOG)/dv/common/agents +$(USER_PROJECT_VERILOG)/rtl/user_reg_map.v + +################################################## +### USER PROJECT RTL +################################################## +#ifdef USER_RTL +#-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr1_top_wb.sv +#else +$(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v +#endif + +################################################## +### YCR INTERFACE +################################################## +#ifdef YCR_INTF_RTL +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/cache/src/core/dcache_top.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/cache/src/core/dcache_tag_fifo.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/cache/src/core/icache_tag_fifo.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/cache/src/core/icache_top.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/cache/src/core/icache_app_fsm.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/lib/ycr_async_wbb.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_dmem_wb.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_intf.sv +#else +$(USER_PROJECT_VERILOG)/gl/ycr_intf.v +#endif +################################################## +### YCR INTER CONNECT +################################################## +#ifdef YCR_ICONNECT_RTL +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_iconnect.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_cross_bar.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_router.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_dmem_router.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_tcm.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_timer.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/lib/ycr_arb.sv +#else +$(USER_PROJECT_VERILOG)/gl/ycr_iconnect.v +#endif + + +################################################## +### YCR CORE +################################################## +#ifdef YCR_CORE_RTL +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_top.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr_core_top.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr_dm.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr_tapc_synchronizer.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr_clk_ctrl.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr_scu.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr_tapc.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr_tapc_shift_reg.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr_dmi.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_ifu.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_idu.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_exu.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_mprf.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_csr.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_ialu.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_mul.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_div.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_lsu.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_hdu.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_tdu.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_ipic.sv +#else +$(USER_PROJECT_VERILOG)/gl/ycr_core_top.v +#endif +################################################## +### QSPIM +################################################## +#ifdef QSPIM_RTL +#-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_top.sv +#-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_if.sv +#-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_regs.sv +#-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_fifo.sv +#-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_clkgen.sv +#-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_ctrl.sv +#-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_rx.sv +#-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_tx.sv +#else +$(USER_PROJECT_VERILOG)/gl/qspim_top.v +#endif + + +################################################## +### WB_HOST +################################################## +#ifdef WB_HOST_RTL +#-v $(USER_PROJECT_VERILOG)/rtl/clk_skew_adjust/src/clk_skew_adjust.v +#-v $(USER_PROJECT_VERILOG)/rtl/wb_host/src/wb_host.sv +#-v $(USER_PROJECT_VERILOG)/rtl/wb_host/src/wb_reset_fsm.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/async_fifo.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/async_wb.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_ctl.v +#-v $(USER_PROJECT_VERILOG)/rtl/lib/ctech_cells.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/registers.v +#-v $(USER_PROJECT_VERILOG)/rtl/lib/reset_sync.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/async_reg_bus.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/double_sync_low.v +#-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_div8.v +#-v $(USER_PROJECT_VERILOG)/rtl/lib/async_fifo_th.sv +#-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_arb.sv +#-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_txfsm.sv +#-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_rxfsm.sv +#-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2wb.sv +#-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2_core.sv +#-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart_msg_handler.v +#-v $(USER_PROJECT_VERILOG)/rtl/sspis/src/sspis_top.sv +#-v $(USER_PROJECT_VERILOG)/rtl/sspis/src/sspis_if.sv +#-v $(USER_PROJECT_VERILOG)/rtl/sspis/src/spi2wb.sv +#else +$(USER_PROJECT_VERILOG)/gl/wb_host.v +#endif + +################################################## +### PINMUX +################################################## +#ifdef PINMUX_RTL +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux_top.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/glbl_reg.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_top.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_intr.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_reg.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm_top.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm_reg.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer_top.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer_reg.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/semaphore_reg.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/ws281x_top.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/ws281x_driver.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/ws281x_reg.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/strap_ctrl.sv +#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/glbl_rst_reg.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type1.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type2.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/registers.v +#-v $(USER_PROJECT_VERILOG)/rtl/lib/ctech_cells.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/reset_sync.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_fifo.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_ctl.v +#-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_skew_adjust.gv +#else +$(USER_PROJECT_VERILOG)/gl/pinmux_top.v +#endif + +################################################## +### UART +################################################## +#ifdef UART_RTL +#-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_core.sv +#-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_cfg.sv +#-v $(USER_PROJECT_VERILOG)/rtl/i2cm/src/core/i2cm_bit_ctrl.v +#-v $(USER_PROJECT_VERILOG)/rtl/i2cm/src/core/i2cm_byte_ctrl.v +#-v $(USER_PROJECT_VERILOG)/rtl/i2cm/src/core/i2cm_top.v +#-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_core.sv +#-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_crc16.sv +#-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_crc5.sv +#-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_fifo.sv +#-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_sie.sv +#-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/phy/usb_fs_phy.v +#-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/phy/usb_transceiver.v +#-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/top/usb1_host.sv +#-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_top.sv +#-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_ctl.sv +#-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_if.sv +#-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_cfg.sv +#-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_clkgen.sv +#-v $(USER_PROJECT_VERILOG)/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv +#else +$(USER_PROJECT_VERILOG)/gl/uart_i2c_usb_spi_top.v +#endif + +################################################## +### WISHBONE INTERCONNECT +################################################## +#ifdef WB_INTER_RTL +#-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_slave_port.sv +#-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_interconnect.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_wbb.sv +#else +$(USER_PROJECT_VERILOG)/gl/wb_interconnect.v +#endif + +#-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_arb.sv +#-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_txfsm.sv +#-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_rxfsm.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_sram_mux.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/primitives/ycr_reset_cells.sv +#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_req_retiming.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_wbb.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_fifo2.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/async_fifo_th.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_skew_adjust.gv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/reset_sync.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/ctech_cells.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/async_fifo.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/async_wb.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/async_reg_bus.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_ctl.v +#-v $(USER_PROJECT_VERILOG)/rtl/lib/registers.v +#-v $(USER_PROJECT_VERILOG)/rtl/lib/double_sync_low.v +#-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type1.sv +#-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type2.sv + +$(USER_PROJECT_VERILOG)/gl/aes_top.v +$(USER_PROJECT_VERILOG)/gl/fpu_wrapper.v +$(USER_PROJECT_VERILOG)/gl/bus_rep_south.v +$(USER_PROJECT_VERILOG)/gl/bus_rep_north.v +$(USER_PROJECT_VERILOG)/gl/bus_rep_east.v +$(USER_PROJECT_VERILOG)/gl/bus_rep_west.v +$(USER_PROJECT_VERILOG)/gl/peri_top.v + +-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/dg_pll.v + +-v $(USER_PROJECT_VERILOG)/rtl/dac/src/dac_top.v
diff --git a/verilog/includes/includes.gl.lib b/verilog/includes/includes.gl.lib new file mode 100644 index 0000000..a047636 --- /dev/null +++ b/verilog/includes/includes.gl.lib
@@ -0,0 +1,13 @@ +########################################################### +# STD CELLS - they need to be below the defines.v files +########################################################### +-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v +-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v +-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog/primitives.v +-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v +-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v +-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v + +#$(USER_PROJECT_VERILOG)/gl/digital_pll.v +-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/digital_pll_controller.v +-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/ring_osc2x13.v
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project new file mode 100644 index 0000000..2f21e49 --- /dev/null +++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -0,0 +1,94 @@ +# Caravel user project includes ++incdir+$(USER_PROJECT_VERILOG)/rtl/ ++incdir+$(USER_PROJECT_VERILOG)/dv/common/bfm ++incdir+$(USER_PROJECT_VERILOG)/dv/common/model ++incdir+$(USER_PROJECT_VERILOG)/dv/common/agents +$(USER_PROJECT_VERILOG)/rtl/user_reg_map.v + +#MBIST Wrapper ++incdir+$(USER_PROJECT_VERILOG)/rtl/mbist/include/ +$(USER_PROJECT_VERILOG)/rtl/mbist_wrapper/src/mbist_wrapper.sv +$(USER_PROJECT_VERILOG)/rtl/mbist_wrapper/src/mbist_wb.sv + +## MBIST CORE +$(USER_PROJECT_VERILOG)/rtl/mbist/src/top/mbist_top.sv +$(USER_PROJECT_VERILOG)/rtl/mbist/src/core/mbist_sti_sel.sv +$(USER_PROJECT_VERILOG)/rtl/mbist/src/core/mbist_pat_sel.sv +$(USER_PROJECT_VERILOG)/rtl/mbist/src/core/mbist_op_sel.sv +$(USER_PROJECT_VERILOG)/rtl/mbist/src/core/mbist_fsm.sv +$(USER_PROJECT_VERILOG)/rtl/mbist/src/core/mbist_data_cmp.sv +$(USER_PROJECT_VERILOG)/rtl/mbist/src/core/mbist_repair_addr.sv +$(USER_PROJECT_VERILOG)/rtl/mbist/src/core/mbist_mux.sv +$(USER_PROJECT_VERILOG)/rtl/mbist/src/core/mbist_mem_wrapper.sv +$(USER_PROJECT_VERILOG)/rtl/mbist/src/core/mbist_addr_gen.sv + +## WB Inter connect +$(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_interconnect.sv +$(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_slave_port.sv + +## WB HOST +$(USER_PROJECT_VERILOG)/rtl/wb_host/src/wb_host.sv + +## LBIST +$(USER_PROJECT_VERILOG)/rtl/lbist/src/lbist_top.sv +$(USER_PROJECT_VERILOG)/rtl/lbist/src/lbist_core.sv +$(USER_PROJECT_VERILOG)/rtl/lbist/src/lbist_reg.sv + +## UART MASTER +$(USER_PROJECT_VERILOG)/rtl/uart/src/uart_txfsm.sv +$(USER_PROJECT_VERILOG)/rtl/uart/src/uart_rxfsm.sv +$(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2wb.sv +$(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2_core.sv +$(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart_msg_handler.v + + +## Pinmux reg +$(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux_top.sv +$(USER_PROJECT_VERILOG)/rtl/glbl/src/glbl_cfg.sv + +### GMAC Block +$(USER_PROJECT_VERILOG)/rtl/mac_wrapper/src/mac_wrapper.sv +$(USER_PROJECT_VERILOG)/rtl/gmac/top/g_mac_top.v +$(USER_PROJECT_VERILOG)/rtl/gmac/mac/g_rx_top.v +$(USER_PROJECT_VERILOG)/rtl/gmac/mac/g_deferral_rx.v +$(USER_PROJECT_VERILOG)/rtl/gmac/mac/g_cfg_mgmt.v +$(USER_PROJECT_VERILOG)/rtl/gmac/mac/dble_reg.v +$(USER_PROJECT_VERILOG)/rtl/gmac/mac/s2f_sync.v +$(USER_PROJECT_VERILOG)/rtl/gmac/mac/g_rx_fsm.v +$(USER_PROJECT_VERILOG)/rtl/gmac/mac/g_mac_core.v +$(USER_PROJECT_VERILOG)/rtl/gmac/mac/byte_reg.v +$(USER_PROJECT_VERILOG)/rtl/gmac/mac/g_tx_top.v +$(USER_PROJECT_VERILOG)/rtl/gmac/mac/g_tx_fsm.v +$(USER_PROJECT_VERILOG)/rtl/gmac/mac/g_mii_intf.v +$(USER_PROJECT_VERILOG)/rtl/gmac/mac/g_md_intf.v +$(USER_PROJECT_VERILOG)/rtl/gmac/mac/g_deferral.v +$(USER_PROJECT_VERILOG)/rtl/gmac/ctrl/eth_parser.v +$(USER_PROJECT_VERILOG)/rtl/gmac/crc32/g_rx_crc32.v +$(USER_PROJECT_VERILOG)/rtl/gmac/crc32/g_tx_crc32.v + +#COMMON FILES +$(USER_PROJECT_VERILOG)/rtl/lib/clk_skew_adjust.gv +$(USER_PROJECT_VERILOG)/rtl/lib/ctech_cells.sv +$(USER_PROJECT_VERILOG)/rtl/lib/reset_sync.sv +$(USER_PROJECT_VERILOG)/rtl/lib/ser_shift.sv +$(USER_PROJECT_VERILOG)/rtl/lib/wb_stagging.sv +$(USER_PROJECT_VERILOG)/rtl/lib/async_fifo.sv +$(USER_PROJECT_VERILOG)/rtl/lib/async_wb.sv +$(USER_PROJECT_VERILOG)/rtl/lib/clk_ctl.v +$(USER_PROJECT_VERILOG)/rtl/lib/registers.v +$(USER_PROJECT_VERILOG)/rtl/lib/async_reg_bus.sv +$(USER_PROJECT_VERILOG)/rtl/lib/clk_gate.sv +$(USER_PROJECT_VERILOG)/rtl/lib/crc_32.sv +$(USER_PROJECT_VERILOG)/rtl/lib/double_sync_low.v +$(USER_PROJECT_VERILOG)/rtl/lib/wb_arb.sv +$(USER_PROJECT_VERILOG)/rtl/lib/ser_inf_32b.sv +$(USER_PROJECT_VERILOG)/rtl/lib/ser_rd_inf_64b.sv +$(USER_PROJECT_VERILOG)/rtl/lib/stat_counter.v +$(USER_PROJECT_VERILOG)/rtl/lib/toggle_sync.v +$(USER_PROJECT_VERILOG)/rtl/lib/wb_rd_mem2mem.v +$(USER_PROJECT_VERILOG)/rtl/lib/wb_wr_mem2mem.v +$(USER_PROJECT_VERILOG)/rtl/lib/g_dpath_ctrl.v +$(USER_PROJECT_VERILOG)/rtl/lib/sync_wbb.sv +$(USER_PROJECT_VERILOG)/rtl/lib/sync_fifo2.sv + +$(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
diff --git a/verilog/includes/includes.rtl.lib b/verilog/includes/includes.rtl.lib new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/verilog/includes/includes.rtl.lib
diff --git a/verilog/rtl/digital_core.v b/verilog/rtl/digital_core.v deleted file mode 100644 index c57d82c..0000000 --- a/verilog/rtl/digital_core.v +++ /dev/null
@@ -1,738 +0,0 @@ - -`include "top_defines.v" -module digital_core ( - - reset_n , - scan_mode , - scan_enable , - fastsim_mode , - mastermode , - xtal_clk , - clkout , - reset_out_n , - - // Reg Bus Interface Signal - ext_reg_cs , - ext_reg_tid , - ext_reg_wr , - ext_reg_addr , - ext_reg_wdata , - ext_reg_be , - - // Outputs - ext_reg_rdata , - ext_reg_ack , - - - // Line Side Interface TX Path - phy_tx_en , - phy_txd , - phy_tx_clk , - - // Line Side Interface RX Path - phy_rx_clk , - phy_rx_dv , - phy_rxd , - - //MDIO interface - mdio_clk , - mdio_in , - mdio_out , - mdio_out_en , - - - // UART Line Interface - si , - so , - - - spi_sck , - spi_so , - spi_si , - spi_cs_n , - - - // External ROM interface - wb_xrom_adr , - wb_xrom_ack , - wb_xrom_err , - wb_xrom_wr , - wb_xrom_rdata , - wb_xrom_wdata , - - wb_xrom_stb , - wb_xrom_cyc , - - // External RAM interface - wb_xram_adr , - wb_xram_ack , - wb_xram_err , - wb_xram_wr , - wb_xram_be , - wb_xram_rdata , - wb_xram_wdata , - - wb_xram_stb , - wb_xram_cyc, - - ea_in - - - - ); - - -//---------------------------------------- -// Global Clock Defination -//---------------------------------------- -input reset_n ; // Active Low Reset -input scan_mode ; // scan mode -input scan_enable ; // scan enable -input fastsim_mode ; // Fast Sim Mode -input mastermode ; // 1 : Risc master mode - -input xtal_clk ; // xtal clock 25Mhz -output clkout ; // clock output -output reset_out_n ; // clock output - -//--------------------------------- -// Reg Bus Interface Signal -//--------------------------------- -input ext_reg_cs ; -input ext_reg_wr ; -input [3:0] ext_reg_tid ; -input [14:0] ext_reg_addr ; -input [31:0] ext_reg_wdata ; -input [3:0] ext_reg_be ; - -// Outputs -output [31:0] ext_reg_rdata ; -output ext_reg_ack ; - -//---------------------------------------- -// MAC Line Side Interface TX Path -//---------------------------------------- -output phy_tx_en ; // MAC Tx Enable -output [7:0] phy_txd ; // MAC Tx Data -input phy_tx_clk ; // MAC Tx Clock - -//---------------------------------------- -// MAC Line Side Interface RX Path -//---------------------------------------- -input phy_rx_clk ; // MAC Rx Clock -input phy_rx_dv ; // MAC Rx Dv -input [7:0] phy_rxd ; // MAC Rxd - -//---------------------------------------- -// MDIO interface -//---------------------------------------- -output mdio_clk ; // MDIO Clock -input mdio_in ; // MDIO Data -output mdio_out ; // MDIO Data -output mdio_out_en ; // MDIO Data - - -//---------------------------------------- -// UART Line Interface -//---------------------------------------- -input si ; // serial in -output so ; // serial out - -//---------------------------------------- -// SPI Line Interface -//---------------------------------------- - -output spi_sck ; // clock -output spi_so ; // data out -input spi_si ; // data in -output [3:0] spi_cs_n ; // chip select - -//---------------------------------------- -// 8051 core ROM related signals -//--------------------------------------- -output [15:0] wb_xrom_adr ; // instruction address -input wb_xrom_ack ; // instruction acknowlage -output wb_xrom_err ; // instruction error -output wb_xrom_wr ; // instruction error -input [31:0] wb_xrom_rdata ; // rom data input -output [31:0] wb_xrom_wdata ; // rom data input - -output wb_xrom_stb ; // instruction strobe -output wb_xrom_cyc ; // instruction cycle - - -//---------------------------------------- -// 8051 core RAM related signals -//--------------------------------------- -output [15:0] wb_xram_adr ; // data-ram address -input wb_xram_ack ; // data-ram acknowlage -output wb_xram_err ; // data-ram error -output wb_xram_wr ; // data-ram error -output [3:0] wb_xram_be ; // Byte enable -input [31:0] wb_xram_rdata ; // ram data input -output [31:0] wb_xram_wdata ; // ram data input - -output wb_xram_stb ; // data-ram strobe -output wb_xram_cyc ; // data-ram cycle - - -input ea_in ; // input for external access (ea signal) - // ea=0 program is in external rom - // ea=1 program is in internal rom -//--------------------------------------------- -// 8051 Instruction ROM interface -//--------------------------------------------- -wire [15:0] wbi_risc_adr; -wire [31:0] wbi_risc_rdata; - - -//----------------------------- -// MAC Related wire Decleration -//----------------------------- -wire [8:0] app_rxfifo_rddata_o ; -wire [31:0] app_rx_desc_data ; -wire mdio_out_en ; -wire mdio_out ; -wire gen_resetn ; - - -//--------------------------------------------- -// 8051 Instruction RAM interface -//--------------------------------------------- -wire [15:0] wbd_risc_adr ; -wire [7:0] wbd_risc_rdata ; -wire [7:0] wbd_risc_wdata ; - -wire [14:0] reg_mac_addr ; -wire [31:0] reg_mac_wdata ; -wire [3:0] reg_mac_be ; -wire [31:0] reg_mac_rdata ; -wire reg_mac_ack ; - -wire [14:0] reg_uart_addr ; -wire [31:0] reg_uart_wdata ; -wire [3:0] reg_uart_be ; -wire [31:0] reg_uart_rdata ; -wire reg_uart_ack ; - -wire [14:0] reg_spi_addr ; -wire [31:0] reg_spi_wdata ; -wire [3:0] reg_spi_be ; -wire [31:0] reg_spi_rdata ; -wire reg_spi_ack ; - -wire [3:0] wb_xrom_be ; -wire [3:0] wb_xram_be ; - -wire [7:0] p0 ; -wire [7:0] p1 ; -wire [7:0] p2 ; -wire [7:0] p3 ; - -wire [3:0] wbgt_taddr ; -wire [31:0] wbgt_din ; -wire [31:0] wbgt_dout ; -wire [12:0] wbgt_addr ; -wire [3:0] wbgt_be ; -wire wbgt_we ; -wire wbgt_ack ; -wire wbgt_stb ; -wire wbgt_cyc ; - -wire [3:0] wbgr_taddr ; -wire [31:0] wbgr_din ; -wire [31:0] wbgr_dout ; -wire [12:0] wbgr_addr ; -wire [3:0] wbgr_be ; -wire wbgr_we ; -wire wbgr_ack ; -wire wbgr_stb ; -wire wbgr_cyc ; - -wire [8:0] app_txfifo_wrdata_i; -wire [15:0] app_txfifo_addr; -wire [15:0] app_rxfifo_addr; -wire [3:0] tx_qcnt ; -wire [3:0] rx_qcnt ; - -wire tx_q_empty = (tx_qcnt == 0); -wire rx_q_empty = (rx_qcnt == 0); - -wire [31:0] reg_rdata = (reg_mac_ack) ? reg_mac_rdata : - (reg_uart_ack) ? reg_uart_rdata : - (reg_spi_ack) ? reg_spi_rdata : 'h0; - -wire reg_ack = reg_mac_ack | reg_uart_ack | reg_spi_ack; - - -assign reset_out_n = gen_resetn; - - -assign wb_xram_adr[15] = 0; -assign wb_xram_adr[1:0] = 2'b00; -assign wb_xrom_adr[15:13] = 0; - -wire [9:0] cfg_tx_buf_qbase_addr; -wire [9:0] cfg_rx_buf_qbase_addr; - -// QCounter Inc/dec generation - -wire tx_qcnt_inc = (cfg_tx_buf_qbase_addr == wb_xram_adr[15:6]) & wb_xram_stb & wb_xram_wr & wb_xram_ack && (wb_xram_be[3] == 1'b1); -wire tx_qcnt_dec = (cfg_tx_buf_qbase_addr == wb_xram_adr[15:6]) & wb_xram_stb & !wb_xram_wr & wb_xram_ack && (wb_xram_be[3] == 1'b1); -wire rx_qcnt_inc = (cfg_rx_buf_qbase_addr == wb_xram_adr[15:6]) & wb_xram_stb & wb_xram_wr & wb_xram_ack && (wb_xram_be[3] == 1'b1); -wire rx_qcnt_dec = (cfg_rx_buf_qbase_addr == wb_xram_adr[15:6]) & wb_xram_stb & !wb_xram_wr & wb_xram_ack && (wb_xram_be[3] == 1'b1); - -assign reg_mac_addr[1:0] = 2'b0; -assign reg_uart_addr[1:0] = 2'b0; -assign reg_spi_addr[1:0] = 2'b0; -//------------------------------------------- -// clock-gen instantiation -//------------------------------------------- -clkgen u_clkgen ( - . reset_n (reset_n ), - . fastsim_mode (fastsim_mode ), - . mastermode (mastermode ), - . xtal_clk (xtal_clk ), - . clkout (clkout ), - . gen_resetn (gen_resetn ), - . risc_reset (risc_reset ), - . app_clk (app_clk ), - . uart_ref_clk (uart_clk_16x ) - - ); - -//-------------------------------------------------------------- -// Target ID Mapping -// 4'b0100 -- MAC core -// 4'b0011 -- UART -// 4'b0010 -- SPI core -// 4'b0001 -- External RAM -// 4'b0000 -- External ROM -//-------------------------------------------------------------- - - -wire [31:0] wb_master2_rdata; - -wire [3:0] wb_master2_be = (wbd_risc_adr[1:0] == 2'b00) ? 4'b0001: - (wbd_risc_adr[1:0] == 2'b01) ? 4'b0010: - (wbd_risc_adr[1:0] == 2'b10) ? 4'b0100: 4'b1000; - -assign wbd_risc_rdata = (wbd_risc_adr[1:0] == 2'b00) ? wb_master2_rdata[7:0]: - (wbd_risc_adr[1:0] == 2'b01) ? wb_master2_rdata[15:8]: - (wbd_risc_adr[1:0] == 2'b10) ? wb_master2_rdata[23:16]: - wb_master2_rdata[31:24]; - -//------------------------------ -// RISC Data Memory Map -// 0x0000 to 0x7FFFF - Data Memory -// 0x8000 to 0x8FFF - SPI -// 0x9000 to 0x9FFF - UART -// 0xA000 to 0xAFFF - MAC Core -//----------------------------- -// -wire [3:0] wbd_tar_id = (wbd_risc_adr[15] == 1'b0 ) ? 4'b0001 : - (wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0010 : - (wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0011 : 4'b0100; - -wb_crossbar #(5,5,32,4,13,4) u_wb_crossbar ( - - .rst_n (gen_resetn ), - .clk (app_clk ), - - - // Master Interface Signal - .wbd_taddr_master ({4'b0000, - wbd_tar_id, - ext_reg_tid, - wbgt_taddr, - wbgr_taddr}), - .wbd_din_master ({32'h0 , - {wbd_risc_wdata[7:0], - wbd_risc_wdata[7:0], - wbd_risc_wdata[7:0], - wbd_risc_wdata[7:0]}, - ext_reg_wdata, - wbgt_din, - wbgr_din} - ), - .wbd_dout_master ({wbi_risc_rdata, - wb_master2_rdata, - ext_reg_rdata, - wbgt_dout, - wbgr_dout} - ), - .wbd_adr_master ({wbi_risc_adr[12:0], - wbd_risc_adr[14:2], - ext_reg_addr[14:2], - wbgt_addr, - wbgr_addr} - ), - .wbd_be_master ({4'b1111, - wb_master2_be, - ext_reg_be, - wbgt_be, - wbgr_be} - ), - .wbd_we_master ({1'b0,wbd_risc_we,ext_reg_wr, - wbgt_we,wbgr_we} ), - .wbd_ack_master ({wbi_risc_ack, - wbd_risc_ack, - ext_reg_ack, - wbgt_ack, - wbgr_ack} ), - .wbd_stb_master ({wbi_risc_stb, - wbd_risc_stb, - ext_reg_cs, - wbgt_stb, - wbgr_stb} ), - .wbd_cyc_master ({wbi_risc_stb|wbi_risc_ack, - wbd_risc_stb|wbd_risc_ack, - ext_reg_cs|ext_reg_ack, - wbgt_cyc,wbgr_cyc}), - .wbd_err_master (), - .wbd_rty_master (), - - // Slave Interface Signal - .wbd_din_slave ({ - reg_mac_wdata, - reg_uart_wdata, - reg_spi_wdata, - wb_xram_wdata, - wb_xrom_wdata - }), - .wbd_dout_slave ({ - reg_mac_rdata, - reg_uart_rdata, - reg_spi_rdata, - {wb_xram_rdata}, - wb_xrom_rdata - }), - .wbd_adr_slave ({reg_mac_addr[14:2], - reg_uart_addr[14:2], - reg_spi_addr[14:2], - wb_xram_adr[14:2], - wb_xrom_adr[12:0]} - ), - .wbd_be_slave ({reg_mac_be, - reg_uart_be, - reg_spi_be, - wb_xram_be, - wb_xrom_be} - ), - .wbd_we_slave ({reg_mac_wr, - reg_uart_wr, - reg_spi_wr, - wb_xram_wr, - wb_xrom_wr - }), - .wbd_ack_slave ({reg_mac_ack, - reg_uart_ack, - reg_spi_ack, - wb_xram_ack, - wb_xrom_ack - }), - .wbd_stb_slave ({reg_mac_cs, - reg_uart_cs, - reg_spi_cs, - wb_xram_stb, - wb_xrom_stb - }), - .wbd_cyc_slave (), - .wbd_err_slave (), - .wbd_rty_slave () - ); - - -//------------------------------------------- -// GMAC core instantiation -//------------------------------------------- - -g_mac_top u_eth_dut ( - - .scan_mode (1'b0 ), - .s_reset_n (gen_resetn ), - .tx_reset_n (gen_resetn ), - .rx_reset_n (gen_resetn ), - .reset_mdio_clk_n (gen_resetn ), - .app_reset_n (gen_resetn ), - - // Reg Bus Interface Signal - . reg_cs (reg_mac_cs ), - . reg_wr (reg_mac_wr ), - . reg_addr (reg_mac_addr[5:2] ), - . reg_wdata (reg_mac_wdata ), - . reg_be (reg_mac_be ), - - // Outputs - . reg_rdata (reg_mac_rdata ), - . reg_ack (reg_mac_ack ), - - - .app_clk (app_clk ), - - // Application RX FIFO Interface - .app_txfifo_wren_i (app_txfifo_wren_i ), - .app_txfifo_wrdata_i (app_txfifo_wrdata_i ), - .app_txfifo_addr (app_txfifo_addr ), - .app_txfifo_full_o (app_txfifo_full_o ), - .app_txfifo_afull_o (app_txfifo_afull_o ), - .app_txfifo_space_o ( ), - - // Application TX FIFO Interface - .app_rxfifo_rden_i (app_rxfifo_rden_i ), - .app_rxfifo_empty_o (app_rxfifo_empty_o ), - .app_rxfifo_aempty_o (app_rxfifo_aempty_o ), - .app_rxfifo_cnt_o ( ), - .app_rxfifo_rdata_o (app_rxfifo_rddata_o ), - .app_rxfifo_addr (app_rxfifo_addr ), - - .app_rx_desc_req (app_rx_desc_req ), - .app_rx_desc_ack (app_rx_desc_ack ), - .app_rx_desc_discard (app_rx_desc_discard ), - .app_rx_desc_data (app_rx_desc_data ), - - // Line Side Interface TX Path - .phy_tx_en (phy_tx_en ), - .phy_tx_er ( ), - .phy_txd (phy_txd ), - .phy_tx_clk (phy_tx_clk ), - - // Line Side Interface RX Path - .phy_rx_clk (phy_rx_clk ), - .phy_rx_er (1'b0 ), - .phy_rx_dv (phy_rx_dv ), - .phy_rxd (phy_rxd ), - .phy_crs (1'b0 ), - - //MDIO interface - .mdio_clk (mdio_clk ), - .mdio_in (mdio_in ), - .mdio_out_en (mdio_out_en ), - .mdio_out (mdio_out ), - - // QCounter - .rx_buf_qbase_addr (cfg_rx_buf_qbase_addr), - .tx_buf_qbase_addr (cfg_tx_buf_qbase_addr), - - .tx_qcnt_inc (tx_qcnt_inc), - .tx_qcnt_dec (tx_qcnt_dec), - .rx_qcnt_inc (rx_qcnt_inc), - .rx_qcnt_dec (rx_qcnt_dec), - .tx_qcnt (tx_qcnt), - .rx_qcnt (rx_qcnt) - - - ); - - - - - -wb_rd_mem2mem #(.D_WD(32),.BE_WD(4),.ADR_WD(13),.TAR_WD(4)) u_wb_gmac_tx ( - - .rst_n ( gen_resetn ), - .clk ( app_clk ), - - // descriptor handshake - .cfg_desc_baddr (cfg_tx_buf_qbase_addr), - .desc_q_empty (tx_q_empty ), - - // Master Interface Signal - .mem_taddr ( 4'h1 ), - .mem_full (app_txfifo_full_o ), - .mem_afull (app_txfifo_afull_o ), - .mem_wr (app_txfifo_wren_i ), - .mem_din (app_txfifo_wrdata_i ), - - // Slave Interface Signal - .wbo_dout ( wbgt_dout ), - .wbo_taddr ( wbgt_taddr ), - .wbo_addr ( wbgt_addr ), - .wbo_be ( wbgt_be ), - .wbo_we ( wbgt_we ), - .wbo_ack ( wbgt_ack ), - .wbo_stb ( wbgt_stb ), - .wbo_cyc ( wbgt_cyc ), - .wbo_err ( wbgt_err ), - .wbo_rty ( wbgt_rty ) - ); - - -wb_wr_mem2mem #(.D_WD(32),.BE_WD(4),.ADR_WD(13),.TAR_WD(4)) u_wb_gmac_rx( - - .rst_n ( gen_resetn ), - .clk ( app_clk ), - - - // Master Interface Signal - .mem_taddr ( 4'h1 ), - .mem_addr (app_rxfifo_addr ), - .mem_empty (app_rxfifo_empty_o ), - .mem_aempty (app_rxfifo_aempty_o ), - .mem_rd (app_rxfifo_rden_i ), - .mem_dout (app_rxfifo_rddata_o[7:0]), - .mem_eop (app_rxfifo_rddata_o[8]), - - .cfg_desc_baddr (cfg_rx_buf_qbase_addr ), - .desc_req (app_rx_desc_req ), - .desc_ack (app_rx_desc_ack ), - .desc_disccard (app_rx_desc_discard ), - .desc_data (app_rx_desc_data ), - // Slave Interface Signal - .wbo_din ( wbgr_din ), - .wbo_taddr ( wbgr_taddr ), - .wbo_addr ( wbgr_addr ), - .wbo_be ( wbgr_be ), - .wbo_we ( wbgr_we ), - .wbo_ack ( wbgr_ack ), - .wbo_stb ( wbgr_stb ), - .wbo_cyc ( wbgr_cyc ), - .wbo_err ( wbgr_err ), - .wbo_rty ( wbgr_rty ) - ); - -//------------------------------------- -// UART core instantiation -//------------------------------------- - -uart_core u_uart_core - - ( - . line_reset_n (gen_resetn ), - . line_clk_16x (uart_clk_16x ), - - . app_reset_n (gen_resetn ), - . app_clk (app_clk ), - - - // Reg Bus Interface Signal - . reg_cs (reg_uart_cs ), - . reg_wr (reg_uart_wr ), - . reg_addr (reg_uart_addr[5:2] ), - . reg_wdata (reg_uart_wdata ), - . reg_be (reg_uart_be ), - - // Outputs - . reg_rdata (reg_uart_rdata ), - . reg_ack (reg_uart_ack ), - - - - // Line Interface - . si (si ), - . so (so ) - - ); - - -//-------------------------------- -// SPI core instantiation -//-------------------------------- - - -spi_core u_spi_core ( - - . clk (app_clk ), - . reset_n (gen_resetn ), - - // Reg Bus Interface Signal - . reg_cs (reg_spi_cs ), - . reg_wr (reg_spi_wr ), - . reg_addr (reg_spi_addr[5:2] ), - . reg_wdata (reg_spi_wdata ), - . reg_be (reg_spi_be ), - - // Outputs - . reg_rdata (reg_spi_rdata ), - . reg_ack (reg_spi_ack ), - - - . sck (spi_sck ), - . so (spi_so ), - . si (spi_si ), - . cs_n (spi_cs_n ) - - ); - - - -oc8051_top u_8051_core ( - . wb_rst_i (risc_reset ), - . wb_clk_i (app_clk ), - -//interface to instruction rom - . wbi_adr_o (wbi_risc_adr ), - . wbi_dat_i (wbi_risc_rdata ), - . wbi_stb_o (wbi_risc_stb ), - . wbi_ack_i (wbi_risc_ack ), - . wbi_cyc_o (wbi_risc_cyc ), - . wbi_err_i (wbi_risc_err ), - -//interface to data ram - . wbd_dat_i (wbd_risc_rdata ), - . wbd_dat_o (wbd_risc_wdata ), - . wbd_adr_o (wbd_risc_adr ), - . wbd_we_o (wbd_risc_we ), - . wbd_ack_i (wbd_risc_ack ), - . wbd_stb_o (wbd_risc_stb ), - . wbd_cyc_o (wbd_risc_cyc ), - . wbd_err_i (wbd_risc_err ), - -// interrupt interface - . int0_i ( ), - . int1_i ( ), - - -// port interface - `ifdef OC8051_PORTS - `ifdef OC8051_PORT0 - .p0_i ( p0 ), - .p0_o ( p0 ), - `endif - - `ifdef OC8051_PORT1 - .p1_i ( p1 ), - .p1_o ( p1 ), - `endif - - `ifdef OC8051_PORT2 - .p2_i ( p2 ), - .p2_o ( p2 ), - `endif - - `ifdef OC8051_PORT3 - .p3_i ( p3 ), - .p3_o ( p3 ), - `endif - `endif - -// serial interface - `ifdef OC8051_UART - .rxd_i ( ), - .txd_o ( ), - `endif - -// counter interface - `ifdef OC8051_TC01 - .t0_i ( ), - .t1_i ( ), - `endif - - `ifdef OC8051_TC2 - .t2_i ( ), - .t2ex_i ( ), - `endif - -// BIST -`ifdef OC8051_BIST - .scanb_rst ( ), - .scanb_clk ( ), - .scanb_si ( ), - .scanb_so ( ), - .scanb_en ( ), -`endif -// external access (active low) - .ea_in (ea_in ) - ); - -endmodule
diff --git a/verilog/rtl/glbl/src/glbl_cfg.sv b/verilog/rtl/glbl/src/glbl_cfg.sv index 6ce06a1..7ac4a7c 100644 --- a/verilog/rtl/glbl/src/glbl_cfg.sv +++ b/verilog/rtl/glbl/src/glbl_cfg.sv
@@ -64,8 +64,7 @@ //// //// ////////////////////////////////////////////////////////////////////// -module glbl_cfg #(parameter SCW = 8 // SCAN CHAIN WIDTH - ) ( +module glbl_cfg ( `ifdef USE_POWER_PINS inout vccd1, // User area 1 1.8V supply @@ -75,20 +74,6 @@ input logic mclk, input logic reset_n, - // Scan I/F - input logic scan_en, - input logic scan_mode, - input logic [SCW-1:0] scan_si, - output logic [SCW-1:0] scan_so, - output logic scan_en_o, - output logic scan_mode_o, - - // Clock Skew Adjust - input logic wbd_clk_int , - input logic [3:0] cfg_cska_glbl , - output logic wbd_clk_glbl , // clock skew adjust for web host - - // Reg Bus Interface Signal input logic reg_cs, input logic reg_wr, @@ -100,26 +85,23 @@ output logic [31:0] reg_rdata, output logic reg_ack, - // BIST I/F - output logic [7:0] bist_en, - output logic [7:0] bist_run, - output logic [7:0] bist_load, + // BIST I/F + output logic bist_en, + output logic bist_run, + output logic bist_load, - output logic [7:0] bist_sdi, - output logic [7:0] bist_shift, - input logic [7:0] bist_sdo, + output logic [1:0] bist_serial_sel, + output logic bist_sdi, + output logic bist_shift, + input logic bist_sdo, - input logic [7:0] bist_done, - input logic [7:0] bist_error, - input logic [7:0] bist_correct, - input logic [3:0] bist_error_cnt0, - input logic [3:0] bist_error_cnt1, - input logic [3:0] bist_error_cnt2, - input logic [3:0] bist_error_cnt3, - input logic [3:0] bist_error_cnt4, - input logic [3:0] bist_error_cnt5, - input logic [3:0] bist_error_cnt6, - input logic [3:0] bist_error_cnt7 + input logic bist_done, + input logic [3:0] bist_error, + input logic [3:0] bist_correct, + input logic [3:0] bist_error_cnt0, + input logic [3:0] bist_error_cnt1, + input logic [3:0] bist_error_cnt2, + input logic [3:0] bist_error_cnt3 ); @@ -143,7 +125,7 @@ logic [31:0] cfg_bist_ctrl_2; // BIST control logic [31:0] cfg_bist_status_1; // BIST Status logic [31:0] cfg_bist_status_2; // BIST Status -logic [31:0] serail_dout; // BIST Serial Signature +logic [63:0] serail_dout; // BIST Serial Signature logic [31:0] reg_9; // Software_Reg 9 logic [31:0] reg_10; // Software Reg 10 logic [31:0] reg_11; // Software Reg 11 @@ -155,20 +137,6 @@ //----------------------------------------------------------------------- -assign scan_en_o = scan_en; -assign scan_mode_o = scan_mode; - -// wb_host clock skew control -clk_skew_adjust u_skew_glbl - ( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif - .clk_in (wbd_clk_int ), - .sel (cfg_cska_glbl ), - .clk_out (wbd_clk_glbl ) - ); //----------------------------------------------------------------------- // register read enable and write enable decoding logic @@ -232,7 +200,7 @@ reg_rdata <= 'h0; reg_ack <= 1'b0; end else if (ser_acc && serial_ack) begin - reg_rdata <= serail_dout ; + reg_rdata <= reg_out ; reg_ack <= 1'b1; end else if (non_ser_acc && !reg_ack) begin reg_rdata <= reg_out ; @@ -254,8 +222,8 @@ 4'b0100 : reg_out [31:0] = cfg_bist_status_1 [31:0]; 4'b0101 : reg_out [31:0] = cfg_bist_status_2 [31:0]; 4'b0110 : reg_out [31:0] = 'h0; // Serial Write Data - 4'b0111 : reg_out [31:0] = serail_dout; // This is with Shift - 4'b1000 : reg_out [31:0] = serail_dout; // This is previous Shift + 4'b0111 : reg_out [31:0] = serail_dout[31:0]; // Lower Shift + 4'b1000 : reg_out [31:0] = serail_dout[63:32]; // Upper Shift 4'b1001 : reg_out [31:0] = reg_9; // Software Reg1 4'b1010 : reg_out [31:0] = reg_10; // Software Reg2 4'b1011 : reg_out [31:0] = reg_11; // Software Reg3 @@ -374,42 +342,15 @@ ); -wire [3:0] bist_serial_sel = cfg_bist_ctrl_1[3:0]; +assign bist_serial_sel = cfg_bist_ctrl_1[1:0]; //----------------------------------------------------------------------- // reg-3 // ----------------------------------------------------------------- // Bist control -assign bist_en[0] = cfg_bist_ctrl_2[0]; -assign bist_run[0] = cfg_bist_ctrl_2[1]; -assign bist_load[0] = cfg_bist_ctrl_2[2]; +assign bist_en = cfg_bist_ctrl_2[0]; +assign bist_run = cfg_bist_ctrl_2[1]; +assign bist_load = cfg_bist_ctrl_2[2]; -assign bist_en[1] = cfg_bist_ctrl_2[4]; -assign bist_run[1] = cfg_bist_ctrl_2[5]; -assign bist_load[1] = cfg_bist_ctrl_2[6]; - -assign bist_en[2] = cfg_bist_ctrl_2[8]; -assign bist_run[2] = cfg_bist_ctrl_2[9]; -assign bist_load[2] = cfg_bist_ctrl_2[10]; - -assign bist_en[3] = cfg_bist_ctrl_2[12]; -assign bist_run[3] = cfg_bist_ctrl_2[13]; -assign bist_load[3] = cfg_bist_ctrl_2[14]; - -assign bist_en[4] = cfg_bist_ctrl_2[16]; -assign bist_run[4] = cfg_bist_ctrl_2[17]; -assign bist_load[4] = cfg_bist_ctrl_2[18]; - -assign bist_en[5] = cfg_bist_ctrl_2[20]; -assign bist_run[5] = cfg_bist_ctrl_2[21]; -assign bist_load[5] = cfg_bist_ctrl_2[22]; - -assign bist_en[6] = cfg_bist_ctrl_2[24]; -assign bist_run[6] = cfg_bist_ctrl_2[25]; -assign bist_load[6] = cfg_bist_ctrl_2[26]; - -assign bist_en[7] = cfg_bist_ctrl_2[28]; -assign bist_run[7] = cfg_bist_ctrl_2[29]; -assign bist_load[7] = cfg_bist_ctrl_2[30]; @@ -461,15 +402,11 @@ // reg-3 //----------------------------------------------------------------- -assign cfg_bist_status_2 = { bist_error_cnt7, 1'b0, bist_correct[7], bist_error[7], bist_done[7], - bist_error_cnt6, 1'b0, bist_correct[6], bist_error[6], bist_done[6], - bist_error_cnt5, 1'b0, bist_correct[5], bist_error[5], bist_done[5], - bist_error_cnt4, 1'b0, bist_correct[4], bist_error[4], bist_done[4] - }; -assign cfg_bist_status_1 = { bist_error_cnt3, 1'b0, bist_correct[3], bist_error[3], bist_done[3], - bist_error_cnt2, 1'b0, bist_correct[2], bist_error[2], bist_done[2], - bist_error_cnt1, 1'b0, bist_correct[1], bist_error[1], bist_done[1], - bist_error_cnt0, 1'b0, bist_correct[0], bist_error[0], bist_done[0] +assign cfg_bist_status_2 = 'h0; +assign cfg_bist_status_1 = { bist_error_cnt3, 1'b0, bist_correct[3], bist_error[3], bist_done, + bist_error_cnt2, 1'b0, bist_correct[2], bist_error[2], bist_done, + bist_error_cnt1, 1'b0, bist_correct[1], bist_error[1], bist_done, + bist_error_cnt0, 1'b0, bist_correct[0], bist_error[0], bist_done }; //----------------------------------------------------------------------- @@ -480,34 +417,11 @@ wire bist_shift_int; wire bist_sdo_int; -assign bist_sdo_int = (bist_serial_sel == 4'b0000) ? bist_sdo[0] : - (bist_serial_sel == 4'b0001) ? bist_sdo[1] : - (bist_serial_sel == 4'b0010) ? bist_sdo[2] : - (bist_serial_sel == 4'b0011) ? bist_sdo[3] : - (bist_serial_sel == 4'b0100) ? bist_sdo[4] : - (bist_serial_sel == 4'b0101) ? bist_sdo[5] : - (bist_serial_sel == 4'b0110) ? bist_sdo[6] : - (bist_serial_sel == 4'b0111) ? bist_sdo[7] : - 1'b0; +assign bist_sdo_int = bist_sdo; +assign bist_shift = bist_shift_int ; +assign bist_sdi = 1'b0 ; // Need fix - Dinesh A -assign bist_shift[0] = (bist_serial_sel == 4'b0000) ? bist_shift_int : 1'b0; -assign bist_shift[1] = (bist_serial_sel == 4'b0001) ? bist_shift_int : 1'b0; -assign bist_shift[2] = (bist_serial_sel == 4'b0010) ? bist_shift_int : 1'b0; -assign bist_shift[3] = (bist_serial_sel == 4'b0011) ? bist_shift_int : 1'b0; -assign bist_shift[4] = (bist_serial_sel == 4'b0100) ? bist_shift_int : 1'b0; -assign bist_shift[5] = (bist_serial_sel == 4'b0101) ? bist_shift_int : 1'b0; -assign bist_shift[6] = (bist_serial_sel == 4'b0110) ? bist_shift_int : 1'b0; -assign bist_shift[7] = (bist_serial_sel == 4'b0111) ? bist_shift_int : 1'b0; - -assign bist_sdi[0] = (bist_serial_sel == 4'b0000) ? bist_sdi_int : 1'b0; -assign bist_sdi[1] = (bist_serial_sel == 4'b0001) ? bist_sdi_int : 1'b0; -assign bist_sdi[2] = (bist_serial_sel == 4'b0010) ? bist_sdi_int : 1'b0; -assign bist_sdi[3] = (bist_serial_sel == 4'b0011) ? bist_sdi_int : 1'b0; -assign bist_sdi[4] = (bist_serial_sel == 4'b0100) ? bist_sdi_int : 1'b0; -assign bist_sdi[5] = (bist_serial_sel == 4'b0101) ? bist_sdi_int : 1'b0; -assign bist_sdi[6] = (bist_serial_sel == 4'b0110) ? bist_sdi_int : 1'b0; -assign bist_sdi[7] = (bist_serial_sel == 4'b0111) ? bist_sdi_int : 1'b0; - +/*** Need Fix for Serial Out ser_inf_32b u_ser_intf ( @@ -515,7 +429,7 @@ .rst_n (reset_n), // Regular Reset signal .clk (mclk), // System clock .reg_wr (sw_wr_en_6 & wb_req_pedge), // Write Request - .reg_rd (sw_rd_en_7 & wb_req_pedge), // Read Request + .reg_rd (1;b0), // Read Request .reg_wdata (reg_wdata) , // data output .reg_rdata (serail_dout), // data input .reg_ack (serial_ack), // acknowlegement @@ -526,7 +440,23 @@ .sdo (bist_sdo_int) // Serial SDO ); +****/ +ser_rd_inf_64b u_ser_intf + ( + + // Master Port + .rst_n (reset_n), // Regular Reset signal + .clk (mclk), // System clock + .reg_rd (sw_rd_en_7 & wb_req_pedge), // Read Request + .reg_rdata (serail_dout), // data input + .reg_ack (serial_ack), // acknowlegement + + // Slave Port + .shift (bist_shift_int), // Shift Signal + .sdo (bist_sdo_int) // Serial SDO + + ); //----------------------------------------- // Software Reg-1 : ASCI Representation of LBST = 32'h4C66_8354
diff --git a/verilog/rtl/lib/async_fifo.sv b/verilog/rtl/lib/async_fifo.sv index fd59cfa..239db2f 100755 --- a/verilog/rtl/lib/async_fifo.sv +++ b/verilog/rtl/lib/async_fifo.sv
@@ -56,7 +56,12 @@ *******************************************************************/ //------------------------------------------- -// async FIFO +// async_fifo:: async FIFO +// Following two ports are newly added +// 1. At write clock domain: +// wr_total_free_space --> Indicate total free transfer available +// 2. At read clock domain: +// rd_total_aval --> Indicate total no of transfer available //----------------------------------------------- //`timescale 1ns/1ps @@ -66,11 +71,13 @@ wr_data, full, // sync'ed to wr_clk afull, // sync'ed to wr_clk + wr_total_free_space, rd_clk, rd_reset_n, rd_en, empty, // sync'ed to rd_clk aempty, // sync'ed to rd_clk + rd_total_aval, rd_data); parameter W = 4'd8; @@ -94,9 +101,13 @@ input wr_clk, wr_reset_n, wr_en, rd_clk, rd_reset_n, rd_en; output full, empty; - output afull, aempty; // about full and about to empty - - + output afull, aempty; // about full and about to empty + output [AW:0] wr_total_free_space; // Total Number of free space aval + // w.r.t write clk + // note: Without accounting byte enables + output [AW:0] rd_total_aval; // Total Number of words avaialble + // w.r.t rd clock, + // note: Without accounting byte enables // synopsys translate_off initial begin @@ -123,6 +134,11 @@ assign full_c = (wr_cnt == FULL_DP) ? 1'b1 : 1'b0; assign afull_c = (wr_cnt == FULL_DP-1) ? 1'b1 : 1'b0; + //-------------------------- + // Shows total number of words + // of free space available w.r.t write clock + //--------------------------- + assign wr_total_free_space = FULL_DP - wr_cnt; always @(posedge wr_clk or negedge wr_reset_n) begin if (!wr_reset_n) begin @@ -154,7 +170,7 @@ end wire [AW:0] grey_rd_ptr_dly ; - assign #1 grey_rd_ptr_dly = grey_rd_ptr; + assign grey_rd_ptr_dly = grey_rd_ptr; // read pointer synchronizer always @(posedge wr_clk or negedge wr_reset_n) begin @@ -183,6 +199,11 @@ assign empty_c = (rd_cnt == 0) ? 1'b1 : 1'b0; assign aempty_c = (rd_cnt == 1) ? 1'b1 : 1'b0; + //-------------------------- + // Shows total number of words + // space available w.r.t write clock + //--------------------------- + assign rd_total_aval = rd_cnt; always @(posedge rd_clk or negedge rd_reset_n) begin if (!rd_reset_n) begin @@ -218,7 +239,7 @@ assign rd_data = (RD_FAST == 1) ? rd_data_c : rd_data_q; wire [AW:0] grey_wr_ptr_dly ; - assign #1 grey_wr_ptr_dly = grey_wr_ptr; + assign grey_wr_ptr_dly = grey_wr_ptr; // write pointer synchronizer always @(posedge rd_clk or negedge rd_reset_n) begin @@ -336,6 +357,49 @@ $stop; end end -// synopsys translate_on + +// gray code monitor +reg [AW:0] last_gwr_ptr; +always @(posedge wr_clk or negedge wr_reset_n) begin + if (!wr_reset_n) begin + last_gwr_ptr <= 0; + end + else if (last_gwr_ptr !== grey_wr_ptr) begin + check_ptr_chg(last_gwr_ptr, grey_wr_ptr); + last_gwr_ptr <= grey_wr_ptr; + end +end + +reg [AW:0] last_grd_ptr; +always @(posedge rd_clk or negedge rd_reset_n) begin + if (!rd_reset_n) begin + last_grd_ptr <= 0; + end + else if (last_grd_ptr !== grey_rd_ptr) begin + check_ptr_chg(last_grd_ptr, grey_rd_ptr); + last_grd_ptr <=grey_rd_ptr; + end +end + +task check_ptr_chg; +input [AW:0] last_ptr; +input [AW:0] cur_ptr; +integer i; +integer ptr_diff; +begin + ptr_diff = 0; + for (i=0; i<= AW; i=i+ 1'b1) begin + if (last_ptr[i] != cur_ptr[i]) begin + ptr_diff = ptr_diff + 1'b1; + end + end + if (ptr_diff !== 1) begin + $display($time, "%m, ERROR! async fifo ptr has changed more than noe bit, last=%h, cur=%h", + last_ptr, cur_ptr); + $stop; + end +end +endtask + // synopsys translate_on endmodule
diff --git a/verilog/rtl/lib/ctech_cells.sv b/verilog/rtl/lib/ctech_cells.sv index 8e3b0de..a9c6693 100644 --- a/verilog/rtl/lib/ctech_cells.sv +++ b/verilog/rtl/lib/ctech_cells.sv
@@ -1,14 +1,72 @@ -module ctech_mux2x1 ( - input logic A0, - input logic A1, +module ctech_mux2x1 #(parameter WB = 1) ( + input logic [WB-1:0] A0, + input logic [WB-1:0] A1, input logic S , - output logic X); + output logic [WB-1:0] X); `ifndef SYNTHESIS assign X = (S) ? A1 : A0; `else -sky130_fd_sc_hd__mux2_8 u_mux (.A0 (A0), .A1 (A1), .S (S), .X (X)); + generate + if (WB > 1) + begin : bus_ + genvar tcnt; + for (tcnt = 0; $unsigned(tcnt) < WB; tcnt=tcnt+1) begin : bit_ + sky130_fd_sc_hd__mux2_8 u_mux (.A0 (A0[tcnt]), .A1 (A1[tcnt]), .S (S), .X (X[tcnt])); + end + end else begin + sky130_fd_sc_hd__mux2_8 u_mux (.A0 (A0), .A1 (A1), .S (S), .X (X)); + end + endgenerate +`endif + +endmodule + +module ctech_mux2x1_2 #(parameter WB = 1) ( + input logic [WB-1:0] A0, + input logic [WB-1:0] A1, + input logic S , + output logic [WB-1:0] X); + +`ifndef SYNTHESIS +assign X = (S) ? A1 : A0; +`else + generate + if (WB > 1) + begin : bus_ + genvar tcnt; + for (tcnt = 0; $unsigned(tcnt) < WB; tcnt=tcnt+1) begin : bit_ + sky130_fd_sc_hd__mux2_2 u_mux (.A0 (A0[tcnt]), .A1 (A1[tcnt]), .S (S), .X (X[tcnt])); + end + end else begin + sky130_fd_sc_hd__mux2_2 u_mux (.A0 (A0), .A1 (A1), .S (S), .X (X)); + end + endgenerate +`endif + +endmodule + +module ctech_mux2x1_4 #(parameter WB = 1) ( + input logic [WB-1:0] A0, + input logic [WB-1:0] A1, + input logic S , + output logic [WB-1:0] X); + +`ifndef SYNTHESIS +assign X = (S) ? A1 : A0; +`else + generate + if (WB > 1) + begin : bus_ + genvar tcnt; + for (tcnt = 0; $unsigned(tcnt) < WB; tcnt=tcnt+1) begin : bit_ + sky130_fd_sc_hd__mux2_4 u_mux (.A0 (A0[tcnt]), .A1 (A1[tcnt]), .S (S), .X (X[tcnt])); + end + end else begin + sky130_fd_sc_hd__mux2_4 u_mux (.A0 (A0), .A1 (A1), .S (S), .X (X)); + end + endgenerate `endif endmodule @@ -49,3 +107,35 @@ endmodule +module ctech_delay_clkbuf ( + input logic A, + output logic X); + +wire X1; +`ifndef SYNTHESIS + assign X = A; +`else + sky130_fd_sc_hd__clkbuf_1 u_dly0 (.X(X1),.A(A)); + sky130_fd_sc_hd__clkbuf_1 u_dly1 (.X(X),.A(X1)); +`endif + +endmodule + +module ctech_clk_gate ( + input logic GATE , + input logic CLK , + output logic GCLK + ); + +`ifndef SYNTHESIS + assign GCLK = CLK & GATE; +`else + sky130_fd_sc_hd__dlclkp_2 u_gate( + .GATE (GATE ), + .CLK (CLK ), + .GCLK (GCLK ) + ); +`endif + +endmodule +
diff --git a/verilog/rtl/lib/ser_rd_inf_64b.sv b/verilog/rtl/lib/ser_rd_inf_64b.sv new file mode 100644 index 0000000..317f9e6 --- /dev/null +++ b/verilog/rtl/lib/ser_rd_inf_64b.sv
@@ -0,0 +1,105 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// +//// //// +//// ser_rd_inf_64 //// +//// //// +//// This file is part of the mbist_ctrl cores project //// +//// https://github.com/dineshannayya/mbist_ctrl.git //// +//// //// +//// Description //// +//// This block manages the serial to Parallel conversion //// +//// This block usefull for Bist SDI/SDO access //// +//// Function: //// +//// 1. When reg_rd=1, this block set shoft=1 and serial //// +//// capture the sdo to reg_rdata for 64 cycles and //// +//// asserts Reg Ack //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.0 - 20th Oct 2021, Dinesh A //// +//// Initial integration //// +//// //// +////////////////////////////////////////////////////////////////////// + +module ser_rd_inf_64b + ( + + // Master Port + input logic rst_n , // Regular Reset signal + input logic clk , // System clock + input logic reg_rd , // Read Request + output logic [63:0] reg_rdata , // data input + output logic reg_ack , // acknowlegement + + // Slave Port + output logic shift , // Shift Signal + input logic sdo // Serial SDO + + ); + + + parameter IDLE = 1'b0; + parameter SHIFT_DATA = 1'b1; + + logic state; + logic [6:0] bit_cnt; + + +always@(negedge rst_n or posedge clk) +begin + if(rst_n == 0) begin + state <= IDLE; + reg_rdata <= 'h0; + reg_ack <= 1'b0; + bit_cnt <= 'h0; + shift <= 'b0; + end else begin + case(state) + IDLE: begin + reg_ack <= 1'b0; + bit_cnt <= 6'h0; + if(reg_rd) begin + shift <= 'b1; + state <= SHIFT_DATA; + end + end + SHIFT_DATA: begin + reg_rdata <= {sdo,reg_rdata[63:1]}; + if(bit_cnt < 63) begin + bit_cnt <= bit_cnt +1; + end else begin + reg_ack <= 1'b1; + shift <= 'b0; + state <= IDLE; + end + end + endcase + end +end + + + + +endmodule
diff --git a/verilog/rtl/lib/wb_arb.sv b/verilog/rtl/lib/wb_arb.sv index 0ad8bbf..8f7b4ba 100644 --- a/verilog/rtl/lib/wb_arb.sv +++ b/verilog/rtl/lib/wb_arb.sv
@@ -68,7 +68,7 @@ input clk; input rstn; -input [2:0] req; // Req input +input [3:0] req; // Req input output [1:0] gnt; // Grant output /////////////////////////////////////////////////////////////////////// @@ -78,9 +78,10 @@ parameter [1:0] - grant0 = 3'h0, - grant1 = 3'h1, - grant2 = 3'h2; + grant0 = 2'h0, + grant1 = 2'h1, + grant2 = 2'h2, + grant3 = 2'h3; /////////////////////////////////////////////////////////////////////// // Local Registers and Wires @@ -113,13 +114,15 @@ grant0: // if this req is dropped or next is asserted, check for other req's if(!req[0] ) begin - if(req[1]) next_state = grant1; + if(req[1]) next_state = grant1; else if(req[2]) next_state = grant2; + else if(req[3]) next_state = grant3; end grant1: // if this req is dropped or next is asserted, check for other req's if(!req[1] ) begin - if(req[2]) next_state = grant2; + if(req[2]) next_state = grant2; + if(req[3]) next_state = grant3; else if(req[0]) next_state = grant0; end grant2: @@ -127,6 +130,14 @@ if(!req[2] ) begin if(req[0]) next_state = grant0; else if(req[1]) next_state = grant1; + else if(req[3]) next_state = grant3; + end + grant3: + // if this req is dropped or next is asserted, check for other req's + if(!req[3] ) begin + if(req[0]) next_state = grant0; + else if(req[1]) next_state = grant1; + else if(req[2]) next_state = grant2; end endcase end
diff --git a/verilog/rtl/lib/wb_stagging.sv b/verilog/rtl/lib/wb_stagging.sv index 8f54f0f..77e26f4 100644 --- a/verilog/rtl/lib/wb_stagging.sv +++ b/verilog/rtl/lib/wb_stagging.sv
@@ -76,18 +76,19 @@ module wb_stagging ( input logic clk_i, - input logic rst_n, + input logic rst_n, + input logic [3:0] cfg_slave_id, // WishBone Input master I/P input logic [31:0] m_wbd_dat_i, input logic [31:0] m_wbd_adr_i, input logic [3:0] m_wbd_sel_i, - input logic m_wbd_we_i, - input logic m_wbd_cyc_i, - input logic m_wbd_stb_i, + input logic m_wbd_we_i, + input logic m_wbd_cyc_i, + input logic m_wbd_stb_i, input logic [3:0] m_wbd_tid_i, output logic [31:0] m_wbd_dat_o, - output logic m_wbd_ack_o, - output logic m_wbd_err_o, + output logic m_wbd_ack_o, + output logic m_wbd_err_o, // Slave Interface input logic [31:0] s_wbd_dat_i, @@ -146,7 +147,7 @@ s_wbd_dat_i_ff <= s_wbd_dat_i; s_wbd_ack_i_ff <= s_wbd_ack_i; s_wbd_err_i_ff <= s_wbd_err_i; - if(m_wbd_stb_i && holding_busy == 0 && m_wbd_ack_o == 0) begin + if(m_wbd_tid_i == cfg_slave_id && m_wbd_stb_i && holding_busy == 0 && m_wbd_ack_o == 0) begin holding_busy <= 1'b1; m_wbd_dat_i_ff <= m_wbd_dat_i; m_wbd_adr_i_ff <= m_wbd_adr_i;
diff --git a/verilog/rtl/mac_wrapper/src/mac_wrapper.sv b/verilog/rtl/mac_wrapper/src/mac_wrapper.sv new file mode 100644 index 0000000..d466634 --- /dev/null +++ b/verilog/rtl/mac_wrapper/src/mac_wrapper.sv
@@ -0,0 +1,328 @@ +module mac_wrapper ( + + input logic app_clk , + input logic reset_n , + + // Clock Skew Adjust + input logic [3:0] cfg_cska_mac, + input logic wbd_clk_int, + output logic wbd_clk_skew, + + + //----------------------------------------------------------------------- + // Line-Tx Signal + //----------------------------------------------------------------------- + output logic phy_tx_en , + output logic phy_tx_er , + output logic [7:0] phy_txd , + input logic phy_tx_clk , + + //----------------------------------------------------------------------- + // Line-Rx Signal + //----------------------------------------------------------------------- + input logic phy_rx_clk , + input logic phy_rx_er , + input logic phy_rx_dv , + input logic [7:0] phy_rxd , + input logic phy_crs , + + + //----------------------------------------------------------------------- + // MDIO Signal + //----------------------------------------------------------------------- + input logic mdio_clk , + input logic mdio_in , + output logic mdio_out_en , + output logic mdio_out , + + //-------------------------------------------- + // GMAC TX WB Master I/F + //-------------------------------------------- + input logic [31:0] wbm_gtx_dat_i , + input logic wbm_gtx_ack_i , + output logic [31:0] wbm_gtx_dat_o , + output logic [12:0] wbm_gtx_adr_o , + output logic [3:0] wbm_gtx_sel_o , + output logic wbm_gtx_we_o , + output logic wbm_gtx_stb_o , + output logic wbm_gtx_cyc_o , + + //-------------------------------------------- + // GMAC RX WB Master I/F + //-------------------------------------------- + input logic [31:0] wbm_grx_dat_i , + input logic wbm_grx_ack_i , + output logic [31:0] wbm_grx_dat_o , + output logic [12:0] wbm_grx_adr_o , + output logic [3:0] wbm_grx_sel_o , + output logic wbm_grx_we_o , + output logic wbm_grx_stb_o , + output logic wbm_grx_cyc_o , + + //-------------------------------------------- + // GMAC REG WB SLAVE I/F + //-------------------------------------------- + output logic [31:0] wbs_grg_dat_o , + output logic wbs_grg_ack_o , + input logic [31:0] wbs_grg_dat_i , + input logic [12:0] wbs_grg_adr_i , + input logic [3:0] wbs_grg_sel_i , + input logic wbs_grg_we_i , + input logic wbs_grg_stb_i , + input logic wbs_grg_cyc_i , + + // Q Occupancy + output logic [9:0] cfg_tx_qbase_addr, + output logic [9:0] cfg_rx_qbase_addr, + + input logic mac_tx_qcnt_inc, + input logic mac_tx_qcnt_dec, + input logic mac_rx_qcnt_inc, + input logic mac_rx_qcnt_dec + + ); + +wire [8:0] app_txfifo_wrdata_i; +wire [15:0] app_txfifo_addr ; +wire [15:0] app_rxfifo_addr ; +wire [3:0] tx_qcnt ; +wire [3:0] rx_qcnt ; + +//----------------------------- +// MAC Related wire Decleration +//----------------------------- +wire [8:0] app_rxfifo_rddata_o; +wire [31:0] app_rx_desc_data ; + +wire tx_q_empty = (tx_qcnt == 0); +wire rx_q_empty = (rx_qcnt == 0); + + +// clock skew control +clk_skew_adjust u_skew_mac + ( +`ifdef USE_POWER_PINS + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground +`endif + .clk_in (wbd_clk_int ), + .sel (cfg_cska_mac ), + .clk_out (wbd_clk_skew ) + ); + +/**************************** +//--------------------------------------------------------------- +// Mapping the MAC Interface Signal to Caravel I/O +//--------------------------------------------------------------- +//----------------------------------------------------------------------- +// Line-Tx Signal +//----------------------------------------------------------------------- +logic phy_tx_clk ; +logic phy_tx_en ; +logic phy_tx_er ; +logic [7:0] phy_txd ; + +assign io_out[7:0] = phy_txd; +assign io_out[8] = phy_tx_en; +assign io_out[9] = phy_tx_er; +assign io_out[10] = phy_tx_clk; +assign io_out[11] = 1'b0; // Reserved + +assign io_oeb[11:0] = 'h0; // All are Output + + +//----------------------------------------------------------------------- +// Line-Rx Signal +//----------------------------------------------------------------------- +input logic phy_rx_clk , +input logic phy_rx_er , +input logic phy_rx_dv , +input logic [7:0] phy_rxd , +input logic phy_crs , + +assign phy_rx_dv = io_in[12]; +assign phy_rx_er = io_in[13]; +assign phy_crs = io_in[14]; +assign phy_rx_clk = io_in[15]; +assign phy_rxd = io_in[23:16]; + +assign io_oeb[23:16] = 12'hFFF; // All are Inputs + + +//----------------------------------------------------------------------- +// MDIO Signal +//----------------------------------------------------------------------- +logic mdio_clk ; +logic mdio_in ; +logic mdio_out_en ; +logic mdio_out ; + + +assign io_in[24] = mdio_clk; +assign io_in[25] = mdio_in; +assign io_out[25] = mdio_out; +assign io_oeb[24] = 1'b1; // mdio clk input +assign io_oeb[25] = mdio_out_en; +*******************/ + + + +// QCounter Inc/dec generation +// Ned to move this logic to wishbone interconnect +//wire tx_qcnt_inc = (cfg_tx_buf_qbase_addr == wb_xram_adr[15:6]) && wb_xram_stb && wb_xram_wr && wb_xram_ack && (wb_xram_be[3] == 1'b1); +//wire tx_qcnt_dec = (cfg_tx_buf_qbase_addr == wb_xram_adr[15:6]) && wb_xram_stb && !wb_xram_wr && wb_xram_ack && (wb_xram_be[3] == 1'b1); +//wire rx_qcnt_inc = (cfg_rx_buf_qbase_addr == wb_xram_adr[15:6]) && wb_xram_stb && wb_xram_wr && wb_xram_ack && (wb_xram_be[3] == 1'b1); +//wire rx_qcnt_dec = (cfg_rx_buf_qbase_addr == wb_xram_adr[15:6]) && wb_xram_stb && !wb_xram_wr && wb_xram_ack && (wb_xram_be[3] == 1'b1); + +//------------------------------------------- +// GMAC core instantiation +//------------------------------------------- + +g_mac_top u_eth_dut ( + + .scan_mode ( 1'b0 ), + .s_reset_n ( reset_n ), + .tx_reset_n ( reset_n ), + .rx_reset_n ( reset_n ), + .reset_mdio_clk_n ( reset_n ), + .app_reset_n ( reset_n ), + + // Reg Bus Interface Signal + .reg_cs ( wbs_grg_stb_i ), + .reg_wr ( wbs_grg_we_i ), + .reg_addr ( wbs_grg_adr_i[5:2] ), + .reg_wdata ( wbs_grg_dat_i ), + .reg_be ( wbs_grg_sel_i ), + + // Outputs + .reg_rdata ( wbs_grg_dat_o ), + .reg_ack ( wbs_grg_ack_o ), + + + .app_clk ( app_clk ), + + // Application RX FIFO Interface + .app_txfifo_wren_i ( app_txfifo_wren_i ), + .app_txfifo_wrdata_i ( app_txfifo_wrdata_i ), + .app_txfifo_addr ( app_txfifo_addr ), + .app_txfifo_full_o ( app_txfifo_full_o ), + .app_txfifo_afull_o ( app_txfifo_afull_o ), + .app_txfifo_space_o ( ), + + // Application TX FIFO Interface + .app_rxfifo_rden_i ( app_rxfifo_rden_i ), + .app_rxfifo_empty_o ( app_rxfifo_empty_o ), + .app_rxfifo_aempty_o ( app_rxfifo_aempty_o ), + .app_rxfifo_cnt_o ( ), + .app_rxfifo_rdata_o ( app_rxfifo_rddata_o ), + .app_rxfifo_addr ( app_rxfifo_addr ), + + .app_rx_desc_req ( app_rx_desc_req ), + .app_rx_desc_ack ( app_rx_desc_ack ), + .app_rx_desc_discard ( app_rx_desc_discard ), + .app_rx_desc_data ( app_rx_desc_data ), + + // Line Side Interface TX Path + .phy_tx_en ( phy_tx_en ), + .phy_tx_er ( phy_tx_er ), + .phy_txd ( phy_txd ), + .phy_tx_clk ( phy_tx_clk ), + + // Line Side Interface RX Path + .phy_rx_clk ( phy_rx_clk ), + .phy_rx_er ( phy_rx_er ), + .phy_rx_dv ( phy_rx_dv ), + .phy_rxd ( phy_rxd ), + .phy_crs ( phy_crs ), + + //MDIO interface + .mdio_clk ( mdio_clk ), + .mdio_in ( mdio_in ), + .mdio_out_en ( mdio_out_en ), + .mdio_out ( mdio_out ), + + // QCounter + .rx_buf_qbase_addr ( cfg_rx_qbase_addr ), + .tx_buf_qbase_addr ( cfg_tx_qbase_addr ), + + .tx_qcnt_inc ( mac_tx_qcnt_inc ), + .tx_qcnt_dec ( mac_tx_qcnt_dec ), + .rx_qcnt_inc ( mac_rx_qcnt_inc ), + .rx_qcnt_dec ( mac_rx_qcnt_dec ), + .tx_qcnt ( tx_qcnt ), + .rx_qcnt ( rx_qcnt ) + + + ); + + + +//------------------------------------------------- +// GMAX => MEMORY WRITE +//------------------------------------------------- + +wb_rd_mem2mem #(.D_WD(32),.BE_WD(4),.ADR_WD(13),.TAR_WD(4)) u_wb_gmac_tx ( + + .rst_n ( gen_resetn ), + .clk ( app_clk ), + + // descriptor handshake + .cfg_desc_baddr (cfg_tx_qbase_addr ), + .desc_q_empty (tx_q_empty ), + + // Master Interface Signal + .mem_taddr ( 4'h1 ), + .mem_full (app_txfifo_full_o ), + .mem_afull (app_txfifo_afull_o ), + .mem_wr (app_txfifo_wren_i ), + .mem_din (app_txfifo_wrdata_i ), + + // Slave Interface Signal + .wbo_dout ( wbm_gtx_dat_i ), + .wbo_ack ( wbm_gtx_ack_i ), + .wbo_taddr ( ), + .wbo_addr ( wbm_gtx_adr_o ), + .wbo_be ( wbm_gtx_sel_o ), + .wbo_we ( wbm_gtx_we_o ), + .wbo_stb ( wbm_gtx_stb_o ), + .wbo_cyc ( wbm_gtx_cyc_o ), + .wbo_err ( ), + .wbo_rty ( 1'b0 ) + ); + + +wb_wr_mem2mem #(.D_WD(32),.BE_WD(4),.ADR_WD(13),.TAR_WD(4)) u_wb_gmac_rx( + + .rst_n ( reset_n ), + .clk ( app_clk ), + + + // Master Interface Signal + .mem_taddr ( 4'h1 ), + .mem_addr (app_rxfifo_addr ), + .mem_empty (app_rxfifo_empty_o ), + .mem_aempty (app_rxfifo_aempty_o ), + .mem_rd (app_rxfifo_rden_i ), + .mem_dout (app_rxfifo_rddata_o[7:0]), + .mem_eop (app_rxfifo_rddata_o[8]), + + .cfg_desc_baddr (cfg_rx_qbase_addr ), + .desc_req (app_rx_desc_req ), + .desc_ack (app_rx_desc_ack ), + .desc_disccard (app_rx_desc_discard ), + .desc_data (app_rx_desc_data ), + // Slave Interface Signal + .wbo_din ( wbm_grx_dat_o ), + .wbo_taddr ( ), + .wbo_addr ( wbm_grx_adr_o ), + .wbo_be ( wbm_grx_sel_o ), + .wbo_we ( wbm_grx_we_o ), + .wbo_ack ( wbm_grx_ack_i ), + .wbo_stb ( wbm_grx_stb_o ), + .wbo_cyc ( wbm_grx_cyc_o ), + .wbo_err ( wbm_grx_err ), + .wbo_rty ( 1'b0 ) + ); + + +endmodule
diff --git a/verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv b/verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv index b631626..8f31671 100644 --- a/verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv +++ b/verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv
@@ -61,60 +61,42 @@ //// //// ////////////////////////////////////////////////////////////////////// module mbist_mem_wrapper #( + parameter BIST_NO_SRAM=4, parameter BIST_ADDR_WD=10, parameter BIST_DATA_WD=32) ( input logic rst_n , // WB I/F + input logic [(BIST_NO_SRAM+1)/2-1:0] sram_id , input logic wb_clk_i , // System clock - input logic wb_cyc_i , // strobe/request - input logic wb_stb_i , // strobe/request - input logic [BIST_ADDR_WD-1:0] wb_adr_i , // address - input logic wb_we_i , // write - input logic [BIST_DATA_WD-1:0] wb_dat_i , // data output - input logic [BIST_DATA_WD/8-1:0] wb_sel_i , // byte enable - output logic [BIST_DATA_WD-1:0] wb_dat_o , // data input - output logic wb_ack_o , // acknowlegement - output logic wb_err_o , // error - // MEM A PORT - output logic func_clk_a , - output logic func_cen_a , - output logic [BIST_ADDR_WD-1:0] func_addr_a , - input logic [BIST_DATA_WD-1:0] func_dout_a , - - // Functional B Port - output logic func_clk_b , - output logic func_cen_b , - output logic func_web_b , - output logic [BIST_DATA_WD/8-1:0] func_mask_b , - output logic [BIST_ADDR_WD-1:0] func_addr_b , - output logic [BIST_DATA_WD-1:0] func_din_b + input logic [(BIST_NO_SRAM+1)/2-1:0] mem_cs , // Chip Select + input logic mem_req , // strobe/request + input logic [BIST_ADDR_WD-1:0] mem_addr , // address + input logic mem_we , // write + input logic [BIST_DATA_WD-1:0] mem_wdata , // data output + input logic [BIST_DATA_WD/8-1:0] mem_wmask , // byte enable + output logic [BIST_DATA_WD-1:0] mem_rdata , // data input + // MEM PORT + output logic func_clk , + output logic func_cen , + output logic func_web , + output logic [BIST_DATA_WD/8-1:0] func_mask , + output logic [BIST_ADDR_WD-1:0] func_addr , + input logic [BIST_DATA_WD-1:0] func_dout , + output logic [BIST_DATA_WD-1:0] func_din ); // Memory Write PORT -assign func_clk_b = wb_clk_i; -assign func_cen_b = !wb_stb_i; -assign func_web_b = !wb_we_i; -assign func_mask_b = wb_sel_i; -assign func_addr_b = wb_adr_i; -assign func_din_b = wb_dat_i; +assign func_clk = wb_clk_i; +assign func_cen = (mem_cs == sram_id) ? !mem_req : 1'b1; +assign func_web = (mem_cs == sram_id) ? !mem_we : 1'b1; +assign func_mask = mem_wmask; +assign func_addr = mem_addr; +assign func_din = mem_wdata; +assign mem_rdata = func_dout; -assign func_clk_a = wb_clk_i; -assign func_cen_a = (wb_stb_i == 1'b1 && wb_we_i == 1'b0 && wb_ack_o ==0) ? 1'b0 : 1'b1; -assign func_addr_a = wb_adr_i; -assign wb_dat_o = func_dout_a; -assign wb_err_o = 1'b0; - -// Generate Once cycle delayed ACK to get the data from SRAM -always_ff @(negedge rst_n or posedge wb_clk_i) begin - if ( rst_n == 1'b0 ) begin - wb_ack_o<= 'h0; - end else begin - wb_ack_o <= (wb_stb_i == 1'b1) & (wb_ack_o == 0); - end -end endmodule
diff --git a/verilog/rtl/mbist/src/core/mbist_mux.sv b/verilog/rtl/mbist/src/core/mbist_mux.sv index c3064f8..77ee052 100755 --- a/verilog/rtl/mbist/src/core/mbist_mux.sv +++ b/verilog/rtl/mbist/src/core/mbist_mux.sv
@@ -48,7 +48,6 @@ parameter BIST_RAD_WD_O = BIST_ADDR_WD) ( input logic scan_mode, - input logic cfg_mem_lphase, input logic rst_n, // MBIST CTRL SIGNAL @@ -65,142 +64,69 @@ input logic bist_shift, output logic bist_sdo, - // FUNCTIONAL CTRL SIGNAL - input logic func_clk_a, - input logic func_cen_a, - input logic [BIST_ADDR_WD-1:0] func_addr_a, - // Common for func and Mbist i/f - output logic [BIST_DATA_WD-1:0] func_dout_a, - - input logic func_clk_b, - input logic func_cen_b, - input logic func_web_b, - input logic [BIST_DATA_WD/8-1:0] func_mask_b, - input logic [BIST_ADDR_WD-1:0] func_addr_b, - input logic [BIST_DATA_WD-1:0] func_din_b, + input logic func_clk, + input logic func_cen, + input logic func_web, + input logic [BIST_DATA_WD/8-1:0] func_mask, + input logic [BIST_ADDR_WD-1:0] func_addr, + input logic [BIST_DATA_WD-1:0] func_din, + output logic [BIST_DATA_WD-1:0] func_dout, // towards memory - output logic mem_clk_a, - output logic mem_cen_a, - output logic [BIST_ADDR_WD-1:0] mem_addr_a, - input logic [BIST_DATA_WD-1:0] mem_dout_a, - output logic mem_clk_b, - output logic mem_cen_b, - output logic mem_web_b, - output logic [BIST_DATA_WD/8-1:0] mem_mask_b, - output logic [BIST_ADDR_WD-1:0] mem_addr_b, - output logic [BIST_DATA_WD-1:0] mem_din_b + output logic mem_clk, + output logic mem_cen, + output logic mem_web, + output logic [BIST_DATA_WD/8-1:0] mem_mask, + output logic [BIST_ADDR_WD-1:0] mem_addr, + output logic [BIST_DATA_WD-1:0] mem_din, + input logic [BIST_DATA_WD-1:0] mem_dout ); parameter BIST_MASK_WD = BIST_DATA_WD/8; -wire [BIST_ADDR_WD-1:0] addr_a; -wire [BIST_ADDR_WD-1:0] addr_b; -wire mem_clk_a_cts; // used for internal clock tree -wire mem_clk_b_cts; // usef for internal clock tree +wire [BIST_ADDR_WD-1:0] addr; -//---------------------------------------------------------------- -// As there SRAM timing model is not correct. we have created -// additional position drive data in negedge -// ---------------------------------------------------------------- -logic mem_cen_a_int; -logic [BIST_ADDR_WD-1:0] mem_addr_a_int; -logic mem_cen_b_int; -logic mem_web_b_int; -logic [BIST_DATA_WD/8-1:0] mem_mask_b_int; -logic [BIST_ADDR_WD-1:0] mem_addr_b_int; -logic [BIST_DATA_WD-1:0] mem_din_b_int; +assign addr = (bist_en) ? bist_addr : func_addr; -logic mem_cen_a_neg; -logic [BIST_ADDR_WD-1:0] mem_addr_a_neg; - -logic mem_cen_b_neg; -logic mem_web_b_neg; -logic [BIST_DATA_WD/8-1:0] mem_mask_b_neg; -logic [BIST_ADDR_WD-1:0] mem_addr_b_neg; -logic [BIST_DATA_WD-1:0] mem_din_b_neg; - -always @(negedge rst_n or negedge mem_clk_a) begin - if(rst_n == 0) begin - mem_cen_a_neg <= '0; - mem_addr_a_neg <= '0; - end else begin - mem_cen_a_neg <= mem_cen_a_int; - mem_addr_a_neg <= mem_addr_a_int; - end -end - -always @(negedge rst_n or negedge mem_clk_b) begin - if(rst_n == 0) begin - mem_cen_b_neg <= '0; - mem_web_b_neg <= '0; - mem_mask_b_neg <= '0; - mem_addr_b_neg <= '0; - mem_din_b_neg <= '0; - end else begin - mem_cen_b_neg <= mem_cen_b_int; - mem_web_b_neg <= mem_web_b_int; - mem_mask_b_neg <= mem_mask_b_int; - mem_addr_b_neg <= mem_addr_b_int; - mem_din_b_neg <= mem_din_b_int; - end -end - -assign mem_cen_a = (cfg_mem_lphase == 0) ? mem_cen_a_int : mem_cen_a_neg; -assign mem_addr_a = (cfg_mem_lphase == 0) ? mem_addr_a_int : mem_addr_a_neg; - -assign mem_cen_b = (cfg_mem_lphase == 0) ? mem_cen_b_int : mem_cen_b_neg; -assign mem_web_b = (cfg_mem_lphase == 0) ? mem_web_b_int : mem_web_b_neg; -assign mem_mask_b = (cfg_mem_lphase == 0) ? mem_mask_b_int : mem_mask_b_neg; -assign mem_addr_b = (cfg_mem_lphase == 0) ? mem_addr_b_int : mem_addr_b_neg; -assign mem_din_b = (cfg_mem_lphase == 0) ? mem_din_b_int : mem_din_b_neg; - -//----------------------------------------- -assign addr_a = (bist_en) ? bist_addr : func_addr_a; -assign addr_b = (bist_en) ? bist_addr : func_addr_b; - -assign mem_cen_a_int = (bist_en) ? !bist_rd : func_cen_a; -assign mem_cen_b_int = (bist_en) ? !bist_wr : func_cen_b; - -assign mem_web_b_int = (bist_en) ? !bist_wr : func_web_b; -assign mem_mask_b_int = (bist_en) ? {{BIST_MASK_WD}{1'b1}} : func_mask_b; +assign mem_cen = (bist_en) ? !(bist_rd | bist_wr) : func_cen; +assign mem_web = (bist_en) ? !bist_wr : func_web; +assign mem_mask = (bist_en) ? {{BIST_MASK_WD}{1'b1}} : func_mask; //assign mem_clk_a = (bist_en) ? bist_clk : func_clk_a; //assign mem_clk_b = (bist_en) ? bist_clk : func_clk_b; -ctech_mux2x1 u_mem_clk_a_sel (.A0 (func_clk_a),.A1 (bist_clk),.S (bist_en), .X (mem_clk_a)); -ctech_mux2x1 u_mem_clk_b_sel (.A0 (func_clk_b),.A1 (bist_clk),.S (bist_en), .X (mem_clk_b)); +ctech_mux2x1 u_mem_clk_sel (.A0 (func_clk),.A1 (bist_clk),.S (bist_en), .X (mem_clk)); -ctech_clk_buf u_cts_mem_clk_a (.A (mem_clk_a), . X(mem_clk_a_cts)); -ctech_clk_buf u_cts_mem_clk_b (.A (mem_clk_b), . X(mem_clk_b_cts)); +//ctech_clk_buf u_mem_clk (.A (mem_clk_cts), . X(mem_clk)); -assign mem_din_b_int = (bist_en) ? bist_wdata : func_din_b; +assign mem_din = (bist_en) ? bist_wdata : func_din; + // During scan, SRAM data is unknown, feed data in back to avoid unknow // propagation -assign func_dout_a = (scan_mode) ? mem_din_b : mem_dout_a; +assign func_dout = (scan_mode) ? mem_din : mem_dout; mbist_repair_addr - #(.BIST_ADDR_WD (BIST_ADDR_WD), + #(.BIST_ADDR_WD (BIST_ADDR_WD), .BIST_DATA_WD (BIST_DATA_WD), .BIST_ADDR_START (BIST_ADDR_START), .BIST_ADDR_END (BIST_ADDR_END), .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START), .BIST_RAD_WD_I (BIST_RAD_WD_I), .BIST_RAD_WD_O (BIST_RAD_WD_O)) - u_repair_A( - .AddressOut (mem_addr_a_int ), + u_repair( + .AddressOut (mem_addr ), .Correct (bist_correct ), .sdo (bist_sdo ), - .AddressIn (addr_a ), - .clk (mem_clk_a_cts ), + .AddressIn (addr ), + .clk (mem_clk ), .rst_n (rst_n ), .Error (bist_error ), .ErrorAddr (bist_error_addr ), @@ -208,27 +134,6 @@ .sdi (bist_sdi ) ); -mbist_repair_addr - #(.BIST_ADDR_WD (BIST_ADDR_WD), - .BIST_DATA_WD (BIST_DATA_WD), - .BIST_ADDR_START (BIST_ADDR_START), - .BIST_ADDR_END (BIST_ADDR_END), - .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START), - .BIST_RAD_WD_I (BIST_RAD_WD_I), - .BIST_RAD_WD_O (BIST_RAD_WD_O)) - u_repair_B( - .AddressOut (mem_addr_b_int ), - .Correct ( ), // Both Bist Correct are same - .sdo ( ), - - .AddressIn (addr_b ), - .clk (mem_clk_b_cts ), - .rst_n (rst_n ), - .Error (bist_error ), - .ErrorAddr (bist_error_addr ), - .scan_shift (1'b0 ), // Both Repair hold same address - .sdi (1'b0 ) -);
diff --git a/verilog/rtl/mbist/src/core/mbist_op_sel.sv b/verilog/rtl/mbist/src/core/mbist_op_sel.sv index a995b8e..e160346 100644 --- a/verilog/rtl/mbist/src/core/mbist_op_sel.sv +++ b/verilog/rtl/mbist/src/core/mbist_op_sel.sv
@@ -95,6 +95,9 @@ assign last_op = (re_init) ? 1'b0 : op_sel[0]; +// Need to update the SDI chain here +assign sdo = sdi; + always_comb begin
diff --git a/verilog/rtl/mbist/src/core/mbist_repair_addr.sv b/verilog/rtl/mbist/src/core/mbist_repair_addr.sv index dbeddcd..71ee7ac 100644 --- a/verilog/rtl/mbist/src/core/mbist_repair_addr.sv +++ b/verilog/rtl/mbist/src/core/mbist_repair_addr.sv
@@ -123,7 +123,9 @@ shift_cnt <= '0; scan_shift_d <= 1'b0; end else begin - if(scan_shift && (shift_cnt[7:4] < BIST_ERR_LIMIT)) begin + if(!scan_shift) begin + shift_cnt <= 'h0; + end else if(scan_shift && (shift_cnt[7:4] < BIST_ERR_LIMIT)) begin shift_cnt <= shift_cnt+1; end scan_shift_d <= scan_shift;
diff --git a/verilog/rtl/mbist/src/top/mbist_top.sv b/verilog/rtl/mbist/src/top/mbist_top.sv index 806ce13..6d02f3d 100644 --- a/verilog/rtl/mbist/src/top/mbist_top.sv +++ b/verilog/rtl/mbist/src/top/mbist_top.sv
@@ -65,7 +65,7 @@ // Clock Skew Adjust input wire wbd_clk_int, - output wire wbd_clk_mbist, + output wire wbd_clk_skew, input wire [3:0] cfg_cska_mbist, // clock skew adjust for web host input logic rst_n, @@ -76,6 +76,7 @@ input wire bist_shift, input wire bist_load, input wire bist_sdi, + input wire [1:0] bist_serial_sel, output wire [3:0] bist_error_cnt0, output wire [3:0] bist_error_cnt1, @@ -222,7 +223,7 @@ // Towards MEMORY PORT - A assign mem_clk_b = 'b0; -assign mem_cen_b = 'b0; +assign mem_cen_b = 'b1; assign mem_addr_b0 = 'b0; assign mem_addr_b1 = 'b0; assign mem_addr_b2 = 'b0; @@ -248,7 +249,10 @@ assign bist_ms_sdi[1] = bist_ms_sdo[0]; assign bist_ms_sdi[2] = bist_ms_sdo[1]; assign bist_ms_sdi[3] = bist_ms_sdo[2]; -assign bist_sdo = bist_ms_sdo[3]; +assign bist_sdo = (bist_serial_sel == 2'b00) ? bist_ms_sdo[0] : + (bist_serial_sel == 2'b01) ? bist_ms_sdo[1] : + (bist_serial_sel == 2'b10) ? bist_ms_sdo[2] : + (bist_serial_sel == 2'b11) ? bist_ms_sdo[3] : 1'b0; // Pick the correct read path assign mem_rdata = wb_dat[mem_cs]; @@ -273,7 +277,7 @@ `endif .clk_in (wbd_clk_int ), .sel (cfg_cska_mbist ), - .clk_out (wbd_clk_mbist ) + .clk_out (wbd_clk_skew ) ); reset_sync u_reset_sync ( @@ -353,8 +357,8 @@ .rst_n (srst_n ), .run (run_addr ), .updown (op_updown ), - .bist_shift (bist_shift ), - .bist_load (bist_load ), + .scan_shift (bist_shift ), + .scan_load (bist_load ), .sdi (bist_sdi ) ); @@ -375,7 +379,7 @@ .sdo (bist_sti_sdo ), .last_stimulus (last_sti ), - .stimulus (stimulus ), + .stimulus (stimulus ), .clk (wb_clk_i ), .rst_n (srst_n ), @@ -399,7 +403,7 @@ ) u_op_sel ( - .op_read (op_read ), + .op_read (op_read ), .op_write (op_write ), .op_invert (op_invert ), .op_updown (op_updown ), @@ -412,9 +416,9 @@ .rst_n (srst_n ), .scan_shift (bist_shift ), .sdi (bist_sti_sdo ), - .re_init (bist_error_correct_or ), + .re_init (bist_error_correct_or ), .run (run_op ), - .stimulus (stimulus ) + .stimulus (stimulus ) ); @@ -520,43 +524,42 @@ ) u_mem_sel ( - .scan_mode (1'b0 ), + .scan_mode (1'b0 ), - .rst_n (srst_n ), - // MBIST CTRL SIGNAL - .bist_en (bist_en ), - .bist_addr (bist_addr ), - .bist_wdata (bist_wdata ), - .bist_clk (wb_clk2_i ), - .bist_wr (bist_wr ), - .bist_rd (bist_rd ), - .bist_error (bist_error_correct[sram_no]), - .bist_error_addr (bist_error_addr[sram_no] ), - .bist_correct (bist_correct[sram_no] ), + .rst_n (srst_n ), + // MBIST CTRL SIGNAL + .bist_en (bist_en ), + .bist_addr (bist_addr ), + .bist_wdata (bist_wdata ), + .bist_clk (wb_clk2_i ), + .bist_wr (bist_wr ), + .bist_rd (bist_rd ), + .bist_error (bist_error_correct[sram_no]), + .bist_error_addr (bist_error_addr[sram_no] ), + .bist_correct (bist_correct[sram_no] ), .bist_sdi (bist_ms_sdi[sram_no] ), - .bist_load (bist_load ), .bist_shift (bist_shift ), .bist_sdo (bist_ms_sdo[sram_no] ), - // FUNCTIONAL CTRL SIGNAL - .func_clk (func_clk[sram_no] ), - .func_cen (func_cen[sram_no] ), - .func_web (func_web[sram_no] ), - .func_mask (func_mask[sram_no] ), - .func_addr (func_addr[sram_no] ), - .func_din (func_din[sram_no] ), - .func_dout (func_dout[sram_no] ), + // FUNCTIONAL CTRL SIGNAL + .func_clk (func_clk[sram_no] ), + .func_cen (func_cen[sram_no] ), + .func_web (func_web[sram_no] ), + .func_mask (func_mask[sram_no] ), + .func_addr (func_addr[sram_no] ), + .func_din (func_din[sram_no] ), + .func_dout (func_dout[sram_no] ), - // towards memory - // Memory Out Port - .mem_clk (mem_clk_a[sram_no] ), - .mem_cen (mem_cen_a[sram_no] ), - .mem_web (mem_web_a[sram_no] ), - .mem_mask (mem_mask_a_i[sram_no] ), - .mem_addr (mem_addr_a_i[sram_no] ), - .mem_din (mem_din_a_i[sram_no] ), - .mem_dout (mem_dout_a_i[sram_no] ) + // towards memory + // Memory Out Port + .mem_clk (mem_clk_a[sram_no] ), + .mem_cen (mem_cen_a[sram_no] ), + .mem_web (mem_web_a[sram_no] ), + .mem_mask (mem_mask_a_i[sram_no] ), + .mem_addr (mem_addr_a_i[sram_no] ), + .mem_din (mem_din_a_i[sram_no] ), + .mem_dout (mem_dout_a_i[sram_no] ) ); end
diff --git a/verilog/rtl/mbist_wrapper/src/mbist_wb.sv b/verilog/rtl/mbist_wrapper/src/mbist_wb.sv index ef989dd..8628ea6 100644 --- a/verilog/rtl/mbist_wrapper/src/mbist_wb.sv +++ b/verilog/rtl/mbist_wrapper/src/mbist_wb.sv
@@ -37,20 +37,20 @@ input logic rst_n, - // WB I/F - input logic wb_clk_i, // System clock - input logic wb_stb_i, // strobe/request - input logic [BIST_ADDR_WD-1:0] wb_adr_i, // address - input logic [(BIST_NO_SRAM+1)/2-1:0] wb_cs_i, // address - input logic wb_we_i , // write - input logic [BIST_DATA_WD-1:0] wb_dat_i, // data output - input logic [BIST_DATA_WD/8-1:0] wb_sel_i, // byte enable - input logic [9:0] wb_bl_i, // Burst Length - input logic wb_bry_i, // Burst Ready - output logic [BIST_DATA_WD-1:0] wb_dat_o, // data input - output logic wb_ack_o, // acknowlegement - output logic wb_lack_o, // acknowlegement - output logic wb_err_o, // error + // WB I/F + input logic wb_clk_i, // System clock + input logic wb_stb_i, // strobe/request + input logic [BIST_ADDR_WD-1:0] wb_adr_i, // address + input logic [(BIST_NO_SRAM+1)/2-1:0] wb_cs_i, // address + input logic wb_we_i , // write + input logic [BIST_DATA_WD-1:0] wb_dat_i, // data output + input logic [BIST_DATA_WD/8-1:0] wb_sel_i, // byte enable + input logic [9:0] wb_bl_i, // Burst Length + input logic wb_bry_i, // Burst Ready + output logic [BIST_DATA_WD-1:0] wb_dat_o, // data input + output logic wb_ack_o, // acknowlegement + output logic wb_lack_o, // acknowlegement + output logic wb_err_o, // error output logic mem_req, output logic [(BIST_NO_SRAM+1)/2-1:0] mem_cs, @@ -86,6 +86,7 @@ mem_bl_cnt <= 'h0; mem_addr <= 'h0; mem_next_addr <= 'h0; + wb_ack_o <= 'b0; wb_ack_l <= 'b0; wb_dat_o <= 'h0; mem_req <= 'b0; @@ -137,7 +138,7 @@ end READ_ACTION1: begin mem_addr <= mem_addr +1; - mem_hval <= 1'b0; + mem_hval <= 1'b0; wb_ack_l <= 'b1; mem_bl_cnt <= 'h1; state <= READ_ACTION2;
diff --git a/verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv b/verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv index 07c5ce3..893f9dd 100644 --- a/verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv +++ b/verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv
@@ -48,8 +48,8 @@ `include "mbist_def.svh" module mbist_wrapper - #( - parameter BIST_NO_SRAM = 4, + #( parameter SCW = 8, // SCAN CHAIN WIDTH + parameter BIST_NO_SRAM = 4, parameter BIST_ADDR_WD = 9, parameter BIST_DATA_WD = 32, parameter BIST_ADDR_START = 9'h000, @@ -62,86 +62,93 @@ inout vccd1, // User area 1 1.8V supply inout vssd1, // User area 1 digital ground `endif + // Scan I/F + input logic scan_en , + input logic scan_mode , + input logic [SCW-1:0] scan_si , + output logic [SCW-1:0] scan_so , + output logic scan_en_o , + output logic scan_mode_o , // Clock Skew Adjust - input wire wbd_clk_int, - output wire wbd_clk_mbist, - input wire [3:0] cfg_cska_mbist, // clock skew adjust for web host + input wire wbd_clk_int , + output wire wbd_clk_skew , + input wire [3:0] cfg_cska_mbist , // clock skew adjust for web host - input logic rst_n, + input logic rst_n , // MBIST I/F - input wire bist_en, - input wire bist_run, - input wire bist_shift, - input wire bist_load, - input wire bist_sdi, + input wire bist_en , + input wire bist_run , + input wire bist_shift , + input wire bist_load , + input wire bist_sdi , + input wire [1:0] bist_serial_sel , - output wire [3:0] bist_error_cnt0, - output wire [3:0] bist_error_cnt1, - output wire [3:0] bist_error_cnt2, - output wire [3:0] bist_error_cnt3, - output wire [BIST_NO_SRAM-1:0] bist_correct , - output wire [BIST_NO_SRAM-1:0] bist_error , - output wire bist_done, - output wire bist_sdo, + output wire [3:0] bist_error_cnt0 , + output wire [3:0] bist_error_cnt1 , + output wire [3:0] bist_error_cnt2 , + output wire [3:0] bist_error_cnt3 , + output wire [BIST_NO_SRAM-1:0] bist_correct , + output wire [BIST_NO_SRAM-1:0] bist_error , + output wire bist_done , + output wire bist_sdo , - // WB I/F - input wire wb_clk_i, // System clock - input wire wb_clk2_i, // System clock2 is no cts - input wire wb_stb_i, // strobe/request - input wire [(BIST_NO_SRAM+1)/2-1:0] wb_cs_i, - input wire [BIST_ADDR_WD-1:0] wb_adr_i, // address - input wire wb_we_i , // write - input wire [BIST_DATA_WD-1:0] wb_dat_i, // data output - input wire [BIST_DATA_WD/8-1:0] wb_sel_i, // byte enable - input wire [9:0] wb_bl_i, // burst - input wire wb_bry_i, // burst ready - output wire [BIST_DATA_WD-1:0] wb_dat_o, // data input - output wire wb_ack_o, // acknowlegement - output wire wb_lack_o, // acknowlegement - output wire wb_err_o, // error + // WB I/F + input wire wb_clk_i , // System clock + input wire wb_clk2_i , // System clock2 is no cts + input wire wb_stb_i , // strobe/request + input wire [(BIST_NO_SRAM+1)/2-1:0] wb_cs_i , + input wire [BIST_ADDR_WD-1:0] wb_adr_i , // address + input wire wb_we_i , // write + input wire [BIST_DATA_WD-1:0] wb_dat_i , // data output + input wire [BIST_DATA_WD/8-1:0] wb_sel_i , // byte enable + input wire [9:0] wb_bl_i , // burst + input wire wb_bry_i , // burst ready + output wire [BIST_DATA_WD-1:0] wb_dat_o , // data input + output wire wb_ack_o , // acknowlegement + output wire wb_lack_o , // acknowlegement + output wire wb_err_o , // error - // towards memory - // PORT-A - output wire [BIST_NO_SRAM-1:0] mem_clk_a, - output wire [BIST_ADDR_WD-1:0] mem_addr_a0, - output wire [BIST_ADDR_WD-1:0] mem_addr_a1, - output wire [BIST_ADDR_WD-1:0] mem_addr_a2, - output wire [BIST_ADDR_WD-1:0] mem_addr_a3, - output wire [BIST_NO_SRAM-1:0] mem_cen_a, - output wire [BIST_NO_SRAM-1:0] mem_web_a, - output wire [BIST_DATA_WD/8-1:0] mem_mask_a0, - output wire [BIST_DATA_WD/8-1:0] mem_mask_a1, - output wire [BIST_DATA_WD/8-1:0] mem_mask_a2, - output wire [BIST_DATA_WD/8-1:0] mem_mask_a3, - output wire [BIST_DATA_WD-1:0] mem_din_a0, - output wire [BIST_DATA_WD-1:0] mem_din_a1, - output wire [BIST_DATA_WD-1:0] mem_din_a2, - output wire [BIST_DATA_WD-1:0] mem_din_a3, + // towards memory + // PORT-A + output wire [BIST_NO_SRAM-1:0] mem_clk_a , + output wire [BIST_ADDR_WD-1:0] mem_addr_a0 , + output wire [BIST_ADDR_WD-1:0] mem_addr_a1 , + output wire [BIST_ADDR_WD-1:0] mem_addr_a2 , + output wire [BIST_ADDR_WD-1:0] mem_addr_a3 , + output wire [BIST_NO_SRAM-1:0] mem_cen_a , + output wire [BIST_NO_SRAM-1:0] mem_web_a , + output wire [BIST_DATA_WD/8-1:0] mem_mask_a0 , + output wire [BIST_DATA_WD/8-1:0] mem_mask_a1 , + output wire [BIST_DATA_WD/8-1:0] mem_mask_a2 , + output wire [BIST_DATA_WD/8-1:0] mem_mask_a3 , + output wire [BIST_DATA_WD-1:0] mem_din_a0 , + output wire [BIST_DATA_WD-1:0] mem_din_a1 , + output wire [BIST_DATA_WD-1:0] mem_din_a2 , + output wire [BIST_DATA_WD-1:0] mem_din_a3 , - input wire [BIST_DATA_WD-1:0] mem_dout_a0, - input wire [BIST_DATA_WD-1:0] mem_dout_a1, - input wire [BIST_DATA_WD-1:0] mem_dout_a2, - input wire [BIST_DATA_WD-1:0] mem_dout_a3, + input wire [BIST_DATA_WD-1:0] mem_dout_a0 , + input wire [BIST_DATA_WD-1:0] mem_dout_a1 , + input wire [BIST_DATA_WD-1:0] mem_dout_a2 , + input wire [BIST_DATA_WD-1:0] mem_dout_a3 , - // PORT-B - output wire [BIST_NO_SRAM-1:0] mem_clk_b, - output wire [BIST_NO_SRAM-1:0] mem_cen_b, - output wire [BIST_ADDR_WD-1:0] mem_addr_b0, - output wire [BIST_ADDR_WD-1:0] mem_addr_b1, - output wire [BIST_ADDR_WD-1:0] mem_addr_b2, - output wire [BIST_ADDR_WD-1:0] mem_addr_b3 + // PORT-B + output wire [BIST_NO_SRAM-1:0] mem_clk_b , + output wire [BIST_NO_SRAM-1:0] mem_cen_b , + output wire [BIST_ADDR_WD-1:0] mem_addr_b0 , + output wire [BIST_ADDR_WD-1:0] mem_addr_b1 , + output wire [BIST_ADDR_WD-1:0] mem_addr_b2 , + output wire [BIST_ADDR_WD-1:0] mem_addr_b3 ); parameter NO_SRAM_WD = (BIST_NO_SRAM+1)/2; -parameter BIST1_ADDR_WD = 11; // 512x32 SRAM logic mem_req; // strobe/request logic [(BIST_NO_SRAM+1)/2-1:0] mem_cs; @@ -152,129 +159,126 @@ logic [BIST_DATA_WD-1:0] mem_rdata; // data input +//Scan FEED Throug +assign scan_en_o = scan_en; +assign scan_mode_o = scan_mode; + + mbist_wb #( .BIST_NO_SRAM (4 ), - .BIST_ADDR_WD (BIST1_ADDR_WD-2 ), + .BIST_ADDR_WD (BIST_ADDR_WD ), .BIST_DATA_WD (BIST_DATA_WD ) ) u_wb ( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif - .rst_n (rst_n ), - // WB I/F - .wb_clk_i (wb_clk_i ), - .wb_stb_i (wb_stb_i ), - .wb_cs_i (wb_cs_i ), - .wb_adr_i (wb_adr_i ), - .wb_we_i (wb_we_i ), - .wb_dat_i (wb_dat_i ), - .wb_sel_i (wb_sel_i ), - .wb_bl_i (wb_bl_i ), - .wb_bry_i (wb_bry_i ), - .wb_dat_o (wb_dat_o ), - .wb_ack_o (wb_ack_o ), - .wb_lack_o (wb_lack_o ), - .wb_err_o ( ), - - .mem_req (mem_req ), - .mem_cs (mem_cs ), - .mem_addr (mem_addr ), - .mem_we (mem_we ), - .mem_wdata (mem_wdata ), - .mem_wmask (mem_wmask ), - .mem_rdata (mem_rdata ) - - - - + .rst_n (rst_n ), + // WB I/F + .wb_clk_i (wb_clk_i ), + .wb_stb_i (wb_stb_i ), + .wb_cs_i (wb_cs_i ), + .wb_adr_i (wb_adr_i ), + .wb_we_i (wb_we_i ), + .wb_dat_i (wb_dat_i ), + .wb_sel_i (wb_sel_i ), + .wb_bl_i (wb_bl_i ), + .wb_bry_i (wb_bry_i ), + .wb_dat_o (wb_dat_o ), + .wb_ack_o (wb_ack_o ), + .wb_lack_o (wb_lack_o ), + .wb_err_o ( ), + .mem_req (mem_req ), + .mem_cs (mem_cs ), + .mem_addr (mem_addr ), + .mem_we (mem_we ), + .mem_wdata (mem_wdata ), + .mem_wmask (mem_wmask ), + .mem_rdata (mem_rdata ) + ); -mbist_top #( +mbist_top # ( `ifndef SYNTHESIS .BIST_NO_SRAM (4 ), - .BIST_ADDR_WD (BIST1_ADDR_WD-2 ), + .BIST_ADDR_WD (BIST_ADDR_WD ), .BIST_DATA_WD (BIST_DATA_WD ), .BIST_ADDR_START (9'h000 ), .BIST_ADDR_END (9'h1FB ), .BIST_REPAIR_ADDR_START (9'h1FC ), - .BIST_RAD_WD_I (BIST1_ADDR_WD-2 ), - .BIST_RAD_WD_O (BIST1_ADDR_WD-2 ) + .BIST_RAD_WD_I (BIST_ADDR_WD ), + .BIST_RAD_WD_O (BIST_ADDR_WD ) `endif ) u_mbist ( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif + // Clock Skew adjust + .wbd_clk_int (wbd_clk_int ), + .cfg_cska_mbist (cfg_cska_mbist ), + .wbd_clk_skew (wbd_clk_skew ), + // WB I/F + .wb_clk2_i (wb_clk2_i ), + .wb_clk_i (wb_clk_i ), + .mem_req (mem_req ), + .mem_cs (mem_cs ), + .mem_addr (mem_addr ), + .mem_we (mem_we ), + .mem_wdata (mem_wdata ), + .mem_wmask (mem_wmask ), + .mem_rdata (mem_rdata ), + .rst_n (rst_n ), - // Clock Skew adjust - .wbd_clk_int (wbd_clk_int ), - .cfg_cska_mbist (cfg_cska_mbist ), - .wbd_clk_mbist (wbd_clk_mbist ), - - // WB I/F - .wb_clk2_i (wb_clk2_i ), - .wb_clk_i (wb_clk_i ), - .mem_req (mem_req ), - .mem_cs (mem_cs ), - .mem_addr (mem_addr ), - .mem_we (mem_we ), - .mem_wdata (mem_wdata ), - .mem_wmask (mem_wmask ), - .mem_rdata (mem_rdata ), - - .rst_n (rst_n ), - - - .bist_en (bist_en ), - .bist_run (bist_run ), - .bist_shift (bist_shift ), - .bist_load (bist_load ), - .bist_sdi (bist_sdi ), - - .bist_error_cnt3 (bist_error_cnt3 ), - .bist_error_cnt2 (bist_error_cnt2 ), - .bist_error_cnt1 (bist_error_cnt1 ), - .bist_error_cnt0 (bist_error_cnt0 ), - .bist_correct (bist_correct ), - .bist_error (bist_error ), - .bist_done (bist_done ), - .bist_sdo (bist_sdo ), + .bist_serial_sel (bist_serial_sel ), + .bist_en (bist_en ), + .bist_run (bist_run ), + .bist_shift (bist_shift ), + .bist_load (bist_load ), + .bist_sdi (bist_sdi ), + .bist_error_cnt3 (bist_error_cnt3 ), + .bist_error_cnt2 (bist_error_cnt2 ), + .bist_error_cnt1 (bist_error_cnt1 ), + .bist_error_cnt0 (bist_error_cnt0 ), + .bist_correct (bist_correct ), + .bist_error (bist_error ), + .bist_done (bist_done ), + .bist_sdo (bist_sdo ), // towards memory // PORT-A - .mem_clk_a (mem_clk_a ), - .mem_addr_a0 (mem_addr_a0 ), - .mem_addr_a1 (mem_addr_a1 ), - .mem_addr_a2 (mem_addr_a2 ), - .mem_addr_a3 (mem_addr_a3 ), - .mem_cen_a (mem_cen_a ), - .mem_web_a (mem_web_a ), - .mem_mask_a0 (mem_mask_a0 ), - .mem_mask_a1 (mem_mask_a1 ), - .mem_mask_a2 (mem_mask_a2 ), - .mem_mask_a3 (mem_mask_a3 ), - .mem_din_a0 (mem_din_a0 ), - .mem_din_a1 (mem_din_a1 ), - .mem_din_a2 (mem_din_a2 ), - .mem_din_a3 (mem_din_a3 ), - .mem_dout_a0 (mem_dout_a0 ), - .mem_dout_a1 (mem_dout_a1 ), - .mem_dout_a2 (mem_dout_a2 ), - .mem_dout_a3 (mem_dout_a3 ), + .mem_clk_a (mem_clk_a ), + .mem_addr_a0 (mem_addr_a0 ), + .mem_addr_a1 (mem_addr_a1 ), + .mem_addr_a2 (mem_addr_a2 ), + .mem_addr_a3 (mem_addr_a3 ), + .mem_cen_a (mem_cen_a ), + .mem_web_a (mem_web_a ), + .mem_mask_a0 (mem_mask_a0 ), + .mem_mask_a1 (mem_mask_a1 ), + .mem_mask_a2 (mem_mask_a2 ), + .mem_mask_a3 (mem_mask_a3 ), + .mem_din_a0 (mem_din_a0 ), + .mem_din_a1 (mem_din_a1 ), + .mem_din_a2 (mem_din_a2 ), + .mem_din_a3 (mem_din_a3 ), + .mem_dout_a0 (mem_dout_a0 ), + .mem_dout_a1 (mem_dout_a1 ), + .mem_dout_a2 (mem_dout_a2 ), + .mem_dout_a3 (mem_dout_a3 ), // PORT-B - .mem_clk_b (mem_clk_b ), - .mem_cen_b (mem_cen_b ), - .mem_addr_b0 (mem_addr_b0 ), - .mem_addr_b1 (mem_addr_b1 ), - .mem_addr_b2 (mem_addr_b2 ), - .mem_addr_b3 (mem_addr_b3 ) + .mem_clk_b (mem_clk_b ), + .mem_cen_b (mem_cen_b ), + .mem_addr_b0 (mem_addr_b0 ), + .mem_addr_b1 (mem_addr_b1 ), + .mem_addr_b2 (mem_addr_b2 ), + .mem_addr_b3 (mem_addr_b3 ) );
diff --git a/verilog/rtl/pinmux/src/pinmux_top.sv b/verilog/rtl/pinmux/src/pinmux_top.sv new file mode 100644 index 0000000..f4bae59 --- /dev/null +++ b/verilog/rtl/pinmux/src/pinmux_top.sv
@@ -0,0 +1,156 @@ + + +module pinmux_top #(parameter SCW = 8 // SCAN CHAIN WIDTH + ) ( + +`ifdef USE_POWER_PINS + inout vccd1, // User area 1 1.8V supply + inout vssd1, // User area 1 digital ground +`endif + + input logic mclk, + input logic reset_n, + + // Scan I/F + input logic scan_en, + input logic scan_mode, + input logic [SCW-1:0] scan_si, + output logic [SCW-1:0] scan_so, + output logic scan_en_o, + output logic scan_mode_o, + + // Clock Skew Adjust + input logic wbd_clk_int , + input logic [3:0] cfg_cska_pinmux, + output logic wbd_clk_skew , // clock skew adjust for web host + + + // Reg Bus Interface Signal + input logic reg_cs, + input logic reg_wr, + input logic [7:0] reg_addr, + input logic [31:0] reg_wdata, + input logic [3:0] reg_be, + + // Outputs + output logic [31:0] reg_rdata, + output logic reg_ack, + + // BIST I/F + output logic bist_en, + output logic bist_run, + output logic bist_load, + + output logic [1:0] bist_serial_sel, + output logic bist_sdi, + output logic bist_shift, + input logic bist_sdo, + + input logic bist_done, + input logic [3:0] bist_error, + input logic [3:0] bist_correct, + input logic [3:0] bist_error_cnt0, + input logic [3:0] bist_error_cnt1, + input logic [3:0] bist_error_cnt2, + input logic [3:0] bist_error_cnt3, + + + //----------------------------------------------------------------------- + // MAC-Tx Signal + //----------------------------------------------------------------------- + input logic mac_tx_en , + input logic mac_tx_er , + input logic [7:0] mac_txd , + output logic mac_tx_clk , + + //----------------------------------------------------------------------- + // MAC-Rx Signal + //----------------------------------------------------------------------- + output logic mac_rx_clk , + output logic mac_rx_er , + output logic mac_rx_dv , + output logic [7:0] mac_rxd , + output logic mac_crs , + + + //----------------------------------------------------------------------- + // MDIO Signal + //----------------------------------------------------------------------- + output logic mdio_clk , + output logic mdio_in , + input logic mdio_out_en , + input logic mdio_out + + + + ); + + +//----------------------------------------------------------------------- +// Main code starts here +//----------------------------------------------------------------------- + + +assign scan_en_o = scan_en; +assign scan_mode_o = scan_mode; + + +// wb_host clock skew control +clk_skew_adjust u_skew_glbl + ( +`ifdef USE_POWER_PINS + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground +`endif + .clk_in (wbd_clk_int ), + .sel (cfg_cska_pinmux ), + .clk_out (wbd_clk_skew ) + ); + + + +glbl_cfg u_glbl( +`ifdef USE_POWER_PINS + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground +`endif + + .mclk (mclk ), + .reset_n (reset_n ), + + // Reg Bus Interface Signal + .reg_cs (reg_cs ), + .reg_wr (reg_wr ), + .reg_addr (reg_addr ), + .reg_wdata (reg_wdata ), + .reg_be (reg_be ), + + // Outputs + .reg_rdata (reg_rdata ), + .reg_ack (reg_ack ), + + + // BIST I/F + .bist_en (bist_en ), + .bist_run (bist_run ), + .bist_load (bist_load ), + + .bist_serial_sel (bist_serial_sel ), + .bist_sdi (bist_sdi ), + .bist_shift (bist_shift ), + .bist_sdo (bist_sdo ), + + .bist_done (bist_done ), + .bist_error (bist_error ), + .bist_correct (bist_correct ), + .bist_error_cnt0 (bist_error_cnt0 ), + .bist_error_cnt1 (bist_error_cnt1 ), + .bist_error_cnt2 (bist_error_cnt2 ), + .bist_error_cnt3 (bist_error_cnt3 ) + ); + + + + +endmodule +
diff --git a/verilog/rtl/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v b/verilog/rtl/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v new file mode 100644 index 0000000..289a770 --- /dev/null +++ b/verilog/rtl/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v
@@ -0,0 +1,114 @@ +// OpenRAM SRAM model +// Words: 512 +// Word size: 32 +// Write size: 8 + +module sky130_sram_2kbyte_1rw1r_32x512_8( +`ifdef USE_POWER_PINS + vccd1, + vssd1, +`endif +// Port 0: RW + clk0,csb0,web0,wmask0,addr0,din0,dout0, +// Port 1: R + clk1,csb1,addr1,dout1 + ); + + parameter NUM_WMASKS = 4 ; + parameter DATA_WIDTH = 32 ; + parameter ADDR_WIDTH = 9 ; + parameter RAM_DEPTH = 1 << ADDR_WIDTH; + // FIXME: This delay is arbitrary. + parameter DELAY = 3 ; + parameter VERBOSE = 0 ; //Set to 0 to only display warnings + parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary + +`ifdef USE_POWER_PINS + inout vccd1; + inout vssd1; +`endif + input clk0; // clock + input csb0; // active low chip select + input web0; // active low write control + input [NUM_WMASKS-1:0] wmask0; // write mask + input [ADDR_WIDTH-1:0] addr0; + input [DATA_WIDTH-1:0] din0; + output [DATA_WIDTH-1:0] dout0; + input clk1; // clock + input csb1; // active low chip select + input [ADDR_WIDTH-1:0] addr1; + output [DATA_WIDTH-1:0] dout1; + + reg csb0_reg; + reg web0_reg; + reg [NUM_WMASKS-1:0] wmask0_reg; + reg [ADDR_WIDTH-1:0] addr0_reg; + reg [DATA_WIDTH-1:0] din0_reg; + reg [DATA_WIDTH-1:0] dout0; + + // All inputs are registers + always @(posedge clk0) + begin + csb0_reg = csb0; + web0_reg = web0; + wmask0_reg = wmask0; + addr0_reg = addr0; + din0_reg = din0; + #(T_HOLD) dout0 = 32'bx; + if ( !csb0_reg && web0_reg && VERBOSE ) + $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]); + if ( !csb0_reg && !web0_reg && VERBOSE ) + $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg); + end + + reg csb1_reg; + reg [ADDR_WIDTH-1:0] addr1_reg; + reg [DATA_WIDTH-1:0] dout1; + + // All inputs are registers + always @(posedge clk1) + begin + csb1_reg = csb1; + addr1_reg = addr1; + if (!csb0 && !web0 && !csb1 && (addr0 == addr1)) + $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1); + #(T_HOLD) dout1 = 32'bx; + if ( !csb1_reg && VERBOSE ) + $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]); + end + +reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; + + // Memory Write Block Port 0 + // Write Operation : When web0 = 0, csb0 = 0 + always @ (negedge clk0) + begin : MEM_WRITE0 + if ( !csb0_reg && !web0_reg ) begin + if (wmask0_reg[0]) + mem[addr0_reg][7:0] = din0_reg[7:0]; + if (wmask0_reg[1]) + mem[addr0_reg][15:8] = din0_reg[15:8]; + if (wmask0_reg[2]) + mem[addr0_reg][23:16] = din0_reg[23:16]; + if (wmask0_reg[3]) + mem[addr0_reg][31:24] = din0_reg[31:24]; + end + end + + // Memory Read Block Port 0 + // Read Operation : When web0 = 1, csb0 = 0 + always @ (negedge clk0) + begin : MEM_READ0 + if (!csb0_reg && web0_reg) + dout0 <= #(DELAY) mem[addr0_reg]; + end + + // Memory Read Block Port 1 + // Read Operation : When web1 = 1, csb1 = 0 + always @ (negedge clk1) + begin : MEM_READ1 + if (!csb1_reg) + dout1 <= #(DELAY) mem[addr1_reg]; + end + +endmodule
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 62c35bf..50ce3b6 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -19,65 +19,32 @@ //// //// //// Digital core //// //// //// -//// This file is part of the mbist_ctrl project //// -//// https://github.com/dineshannayya/mbist_ctrl.git //// +//// This file is part of the riscduino-pxt project //// +//// https://github.com/dineshannayya/riscduino_pxt1.git //// //// //// //// Description //// //// This is digital core and integrate all the main block //// //// here. //// //// 1. Wishbone Host //// //// 2. 4x MBIST Controller //// -//// 3. 2x SRAM 2KB //// -//// 4. 2x SRAM 1KB //// -//// 5. Wishbone Interconnect //// -//// 6. Global Register //// +//// 3. 4x SRAM 2KB //// +//// 4. Wishbone Interconnect //// +//// 5. Global Register //// +//// 6. GMAC //// //// //// //// To Do: //// //// nothing //// //// //// //// Author(s): //// -//// - Dinesh Annayya, dinesha@opencores.org //// +//// - Dinesh Annayya, dinesh.annayya@gmail.com //// //// //// //// Revision : //// -//// 0.1 - 13th Oct 2021, Dinesh A //// +//// 0.1 - 15th Dec 2022, Dinesh A //// //// Initial Version //// -//// 0.2 - 19, Nov 2021, Dinesh A //// -//// Following things are integrated //// -//// 2x SRAM 2KB, 2x SRAM 1KB, 4 MBIST , //// -//// 1 Wishbone Interconnect, 1 Global register //// -//// 0.3 - 20, Nov 2021, Dinesh A //// -//// Following are integrated //// -//// 4x SRAM 2KB, 4x SRAM 1KB, 8 MBIST , //// -//// 1 Wishbone Interconnect, 1 Global register //// -//// 0.4 - 23 Nov 2021, Dinesh A //// -//// Three Software Register added for signature at glbl //// -//// 1.0 - 01 Dec 2021, Dinesh A -MPW-4 //// -//// A. Logic Bist Integrated inside the Wb_host //// -//// B. Below Scan chain created //// -//// WB_HOST(LBIST) => GLBL => MBIST5 => MBIST6 => MBIST7 //// -//// => MBIST8 => WB_INTERCONNECT => MBIST4 => MBIST3 => //// -//// MBIST2 => MBIST1 => WB_HOST(LBIST) //// -//// 1.1 - 03 Dec 2021, Dinesh A //// -//// Timing closure clean-up //// -//// 1.2 - 10 Dec 2021, Dinesh A //// -//// Full Chip Timing closure wth caravel //// -//// 1.3 - 21 Dec 2021, Dinesh A //// -//// A. LBIST bypass added, SCAN can be controlled through //// -//// LA ports //// -//// B. LBIST reset chain check compare bypass added //// -//// 1.4 Jan 02, 2022, Dinesh A //// -//// 1. LA[0] is added as soft reset option at wb_port //// -//// 2. Uart Master is added at wb_port //// -//// 1.5 Feb 18, 2022, Dinesh A //// -//// As SRAM timing model are not accurate, added additionl //// -//// drive data towards SRAM in negedge phase(cfg_mem_lphase)/// -//// 1.6 Mar 16, 2022, Dinesh A //// -//// RTL changes in wb_host to fix caraval wb address //// -//// reduction to 0x3000_0000 to 0x300F_FFFF //// ////////////////////////////////////////////////////////////////////// `default_nettype none -module user_project_wrapper( +module user_project_wrapper ( `ifdef USE_POWER_PINS inout vdda1, // User area 1 3.3V supply inout vdda2, // User area 2 3.3V supply @@ -89,16 +56,16 @@ inout vssd2, // User area 2 digital ground `endif - // Wishbone Slave ports (WB MI A) - input wb_clk_i, - input wb_rst_i, - input wbs_stb_i, - input wbs_cyc_i, - input wbs_we_i, - input [3:0] wbs_sel_i, - input [31:0] wbs_dat_i, - input [31:0] wbs_adr_i, - output wbs_ack_o, + // Wishbone Slave ports (WB MI A ) + input wb_clk_i, + input wb_rst_i, + input wbs_stb_i, + input wbs_cyc_i, + input wbs_we_i, + input [3:0] wbs_sel_i, + input [31:0] wbs_dat_i, + input [31:0] wbs_adr_i, + output wbs_ack_o, output [31:0] wbs_dat_o, // Logic Analyzer Signals @@ -114,7 +81,7 @@ // Analog (direct connection to GPIO pad---use with caution) // Note that analog I/O is not available on the 7 lowest-numbered // GPIO pads, and so the analog_io indexing is offset from the - // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io). + // GPIO indexing by (also upper 2 GPIOs do not havanalog_io ) . inout [28:0] analog_io, // Independent clock (on independent integer divider) @@ -124,390 +91,258 @@ output [2:0] user_irq ); -parameter BIST1_ADDR_WD = 11; // 512x32 SRAM -parameter BIST2_ADDR_WD = 10; // 256x32 SRAM +parameter BIST_ADDR_WD = 9; // 512x32 SRAM parameter BIST_DATA_WD = 32; parameter WB_WIDTH = 32; // WB ADDRESS/DARA WIDTH +parameter BIST_NO_SRAM = 4; parameter SCW = 8; // SCAN CHAIN WIDTH //--------------------------------------------------------------------- -// WB HOST Interface +// WB HOST <=> WB Interconnect Interface //--------------------------------------------------------------------- -wire wbd_int_cyc_i; // strobe/request -wire wbd_int_stb_i; // strobe/request -wire [WB_WIDTH-1:0] wbd_int_adr_i; // address -wire wbd_int_we_i; // write -wire [WB_WIDTH-1:0] wbd_int_dat_i; // data output -wire [3:0] wbd_int_sel_i; // byte enable -wire [WB_WIDTH-1:0] wbd_int_dat_o; // data input -wire wbd_int_ack_o; // acknowlegement -wire wbd_int_err_o; // error +wire wbd_int_cyc_i ; // strobe/request +wire wbd_int_stb_i ; // strobe/request +wire [WB_WIDTH-1:0] wbd_int_adr_i ; // address +wire wbd_int_we_i ; // write +wire [WB_WIDTH-1:0] wbd_int_dat_i ; // data output +wire [3:0] wbd_int_sel_i ; // byte enable +wire [WB_WIDTH-1:0] wbd_int_dat_o ; // data input +wire wbd_int_ack_o ; // acknowlegement +wire wbd_int_err_o ; // error //--------------------------------------------------------------------- -// Global Register Wishbone Interface +// Pinmux Register <==> WB Interconnect Interface //--------------------------------------------------------------------- -wire wbd_glbl_stb_o; // strobe/request -wire [7:0] wbd_glbl_adr_o; // address -wire wbd_glbl_we_o; // write -wire [WB_WIDTH-1:0] wbd_glbl_dat_o; // data output -wire [3:0] wbd_glbl_sel_o; // byte enable -wire wbd_glbl_cyc_o ; -wire [WB_WIDTH-1:0] wbd_glbl_dat_i; // data input -wire wbd_glbl_ack_i; // acknowlegement -wire wbd_glbl_err_i; // error +wire wbd_pinmux_stb_o ; // strobe/request +wire [7:0] wbd_pinmux_adr_o ; // address +wire wbd_pinmux_we_o ; // write +wire [WB_WIDTH-1:0] wbd_pinmux_dat_o ; // data output +wire [3:0] wbd_pinmux_sel_o ; // byte enable +wire wbd_pinmux_cyc_o ; +wire [WB_WIDTH-1:0] wbd_pinmux_dat_i ; // data input +wire wbd_pinmux_ack_i ; // acknowlegement +wire wbd_pinmux_err_i ; // error //--------------------------------------------------------------------- -// MBIST1 +// MBIST <===> WB Interconnect Interface //--------------------------------------------------------------------- -wire wbd_mbist1_stb_o; // strobe/request -wire [BIST1_ADDR_WD-1:0] wbd_mbist1_adr_o; // address -wire wbd_mbist1_we_o; // write -wire [WB_WIDTH-1:0] wbd_mbist1_dat_o; // data output -wire [3:0] wbd_mbist1_sel_o; // byte enable -wire wbd_mbist1_cyc_o ; -wire [WB_WIDTH-1:0] wbd_mbist1_dat_i; // data input -wire wbd_mbist1_ack_i; // acknowlegement -wire wbd_mbist1_err_i; // error - -//--------------------------------------------------------------------- -// MBIST2 -//--------------------------------------------------------------------- -wire wbd_mbist2_stb_o; // strobe/request -wire [BIST1_ADDR_WD-1:0] wbd_mbist2_adr_o; // address -wire wbd_mbist2_we_o; // write -wire [WB_WIDTH-1:0] wbd_mbist2_dat_o; // data output -wire [3:0] wbd_mbist2_sel_o; // byte enable -wire wbd_mbist2_cyc_o ; -wire [WB_WIDTH-1:0] wbd_mbist2_dat_i; // data input -wire wbd_mbist2_ack_i; // acknowlegement -wire wbd_mbist2_err_i; // error - -//--------------------------------------------------------------------- -// MBIST3 -//--------------------------------------------------------------------- -wire wbd_mbist3_stb_o; // strobe/request -wire [BIST1_ADDR_WD-1:0] wbd_mbist3_adr_o; // address -wire wbd_mbist3_we_o; // write -wire [WB_WIDTH-1:0] wbd_mbist3_dat_o; // data output -wire [3:0] wbd_mbist3_sel_o; // byte enable -wire wbd_mbist3_cyc_o ; -wire [WB_WIDTH-1:0] wbd_mbist3_dat_i; // data input -wire wbd_mbist3_ack_i; // acknowlegement -wire wbd_mbist3_err_i; // error - -//--------------------------------------------------------------------- -// MBIST4 -//--------------------------------------------------------------------- -wire wbd_mbist4_stb_o; // strobe/request -wire [BIST1_ADDR_WD-1:0] wbd_mbist4_adr_o; // address -wire wbd_mbist4_we_o; // write -wire [WB_WIDTH-1:0] wbd_mbist4_dat_o; // data output -wire [3:0] wbd_mbist4_sel_o; // byte enable -wire wbd_mbist4_cyc_o ; -wire [WB_WIDTH-1:0] wbd_mbist4_dat_i; // data input -wire wbd_mbist4_ack_i; // acknowlegement -wire wbd_mbist4_err_i; // error - -//--------------------------------------------------------------------- -// MBIST5 -//--------------------------------------------------------------------- -wire wbd_mbist5_stb_o; // strobe/request -wire [BIST2_ADDR_WD-1:0] wbd_mbist5_adr_o; // address -wire wbd_mbist5_we_o; // write -wire [WB_WIDTH-1:0] wbd_mbist5_dat_o; // data output -wire [3:0] wbd_mbist5_sel_o; // byte enable -wire wbd_mbist5_cyc_o ; -wire [WB_WIDTH-1:0] wbd_mbist5_dat_i; // data input -wire wbd_mbist5_ack_i; // acknowlegement -wire wbd_mbist5_err_i; // error - -//--------------------------------------------------------------------- -// MBIST6 -//--------------------------------------------------------------------- -wire wbd_mbist6_stb_o; // strobe/request -wire [BIST2_ADDR_WD-1:0] wbd_mbist6_adr_o; // address -wire wbd_mbist6_we_o; // write -wire [WB_WIDTH-1:0] wbd_mbist6_dat_o; // data output -wire [3:0] wbd_mbist6_sel_o; // byte enable -wire wbd_mbist6_cyc_o ; -wire [WB_WIDTH-1:0] wbd_mbist6_dat_i; // data input -wire wbd_mbist6_ack_i; // acknowlegement -wire wbd_mbist6_err_i; // error - -//--------------------------------------------------------------------- -// MBIST7 -//--------------------------------------------------------------------- -wire wbd_mbist7_stb_o; // strobe/request -wire [BIST2_ADDR_WD-1:0] wbd_mbist7_adr_o; // address -wire wbd_mbist7_we_o; // write -wire [WB_WIDTH-1:0] wbd_mbist7_dat_o; // data output -wire [3:0] wbd_mbist7_sel_o; // byte enable -wire wbd_mbist7_cyc_o ; -wire [WB_WIDTH-1:0] wbd_mbist7_dat_i; // data input -wire wbd_mbist7_ack_i; // acknowlegement -wire wbd_mbist7_err_i; // error - -//--------------------------------------------------------------------- -// MBIST8 -//--------------------------------------------------------------------- -wire wbd_mbist8_stb_o; // strobe/request -wire [BIST2_ADDR_WD-1:0] wbd_mbist8_adr_o; // address -wire wbd_mbist8_we_o; // write -wire [WB_WIDTH-1:0] wbd_mbist8_dat_o; // data output -wire [3:0] wbd_mbist8_sel_o; // byte enable -wire wbd_mbist8_cyc_o ; -wire [WB_WIDTH-1:0] wbd_mbist8_dat_i; // data input -wire wbd_mbist8_ack_i; // acknowlegement -wire wbd_mbist8_err_i; // error +wire wbd_mbist_stb_o ; // strobe/request +wire [12:0] wbd_mbist_adr_o ; // address +wire wbd_mbist_we_o ; // write +wire [WB_WIDTH-1:0] wbd_mbist_dat_o ; // data output +wire [3:0] wbd_mbist_sel_o ; // byte enable +wire [9:0] wbd_mbist_bl_o ; // Burst Length +wire wbd_mbist_bry_o ; // Burst Ready +wire wbd_mbist_cyc_o ; +wire [WB_WIDTH-1:0] wbd_mbist_dat_i ; // data input +wire wbd_mbist_ack_i ; // acknowlegement +wire wbd_mbist_err_i ; // error -wire wbd_int_rst_n; -wire bist_rst_n; +//-------------------------------------------- +// GMAC TX WB Master I/F +//-------------------------------------------- +wire [31:0] wbm_gtx_dat_i ; +wire wbm_gtx_ack_i ; +wire [31:0] wbm_gtx_dat_o ; +wire [12:0] wbm_gtx_adr_o ; +wire [3:0] wbm_gtx_sel_o ; +wire wbm_gtx_we_o ; +wire wbm_gtx_stb_o ; +wire wbm_gtx_cyc_o ; + +//-------------------------------------------- +// GMAC RX WB Master I/F +//-------------------------------------------- +wire [31:0] wbm_grx_dat_i ; +wire wbm_grx_ack_i ; +wire [31:0] wbm_grx_dat_o ; +wire [12:0] wbm_grx_adr_o ; +wire [3:0] wbm_grx_sel_o ; +wire wbm_grx_we_o ; +wire wbm_grx_stb_o ; +wire wbm_grx_cyc_o ; + +//-------------------------------------------- +// GMAC REG WB SLAVE I/F +//-------------------------------------------- +wire [31:0] wbs_grg_dat_o ; +wire wbs_grg_ack_o ; +wire [31:0] wbs_grg_dat_i ; +wire [12:0] wbs_grg_adr_i ; +wire [3:0] wbs_grg_sel_i ; +wire wbs_grg_we_i ; +wire wbs_grg_stb_i ; +wire wbs_grg_cyc_i ; + +//---------------------------------------------------- + +wire wbd_int_rst_n ; +wire bist_rst_n ; +wire mac_rst_n ; + +//---------------------------------------------------------------------- // MBIST I/F -wire [7:0] bist_en; -wire [7:0] bist_run; -wire [7:0] bist_shift; -wire [7:0] bist_load; -wire [7:0] bist_sdi; +//---------------------------------------------------------------------- +wire bist_en ; +wire bist_run ; +wire bist_shift ; +wire bist_load ; +wire bist_sdi ; +wire [1:0] bist_serial_sel ; -wire [7:0] bist_correct; -wire [7:0] bist_error; -wire [7:0] bist_done; -wire [7:0] bist_sdo; +wire [3:0] bist_correct ; +wire [3:0] bist_error ; +wire bist_done ; +wire bist_sdo ; -wire [3:0] bist_error_cnt0; -wire [3:0] bist_error_cnt1; -wire [3:0] bist_error_cnt2; +wire [3:0] bist_error_cnt0 ; +wire [3:0] bist_error_cnt1 ; +wire [3:0] bist_error_cnt2 ; wire [3:0] bist_error_cnt3; -wire [3:0] bist_error_cnt4; -wire [3:0] bist_error_cnt5; -wire [3:0] bist_error_cnt6; -wire [3:0] bist_error_cnt7; -// MBIST I/F Buffered -wire [7:0] bist_en_int; -wire [7:0] bist_run_int; -wire [7:0] bist_shift_int; -wire [7:0] bist_load_int; -wire [7:0] bist_sdi_int; +// MBIST I/F Bus Repeater +wire bist_en_rp ; +wire bist_run_rp ; +wire bist_shift_rp ; +wire bist_load_rp ; +wire bist_sdi_rp ; -wire [7:0] bist_correct_int; -wire [7:0] bist_error_int; -wire [7:0] bist_done_int; -wire [7:0] bist_sdo_int; +wire [3:0] bist_correct_rp ; +wire [3:0] bist_error_rp ; +wire bist_done_rp ; +wire bist_sdo_rp ; -wire [3:0] bist_error_cnt0_int; -wire [3:0] bist_error_cnt1_int; -wire [3:0] bist_error_cnt2_int; -wire [3:0] bist_error_cnt3_int; -wire [3:0] bist_error_cnt4_int; -wire [3:0] bist_error_cnt5_int; -wire [3:0] bist_error_cnt6_int; -wire [3:0] bist_error_cnt7_int; +wire [3:0] bist_error_cnt0_rp ; +wire [3:0] bist_error_cnt1_rp ; +wire [3:0] bist_error_cnt2_rp ; +wire [3:0] bist_error_cnt3_rp ; -// towards memory MBIST1 -// PORT-A -wire mem1_clk_a; -wire [BIST1_ADDR_WD-1:2] mem1_addr_a; -wire mem1_cen_a; -wire [BIST_DATA_WD-1:0] mem1_din_b; +//----------------------------------------------------- +// towards MBIST <==> memory 0/1/2/3 +//------------------------------------------------------ +// PORT-A Common Signals +wire [BIST_NO_SRAM-1:0] mem_clk_a ; +wire [BIST_NO_SRAM-1:0] mem_cen_a ; +wire [BIST_NO_SRAM-1:0] mem_web_a ; -// PORT-B -wire mem1_clk_b; -wire mem1_cen_b; -wire mem1_web_b; -wire [BIST_DATA_WD/8-1:0] mem1_mask_b; -wire [BIST1_ADDR_WD-1:2] mem1_addr_b; -wire [BIST_DATA_WD-1:0] mem1_dout_a; +// MEM0 - PORT-A Signals +wire [BIST_ADDR_WD-1:0] mem0_addr_a ; +wire [BIST_DATA_WD/8-1:0] mem0_mask_a ; +wire [BIST_DATA_WD-1:0] mem0_din_a ; +wire [BIST_DATA_WD-1:0] mem0_dout_a ; -// towards memory MBIST2 -// PORT-A -wire mem2_clk_a; -wire [BIST1_ADDR_WD-1:2] mem2_addr_a; -wire mem2_cen_a; -wire [BIST_DATA_WD-1:0] mem2_din_b; +// MEM1 - PORT-A Signals +wire [BIST_ADDR_WD-1:0] mem1_addr_a ; +wire [BIST_DATA_WD/8-1:0] mem1_mask_a ; +wire [BIST_DATA_WD-1:0] mem1_din_a ; +wire [BIST_DATA_WD-1:0] mem1_dout_a ; -// PORT-B -wire mem2_clk_b; -wire mem2_cen_b; -wire mem2_web_b; -wire [BIST_DATA_WD/8-1:0] mem2_mask_b; -wire [BIST1_ADDR_WD-1:2] mem2_addr_b; -wire [BIST_DATA_WD-1:0] mem2_dout_a; +// MEM2 - PORT-A Signals +wire [BIST_ADDR_WD-1:0] mem2_addr_a ; +wire [BIST_DATA_WD/8-1:0] mem2_mask_a ; +wire [BIST_DATA_WD-1:0] mem2_din_a ; +wire [BIST_DATA_WD-1:0] mem2_dout_a ; -// towards memory MBIST3 -// PORT-A -wire mem3_clk_a; -wire [BIST1_ADDR_WD-1:2] mem3_addr_a; -wire mem3_cen_a; -wire [BIST_DATA_WD-1:0] mem3_din_b; +// MEM3 - PORT-A Signals +wire [BIST_ADDR_WD-1:0] mem3_addr_a ; +wire [BIST_DATA_WD/8-1:0] mem3_mask_a ; +wire [BIST_DATA_WD-1:0] mem3_din_a ; +wire [BIST_DATA_WD-1:0] mem3_dout_a ; -// PORT-B -wire mem3_clk_b; -wire mem3_cen_b; -wire mem3_web_b; -wire [BIST_DATA_WD/8-1:0] mem3_mask_b; -wire [BIST1_ADDR_WD-1:2] mem3_addr_b; -wire [BIST_DATA_WD-1:0] mem3_dout_a; +// PORT-B Signals +wire [BIST_NO_SRAM-1:0] mem_clk_b ; +wire [BIST_NO_SRAM-1:0] mem_cen_b ; -// towards memory MBIST4 -// PORT-A -wire mem4_clk_a; -wire [BIST1_ADDR_WD-1:2] mem4_addr_a; -wire mem4_cen_a; -wire [BIST_DATA_WD-1:0] mem4_din_b; +wire [BIST_ADDR_WD-1:0] mem0_addr_b ; +wire [BIST_ADDR_WD-1:0] mem1_addr_b ; +wire [BIST_ADDR_WD-1:0] mem2_addr_b ; +wire [BIST_ADDR_WD-1:0] mem3_addr_b ; -// PORT-B -wire mem4_clk_b; -wire mem4_cen_b; -wire mem4_web_b; -wire [BIST_DATA_WD/8-1:0] mem4_mask_b; -wire [BIST1_ADDR_WD-1:2] mem4_addr_b; -wire [BIST_DATA_WD-1:0] mem4_dout_a; +//---------------------------------------------------- +// Clock & clock skew feed through +//-------------------------------------------------- +wire wbd_clk_pinmux_rp ; +wire wbd_clk_mbist_rp ; +wire wbd_clk_mac_rp ; -// towards memory MBIST5 -// PORT-A -wire mem5_clk_a; -wire [BIST2_ADDR_WD-1:2] mem5_addr_a; -wire mem5_cen_a; -wire [BIST_DATA_WD-1:0] mem5_din_b; - -// PORT-B -wire mem5_clk_b; -wire mem5_cen_b; -wire mem5_web_b; -wire [BIST_DATA_WD/8-1:0] mem5_mask_b; -wire [BIST2_ADDR_WD-1:2] mem5_addr_b; -wire [BIST_DATA_WD-1:0] mem5_dout_a; - -// towards memory MBIST6 -// PORT-A -wire mem6_clk_a; -wire [BIST2_ADDR_WD-1:2] mem6_addr_a; -wire mem6_cen_a; -wire [BIST_DATA_WD-1:0] mem6_din_b; - -// PORT-B -wire mem6_clk_b; -wire mem6_cen_b; -wire mem6_web_b; -wire [BIST_DATA_WD/8-1:0] mem6_mask_b; -wire [BIST2_ADDR_WD-1:2] mem6_addr_b; -wire [BIST_DATA_WD-1:0] mem6_dout_a; - -// towards memory MBIST7 -// PORT-A -wire mem7_clk_a; -wire [BIST2_ADDR_WD-1:2] mem7_addr_a; -wire mem7_cen_a; -wire [BIST_DATA_WD-1:0] mem7_din_b; - -// PORT-B -wire mem7_clk_b; -wire mem7_cen_b; -wire mem7_web_b; -wire [BIST_DATA_WD/8-1:0] mem7_mask_b; -wire [BIST2_ADDR_WD-1:2] mem7_addr_b; -wire [BIST_DATA_WD-1:0] mem7_dout_a; - -// towards memory MBIST8 -// PORT-A -wire mem8_clk_a; -wire [BIST2_ADDR_WD-1:2] mem8_addr_a; -wire mem8_cen_a; -wire [BIST_DATA_WD-1:0] mem8_din_b; - -// PORT-B -wire mem8_clk_b; -wire mem8_cen_b; -wire mem8_web_b; -wire [BIST_DATA_WD/8-1:0] mem8_mask_b; -wire [BIST2_ADDR_WD-1:2] mem8_addr_b; -wire [BIST_DATA_WD-1:0] mem8_dout_a; +wire wbd_clk_wi_skew ; +wire wbd_clk_pinmux_skew ; +wire wbd_clk_mbist_skew ; +wire wbd_clk_mac_skew ; wire lbist_clk ; wire wbd_clk_wh ; wire wbd_clk_int ; -wire wbd_clk_glbl_int ; -wire wbd_clk_mbist1_int ; -wire wbd_clk_mbist2_int ; -wire wbd_clk_mbist3_int ; -wire wbd_clk_mbist4_int ; -wire wbd_clk_mbist5_int ; -wire wbd_clk_mbist6_int ; -wire wbd_clk_mbist7_int ; -wire wbd_clk_mbist8_int ; -wire wbd_clk_wi ; -wire wbd_clk_glbl ; // clock for global reg -wire wbd_clk_mbist1 ; // clock for global reg -wire wbd_clk_mbist2 ; // clock for global reg -wire wbd_clk_mbist3 ; // clock for global reg -wire wbd_clk_mbist4 ; // clock for global reg -wire wbd_clk_mbist5 ; // clock for global reg -wire wbd_clk_mbist6 ; // clock for global reg -wire wbd_clk_mbist7 ; // clock for global reg -wire wbd_clk_mbist8 ; // clock for global reg - wire [31:0] cfg_clk_ctrl1 ; wire [31:0] cfg_clk_ctrl2 ; +//--------------------------------------------------- // Scan Control Signal -wire scan_clk ; -wire scan_rst_n ; - -wire scan_mode ; -wire scan_en ; -wire [SCW-1:0] scan_in ; -wire [SCW-1:0] scan_out ; - -wire scan_mode_glbl ; -wire scan_en_glbl ; -wire [SCW-1:0] scan_out_glbl ; - -wire scan_mode_wbi ; -wire scan_en_wbi ; -wire [SCW-1:0] scan_out_wbi ; - -wire scan_mode_mbist1 ; -wire scan_en_mbist1 ; -wire [SCW-1:0] scan_out_mbist1 ; - -wire scan_mode_mbist2 ; -wire scan_en_mbist2 ; -wire [SCW-1:0] scan_out_mbist2 ; - -wire scan_mode_mbist3 ; -wire scan_en_mbist3 ; -wire [SCW-1:0] scan_out_mbist3 ; - -wire scan_mode_mbist4 ; -wire scan_en_mbist4 ; -wire [SCW-1:0] scan_out_mbist4 ; - -wire scan_mode_mbist5 ; -wire scan_en_mbist5 ; -wire [SCW-1:0] scan_out_mbist5 ; - -wire scan_mode_mbist6 ; -wire scan_en_mbist6 ; -wire [SCW-1:0] scan_out_mbist6 ; - -wire scan_mode_mbist7 ; -wire scan_en_mbist7 ; -wire [SCW-1:0] scan_out_mbist7 ; - -wire scan_mode_mbist8 ; -wire scan_en_mbist8 ; -wire [SCW-1:0] scan_out_mbist8 ; - +//--------------------------------------------------- //////////////////////////////////////////////////////////// // Scan Tree Map /////////////////////////////////////////////////////////// -// WB_HOST(LBIST) => GLBL => MBIST5 => MBIST6 => MBIST7 -// => MBIST8 => WB_INTERCONNECT => MBIST4 => MBIST3 -// => MBIST2 => MBIST1 => WB_HOST(LBIST) +// WB_HOST(LBIST) => GLBL => MBIST => WB_INTERCONNECT => WB_HOST(LBIST) +wire scan_clk ; // Scan Clock +wire scan_rst_n ; // Scan Reset + +wire scan_mode ; // Scan Mode +wire scan_en ; // Scan Enable +wire [SCW-1:0] scan_in ; // Scan Chain-In +wire [SCW-1:0] scan_out ; // Scan Chain Out + +wire scan_mode_pinmux ; +wire scan_en_pinmux ; +wire [SCW-1:0] scan_out_pinmux ; + +wire scan_mode_wbi ; +wire scan_en_wbi ; +wire [SCW-1:0] scan_out_wbi ; + +wire scan_mode_mbist ; +wire scan_en_mbist ; +wire [SCW-1:0] scan_out_mbist ; + +//----------------------------------------------------------------------- +// MAC Line-Tx Signal +//----------------------------------------------------------------------- +wire mac_tx_en ; +wire mac_tx_er ; +wire [7:0] mac_txd ; +wire mac_tx_clk ; + +//----------------------------------------------------------------------- +// MAC Line-Rx Signal +//----------------------------------------------------------------------- +wire mac_rx_clk ; +wire mac_rx_er ; +wire mac_rx_dv ; +wire [7:0] mac_rxd ; +wire mac_crs ; + + +//----------------------------------------------------------------------- +// MAC MDIO Signal +//----------------------------------------------------------------------- +wire mdio_clk ; +wire mdio_in ; +wire mdio_out_en ; +wire mdio_out ; + +//-------------------------------------------- +// MAC Q Occupancy +//-------------------------------------------- +wire [9:0] mac_tx_qbase_addr; +wire [9:0] mac_rx_qbase_addr; +wire mac_tx_qcnt_inc; +wire mac_tx_qcnt_dec; +wire mac_rx_qcnt_inc; +wire mac_rx_qcnt_dec; + + ///////////////////////////////////////////////////////// // Clock Skew Ctrl @@ -515,1290 +350,603 @@ wire [3:0] cfg_cska_wh = cfg_clk_ctrl1[3:0]; wire [3:0] cfg_cska_wi = cfg_clk_ctrl1[7:4]; -wire [3:0] cfg_cska_glbl = cfg_clk_ctrl1[11:8]; +wire [3:0] cfg_cska_pinmux = cfg_clk_ctrl1[11:8]; wire [3:0] cfg_cska_lbist = cfg_clk_ctrl1[15:12]; +wire [3:0] cfg_cska_mbist = cfg_clk_ctrl1[19:16]; +wire [3:0] cfg_cska_mac = cfg_clk_ctrl1[23:20]; -wire cfg_mem_lphase = cfg_clk_ctrl1[31]; // SRAM data lanuch phase selection +wire cfg_mem_lphase = cfg_clk_ctrl1[31]; // SRAM data lanuch phase selection -wire [3:0] cfg_cska_mbist1 = cfg_clk_ctrl2[3:0]; -wire [3:0] cfg_cska_mbist2 = cfg_clk_ctrl2[7:4]; -wire [3:0] cfg_cska_mbist3 = cfg_clk_ctrl2[11:8]; -wire [3:0] cfg_cska_mbist4 = cfg_clk_ctrl2[15:12]; -wire [3:0] cfg_cska_mbist5 = cfg_clk_ctrl2[19:16]; -wire [3:0] cfg_cska_mbist6 = cfg_clk_ctrl2[23:20]; -wire [3:0] cfg_cska_mbist7 = cfg_clk_ctrl2[27:24]; -wire [3:0] cfg_cska_mbist8 = cfg_clk_ctrl2[31:28]; wb_host #( `ifndef SYNTHESIS - .SCW(SCW) // SCAN CHAIN WIDTH + .SCW (SCW ) // SCAN CHAIN WIDTH `endif ) u_wb_host( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif - .user_clock1 (wb_clk_i ), - .user_clock2 (user_clock2 ), - .user_irq (user_irq ), + .user_clock1 (wb_clk_i ), + .user_clock2 (user_clock2 ), + .user_irq (user_irq ), // Master Port - .wbm_rst_i (wb_rst_i ), - .wbm_clk_i (wb_clk_i ), - .wbm_cyc_i (wbs_cyc_i ), - .wbm_stb_i (wbs_stb_i ), - .wbm_adr_i (wbs_adr_i ), - .wbm_we_i (wbs_we_i ), - .wbm_dat_i (wbs_dat_i ), - .wbm_sel_i (wbs_sel_i ), - .wbm_dat_o (wbs_dat_o ), - .wbm_ack_o (wbs_ack_o ), - .wbm_err_o ( ), + .wbm_rst_i (wb_rst_i ), + .wbm_clk_i (wb_clk_i ), + .wbm_cyc_i (wbs_cyc_i ), + .wbm_stb_i (wbs_stb_i ), + .wbm_adr_i (wbs_adr_i ), + .wbm_we_i (wbs_we_i ), + .wbm_dat_i (wbs_dat_i ), + .wbm_sel_i (wbs_sel_i ), + .wbm_dat_o (wbs_dat_o ), + .wbm_ack_o (wbs_ack_o ), + .wbm_err_o ( ), // Clock Skeq Adjust - .wbd_clk_int (wbd_clk_int ), - .wbd_clk_wh (wbd_clk_wh ), - .cfg_cska_wh (cfg_cska_wh ), + .wbd_clk_int (wbd_clk_int ), + .wbd_clk_wh (wbd_clk_wh ), + .cfg_cska_wh (cfg_cska_wh ), // Clock Skeq Adjust - .lbist_clk_int (lbist_clk ), - .lbist_clk_out (lbist_clk ), - .cfg_cska_lbist (cfg_cska_lbist ), + .lbist_clk_int (lbist_clk ), + .lbist_clk_out (lbist_clk ), + .cfg_cska_lbist (cfg_cska_lbist ), // Slave Port - .wbs_clk_out (wbd_clk_int ), - .wbs_clk_i (wbd_clk_wh ), - .wbs_cyc_o (wbd_int_cyc_i ), - .wbs_stb_o (wbd_int_stb_i ), - .wbs_adr_o (wbd_int_adr_i ), - .wbs_we_o (wbd_int_we_i ), - .wbs_dat_o (wbd_int_dat_i ), - .wbs_sel_o (wbd_int_sel_i ), - .wbs_dat_i (wbd_int_dat_o ), - .wbs_ack_i (wbd_int_ack_o ), - .wbs_err_i (wbd_int_err_o ), + .wbs_clk_out (wbd_clk_int ), + .wbs_clk_i (wbd_clk_wh ), + .wbs_cyc_o (wbd_int_cyc_i ), + .wbs_stb_o (wbd_int_stb_i ), + .wbs_adr_o (wbd_int_adr_i ), + .wbs_we_o (wbd_int_we_i ), + .wbs_dat_o (wbd_int_dat_i ), + .wbs_sel_o (wbd_int_sel_i ), + .wbs_dat_i (wbd_int_dat_o ), + .wbs_ack_i (wbd_int_ack_o ), + .wbs_err_i (wbd_int_err_o ), - .cfg_clk_ctrl1 (cfg_clk_ctrl1 ), - .cfg_clk_ctrl2 (cfg_clk_ctrl2 ), + .cfg_clk_ctrl1 (cfg_clk_ctrl1 ), + .cfg_clk_ctrl2 (cfg_clk_ctrl2 ), - .bist_rst_n (bist_rst_n ), - .wbd_int_rst_n (wbd_int_rst_n ), + .mac_rst_n (mac_rst_n ), + .bist_rst_n (bist_rst_n ), + .wbd_int_rst_n (wbd_int_rst_n ), - .io_in (io_in[0] ), - .io_out (io_out ), - .io_oeb (io_oeb ), - .la_data_in (la_data_in[35:0] ), - .la_data_out (la_data_out ), + .io_in (io_in[0] ), + .io_out (io_out ), + .io_oeb (io_oeb ), + .la_data_in (la_data_in[35:0] ), + .la_data_out (la_data_out ), // Scan Control Signal - .scan_clk (scan_clk ), - .scan_rst_n (scan_rst_n ), - .scan_mode (scan_mode ), - .scan_en (scan_en ), - .scan_in (scan_in ), - .scan_out (scan_out_mbist1 ) + .scan_clk (scan_clk ), + .scan_rst_n (scan_rst_n ), + .scan_mode (scan_mode ), + .scan_en (scan_en ), + .scan_in (scan_in ), + .scan_out (scan_out_mbist ) ); wb_interconnect #( `ifndef SYNTHESIS - .SCW(SCW), // SCAN CHAIN WIDTH - .CH_CLK_WD(9), - .CH_DATA_WD(104) + .SCW (SCW ), // SCAN CHAIN WIDTH + .CH_CLK_WD (3 ), + .CH_DATA_WD (31 ) `endif ) u_intercon ( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif // SCAN I/F - .scan_en (scan_en_mbist8 ), - .scan_mode (scan_mode_mbist8 ), - .scan_si (scan_out_mbist8 ), + .scan_en (scan_en_mbist ), + .scan_mode (scan_mode_mbist ), + .scan_si (scan_out_mbist ), - .scan_en_o (scan_en_wbi ), - .scan_mode_o (scan_mode_wbi ), - .scan_so (scan_out_wbi ), + .scan_en_o (scan_en_wbi ), + .scan_mode_o (scan_mode_wbi ), + .scan_so (scan_out_wbi ), // Clock Skew adjust - .wbd_clk_int (wbd_clk_int ), - .cfg_cska_wi (cfg_cska_wi ), - .wbd_clk_wi (wbd_clk_wi ), + .wbd_clk_int (wbd_clk_int ), + .cfg_cska_wi (cfg_cska_wi ), + .wbd_clk_skew (wbd_clk_wi_skew ), - .ch_clk_in ({ - wbd_clk_int, - wbd_clk_int, - wbd_clk_int, - wbd_clk_int, - wbd_clk_int, - wbd_clk_int, - wbd_clk_int, - wbd_clk_int, - wbd_clk_int}), - .ch_clk_out ({ - wbd_clk_mbist8_int, - wbd_clk_mbist7_int, - wbd_clk_mbist6_int, - wbd_clk_mbist5_int, - wbd_clk_mbist4_int, - wbd_clk_mbist3_int, - wbd_clk_mbist2_int, - wbd_clk_mbist1_int, - wbd_clk_glbl_int - }), - .ch_data_in ({ - bist_error_cnt7, - bist_correct[7], - bist_error[7], - bist_done[7], - bist_sdo[7], - bist_sdi[7], - bist_load[7], - bist_shift[7], - bist_run[7], - bist_en[7], - - bist_error_cnt6, - bist_correct[6], - bist_error[6], - bist_done[6], - bist_sdo[6], - bist_sdi[6], - bist_load[6], - bist_shift[6], - bist_run[6], - bist_en[6], - - bist_error_cnt5, - bist_correct[5], - bist_error[5], - bist_done[5], - bist_sdo[5], - bist_sdi[5], - bist_load[5], - bist_shift[5], - bist_run[5], - bist_en[5], - - bist_error_cnt4, - bist_correct[4], - bist_error[4], - bist_done[4], - bist_sdo[4], - bist_sdi[4], - bist_load[4], - bist_shift[4], - bist_run[4], - bist_en[4], - + .ch_clk_in ({ wbd_clk_int, + wbd_clk_int, + wbd_clk_int} ), + .ch_clk_out ({ + wbd_clk_mac_rp, + wbd_clk_mbist_rp, + wbd_clk_pinmux_rp + }), + .ch_data_in ({ + bist_error_cnt3, bist_correct[3], bist_error[3], - bist_done[3], - bist_sdo[3], - bist_sdi[3], - bist_load[3], - bist_shift[3], - bist_run[3], - bist_en[3], bist_error_cnt2, bist_correct[2], bist_error[2], - bist_done[2], - bist_sdo[2], - bist_sdi[2], - bist_load[2], - bist_shift[2], - bist_run[2], - bist_en[2], bist_error_cnt1, bist_correct[1], bist_error[1], - bist_done[1], - bist_sdo[1], - bist_sdi[1], - bist_load[1], - bist_shift[1], - bist_run[1], - bist_en[1], bist_error_cnt0, bist_correct[0], bist_error[0], - bist_done[0], - bist_sdo[0], - bist_sdi[0], - bist_load[0], - bist_shift[0], - bist_run[0], - bist_en[0] - } ), - .ch_data_out ({ - bist_error_cnt7_int, - bist_correct_int[7], - bist_error_int[7], - bist_done_int[7], - bist_sdo_int[7], - bist_sdi_int[7], - bist_load_int[7], - bist_shift_int[7], - bist_run_int[7], - bist_en_int[7], + bist_done, + bist_sdo, + bist_sdi, + bist_load, + bist_shift, + bist_run, + bist_en + }), + .ch_data_out ({ - bist_error_cnt6_int, - bist_correct_int[6], - bist_error_int[6], - bist_done_int[6], - bist_sdo_int[6], - bist_sdi_int[6], - bist_load_int[6], - bist_shift_int[6], - bist_run_int[6], - bist_en_int[6], + bist_error_cnt3_rp, + bist_correct_rp[3], + bist_error_rp[3], - bist_error_cnt5_int, - bist_correct_int[5], - bist_error_int[5], - bist_done_int[5], - bist_sdo_int[5], - bist_sdi_int[5], - bist_load_int[5], - bist_shift_int[5], - bist_run_int[5], - bist_en_int[5], + bist_error_cnt2_rp, + bist_correct_rp[2], + bist_error_rp[2], - bist_error_cnt4_int, - bist_correct_int[4], - bist_error_int[4], - bist_done_int[4], - bist_sdo_int[4], - bist_sdi_int[4], - bist_load_int[4], - bist_shift_int[4], - bist_run_int[4], - bist_en_int[4], - - bist_error_cnt3_int, - bist_correct_int[3], - bist_error_int[3], - bist_done_int[3], - bist_sdo_int[3], - bist_sdi_int[3], - bist_load_int[3], - bist_shift_int[3], - bist_run_int[3], - bist_en_int[3], - - bist_error_cnt2_int, - bist_correct_int[2], - bist_error_int[2], - bist_done_int[2], - bist_sdo_int[2], - bist_sdi_int[2], - bist_load_int[2], - bist_shift_int[2], - bist_run_int[2], - bist_en_int[2], - - bist_error_cnt1_int, - bist_correct_int[1], - bist_error_int[1], - bist_done_int[1], - bist_sdo_int[1], - bist_sdi_int[1], - bist_load_int[1], - bist_shift_int[1], - bist_run_int[1], - bist_en_int[1], + bist_error_cnt1_rp, + bist_correct_rp[1], + bist_error_rp[1], - bist_error_cnt0_int, - bist_correct_int[0], - bist_error_int[0], - bist_done_int[0], - bist_sdo_int[0], - bist_sdi_int[0], - bist_load_int[0], - bist_shift_int[0], - bist_run_int[0], - bist_en_int[0] - }), + bist_error_cnt0_rp, + bist_correct_rp[0], + bist_error_rp[0], - .clk_i (wbd_clk_wi ), - .rst_n (wbd_int_rst_n ), + bist_done_rp, + bist_sdo_rp, + bist_sdi_rp, + bist_load_rp, + bist_shift_rp, + bist_run_rp, + bist_en_rp + }), + + .clk_i (wbd_clk_wi_skew ), + .rst_n (wbd_int_rst_n ), // Master 0 Interface - .m0_wbd_dat_i (wbd_int_dat_i ), - .m0_wbd_adr_i (wbd_int_adr_i ), - .m0_wbd_sel_i (wbd_int_sel_i ), - .m0_wbd_we_i (wbd_int_we_i ), - .m0_wbd_cyc_i (wbd_int_cyc_i ), - .m0_wbd_stb_i (wbd_int_stb_i ), - .m0_wbd_dat_o (wbd_int_dat_o ), - .m0_wbd_ack_o (wbd_int_ack_o ), - .m0_wbd_err_o (wbd_int_err_o ), + .m0_wbd_dat_i (wbd_int_dat_i ), + .m0_wbd_adr_i (wbd_int_adr_i ), + .m0_wbd_sel_i (wbd_int_sel_i ), + .m0_wbd_we_i (wbd_int_we_i ), + .m0_wbd_cyc_i (wbd_int_cyc_i ), + .m0_wbd_stb_i (wbd_int_stb_i ), + .m0_wbd_dat_o (wbd_int_dat_o ), + .m0_wbd_ack_o (wbd_int_ack_o ), + .m0_wbd_err_o (wbd_int_err_o ), + + // Master 1 Interface + .m1_wbd_dat_i (wbm_gtx_dat_o ), + .m1_wbd_adr_i (wbm_gtx_adr_o ), + .m1_wbd_sel_i (wbm_gtx_sel_o ), + .m1_wbd_we_i (wbm_gtx_we_o ), + .m1_wbd_cyc_i (wbm_gtx_cyc_o ), + .m1_wbd_stb_i (wbm_gtx_stb_o ), + .m1_wbd_dat_o (wbm_gtx_dat_i ), + .m1_wbd_ack_o (wbm_gtx_ack_i ), + .m1_wbd_err_o ( ), + + // Master 2 Interface + .m2_wbd_dat_i (wbm_grx_dat_o ), + .m2_wbd_adr_i (wbm_grx_adr_o ), + .m2_wbd_sel_i (wbm_grx_sel_o ), + .m2_wbd_we_i (wbm_grx_we_o ), + .m2_wbd_cyc_i (wbm_grx_cyc_o ), + .m2_wbd_stb_i (wbm_grx_stb_o ), + .m2_wbd_dat_o (wbm_grx_dat_i ), + .m2_wbd_ack_o (wbm_grx_ack_i ), + .m2_wbd_err_o ( ), // Slave 0 Interface - // .s0_wbd_err_i (1'b0 ), - Moved inside IP - .s0_wbd_dat_i (wbd_glbl_dat_i ), - .s0_wbd_ack_i (wbd_glbl_ack_i ), - .s0_wbd_dat_o (wbd_glbl_dat_o ), - .s0_wbd_adr_o (wbd_glbl_adr_o ), - .s0_wbd_sel_o (wbd_glbl_sel_o ), - .s0_wbd_we_o (wbd_glbl_we_o ), - .s0_wbd_cyc_o (wbd_glbl_cyc_o ), - .s0_wbd_stb_o (wbd_glbl_stb_o ), - - // Slave 0 Interface - // .s0_wbd_err_i (1'b0 ), - Moved inside IP - .s1_wbd_dat_i (wbd_mbist1_dat_i ), - .s1_wbd_ack_i (wbd_mbist1_ack_i ), - .s1_wbd_dat_o (wbd_mbist1_dat_o ), - .s1_wbd_adr_o (wbd_mbist1_adr_o ), - .s1_wbd_sel_o (wbd_mbist1_sel_o ), - .s1_wbd_we_o (wbd_mbist1_we_o ), - .s1_wbd_cyc_o (wbd_mbist1_cyc_o ), - .s1_wbd_stb_o (wbd_mbist1_stb_o ), - - // Slave 1 Interface - // .s1_wbd_err_i (1'b0 ), - Moved inside IP - .s2_wbd_dat_i (wbd_mbist2_dat_i ), - .s2_wbd_ack_i (wbd_mbist2_ack_i ), - .s2_wbd_dat_o (wbd_mbist2_dat_o ), - .s2_wbd_adr_o (wbd_mbist2_adr_o ), - .s2_wbd_sel_o (wbd_mbist2_sel_o ), - .s2_wbd_we_o (wbd_mbist2_we_o ), - .s2_wbd_cyc_o (wbd_mbist2_cyc_o ), - .s2_wbd_stb_o (wbd_mbist2_stb_o ), - + // .s0_wbd_err_i (1'b0 ), - Moved inside IP + .s0_wbd_dat_i (wbd_pinmux_dat_i ), + .s0_wbd_ack_i (wbd_pinmux_ack_i ), + .s0_wbd_dat_o (wbd_pinmux_dat_o ), + .s0_wbd_adr_o (wbd_pinmux_adr_o ), + .s0_wbd_sel_o (wbd_pinmux_sel_o ), + .s0_wbd_we_o (wbd_pinmux_we_o ), + .s0_wbd_cyc_o (wbd_pinmux_cyc_o ), + .s0_wbd_stb_o (wbd_pinmux_stb_o ), + + // Slave 1 Interface + //.s1_wbd_err_i (1'b0 ), - Moved inside IP + .s1_wbd_dat_i (wbs_grg_dat_o ), + .s1_wbd_ack_i (wbs_grg_ack_o ), + .s1_wbd_dat_o (wbs_grg_dat_i ), + .s1_wbd_adr_o (wbs_grg_adr_i ), + .s1_wbd_sel_o (wbs_grg_sel_i ), + .s1_wbd_we_o (wbs_grg_we_i ), + .s1_wbd_cyc_o (wbs_grg_cyc_i ), + .s1_wbd_stb_o (wbs_grg_stb_i ), + // Slave 2 Interface - // .s2_wbd_err_i (1'b0 ), - Moved inside IP - .s3_wbd_dat_i (wbd_mbist3_dat_i ), - .s3_wbd_ack_i (wbd_mbist3_ack_i ), - .s3_wbd_dat_o (wbd_mbist3_dat_o ), - .s3_wbd_adr_o (wbd_mbist3_adr_o ), - .s3_wbd_sel_o (wbd_mbist3_sel_o ), - .s3_wbd_we_o (wbd_mbist3_we_o ), - .s3_wbd_cyc_o (wbd_mbist3_cyc_o ), - .s3_wbd_stb_o (wbd_mbist3_stb_o ), + //.s2_wbd_err_i (1'b0 ), - Moved inside IP + .s2_wbd_dat_i (wbd_mbist_dat_i ), + .s2_wbd_ack_i (wbd_mbist_ack_i ), + .s2_wbd_dat_o (wbd_mbist_dat_o ), + .s2_wbd_adr_o (wbd_mbist_adr_o ), + .s2_wbd_sel_o (wbd_mbist_sel_o ), + .s2_wbd_bl_o (wbd_mbist_bl_o ), + .s2_wbd_bry_o (wbd_mbist_bry_o ), + .s2_wbd_we_o (wbd_mbist_we_o ), + .s2_wbd_cyc_o (wbd_mbist_cyc_o ), + .s2_wbd_stb_o (wbd_mbist_stb_o ), - // Slave 3 Interface - // .s3_wbd_err_i (1'b0 ), - Moved inside IP - .s4_wbd_dat_i (wbd_mbist4_dat_i ), - .s4_wbd_ack_i (wbd_mbist4_ack_i ), - .s4_wbd_dat_o (wbd_mbist4_dat_o ), - .s4_wbd_adr_o (wbd_mbist4_adr_o ), - .s4_wbd_sel_o (wbd_mbist4_sel_o ), - .s4_wbd_we_o (wbd_mbist4_we_o ), - .s4_wbd_cyc_o (wbd_mbist4_cyc_o ), - .s4_wbd_stb_o (wbd_mbist4_stb_o ), - // Slave 4 Interface - // .s0_wbd_err_i (1'b0 ), - Moved inside IP - .s5_wbd_dat_i (wbd_mbist5_dat_i ), - .s5_wbd_ack_i (wbd_mbist5_ack_i ), - .s5_wbd_dat_o (wbd_mbist5_dat_o ), - .s5_wbd_adr_o (wbd_mbist5_adr_o ), - .s5_wbd_sel_o (wbd_mbist5_sel_o ), - .s5_wbd_we_o (wbd_mbist5_we_o ), - .s5_wbd_cyc_o (wbd_mbist5_cyc_o ), - .s5_wbd_stb_o (wbd_mbist5_stb_o ), - - // Slave 5 Interface - // .s6_wbd_err_i (1'b0 ), - Moved inside IP - .s6_wbd_dat_i (wbd_mbist6_dat_i ), - .s6_wbd_ack_i (wbd_mbist6_ack_i ), - .s6_wbd_dat_o (wbd_mbist6_dat_o ), - .s6_wbd_adr_o (wbd_mbist6_adr_o ), - .s6_wbd_sel_o (wbd_mbist6_sel_o ), - .s6_wbd_we_o (wbd_mbist6_we_o ), - .s6_wbd_cyc_o (wbd_mbist6_cyc_o ), - .s6_wbd_stb_o (wbd_mbist6_stb_o ), - - // Slave 6 Interface - // .s7_wbd_err_i (1'b0 ), - Moved inside IP - .s7_wbd_dat_i (wbd_mbist7_dat_i ), - .s7_wbd_ack_i (wbd_mbist7_ack_i ), - .s7_wbd_dat_o (wbd_mbist7_dat_o ), - .s7_wbd_adr_o (wbd_mbist7_adr_o ), - .s7_wbd_sel_o (wbd_mbist7_sel_o ), - .s7_wbd_we_o (wbd_mbist7_we_o ), - .s7_wbd_cyc_o (wbd_mbist7_cyc_o ), - .s7_wbd_stb_o (wbd_mbist7_stb_o ), + // Q Occupancy + .mac_tx_qbase_addr (mac_tx_qbase_addr ) , + .mac_rx_qbase_addr (mac_rx_qbase_addr ) , - // Slave 7 Interface - // .s8_wbd_err_i (1'b0 ), - Moved inside IP - .s8_wbd_dat_i (wbd_mbist8_dat_i ), - .s8_wbd_ack_i (wbd_mbist8_ack_i ), - .s8_wbd_dat_o (wbd_mbist8_dat_o ), - .s8_wbd_adr_o (wbd_mbist8_adr_o ), - .s8_wbd_sel_o (wbd_mbist8_sel_o ), - .s8_wbd_we_o (wbd_mbist8_we_o ), - .s8_wbd_cyc_o (wbd_mbist8_cyc_o ), - .s8_wbd_stb_o (wbd_mbist8_stb_o ) + .mac_tx_qcnt_inc (mac_tx_qcnt_inc ), + .mac_tx_qcnt_dec (mac_tx_qcnt_dec ), + .mac_rx_qcnt_inc (mac_rx_qcnt_inc ), + .mac_rx_qcnt_dec (mac_rx_qcnt_dec ) ); -glbl_cfg #( +pinmux_top #( `ifndef SYNTHESIS - .SCW(SCW) // SCAN CHAIN WIDTH + .SCW (SCW ) // SCAN CHAIN WIDTH `endif - ) u_glbl( + ) u_pinmux( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif // SCAN I/F - .scan_en (scan_en ), - .scan_mode (scan_mode ), - .scan_si (scan_in ), + .scan_en (scan_en ), + .scan_mode (scan_mode ), + .scan_si (scan_in ), - .scan_en_o (scan_en_glbl ), - .scan_mode_o (scan_mode_glbl ), - .scan_so (scan_out_glbl ), + .scan_en_o (scan_en_pinmux ), + .scan_mode_o (scan_mode_pinmux ), + .scan_so (scan_out_pinmux ), - .wbd_clk_int (wbd_clk_glbl_int ), - .cfg_cska_glbl (cfg_cska_glbl ), - .wbd_clk_glbl (wbd_clk_glbl ), + .wbd_clk_int (wbd_clk_pinmux_rp ), + .cfg_cska_pinmux (cfg_cska_pinmux ), + .wbd_clk_skew (wbd_clk_pinmux_skew ), - .mclk (wbd_clk_glbl ), - .reset_n (wbd_int_rst_n ), + .mclk (wbd_clk_pinmux_skew ), + .reset_n (wbd_int_rst_n ), // Reg Bus Interface Signal - .reg_cs (wbd_glbl_stb_o ), - .reg_wr (wbd_glbl_we_o ), - .reg_addr (wbd_glbl_adr_o ), - .reg_wdata (wbd_glbl_dat_o ), - .reg_be (wbd_glbl_sel_o ), + .reg_cs (wbd_pinmux_stb_o ), + .reg_wr (wbd_pinmux_we_o ), + .reg_addr (wbd_pinmux_adr_o ), + .reg_wdata (wbd_pinmux_dat_o ), + .reg_be (wbd_pinmux_sel_o ), // Outputs - .reg_rdata (wbd_glbl_dat_i ), - .reg_ack (wbd_glbl_ack_i ), + .reg_rdata (wbd_pinmux_dat_i ), + .reg_ack (wbd_pinmux_ack_i ), - // BIST I/F Outputs - .bist_en (bist_en), - .bist_run (bist_run), - .bist_load (bist_load), + // BIST I/F + .bist_en (bist_en ), + .bist_run (bist_run ), + .bist_load (bist_load ), + + .bist_serial_sel (bist_serial_sel ), + .bist_sdi (bist_sdi ), + .bist_shift (bist_shift ), + .bist_sdo (bist_sdo_rp ), + + .bist_done (bist_done_rp ), + .bist_error (bist_error_rp ), + .bist_correct (bist_correct_rp ), + .bist_error_cnt0 (bist_error_cnt0_rp ), + .bist_error_cnt1 (bist_error_cnt1_rp ), + .bist_error_cnt2 (bist_error_cnt2_rp ), + .bist_error_cnt3 (bist_error_cnt3_rp ), - .bist_sdi (bist_sdi), - .bist_shift (bist_shift), - - // BIST Inputs - .bist_sdo (bist_sdo_int), - .bist_done (bist_done_int), - .bist_error (bist_error_int), - .bist_correct (bist_correct_int), - .bist_error_cnt0 (bist_error_cnt0_int), - .bist_error_cnt1 (bist_error_cnt1_int), - .bist_error_cnt2 (bist_error_cnt2_int), - .bist_error_cnt3 (bist_error_cnt3_int), - .bist_error_cnt4 (bist_error_cnt4_int), - .bist_error_cnt5 (bist_error_cnt5_int), - .bist_error_cnt6 (bist_error_cnt6_int), - .bist_error_cnt7 (bist_error_cnt7_int) - - ); + //----------------------------------------------------------------------- + // MAC Line-Tx Signal + //----------------------------------------------------------------------- + .mac_tx_en (mac_tx_en ), + .mac_tx_er (mac_tx_er ), + .mac_txd (mac_txd ), + .mac_tx_clk (mac_tx_clk ), + + //----------------------------------------------------------------------- + // MAC Line-Rx Signal + //----------------------------------------------------------------------- + .mac_rx_clk (mac_rx_clk ), + .mac_rx_er (mac_rx_er ), + .mac_rx_dv (mac_rx_dv ), + .mac_rxd (mac_rxd ), + .mac_crs (mac_crs ), + + + //----------------------------------------------------------------------- + // MAC MDIO Signal + //----------------------------------------------------------------------- + .mdio_clk (mdio_clk ), + .mdio_in (mdio_in ), + .mdio_out_en (mdio_out_en ), + .mdio_out (mdio_out ) -//------------- MBIST1 - 512x32 ---- -mbist_top1 #( + ); + +//------------- MBIST - 512x32 * 4 ---- + +wire [1:0] wb_cs_mbist = wbd_mbist_adr_o[12:11]; +wire [10:2] wb_adr_mbist = wbd_mbist_adr_o[10:2]; + +mbist_wrapper #( `ifndef SYNTHESIS - .SCW (SCW), // SCAN CHAIN WIDTH - .BIST_ADDR_WD (BIST1_ADDR_WD-2 ), - .BIST_DATA_WD (BIST_DATA_WD ), - .BIST_ADDR_START (9'h000 ), - .BIST_ADDR_END (9'h1FB ), - .BIST_REPAIR_ADDR_START (9'h1FC ), - .BIST_RAD_WD_I (BIST1_ADDR_WD-2 ), - .BIST_RAD_WD_O (BIST1_ADDR_WD-2 ) + .SCW (SCW ), + .BIST_NO_SRAM (4 ), + .BIST_ADDR_WD (BIST_ADDR_WD ), + .BIST_DATA_WD (BIST_DATA_WD ), + .BIST_ADDR_START (9'h000 ), + .BIST_ADDR_END (9'h1FB ), + .BIST_REPAIR_ADDR_START(9'h1FC ), + .BIST_RAD_WD_I (BIST_ADDR_WD ), + .BIST_RAD_WD_O (BIST_ADDR_WD ) `endif ) - u_mbist1 ( - + u_mbist_wrapper ( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif - // SCAN I/F - .scan_en (scan_en_mbist2 ), - .scan_mode (scan_mode_mbist2 ), - .scan_si (scan_out_mbist2 ), - - .scan_en_o (scan_en_mbist1 ), - .scan_mode_o (scan_mode_mbist1 ), - .scan_so (scan_out_mbist1 ), - - .cfg_mem_lphase (cfg_mem_lphase ), - // Clock Skew adjust - .wbd_clk_int (wbd_clk_mbist1_int), - .cfg_cska_mbist (cfg_cska_mbist1 ), - .wbd_clk_mbist (wbd_clk_mbist1 ), + .wbd_clk_int (wbd_clk_mbist_rp ), + .cfg_cska_mbist (cfg_cska_mbist ), + .wbd_clk_skew (wbd_clk_mbist_skew ), // WB I/F - .wb_clk_i (wbd_clk_mbist1 ), - .wb_cyc_i (wbd_mbist1_cyc_o), - .wb_stb_i (wbd_mbist1_stb_o), - .wb_adr_i (wbd_mbist1_adr_o[BIST1_ADDR_WD-1:2]), - .wb_we_i (wbd_mbist1_we_o ), - .wb_dat_i (wbd_mbist1_dat_o), - .wb_sel_i (wbd_mbist1_sel_o), - .wb_dat_o (wbd_mbist1_dat_i), - .wb_ack_o (wbd_mbist1_ack_i), - .wb_err_o ( ), + .wb_clk2_i (wbd_clk_mbist_skew ), + .wb_clk_i (wbd_clk_mbist_skew ), + .wb_stb_i (wbd_mbist_stb_o ), + .wb_cs_i (wb_cs_mbist ), + .wb_adr_i (wb_adr_mbist ), + .wb_we_i (wbd_mbist_we_o ), + .wb_dat_i (wbd_mbist_dat_o ), + .wb_sel_i (wbd_mbist_sel_o ), + .wb_bl_i (wbd_mbist_bl_o ), + .wb_bry_i (wbd_mbist_bry_o ), + .wb_dat_o (wbd_mbist_dat_i ), + .wb_ack_o (wbd_mbist_ack_i ), + .wb_err_o ( ), + .rst_n (bist_rst_n ), - .rst_n (bist_rst_n ), - - - .bist_en (bist_en_int[0] ), - .bist_run (bist_run_int[0] ), - .bist_shift (bist_shift_int[0] ), - .bist_load (bist_load_int[0] ), - .bist_sdi (bist_sdi_int[0] ), - - .bist_error_cnt (bist_error_cnt0 ), - .bist_correct (bist_correct[0] ), - .bist_error (bist_error[0] ), - .bist_done (bist_done[0] ), - .bist_sdo (bist_sdo[0] ), + // BIST Control Signals + .bist_en (bist_en_rp ), + .bist_run (bist_run_rp ), + .bist_shift (bist_shift_rp ), + .bist_load (bist_load_rp ), + .bist_sdi (bist_sdi_rp ), + .bist_error_cnt3 (bist_error_cnt3 ), + .bist_error_cnt2 (bist_error_cnt2 ), + .bist_error_cnt1 (bist_error_cnt1 ), + .bist_error_cnt0 (bist_error_cnt0 ), + .bist_correct (bist_correct ), + .bist_error (bist_error ), + .bist_done (bist_done ), + .bist_sdo (bist_sdo ), + .bist_serial_sel (bist_serial_sel ), // towards memory // PORT-A - .mem_clk_a (mem1_clk_a ), - .mem_addr_a (mem1_addr_a ), - .mem_cen_a (mem1_cen_a ), - .mem_dout_a (mem1_dout_a ), + .mem_clk_a (mem_clk_a ), + .mem_cen_a (mem_cen_a ), + .mem_web_a (mem_web_a ), + + .mem_addr_a0 (mem0_addr_a ), + .mem_mask_a0 (mem0_mask_a ), + .mem_din_a0 (mem0_din_a ), + .mem_dout_a0 (mem0_dout_a ), + + .mem_addr_a1 (mem1_addr_a ), + .mem_mask_a1 (mem1_mask_a ), + .mem_din_a1 (mem1_din_a ), + .mem_dout_a1 (mem1_dout_a ), + + .mem_addr_a2 (mem2_addr_a ), + .mem_mask_a2 (mem2_mask_a ), + .mem_din_a2 (mem2_din_a ), + .mem_dout_a2 (mem2_dout_a ), + + .mem_addr_a3 (mem3_addr_a ), + .mem_mask_a3 (mem3_mask_a ), + .mem_din_a3 (mem3_din_a ), + .mem_dout_a3 (mem3_dout_a ), + // PORT-B - .mem_clk_b (mem1_clk_b ), - .mem_cen_b (mem1_cen_b ), - .mem_web_b (mem1_web_b ), - .mem_mask_b (mem1_mask_b ), - .mem_addr_b (mem1_addr_b ), - .mem_din_b (mem1_din_b ) + .mem_clk_b (mem_clk_b ), + .mem_cen_b (mem_cen_b ), - + .mem_addr_b0 (mem0_addr_b ), + .mem_addr_b1 (mem1_addr_b ), + .mem_addr_b2 (mem2_addr_b ), + .mem_addr_b3 (mem3_addr_b ) ); + + +sky130_sram_2kbyte_1rw1r_32x512_8 u_sram0_2kb( +`ifdef USE_POWER_PINS + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground +`endif +// Port 0: RW + .clk0 (mem_clk_a[0] ), + .csb0 (mem_cen_a[0] ), + .web0 (mem_web_a[0] ), + .wmask0 (mem0_mask_a ), + .addr0 (mem0_addr_a ), + .din0 (mem0_din_a ), + .dout0 (mem0_dout_a ), +// Port 1: R + .clk1 (mem_clk_b[0] ), + .csb1 (mem_cen_b[0] ), + .addr1 (mem0_addr_b ), + .dout1 ( ) + ); sky130_sram_2kbyte_1rw1r_32x512_8 u_sram1_2kb( `ifdef USE_POWER_PINS - .vccd1 (vccd1),// User area 1 1.8V supply - .vssd1 (vssd1),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif // Port 0: RW - .clk0 (mem1_clk_b), - .csb0 (mem1_cen_b), - .web0 (mem1_web_b), - .wmask0 (mem1_mask_b), - .addr0 (mem1_addr_b), - .din0 (mem1_din_b), - .dout0 (), + .clk0 (mem_clk_a[1] ), + .csb0 (mem_cen_a[1] ), + .web0 (mem_web_a[1] ), + .wmask0 (mem1_mask_a ), + .addr0 (mem1_addr_a ), + .din0 (mem1_din_a ), + .dout0 (mem1_dout_a ), // Port 1: R - .clk1 (mem1_clk_a), - .csb1 (mem1_cen_a), - .addr1 (mem1_addr_a), - .dout1 (mem1_dout_a) + .clk1 (mem_clk_b[1] ), + .csb1 (mem_cen_b[1] ), + .addr1 (mem1_addr_b ), + .dout1 ( ) ); - -//------------- MBIST2 - 512x32 ---- - -mbist_top1 #( - `ifndef SYNTHESIS - .SCW (SCW), // SCAN CHAIN WIDTH - .BIST_ADDR_WD (BIST1_ADDR_WD-2 ), - .BIST_DATA_WD (BIST_DATA_WD ), - .BIST_ADDR_START (9'h000 ), - .BIST_ADDR_END (9'h1FB ), - .BIST_REPAIR_ADDR_START (9'h1FC ), - .BIST_RAD_WD_I (BIST1_ADDR_WD-2 ), - .BIST_RAD_WD_O (BIST1_ADDR_WD-2 ) - `endif - ) - u_mbist2 ( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif - // SCAN I/F - .scan_en (scan_en_mbist3 ), - .scan_mode (scan_mode_mbist3 ), - .scan_si (scan_out_mbist3 ), - - .scan_en_o (scan_en_mbist2 ), - .scan_mode_o (scan_mode_mbist2 ), - .scan_so (scan_out_mbist2 ), - - .cfg_mem_lphase (cfg_mem_lphase ), - - // Clock Skew adjust - .wbd_clk_int (wbd_clk_mbist2_int), - .cfg_cska_mbist (cfg_cska_mbist2 ), - .wbd_clk_mbist (wbd_clk_mbist2 ), - - // WB I/F - .wb_clk_i (wbd_clk_mbist2 ), - .wb_cyc_i (wbd_mbist2_cyc_o), - .wb_stb_i (wbd_mbist2_stb_o), - .wb_adr_i (wbd_mbist2_adr_o[BIST1_ADDR_WD-1:2]), - .wb_we_i (wbd_mbist2_we_o ), - .wb_dat_i (wbd_mbist2_dat_o), - .wb_sel_i (wbd_mbist2_sel_o), - .wb_dat_o (wbd_mbist2_dat_i), - .wb_ack_o (wbd_mbist2_ack_i), - .wb_err_o ( ), - - .rst_n (bist_rst_n ), - - - .bist_en (bist_en_int[1] ), - .bist_run (bist_run_int[1] ), - .bist_shift (bist_shift_int[1] ), - .bist_load (bist_load_int[1] ), - .bist_sdi (bist_sdi_int[1] ), - - .bist_error_cnt (bist_error_cnt1 ), - .bist_correct (bist_correct[1] ), - .bist_error (bist_error[1] ), - .bist_done (bist_done[1] ), - .bist_sdo (bist_sdo[1] ), - - // towards memory - // PORT-A - .mem_clk_a (mem2_clk_a ), - .mem_addr_a (mem2_addr_a ), - .mem_cen_a (mem2_cen_a ), - .mem_dout_a (mem2_dout_a ), - // PORT-B - .mem_clk_b (mem2_clk_b ), - .mem_cen_b (mem2_cen_b ), - .mem_web_b (mem2_web_b ), - .mem_mask_b (mem2_mask_b ), - .mem_addr_b (mem2_addr_b ), - .mem_din_b (mem2_din_b ) - - -); - sky130_sram_2kbyte_1rw1r_32x512_8 u_sram2_2kb( `ifdef USE_POWER_PINS - .vccd1 (vccd1),// User area 1 1.8V supply - .vssd1 (vssd1),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif // Port 0: RW - .clk0 (mem2_clk_b), - .csb0 (mem2_cen_b), - .web0 (mem2_web_b), - .wmask0 (mem2_mask_b), - .addr0 (mem2_addr_b), - .din0 (mem2_din_b), - .dout0 (), + .clk0 (mem_clk_a[2] ), + .csb0 (mem_cen_a[2] ), + .web0 (mem_web_a[2] ), + .wmask0 (mem2_mask_a ), + .addr0 (mem2_addr_a ), + .din0 (mem2_din_a ), + .dout0 (mem2_dout_a ), // Port 1: R - .clk1 (mem2_clk_a), - .csb1 (mem2_cen_a), - .addr1 (mem2_addr_a), - .dout1 (mem2_dout_a) + .clk1 (mem_clk_b[2] ), + .csb1 (mem_cen_b[2] ), + .addr1 (mem2_addr_b ), + .dout1 ( ) ); - -//------------- MBIST3 - 512x32 ---- - -mbist_top1 #( - `ifndef SYNTHESIS - .SCW (SCW), // SCAN CHAIN WIDTH - .BIST_ADDR_WD (BIST1_ADDR_WD-2 ), - .BIST_DATA_WD (BIST_DATA_WD ), - .BIST_ADDR_START (9'h000 ), - .BIST_ADDR_END (9'h1FB ), - .BIST_REPAIR_ADDR_START (9'h1FC ), - .BIST_RAD_WD_I (BIST1_ADDR_WD-2 ), - .BIST_RAD_WD_O (BIST1_ADDR_WD-2 ) - `endif - ) - u_mbist3 ( - -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif - // SCAN I/F - .scan_en (scan_en_mbist4 ), - .scan_mode (scan_mode_mbist4 ), - .scan_si (scan_out_mbist4 ), - - .scan_en_o (scan_en_mbist3 ), - .scan_mode_o (scan_mode_mbist3 ), - .scan_so (scan_out_mbist3 ), - - .cfg_mem_lphase (cfg_mem_lphase ), - - // Clock Skew adjust - .wbd_clk_int (wbd_clk_mbist3_int ), - .cfg_cska_mbist (cfg_cska_mbist3 ), - .wbd_clk_mbist (wbd_clk_mbist3 ), - - // WB I/F - .wb_clk_i (wbd_clk_mbist3 ), - .wb_cyc_i (wbd_mbist3_cyc_o), - .wb_stb_i (wbd_mbist3_stb_o), - .wb_adr_i (wbd_mbist3_adr_o[BIST1_ADDR_WD-1:2]), - .wb_we_i (wbd_mbist3_we_o ), - .wb_dat_i (wbd_mbist3_dat_o), - .wb_sel_i (wbd_mbist3_sel_o), - .wb_dat_o (wbd_mbist3_dat_i), - .wb_ack_o (wbd_mbist3_ack_i), - .wb_err_o ( ), - - .rst_n (bist_rst_n ), - - - .bist_en (bist_en_int[2] ), - .bist_run (bist_run_int[2] ), - .bist_shift (bist_shift_int[2]), - .bist_load (bist_load_int[2] ), - .bist_sdi (bist_sdi_int[2] ), - - .bist_error_cnt (bist_error_cnt2 ), - .bist_correct (bist_correct[2] ), - .bist_error (bist_error[2] ), - .bist_done (bist_done[2] ), - .bist_sdo (bist_sdo[2] ), - - // towards memory - // PORT-A - .mem_clk_a (mem3_clk_a ), - .mem_addr_a (mem3_addr_a ), - .mem_cen_a (mem3_cen_a ), - .mem_dout_a (mem3_dout_a ), - // PORT-B - .mem_clk_b (mem3_clk_b ), - .mem_cen_b (mem3_cen_b ), - .mem_web_b (mem3_web_b ), - .mem_mask_b (mem3_mask_b ), - .mem_addr_b (mem3_addr_b ), - .mem_din_b (mem3_din_b ) - - -); - sky130_sram_2kbyte_1rw1r_32x512_8 u_sram3_2kb( `ifdef USE_POWER_PINS - .vccd1 (vccd1),// User area 1 1.8V supply - .vssd1 (vssd1),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif // Port 0: RW - .clk0 (mem3_clk_b), - .csb0 (mem3_cen_b), - .web0 (mem3_web_b), - .wmask0 (mem3_mask_b), - .addr0 (mem3_addr_b), - .din0 (mem3_din_b), - .dout0 (), + .clk0 (mem_clk_a[3] ), + .csb0 (mem_cen_a[3] ), + .web0 (mem_web_a[3] ), + .wmask0 (mem3_mask_a ), + .addr0 (mem3_addr_a ), + .din0 (mem3_din_a ), + .dout0 (mem3_dout_a ), // Port 1: R - .clk1 (mem3_clk_a), - .csb1 (mem3_cen_a), - .addr1 (mem3_addr_a), - .dout1 (mem3_dout_a) + .clk1 (mem_clk_b[3] ), + .csb1 (mem_cen_b[3] ), + .addr1 (mem3_addr_b ), + .dout1 ( ) ); -//------------- MBIST4 - 512x32 ---- -mbist_top1 #( - `ifndef SYNTHESIS - .SCW (SCW), // SCAN CHAIN WIDTH - .BIST_ADDR_WD (BIST1_ADDR_WD-2 ), - .BIST_DATA_WD (BIST_DATA_WD ), - .BIST_ADDR_START (9'h000 ), - .BIST_ADDR_END (9'h1FB ), - .BIST_REPAIR_ADDR_START (9'h1FC ), - .BIST_RAD_WD_I (BIST1_ADDR_WD-2 ), - .BIST_RAD_WD_O (BIST1_ADDR_WD-2 ) - `endif - ) - u_mbist4 ( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif - // SCAN I/F - .scan_en (scan_en_wbi ), - .scan_mode (scan_mode_wbi ), - .scan_si (scan_out_wbi ), +mac_wrapper u_mac_wrap( - .scan_en_o (scan_en_mbist4 ), - .scan_mode_o (scan_mode_mbist4 ), - .scan_so (scan_out_mbist4 ), + .app_clk (wbd_clk_mac_skew ), + .reset_n (mac_rst_n ), - .cfg_mem_lphase (cfg_mem_lphase ), + // Clock Skeq Adjust + .wbd_clk_int (wbd_clk_mac_rp ), + .wbd_clk_skew (wbd_clk_mac_skew ), + .cfg_cska_mac (cfg_cska_mac ), - // Clock Skew adjust - .wbd_clk_int (wbd_clk_mbist4_int ), - .cfg_cska_mbist (cfg_cska_mbist4 ), - .wbd_clk_mbist (wbd_clk_mbist4 ), + //----------------------------------------------------------------------- + // MAC Line-Tx Signal + //----------------------------------------------------------------------- + .phy_tx_en (mac_tx_en ), + .phy_tx_er (mac_tx_er ), + .phy_txd (mac_txd ), + .phy_tx_clk (mac_tx_clk ), + + //----------------------------------------------------------------------- + // MAC Line-Rx Signal + //----------------------------------------------------------------------- + .phy_rx_clk (mac_rx_clk ), + .phy_rx_er (mac_rx_er ), + .phy_rx_dv (mac_rx_dv ), + .phy_rxd (mac_rxd ), + .phy_crs (mac_crs ), + + + //----------------------------------------------------------------------- + // MAC MDIO Signal + //----------------------------------------------------------------------- + .mdio_clk (mdio_clk ), + .mdio_in (mdio_in ), + .mdio_out_en (mdio_out_en ), + .mdio_out (mdio_out ), - // WB I/F - .wb_clk_i (wbd_clk_mbist4 ), - .wb_cyc_i (wbd_mbist4_cyc_o), - .wb_stb_i (wbd_mbist4_stb_o), - .wb_adr_i (wbd_mbist4_adr_o[BIST1_ADDR_WD-1:2]), - .wb_we_i (wbd_mbist4_we_o ), - .wb_dat_i (wbd_mbist4_dat_o), - .wb_sel_i (wbd_mbist4_sel_o), - .wb_dat_o (wbd_mbist4_dat_i), - .wb_ack_o (wbd_mbist4_ack_i), - .wb_err_o ( ), + //-------------------------------------------- + // GMAC TX WB Master I/F + //-------------------------------------------- + .wbm_gtx_dat_i (wbm_gtx_dat_i ), + .wbm_gtx_ack_i (wbm_gtx_ack_i ), + .wbm_gtx_dat_o (wbm_gtx_dat_o ), + .wbm_gtx_adr_o (wbm_gtx_adr_o ), + .wbm_gtx_sel_o (wbm_gtx_sel_o ), + .wbm_gtx_we_o (wbm_gtx_we_o ), + .wbm_gtx_stb_o (wbm_gtx_stb_o ), + .wbm_gtx_cyc_o (wbm_gtx_cyc_o ), + + //-------------------------------------------- + // GMAC RX WB Master I/F + //-------------------------------------------- + .wbm_grx_dat_i (wbm_grx_dat_i ), + .wbm_grx_ack_i (wbm_grx_ack_i ), + .wbm_grx_dat_o (wbm_grx_dat_o ), + .wbm_grx_adr_o (wbm_grx_adr_o ), + .wbm_grx_sel_o (wbm_grx_sel_o ), + .wbm_grx_we_o (wbm_grx_we_o ), + .wbm_grx_stb_o (wbm_grx_stb_o ), + .wbm_grx_cyc_o (wbm_grx_cyc_o ), + + //-------------------------------------------- + // GMAC REG WB SLAVE I/F + //-------------------------------------------- + .wbs_grg_dat_o (wbs_grg_dat_o ), + .wbs_grg_ack_o (wbs_grg_ack_o ), + .wbs_grg_dat_i (wbs_grg_dat_i ), + .wbs_grg_adr_i (wbs_grg_adr_i ), + .wbs_grg_sel_i (wbs_grg_sel_i ), + .wbs_grg_we_i (wbs_grg_we_i ), + .wbs_grg_stb_i (wbs_grg_stb_i ), + .wbs_grg_cyc_i (wbs_grg_cyc_i ), + + // Q Occupancy + .cfg_tx_qbase_addr (mac_tx_qbase_addr ) , + .cfg_rx_qbase_addr (mac_rx_qbase_addr ) , - .rst_n (bist_rst_n ), + .mac_tx_qcnt_inc (mac_tx_qcnt_inc ), + .mac_tx_qcnt_dec (mac_tx_qcnt_dec ), + .mac_rx_qcnt_inc (mac_rx_qcnt_inc ), + .mac_rx_qcnt_dec (mac_rx_qcnt_dec ) - - .bist_en (bist_en_int[3] ), - .bist_run (bist_run_int[3] ), - .bist_shift (bist_shift_int[3] ), - .bist_load (bist_load_int[3] ), - .bist_sdi (bist_sdi_int[3] ), - - .bist_error_cnt (bist_error_cnt3 ), - .bist_correct (bist_correct[3] ), - .bist_error (bist_error[3] ), - .bist_done (bist_done[3] ), - .bist_sdo (bist_sdo[3] ), - - // towards memory - // PORT-A - .mem_clk_a (mem4_clk_a ), - .mem_addr_a (mem4_addr_a ), - .mem_cen_a (mem4_cen_a ), - .mem_dout_a (mem4_dout_a ), - // PORT-B - .mem_clk_b (mem4_clk_b ), - .mem_cen_b (mem4_cen_b ), - .mem_web_b (mem4_web_b ), - .mem_mask_b (mem4_mask_b ), - .mem_addr_b (mem4_addr_b ), - .mem_din_b (mem4_din_b ) + ); -); - -sky130_sram_2kbyte_1rw1r_32x512_8 u_sram4_2kb( -`ifdef USE_POWER_PINS - .vccd1 (vccd1),// User area 1 1.8V supply - .vssd1 (vssd1),// User area 1 digital ground -`endif -// Port 0: RW - .clk0 (mem4_clk_b), - .csb0 (mem4_cen_b), - .web0 (mem4_web_b), - .wmask0 (mem4_mask_b), - .addr0 (mem4_addr_b), - .din0 (mem4_din_b), - .dout0 (), -// Port 1: R - .clk1 (mem4_clk_a), - .csb1 (mem4_cen_a), - .addr1 (mem4_addr_a), - .dout1 (mem4_dout_a) - ); - -//------------- MBIST5 - 256x32 ---- - -mbist_top2 #( - `ifndef SYNTHESIS - .SCW (SCW), // SCAN CHAIN WIDTH - .BIST_ADDR_WD (BIST2_ADDR_WD-2 ), - .BIST_DATA_WD (BIST_DATA_WD ), - .BIST_ADDR_START (8'h00 ), - .BIST_ADDR_END (8'hFB ), - .BIST_REPAIR_ADDR_START (8'hFC ), - .BIST_RAD_WD_I (BIST2_ADDR_WD-2 ), - .BIST_RAD_WD_O (BIST2_ADDR_WD-2 ) - `endif - ) - u_mbist5 ( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif - // SCAN I/F - .scan_en (scan_en_glbl ), - .scan_mode (scan_mode_glbl ), - .scan_si (scan_out_glbl ), - - .scan_en_o (scan_en_mbist5 ), - .scan_mode_o (scan_mode_mbist5 ), - .scan_so (scan_out_mbist5 ), - - .cfg_mem_lphase (cfg_mem_lphase ), - - // Clock Skew adjust - .wbd_clk_int (wbd_clk_mbist5_int ), - .cfg_cska_mbist (cfg_cska_mbist5 ), - .wbd_clk_mbist (wbd_clk_mbist5 ), - - // WB I/F - .wb_clk_i (wbd_clk_mbist5 ), - .wb_cyc_i (wbd_mbist5_cyc_o), - .wb_stb_i (wbd_mbist5_stb_o), - .wb_adr_i (wbd_mbist5_adr_o[BIST2_ADDR_WD-1:2]), - .wb_we_i (wbd_mbist5_we_o ), - .wb_dat_i (wbd_mbist5_dat_o), - .wb_sel_i (wbd_mbist5_sel_o), - .wb_dat_o (wbd_mbist5_dat_i), - .wb_ack_o (wbd_mbist5_ack_i), - .wb_err_o ( ), - - .rst_n (bist_rst_n ), - - - .bist_en (bist_en_int[4] ), - .bist_run (bist_run_int[4] ), - .bist_shift (bist_shift_int[4]), - .bist_load (bist_load_int[4] ), - .bist_sdi (bist_sdi_int[4] ), - - .bist_error_cnt (bist_error_cnt4 ), - .bist_correct (bist_correct[4] ), - .bist_error (bist_error[4] ), - .bist_done (bist_done[4] ), - .bist_sdo (bist_sdo[4] ), - - - // towards memory - // PORT-A - .mem_clk_a (mem5_clk_a ), - .mem_addr_a (mem5_addr_a ), - .mem_cen_a (mem5_cen_a ), - .mem_dout_a (mem5_dout_a ), - // PORT-B - .mem_clk_b (mem5_clk_b ), - .mem_cen_b (mem5_cen_b ), - .mem_web_b (mem5_web_b ), - .mem_mask_b (mem5_mask_b ), - .mem_addr_b (mem5_addr_b ), - .mem_din_b (mem5_din_b ) - - -); - -sky130_sram_1kbyte_1rw1r_32x256_8 u_sram5_1kb( -`ifdef USE_POWER_PINS - .vccd1 (vccd1),// User area 1 1.8V supply - .vssd1 (vssd1),// User area 1 digital ground -`endif -// Port 0: RW - .clk0 (mem5_clk_b), - .csb0 (mem5_cen_b), - .web0 (mem5_web_b), - .wmask0 (mem5_mask_b), - .addr0 (mem5_addr_b), - .din0 (mem5_din_b), - .dout0 (), -// Port 1: R - .clk1 (mem5_clk_a), - .csb1 (mem5_cen_a), - .addr1 (mem5_addr_a), - .dout1 (mem5_dout_a) - ); - -//------------- MBIST6 - 256x32 ---- - -mbist_top2 #( - `ifndef SYNTHESIS - .SCW (SCW), // SCAN CHAIN WIDTH - .BIST_ADDR_WD (BIST2_ADDR_WD-2 ), - .BIST_DATA_WD (BIST_DATA_WD ), - .BIST_ADDR_START (8'h00 ), - .BIST_ADDR_END (8'hFB ), - .BIST_REPAIR_ADDR_START (8'hFC ), - .BIST_RAD_WD_I (BIST2_ADDR_WD-2 ), - .BIST_RAD_WD_O (BIST2_ADDR_WD-2 ) - `endif - ) - u_mbist6 ( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif - // SCAN I/F - .scan_en (scan_en_mbist5 ), - .scan_mode (scan_mode_mbist5 ), - .scan_si (scan_out_mbist5 ), - - .scan_en_o (scan_en_mbist6 ), - .scan_mode_o (scan_mode_mbist6 ), - .scan_so (scan_out_mbist6 ), - - .cfg_mem_lphase (cfg_mem_lphase ), - - // Clock Skew adjust - .wbd_clk_int (wbd_clk_mbist6_int ), - .cfg_cska_mbist (cfg_cska_mbist6 ), - .wbd_clk_mbist (wbd_clk_mbist6 ), - - // WB I/F - .wb_clk_i (wbd_clk_mbist6 ), - .wb_cyc_i (wbd_mbist6_cyc_o), - .wb_stb_i (wbd_mbist6_stb_o), - .wb_adr_i (wbd_mbist6_adr_o[BIST2_ADDR_WD-1:2]), - .wb_we_i (wbd_mbist6_we_o ), - .wb_dat_i (wbd_mbist6_dat_o), - .wb_sel_i (wbd_mbist6_sel_o), - .wb_dat_o (wbd_mbist6_dat_i), - .wb_ack_o (wbd_mbist6_ack_i), - .wb_err_o ( ), - - .rst_n (bist_rst_n ), - - - .bist_en (bist_en_int[5] ), - .bist_run (bist_run_int[5] ), - .bist_shift (bist_shift_int[5]), - .bist_load (bist_load_int[5] ), - .bist_sdi (bist_sdi_int[5] ), - - .bist_error_cnt (bist_error_cnt5 ), - .bist_correct (bist_correct[5] ), - .bist_error (bist_error[5] ), - .bist_done (bist_done[5] ), - .bist_sdo (bist_sdo[5] ), - - // towards memory - // PORT-A - .mem_clk_a (mem6_clk_a ), - .mem_addr_a (mem6_addr_a ), - .mem_cen_a (mem6_cen_a ), - .mem_dout_a (mem6_dout_a ), - // PORT-B - .mem_clk_b (mem6_clk_b ), - .mem_cen_b (mem6_cen_b ), - .mem_web_b (mem6_web_b ), - .mem_mask_b (mem6_mask_b ), - .mem_addr_b (mem6_addr_b ), - .mem_din_b (mem6_din_b ) - - -); - -sky130_sram_1kbyte_1rw1r_32x256_8 u_sram6_1kb( -`ifdef USE_POWER_PINS - .vccd1 (vccd1),// User area 1 1.8V supply - .vssd1 (vssd1),// User area 1 digital ground -`endif -// Port 0: RW - .clk0 (mem6_clk_b), - .csb0 (mem6_cen_b), - .web0 (mem6_web_b), - .wmask0 (mem6_mask_b), - .addr0 (mem6_addr_b), - .din0 (mem6_din_b), - .dout0 (), -// Port 1: R - .clk1 (mem6_clk_a), - .csb1 (mem6_cen_a), - .addr1 (mem6_addr_a), - .dout1 (mem6_dout_a) - ); -//------------- MBIST7 - 256x32 ---- - -mbist_top2 #( - `ifndef SYNTHESIS - .SCW (SCW), // SCAN CHAIN WIDTH - .BIST_ADDR_WD (BIST2_ADDR_WD-2 ), - .BIST_DATA_WD (BIST_DATA_WD ), - .BIST_ADDR_START (8'h00 ), - .BIST_ADDR_END (8'hFB ), - .BIST_REPAIR_ADDR_START (8'hFC ), - .BIST_RAD_WD_I (BIST2_ADDR_WD-2 ), - .BIST_RAD_WD_O (BIST2_ADDR_WD-2 ) - `endif - ) - u_mbist7 ( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif - // SCAN I/F - .scan_en (scan_en_mbist6 ), - .scan_mode (scan_mode_mbist6 ), - .scan_si (scan_out_mbist6 ), - - .scan_en_o (scan_en_mbist7 ), - .scan_mode_o (scan_mode_mbist7 ), - .scan_so (scan_out_mbist7 ), - - .cfg_mem_lphase (cfg_mem_lphase ), - // Clock Skew adjust - .wbd_clk_int (wbd_clk_mbist7_int ), - .cfg_cska_mbist (cfg_cska_mbist7 ), - .wbd_clk_mbist (wbd_clk_mbist7 ), - - // WB I/F - .wb_clk_i (wbd_clk_mbist7 ), - .wb_cyc_i (wbd_mbist7_cyc_o), - .wb_stb_i (wbd_mbist7_stb_o), - .wb_adr_i (wbd_mbist7_adr_o[BIST2_ADDR_WD-1:2]), - .wb_we_i (wbd_mbist7_we_o ), - .wb_dat_i (wbd_mbist7_dat_o), - .wb_sel_i (wbd_mbist7_sel_o), - .wb_dat_o (wbd_mbist7_dat_i), - .wb_ack_o (wbd_mbist7_ack_i), - .wb_err_o ( ), - - .rst_n (bist_rst_n ), - - - .bist_en (bist_en_int[6] ), - .bist_run (bist_run_int[6] ), - .bist_shift (bist_shift_int[6]), - .bist_load (bist_load_int[6] ), - .bist_sdi (bist_sdi_int[6] ), - - .bist_error_cnt (bist_error_cnt6 ), - .bist_correct (bist_correct[6] ), - .bist_error (bist_error[6] ), - .bist_done (bist_done[6] ), - .bist_sdo (bist_sdo[6] ), - - - // towards memory - // PORT-A - .mem_clk_a (mem7_clk_a ), - .mem_addr_a (mem7_addr_a ), - .mem_cen_a (mem7_cen_a ), - .mem_dout_a (mem7_dout_a ), - // PORT-B - .mem_clk_b (mem7_clk_b ), - .mem_cen_b (mem7_cen_b ), - .mem_web_b (mem7_web_b ), - .mem_mask_b (mem7_mask_b ), - .mem_addr_b (mem7_addr_b ), - .mem_din_b (mem7_din_b ) - - -); - -sky130_sram_1kbyte_1rw1r_32x256_8 u_sram7_1kb( -`ifdef USE_POWER_PINS - .vccd1 (vccd1),// User area 1 1.8V supply - .vssd1 (vssd1),// User area 1 digital ground -`endif -// Port 0: RW - .clk0 (mem7_clk_b), - .csb0 (mem7_cen_b), - .web0 (mem7_web_b), - .wmask0 (mem7_mask_b), - .addr0 (mem7_addr_b), - .din0 (mem7_din_b), - .dout0 (), -// Port 1: R - .clk1 (mem7_clk_a), - .csb1 (mem7_cen_a), - .addr1 (mem7_addr_a), - .dout1 (mem7_dout_a) - ); - -//------------- MBIST6 - 256x32 ---- - -mbist_top2 #( - `ifndef SYNTHESIS - .SCW (SCW), // SCAN CHAIN WIDTH - .BIST_ADDR_WD (BIST2_ADDR_WD-2 ), - .BIST_DATA_WD (BIST_DATA_WD ), - .BIST_ADDR_START (8'h00 ), - .BIST_ADDR_END (8'hFB ), - .BIST_REPAIR_ADDR_START (8'hFC ), - .BIST_RAD_WD_I (BIST2_ADDR_WD-2 ), - .BIST_RAD_WD_O (BIST2_ADDR_WD-2 ) - `endif - ) - u_mbist8 ( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif - // SCAN I/F - .scan_en (scan_en_mbist7 ), - .scan_mode (scan_mode_mbist7 ), - .scan_si (scan_out_mbist7 ), - - .scan_en_o (scan_en_mbist8 ), - .scan_mode_o (scan_mode_mbist8 ), - .scan_so (scan_out_mbist8 ), - - .cfg_mem_lphase (cfg_mem_lphase ), - - // Clock Skew adjust - .wbd_clk_int (wbd_clk_mbist8_int), - .cfg_cska_mbist (cfg_cska_mbist8 ), - .wbd_clk_mbist (wbd_clk_mbist8 ), - - // WB I/F - .wb_clk_i (wbd_clk_mbist8 ), - .wb_cyc_i (wbd_mbist8_cyc_o), - .wb_stb_i (wbd_mbist8_stb_o), - .wb_adr_i (wbd_mbist8_adr_o[BIST2_ADDR_WD-1:2]), - .wb_we_i (wbd_mbist8_we_o ), - .wb_dat_i (wbd_mbist8_dat_o), - .wb_sel_i (wbd_mbist8_sel_o), - .wb_dat_o (wbd_mbist8_dat_i), - .wb_ack_o (wbd_mbist8_ack_i), - .wb_err_o ( ), - - .rst_n (bist_rst_n ), - - - .bist_en (bist_en_int[7] ), - .bist_run (bist_run_int[7] ), - .bist_shift (bist_shift_int[7]), - .bist_load (bist_load_int[7] ), - .bist_sdi (bist_sdi_int[7] ), - - .bist_error_cnt (bist_error_cnt7 ), - .bist_correct (bist_correct[7] ), - .bist_error (bist_error[7] ), - .bist_done (bist_done[7] ), - .bist_sdo (bist_sdo[7] ), - - // towards memory - // PORT-A - .mem_clk_a (mem8_clk_a ), - .mem_addr_a (mem8_addr_a ), - .mem_cen_a (mem8_cen_a ), - .mem_dout_a (mem8_dout_a ), - // PORT-B - .mem_clk_b (mem8_clk_b ), - .mem_cen_b (mem8_cen_b ), - .mem_web_b (mem8_web_b ), - .mem_mask_b (mem8_mask_b ), - .mem_addr_b (mem8_addr_b ), - .mem_din_b (mem8_din_b ) - - -); - -sky130_sram_1kbyte_1rw1r_32x256_8 u_sram8_1kb( -`ifdef USE_POWER_PINS - .vccd1 (vccd1),// User area 1 1.8V supply - .vssd1 (vssd1),// User area 1 digital ground -`endif -// Port 0: RW - .clk0 (mem8_clk_b), - .csb0 (mem8_cen_b), - .web0 (mem8_web_b), - .wmask0 (mem8_mask_b), - .addr0 (mem8_addr_b), - .din0 (mem8_din_b), - .dout0 (), -// Port 1: R - .clk1 (mem8_clk_a), - .csb1 (mem8_cen_a), - .addr1 (mem8_addr_a), - .dout1 (mem8_dout_a) - ); endmodule // user_project_wrapper
diff --git a/verilog/rtl/user_reg_map.v b/verilog/rtl/user_reg_map.v index 0868a11..03b1efc 100644 --- a/verilog/rtl/user_reg_map.v +++ b/verilog/rtl/user_reg_map.v
@@ -5,22 +5,19 @@ `define ADDR_SPACE_WBHOST 32'h3008_0000 `define ADDR_SPACE_LBIST 32'h300C_0000 `define ADDR_SPACE_GLBL 32'h3000_0000 -`define ADDR_SPACE_MBIST1 32'h3000_1000 -`define ADDR_SPACE_MBIST2 32'h3000_2000 -`define ADDR_SPACE_MBIST3 32'h3000_3000 -`define ADDR_SPACE_MBIST4 32'h3000_4000 -`define ADDR_SPACE_MBIST5 32'h3000_5000 -`define ADDR_SPACE_MBIST6 32'h3000_6000 -`define ADDR_SPACE_MBIST7 32'h3000_7000 -`define ADDR_SPACE_MBIST8 32'h3000_8000 +`define ADDR_SPACE_MAC 32'h3000_1000 +`define ADDR_SPACE_SRAM0 32'h3000_2000 +`define ADDR_SPACE_SRAM1 32'h3000_2800 +`define ADDR_SPACE_SRAM2 32'h3000_3000 +`define ADDR_SPACE_SRAM3 32'h3000_3800 //-------------------------------------------------- // WB Host Register //-------------------------------------------------- -`define WBHOST_GLBL_CFG 8'h00 // reg_0 - Global Config -`define WBHOST_BANK_SEL 8'h04 // reg_1 - Bank Select -`define WBHOST_CLK_CTRL1 8'h08 // reg_2 - Clock Control-1 -`define WBHOST_CLK_CTRL2 8'h0C // reg_3 - Clock Control-2 +`define WBHOST_GLBL_CFG 8'h00 // reg_0 - Global Config +`define WBHOST_BANK_SEL 8'h04 // reg_1 - Bank Select +`define WBHOST_CLK_CTRL1 8'h08 // reg_2 - Clock Control-1 +`define WBHOST_CLK_CTRL2 8'h0C // reg_3 - Clock Control-2 //-------------------------------------------------- // LBIST Register @@ -33,15 +30,14 @@ // GLBL Register //------------------------------------------------- -`define GLBL_BIST_CTRL1 'h08 -`define GLBL_BIST_CTRL2 'h0C -`define GLBL_BIST_STAT1 'h10 -`define GLBL_BIST_STAT2 'h14 -`define GLBL_BIST_SWDATA 'h18 -`define GLBL_BIST_SRDATA 'h1C -`define GLBL_BIST_SPDATA 'h20 -`define GLBL_BIST_SOFT1 'h24 -`define GLBL_BIST_SOFT2 'h28 -`define GLBL_BIST_SOFT3 'h2C +`define GLBL_BIST_CTRL1 'h08 +`define GLBL_BIST_CTRL2 'h0C +`define GLBL_BIST_STAT 'h10 +`define GLBL_BIST_SWDATA 'h18 +`define GLBL_BIST_SRLDATA 'h1C +`define GLBL_BIST_SRMDATA 'h20 +`define GLBL_BIST_SOFT1 'h24 +`define GLBL_BIST_SOFT2 'h28 +`define GLBL_BIST_SOFT3 'h2C
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv index b9a8749..23591a9 100644 --- a/verilog/rtl/wb_host/src/wb_host.sv +++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -88,6 +88,7 @@ output logic wbd_int_rst_n , output logic bist_rst_n , + output logic mac_rst_n , // Master Port input logic wbm_rst_i , // Regular Reset signal @@ -312,7 +313,7 @@ wb_arb u_arb( .clk (wbm_clk_i), .rstn (wbm_rst_n), - .req ({1'b0,wbm_uart_stb_i,(wbm_stb_i & wbm_cyc_i)}), + .req ({1'b0,1'b0,wbm_uart_stb_i,(wbm_stb_i & wbm_cyc_i)}), .gnt (grnt) ); @@ -341,6 +342,7 @@ // Reset bypass for scan mode ctech_mux2x1 u_wb_rst_scan_sel (.A0 (cfg_glb_ctrl[0]), .A1 (scan_rst_n), .S (scan_mode), .X (wbd_int_rst_n)); ctech_mux2x1 u_bist_rst_scan_sel (.A0 (cfg_glb_ctrl[1]), .A1 (scan_rst_n), .S (scan_mode), .X (bist_rst_n)); +ctech_mux2x1 u_mac_rst_scan_sel (.A0 (cfg_glb_ctrl[2]), .A1 (scan_rst_n), .S (scan_mode), .X (mac_rst_n)); // wb_host clock skew control clk_skew_adjust u_skew_wh
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv index 18fc86d..9279cc6 100644 --- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv +++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -13,7 +13,7 @@ // See the License for the specific language governing permissions and // limitations under the License. // SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// SPDX-FileContributor: Created by Dinesh Annayya <dinesh.annayya@gmail.com> // ////////////////////////////////////////////////////////////////////// //// //// @@ -23,22 +23,30 @@ //// https://github.com/dineshannayya/mbist_ctrl.git //// //// //// //// Description //// -//// 1. 1 masters and 5 slaves share bus Wishbone connection //// +//// 1. 1 masters and 2 slaves share bus Wishbone connection //// //// M0 - WB_PORT //// +//// M1 - MAC-TX //// +//// M2 - MAC-RX //// //// S0 - Glbl_Reg //// -//// S1 - MBIST1 //// -//// S2 - MBIST2 //// -//// S3 - MBIST3 //// -//// S4 - MBIST4 //// +//// S1 - MAC //// +//// S2 - MBIST/SRAM BANK //// +//// Architecturally M0 can communicate to S0/S1/S2 //// +//// M1/M2 will communicate only S2 //// +//// Wishone Interconnect Build with Architecture Advantage to //// +//// Avoid Routing conjustion //// //// //// //// To Do: //// //// nothing //// //// //// //// Author(s): //// -//// - Dinesh Annayya, dinesha@opencores.org //// +//// - Dinesh Annayya, dinesh.annayya@gmail.com //// //// //// //// Revision : //// -//// //// +//// 0.0 - Dec 15, 2022, Dinesh A //// +//// Inital Version //// +//// 0.1 - Dec 17, 2022, Dinesh A //// +//// A. Master Port M1/M2 Added //// +//// B. Slave Port S2 Added //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// @@ -74,8 +82,8 @@ parameter CH_DATA_WD = 95 ) ( `ifdef USE_POWER_PINS - input logic vccd1, // User area 1 1.8V supply - input logic vssd1, // User area 1 digital ground + input logic vccd1, // User area 1 1.8V supply + input logic vssd1, // User area 1 digital ground `endif input logic scan_en, input logic scan_mode, @@ -85,137 +93,106 @@ output logic scan_mode_o, // Clock Skew Adjust - input logic [3:0] cfg_cska_wi, - input logic wbd_clk_int, - output logic wbd_clk_wi, + input logic [3:0] cfg_cska_wi, + input logic wbd_clk_int, + output logic wbd_clk_skew, - // Bus repeaters - input [CH_CLK_WD-1:0] ch_clk_in, - output [CH_CLK_WD-1:0] ch_clk_out, - input [CH_DATA_WD-1:0] ch_data_in, - output [CH_DATA_WD-1:0]ch_data_out, + // Bus repeaters + input [CH_CLK_WD-1:0] ch_clk_in, + output [CH_CLK_WD-1:0] ch_clk_out, + input [CH_DATA_WD-1:0] ch_data_in, + output [CH_DATA_WD-1:0] ch_data_out, - input logic clk_i, - input logic rst_n, + input logic clk_i, + input logic rst_n, - // Master 0 Interface - input logic [31:0] m0_wbd_dat_i, - input logic [31:0] m0_wbd_adr_i, - input logic [3:0] m0_wbd_sel_i, - input logic m0_wbd_we_i, - input logic m0_wbd_cyc_i, - input logic m0_wbd_stb_i, - output logic [31:0] m0_wbd_dat_o, - output logic m0_wbd_ack_o, - output logic m0_wbd_err_o, + // Master 0 Interface - WB-HOST + input logic [31:0] m0_wbd_dat_i, + input logic [31:0] m0_wbd_adr_i, + input logic [3:0] m0_wbd_sel_i, + input logic m0_wbd_we_i, + input logic m0_wbd_cyc_i, + input logic m0_wbd_stb_i, + output logic [31:0] m0_wbd_dat_o, + output logic m0_wbd_ack_o, + output logic m0_wbd_err_o, + + // Master 1 Interface - MAC-TX + input logic [31:0] m1_wbd_dat_i, + input logic [12:0] m1_wbd_adr_i, + input logic [3:0] m1_wbd_sel_i, + input logic m1_wbd_we_i, + input logic m1_wbd_cyc_i, + input logic m1_wbd_stb_i, + output logic [31:0] m1_wbd_dat_o, + output logic m1_wbd_ack_o, + output logic m1_wbd_err_o, + // Master 2 Interface - MAC-TX + input logic [31:0] m2_wbd_dat_i, + input logic [12:0] m2_wbd_adr_i, + input logic [3:0] m2_wbd_sel_i, + input logic m2_wbd_we_i, + input logic m2_wbd_cyc_i, + input logic m2_wbd_stb_i, + output logic [31:0] m2_wbd_dat_o, + output logic m2_wbd_ack_o, + output logic m2_wbd_err_o, - // Slave 0 Interface + // Slave 0 Interface - GLOBAL-REG/PINMUX input logic [31:0] s0_wbd_dat_i, input logic s0_wbd_ack_i, - //input logic s0_wbd_err_i, - unused output logic [31:0] s0_wbd_dat_o, - output logic [7:0] s0_wbd_adr_o, - output logic [3:0] s0_wbd_sel_o, + output logic [7:0] s0_wbd_adr_o, + output logic [3:0] s0_wbd_sel_o, output logic s0_wbd_we_o, output logic s0_wbd_cyc_o, output logic s0_wbd_stb_o, + //input logic s0_wbd_err_i, - unused - // Slave 1 Interface + // Slave 1 Interface - MAC input logic [31:0] s1_wbd_dat_i, input logic s1_wbd_ack_i, - // input logic s1_wbd_err_i, - unused output logic [31:0] s1_wbd_dat_o, - output logic [10:0] s1_wbd_adr_o, - output logic [3:0] s1_wbd_sel_o, + output logic [12:0] s1_wbd_adr_o, + output logic [3:0] s1_wbd_sel_o, output logic s1_wbd_we_o, output logic s1_wbd_cyc_o, output logic s1_wbd_stb_o, - - // Slave 2 Interface + // input logic s1_wbd_err_i, - unused + + // Slave 2 Interface - MBIST/SRAM WRAPPER input logic [31:0] s2_wbd_dat_i, input logic s2_wbd_ack_i, - // input logic s2_wbd_err_i, - unused output logic [31:0] s2_wbd_dat_o, - output logic [10:0] s2_wbd_adr_o, // glbl reg need only 8 bits - output logic [3:0] s2_wbd_sel_o, + output logic [12:0] s2_wbd_adr_o, + output logic [3:0] s2_wbd_sel_o, + output logic [9:0] s2_wbd_bl_o, + output logic s2_wbd_bry_o, output logic s2_wbd_we_o, output logic s2_wbd_cyc_o, output logic s2_wbd_stb_o, + // input logic s2_wbd_err_i, - unused - // Slave 3 Interface - // Uart is 8bit interface - input logic [31:0] s3_wbd_dat_i, - input logic s3_wbd_ack_i, - // input logic s3_wbd_err_i, - output logic [31:0] s3_wbd_dat_o, - output logic [10:0] s3_wbd_adr_o, - output logic [3:0] s3_wbd_sel_o, - output logic s3_wbd_we_o, - output logic s3_wbd_cyc_o, - output logic s3_wbd_stb_o, + // MAC Q Occupancy computation + input logic [9:0] mac_tx_qbase_addr, + input logic [9:0] mac_rx_qbase_addr, + output logic mac_tx_qcnt_inc, + output logic mac_tx_qcnt_dec, + output logic mac_rx_qcnt_inc, + output logic mac_rx_qcnt_dec + - // Slave 4 Interface - input logic [31:0] s4_wbd_dat_i, - input logic s4_wbd_ack_i, - // input logic s4_wbd_err_i, - output logic [31:0] s4_wbd_dat_o, - output logic [10:0] s4_wbd_adr_o, - output logic [3:0] s4_wbd_sel_o, - output logic s4_wbd_we_o, - output logic s4_wbd_cyc_o, - output logic s4_wbd_stb_o, - - // Slave 5 Interface - input logic [31:0] s5_wbd_dat_i, - input logic s5_wbd_ack_i, - // input logic s5_wbd_err_i, - unused - output logic [31:0] s5_wbd_dat_o, - output logic [9:0] s5_wbd_adr_o, - output logic [3:0] s5_wbd_sel_o, - output logic s5_wbd_we_o, - output logic s5_wbd_cyc_o, - output logic s5_wbd_stb_o, - - // Slave 6 Interface - input logic [31:0] s6_wbd_dat_i, - input logic s6_wbd_ack_i, - // input logic s6_wbd_err_i, - unused - output logic [31:0] s6_wbd_dat_o, - output logic [9:0] s6_wbd_adr_o, // glbl reg need only 8 bits - output logic [3:0] s6_wbd_sel_o, - output logic s6_wbd_we_o, - output logic s6_wbd_cyc_o, - output logic s6_wbd_stb_o, - - // Slave 7 Interface - // Uart is 8bit interface - input logic [31:0] s7_wbd_dat_i, - input logic s7_wbd_ack_i, - // input logic s7_wbd_err_i, - output logic [31:0] s7_wbd_dat_o, - output logic [9:0] s7_wbd_adr_o, - output logic [3:0] s7_wbd_sel_o, - output logic s7_wbd_we_o, - output logic s7_wbd_cyc_o, - output logic s7_wbd_stb_o, - - // Slave 8 Interface - input logic [31:0] s8_wbd_dat_i, - input logic s8_wbd_ack_i, - // input logic s8_wbd_err_i, - output logic [31:0] s8_wbd_dat_o, - output logic [9:0] s8_wbd_adr_o, - output logic [3:0] s8_wbd_sel_o, - output logic s8_wbd_we_o, - output logic s8_wbd_cyc_o, - output logic s8_wbd_stb_o - ); + ); //////////////////////////////////////////////////////////////////// // // Type define // +parameter TARGET_NULL = 4'b0000; +parameter TARGET_PINMUX = 4'b0001; +parameter TARGET_MAC = 4'b0010; +parameter TARGET_SRAM = 4'b0011; // WishBone Wr Interface @@ -223,6 +200,8 @@ logic [31:0] wbd_dat; logic [31:0] wbd_adr; logic [3:0] wbd_sel; + logic [9:0] wbd_bl; + logic wbd_bry; logic wbd_we; logic wbd_cyc; logic wbd_stb; @@ -233,45 +212,39 @@ typedef struct packed { logic [31:0] wbd_dat; logic wbd_ack; + logic wbd_lack; logic wbd_err; } type_wb_rd_intf; // Master Write Interface type_wb_wr_intf m0_wb_wr; +type_wb_wr_intf m1_wb_wr; +type_wb_wr_intf m2_wb_wr; // Master Read Interface type_wb_rd_intf m0_wb_rd; +type_wb_rd_intf m0_s0_wb_rd; +type_wb_rd_intf m0_s1_wb_rd; +type_wb_rd_intf m0_s2_wb_rd; + +type_wb_rd_intf m1_wb_rd; +type_wb_rd_intf m1_s2_wb_rd; + +type_wb_rd_intf m2_wb_rd; +type_wb_rd_intf m2_s2_wb_rd; // Slave Write Interface type_wb_wr_intf s0_wb_wr; type_wb_wr_intf s1_wb_wr; type_wb_wr_intf s2_wb_wr; -type_wb_wr_intf s3_wb_wr; -type_wb_wr_intf s4_wb_wr; -type_wb_wr_intf s5_wb_wr; -type_wb_wr_intf s6_wb_wr; -type_wb_wr_intf s7_wb_wr; -type_wb_wr_intf s8_wb_wr; // Slave Read Interface type_wb_rd_intf s0_wb_rd; type_wb_rd_intf s1_wb_rd; type_wb_rd_intf s2_wb_rd; -type_wb_rd_intf s3_wb_rd; -type_wb_rd_intf s4_wb_rd; -type_wb_rd_intf s5_wb_rd; -type_wb_rd_intf s6_wb_rd; -type_wb_rd_intf s7_wb_rd; -type_wb_rd_intf s8_wb_rd; -type_wb_wr_intf m_bus_wr; // Multiplexed Master I/F -type_wb_rd_intf m_bus_rd; // Multiplexed Slave I/F - -type_wb_wr_intf s_bus_wr; // Multiplexed Master I/F -type_wb_rd_intf s_bus_rd; // Multiplexed Slave I/F - // channel repeater assign ch_clk_out = ch_clk_in; assign ch_data_out = ch_data_in; @@ -286,37 +259,50 @@ .vccd1 (vccd1 ),// User area 1 1.8V supply .vssd1 (vssd1 ),// User area 1 digital ground `endif - .clk_in (wbd_clk_int ), - .sel (cfg_cska_wi ), - .clk_out (wbd_clk_wi ) + .clk_in (wbd_clk_int ), + .sel (cfg_cska_wi ), + .clk_out (wbd_clk_skew ) ); //------------------------------------------------------------------- // EXTERNAL MEMORY MAP // 0x0000_0000 to 0x0000_0FFF - GLBL -// 0x0000_1000 to 0x0000_1FFF - MBIST1 -// 0x0000_2000 to 0x0000_2FFF - MBIST2 -// 0x0000_3000 to 0x0000_3FFF - MBIST3 -// 0x0000_4000 to 0x0000_4FFF - MBIST4 -// 0x0000_5000 to 0x0000_5FFF - MBIST5 -// 0x0000_6000 to 0x0000_6FFF - MBIST6 -// 0x0000_7000 to 0x0000_7FFF - MBIST7 -// 0x0000_8000 to 0x0000_8FFF - MBIST8 +// 0x0000_1000 to 0x0001_0FFF - MAC +// 0x0000_2000 to 0x0000_27FF - SRAM-2KB - 0 +// 0x0000_2800 to 0x0000_2FFF - SRAM-2KB - 1 +// 0x0000_3000 to 0x0000_37FF - SRAM-2KB - 2 +// 0x0000_3800 to 0x0000_3FFF - SRAM-2KB - 3 // --------------------------------------------------------------------------- // -wire [3:0] m0_wbd_tid_i = (m0_wbd_adr_i[15:12] == 4'b0000 ) ? 4'b0000 : // GLBL - (m0_wbd_adr_i[15:12] == 4'b0001 ) ? 4'b0001 : // MBIST1 - (m0_wbd_adr_i[15:12] == 4'b0010 ) ? 4'b0010 : // MBIST2 - (m0_wbd_adr_i[15:12] == 4'b0011 ) ? 4'b0011 : // MBIST3 - (m0_wbd_adr_i[15:12] == 4'b0100 ) ? 4'b0100 : // MBIST4 - (m0_wbd_adr_i[15:12] == 4'b0101 ) ? 4'b0101 : // MBIST5 - (m0_wbd_adr_i[15:12] == 4'b0110 ) ? 4'b0110 : // MBIST6 - (m0_wbd_adr_i[15:12] == 4'b0111 ) ? 4'b0111 : // MBIST7 - (m0_wbd_adr_i[15:12] == 4'b1000 ) ? 4'b1000 : // MBIST8 - 4'b0000; +wire [3:0] m0_wbd_tid_i = (m0_wbd_adr_i[15:12] == 4'b0000 ) ? TARGET_PINMUX : // GLBL + (m0_wbd_adr_i[15:12] == 4'b0001 ) ? TARGET_MAC : // MAC + (m0_wbd_adr_i[15:13] == 3'b001 ) ? TARGET_SRAM : // MBIST WRAPPER + TARGET_NULL; +//------------------------------------------------------------------- +// EXTERNAL MEMORY MAP +// 0x0000_0000 to 0x0000_0FFF - GLBL +// 0x0000_1000 to 0x0001_0FFF - MAC +// 0x0000_2000 to 0x0000_27FF - SRAM-2KB - 0 +// 0x0000_2800 to 0x0000_2FFF - SRAM-2KB - 1 +// 0x0000_3000 to 0x0000_37FF - SRAM-2KB - 2 +// 0x0000_3800 to 0x0000_3FFF - SRAM-2KB - 3 +// --------------------------------------------------------------------------- +// +wire [3:0] m1_wbd_tid_i = TARGET_SRAM; +//------------------------------------------------------------------- +// EXTERNAL MEMORY MAP +// 0x0000_0000 to 0x0000_0FFF - GLBL +// 0x0000_1000 to 0x0001_0FFF - MAC +// 0x0000_2000 to 0x0000_27FF - SRAM-2KB - 0 +// 0x0000_2800 to 0x0000_2FFF - SRAM-2KB - 1 +// 0x0000_3000 to 0x0000_37FF - SRAM-2KB - 2 +// 0x0000_3800 to 0x0000_3FFF - SRAM-2KB - 3 +// --------------------------------------------------------------------------- +// +wire [3:0] m2_wbd_tid_i = TARGET_SRAM; //---------------------------------------- -// Master Mapping +// Master Mapping - M0 // ------------------------------------- assign m0_wb_wr.wbd_dat = m0_wbd_dat_i; assign m0_wb_wr.wbd_adr = {m0_wbd_adr_i[31:2],2'b00}; @@ -326,11 +312,39 @@ assign m0_wb_wr.wbd_stb = m0_wbd_stb_i; assign m0_wb_wr.wbd_tid = m0_wbd_tid_i; -assign m0_wbd_dat_o = m0_wb_rd.wbd_dat; -assign m0_wbd_ack_o = m0_wb_rd.wbd_ack; -assign m0_wbd_err_o = m0_wb_rd.wbd_err; +assign m0_wbd_dat_o = m0_wb_rd.wbd_dat; +assign m0_wbd_ack_o = m0_wb_rd.wbd_ack; +assign m0_wbd_err_o = m0_wb_rd.wbd_err; +//---------------------------------------- +// Master Mapping - M1 +// ------------------------------------- +assign m1_wb_wr.wbd_dat = m1_wbd_dat_i; +assign m1_wb_wr.wbd_adr = {19'h0,m1_wbd_adr_i[12:2],2'b00}; +assign m1_wb_wr.wbd_sel = m1_wbd_sel_i; +assign m1_wb_wr.wbd_we = m1_wbd_we_i; +assign m1_wb_wr.wbd_cyc = m1_wbd_cyc_i; +assign m1_wb_wr.wbd_stb = m1_wbd_stb_i; +assign m1_wb_wr.wbd_tid = m1_wbd_tid_i; +assign m1_wbd_dat_o = m1_wb_rd.wbd_dat; +assign m1_wbd_ack_o = m1_wb_rd.wbd_ack; +assign m1_wbd_err_o = m1_wb_rd.wbd_err; + +//---------------------------------------- +// Master Mapping - M2 +// ------------------------------------- +assign m2_wb_wr.wbd_dat = m2_wbd_dat_i; +assign m2_wb_wr.wbd_adr = {19'h0,m2_wbd_adr_i[12:2],2'b00}; +assign m2_wb_wr.wbd_sel = m2_wbd_sel_i; +assign m2_wb_wr.wbd_we = m2_wbd_we_i; +assign m2_wb_wr.wbd_cyc = m2_wbd_cyc_i; +assign m2_wb_wr.wbd_stb = m2_wbd_stb_i; +assign m2_wb_wr.wbd_tid = m2_wbd_tid_i; + +assign m2_wbd_dat_o = m2_wb_rd.wbd_dat; +assign m2_wbd_ack_o = m2_wb_rd.wbd_ack; +assign m2_wbd_err_o = m2_wb_rd.wbd_err; //---------------------------------------- // Slave Mapping // ------------------------------------- @@ -342,177 +356,187 @@ assign s0_wbd_cyc_o = s0_wb_wr.wbd_cyc ; assign s0_wbd_stb_o = s0_wb_wr.wbd_stb ; -// 2KB SRAM + assign s0_wb_rd.wbd_dat = s0_wbd_dat_i ; + assign s0_wb_rd.wbd_ack = s0_wbd_ack_i ; + assign s0_wb_rd.wbd_err = 1'b0; // s0_wbd_err_i ; - unused + +//-------------------------------------------- +// MAC +//-------------------------------------------- assign s1_wbd_dat_o = s1_wb_wr.wbd_dat ; - assign s1_wbd_adr_o = s1_wb_wr.wbd_adr[10:0] ; + assign s1_wbd_adr_o = s1_wb_wr.wbd_adr[12:0] ; assign s1_wbd_sel_o = s1_wb_wr.wbd_sel ; assign s1_wbd_we_o = s1_wb_wr.wbd_we ; assign s1_wbd_cyc_o = s1_wb_wr.wbd_cyc ; assign s1_wbd_stb_o = s1_wb_wr.wbd_stb ; - assign s2_wbd_dat_o = s2_wb_wr.wbd_dat ; - assign s2_wbd_adr_o = s2_wb_wr.wbd_adr[10:0] ; // Global Reg Need 8 bit - assign s2_wbd_sel_o = s2_wb_wr.wbd_sel ; - assign s2_wbd_we_o = s2_wb_wr.wbd_we ; - assign s2_wbd_cyc_o = s2_wb_wr.wbd_cyc ; - assign s2_wbd_stb_o = s2_wb_wr.wbd_stb ; - - assign s3_wbd_dat_o = s3_wb_wr.wbd_dat; - assign s3_wbd_adr_o = s3_wb_wr.wbd_adr[10:0] ; // Global Reg Need 8 bit - assign s3_wbd_sel_o = s3_wb_wr.wbd_sel; - assign s3_wbd_we_o = s3_wb_wr.wbd_we ; - assign s3_wbd_cyc_o = s3_wb_wr.wbd_cyc ; - assign s3_wbd_stb_o = s3_wb_wr.wbd_stb ; - - assign s4_wbd_dat_o = s4_wb_wr.wbd_dat ; - assign s4_wbd_adr_o = s4_wb_wr.wbd_adr[10:0] ; // Global Reg Need 8 bit - assign s4_wbd_sel_o = s4_wb_wr.wbd_sel ; - assign s4_wbd_we_o = s4_wb_wr.wbd_we ; - assign s4_wbd_cyc_o = s4_wb_wr.wbd_cyc ; - assign s4_wbd_stb_o = s4_wb_wr.wbd_stb ; - -// 1KB SRAM - assign s5_wbd_dat_o = s5_wb_wr.wbd_dat ; - assign s5_wbd_adr_o = s5_wb_wr.wbd_adr[9:0] ; - assign s5_wbd_sel_o = s5_wb_wr.wbd_sel ; - assign s5_wbd_we_o = s5_wb_wr.wbd_we ; - assign s5_wbd_cyc_o = s5_wb_wr.wbd_cyc ; - assign s5_wbd_stb_o = s5_wb_wr.wbd_stb ; - - assign s6_wbd_dat_o = s6_wb_wr.wbd_dat ; - assign s6_wbd_adr_o = s6_wb_wr.wbd_adr[9:0] ; // Global Reg Need 8 bit - assign s6_wbd_sel_o = s6_wb_wr.wbd_sel ; - assign s6_wbd_we_o = s6_wb_wr.wbd_we ; - assign s6_wbd_cyc_o = s6_wb_wr.wbd_cyc ; - assign s6_wbd_stb_o = s6_wb_wr.wbd_stb ; - - assign s7_wbd_dat_o = s7_wb_wr.wbd_dat; - assign s7_wbd_adr_o = s7_wb_wr.wbd_adr[9:0] ; // Global Reg Need 8 bit - assign s7_wbd_sel_o = s7_wb_wr.wbd_sel; - assign s7_wbd_we_o = s7_wb_wr.wbd_we ; - assign s7_wbd_cyc_o = s7_wb_wr.wbd_cyc ; - assign s7_wbd_stb_o = s7_wb_wr.wbd_stb ; - - assign s8_wbd_dat_o = s8_wb_wr.wbd_dat ; - assign s8_wbd_adr_o = s8_wb_wr.wbd_adr[9:0] ; // Global Reg Need 8 bit - assign s8_wbd_sel_o = s8_wb_wr.wbd_sel ; - assign s8_wbd_we_o = s8_wb_wr.wbd_we ; - assign s8_wbd_cyc_o = s8_wb_wr.wbd_cyc ; - assign s8_wbd_stb_o = s8_wb_wr.wbd_stb ; - - assign s0_wb_rd.wbd_dat = s0_wbd_dat_i ; - assign s0_wb_rd.wbd_ack = s0_wbd_ack_i ; - assign s0_wb_rd.wbd_err = 1'b0; // s0_wbd_err_i ; - unused - assign s1_wb_rd.wbd_dat = s1_wbd_dat_i ; assign s1_wb_rd.wbd_ack = s1_wbd_ack_i ; assign s1_wb_rd.wbd_err = 1'b0; // s1_wbd_err_i ; - unused - + +//--------------------------------------------- +// 2KB * 4 SRAM +//--------------------------------------------- + assign s2_wbd_dat_o = s2_wb_wr.wbd_dat ; + assign s2_wbd_adr_o = s2_wb_wr.wbd_adr[12:0] ; + assign s2_wbd_sel_o = s2_wb_wr.wbd_sel ; + assign s2_wbd_bl_o = 'h1 ; + assign s2_wbd_bry_o = 'b1 ; + assign s2_wbd_we_o = s2_wb_wr.wbd_we ; + assign s2_wbd_cyc_o = s2_wb_wr.wbd_cyc ; + assign s2_wbd_stb_o = s2_wb_wr.wbd_stb ; + assign s2_wb_rd.wbd_dat = s2_wbd_dat_i ; assign s2_wb_rd.wbd_ack = s2_wbd_ack_i ; - assign s2_wb_rd.wbd_err = 1'b0; // s2_wbd_err_i ; - unused - - assign s3_wb_rd.wbd_dat = s3_wbd_dat_i ; - assign s3_wb_rd.wbd_ack = s3_wbd_ack_i ; - assign s3_wb_rd.wbd_err = 1'b0; // s3_wbd_err_i ; - unused - - assign s4_wb_rd.wbd_dat = s4_wbd_dat_i ; - assign s4_wb_rd.wbd_ack = s4_wbd_ack_i ; - assign s4_wb_rd.wbd_err = 1'b0; // s4_wbd_err_i ; - unused + assign s2_wb_rd.wbd_err = 1'b0; // s1_wbd_err_i ; - unused - assign s5_wb_rd.wbd_dat = s5_wbd_dat_i ; - assign s5_wb_rd.wbd_ack = s5_wbd_ack_i ; - assign s5_wb_rd.wbd_err = 1'b0; // s5_wbd_err_i ; - unused - - assign s6_wb_rd.wbd_dat = s6_wbd_dat_i ; - assign s6_wb_rd.wbd_ack = s6_wbd_ack_i ; - assign s6_wb_rd.wbd_err = 1'b0; // s6_wbd_err_i ; - unused - assign s7_wb_rd.wbd_dat = s7_wbd_dat_i ; - assign s7_wb_rd.wbd_ack = s7_wbd_ack_i ; - assign s7_wb_rd.wbd_err = 1'b0; // s7_wbd_err_i ; - unused - - assign s8_wb_rd.wbd_dat = s8_wbd_dat_i ; - assign s8_wb_rd.wbd_ack = s8_wbd_ack_i ; - assign s8_wb_rd.wbd_err = 1'b0; // s8_wbd_err_i ; - unused -// -// arbitor removed as only one master -// -wire [1:0] gnt = 2'b0;; - - -// Generate Multiplexed Master Interface based on grant -always_comb begin - case(gnt) - 2'h0: m_bus_wr = m0_wb_wr; - default: m_bus_wr = m0_wb_wr; - endcase -end - - -// Generate Multiplexed Slave Interface based on target Id -wire [3:0] s_wbd_tid = s_bus_wr.wbd_tid; // to fix iverilog warning -always_comb begin - case(s_wbd_tid) - 4'h0: s_bus_rd = s0_wb_rd; - 4'h1: s_bus_rd = s1_wb_rd; - 4'h2: s_bus_rd = s2_wb_rd; - 4'h3: s_bus_rd = s3_wb_rd; - 4'h4: s_bus_rd = s4_wb_rd; - 4'h5: s_bus_rd = s5_wb_rd; - 4'h6: s_bus_rd = s6_wb_rd; - 4'h7: s_bus_rd = s7_wb_rd; - 4'h8: s_bus_rd = s8_wb_rd; - default: s_bus_rd = s0_wb_rd; - endcase -end - - +//--------------------------------------------- // Connect Master => Slave -assign s0_wb_wr = (s_wbd_tid == 4'b0000) ? s_bus_wr : 'h0; -assign s1_wb_wr = (s_wbd_tid == 4'b0001) ? s_bus_wr : 'h0; -assign s2_wb_wr = (s_wbd_tid == 4'b0010) ? s_bus_wr : 'h0; -assign s3_wb_wr = (s_wbd_tid == 4'b0011) ? s_bus_wr : 'h0; -assign s4_wb_wr = (s_wbd_tid == 4'b0100) ? s_bus_wr : 'h0; -assign s5_wb_wr = (s_wbd_tid == 4'b0101) ? s_bus_wr : 'h0; -assign s6_wb_wr = (s_wbd_tid == 4'b0110) ? s_bus_wr : 'h0; -assign s7_wb_wr = (s_wbd_tid == 4'b0111) ? s_bus_wr : 'h0; -assign s8_wb_wr = (s_wbd_tid == 4'b1000) ? s_bus_wr : 'h0; - // Connect Slave to Master -assign m0_wb_rd = (gnt == 2'b00) ? m_bus_rd : 'h0; +//--------------------------------------------- +assign m0_wb_rd = (m0_wbd_tid_i == TARGET_PINMUX) ? m0_s0_wb_rd : + (m0_wbd_tid_i == TARGET_MAC) ? m0_s1_wb_rd : + (m0_wbd_tid_i == TARGET_SRAM) ? m0_s2_wb_rd : 'h0; + +assign m1_wb_rd = (m1_wbd_tid_i == TARGET_SRAM) ? m1_s2_wb_rd : 'h0; +assign m2_wb_rd = (m2_wbd_tid_i == TARGET_SRAM) ? m2_s2_wb_rd : 'h0; + +// M0 (WB-HOST) only can access S0 (Pinmux/Glbl Reg) // Stagging FF to break write and read timing path -wb_stagging u_m_wb_stage( - .clk_i (clk_i ), - .rst_n (rst_n ), +wb_stagging u_s0( + .clk_i (clk_i ), + .rst_n (rst_n ), + .cfg_slave_id (TARGET_PINMUX ), // WishBone Input master I/P - .m_wbd_dat_i (m_bus_wr.wbd_dat ), - .m_wbd_adr_i (m_bus_wr.wbd_adr ), - .m_wbd_sel_i (m_bus_wr.wbd_sel ), - .m_wbd_we_i (m_bus_wr.wbd_we ), - .m_wbd_cyc_i (m_bus_wr.wbd_cyc ), - .m_wbd_stb_i (m_bus_wr.wbd_stb ), - .m_wbd_tid_i (m_bus_wr.wbd_tid ), - .m_wbd_dat_o (m_bus_rd.wbd_dat ), - .m_wbd_ack_o (m_bus_rd.wbd_ack ), - .m_wbd_err_o (m_bus_rd.wbd_err ), + .m_wbd_dat_i (m0_wb_wr.wbd_dat ), + .m_wbd_adr_i (m0_wb_wr.wbd_adr ), + .m_wbd_sel_i (m0_wb_wr.wbd_sel ), + .m_wbd_we_i (m0_wb_wr.wbd_we ), + .m_wbd_cyc_i (m0_wb_wr.wbd_cyc ), + .m_wbd_stb_i (m0_wb_wr.wbd_stb ), + .m_wbd_tid_i (m0_wb_wr.wbd_tid ), + .m_wbd_dat_o (m0_s0_wb_rd.wbd_dat ), + .m_wbd_ack_o (m0_s0_wb_rd.wbd_ack ), + .m_wbd_err_o (m0_s0_wb_rd.wbd_err ), // Slave Interface - .s_wbd_dat_i (s_bus_rd.wbd_dat ), - .s_wbd_ack_i (s_bus_rd.wbd_ack ), - .s_wbd_err_i (s_bus_rd.wbd_err ), - .s_wbd_dat_o (s_bus_wr.wbd_dat ), - .s_wbd_adr_o (s_bus_wr.wbd_adr ), - .s_wbd_sel_o (s_bus_wr.wbd_sel ), - .s_wbd_we_o (s_bus_wr.wbd_we ), - .s_wbd_cyc_o (s_bus_wr.wbd_cyc ), - .s_wbd_stb_o (s_bus_wr.wbd_stb ), - .s_wbd_tid_o (s_bus_wr.wbd_tid ) + .s_wbd_dat_i (s0_wb_rd.wbd_dat ), + .s_wbd_ack_i (s0_wb_rd.wbd_ack ), + .s_wbd_err_i (s0_wb_rd.wbd_err ), + .s_wbd_dat_o (s0_wb_wr.wbd_dat ), + .s_wbd_adr_o (s0_wb_wr.wbd_adr ), + .s_wbd_sel_o (s0_wb_wr.wbd_sel ), + .s_wbd_we_o (s0_wb_wr.wbd_we ), + .s_wbd_cyc_o (s0_wb_wr.wbd_cyc ), + .s_wbd_stb_o (s0_wb_wr.wbd_stb ), + .s_wbd_tid_o (s0_wb_wr.wbd_tid ) ); +// M0 (WB-HOST) only can access S1 (MAC) +// Stagging FF to break write and read timing path +wb_stagging u_s1( + .clk_i (clk_i ), + .rst_n (rst_n ), + .cfg_slave_id (TARGET_MAC ), + // WishBone Input master I/P + .m_wbd_dat_i (m0_wb_wr.wbd_dat ), + .m_wbd_adr_i (m0_wb_wr.wbd_adr ), + .m_wbd_sel_i (m0_wb_wr.wbd_sel ), + .m_wbd_we_i (m0_wb_wr.wbd_we ), + .m_wbd_cyc_i (m0_wb_wr.wbd_cyc ), + .m_wbd_stb_i (m0_wb_wr.wbd_stb ), + .m_wbd_tid_i (m0_wb_wr.wbd_tid ), + .m_wbd_dat_o (m0_s1_wb_rd.wbd_dat ), + .m_wbd_ack_o (m0_s1_wb_rd.wbd_ack ), + .m_wbd_err_o (m0_s1_wb_rd.wbd_err ), + + // Slave Interface + .s_wbd_dat_i (s1_wb_rd.wbd_dat ), + .s_wbd_ack_i (s1_wb_rd.wbd_ack ), + .s_wbd_err_i (s1_wb_rd.wbd_err ), + .s_wbd_dat_o (s1_wb_wr.wbd_dat ), + .s_wbd_adr_o (s1_wb_wr.wbd_adr ), + .s_wbd_sel_o (s1_wb_wr.wbd_sel ), + .s_wbd_we_o (s1_wb_wr.wbd_we ), + .s_wbd_cyc_o (s1_wb_wr.wbd_cyc ), + .s_wbd_stb_o (s1_wb_wr.wbd_stb ), + .s_wbd_tid_o (s1_wb_wr.wbd_tid ) + +); + +// M0 (WB-HOST) M1 (MAC-TX) and M2 (MAC-RX) can access S2 (SRAM/MBIST WRAPPER) +// Target Port -0 +// QCounter Inc/dec generation +// Ned to move this logic to wishbone interconnect +assign mac_tx_qcnt_inc = (mac_tx_qbase_addr == s2_wb_wr.wbd_adr[15:6]) && s2_wb_wr.wbd_stb && s2_wb_wr.wbd_we && s2_wb_rd.wbd_ack && (s2_wb_wr.wbd_sel[3] == 1'b1); +assign mac_tx_qcnt_dec = (mac_tx_qbase_addr == s2_wb_wr.wbd_adr[15:6]) && s2_wb_wr.wbd_stb && !s2_wb_wr.wbd_we && s2_wb_rd.wbd_ack && (s2_wb_wr.wbd_sel[3] == 1'b1); +assign mac_rx_qcnt_inc = (mac_rx_qbase_addr == s2_wb_wr.wbd_adr[15:6]) && s2_wb_wr.wbd_stb && s2_wb_wr.wbd_we && s2_wb_rd.wbd_ack && (s2_wb_wr.wbd_sel[3] == 1'b1); +assign mac_rx_qcnt_dec = (mac_rx_qbase_addr == s2_wb_wr.wbd_adr[15:6]) && s2_wb_wr.wbd_stb && !s2_wb_wr.wbd_we && s2_wb_rd.wbd_ack && (s2_wb_wr.wbd_sel[3] == 1'b1); + +wb_slave_port u_s2 ( + + .clk_i (clk_i ), + .rst_n (rst_n ), + .cfg_slave_id (TARGET_SRAM ), + + // Master 0 Interface + .m0_wbd_dat_i (m0_wb_wr.wbd_dat ), + .m0_wbd_adr_i (m0_wb_wr.wbd_adr ), + .m0_wbd_sel_i (m0_wb_wr.wbd_sel ), + .m0_wbd_we_i (m0_wb_wr.wbd_we ), + .m0_wbd_cyc_i (m0_wb_wr.wbd_cyc ), + .m0_wbd_stb_i (m0_wb_wr.wbd_stb ), + .m0_wbd_tid_i (m0_wb_wr.wbd_tid ), + .m0_wbd_dat_o (m0_s2_wb_rd.wbd_dat ), + .m0_wbd_ack_o (m0_s2_wb_rd.wbd_ack ), + .m0_wbd_lack_o (m0_s2_wb_rd.wbd_lack ), + .m0_wbd_err_o (m0_s2_wb_rd.wbd_err ), + + // Master 1 Interface + .m1_wbd_dat_i (m1_wb_wr.wbd_dat ), + .m1_wbd_adr_i (m1_wb_wr.wbd_adr ), + .m1_wbd_sel_i (m1_wb_wr.wbd_sel ), + .m1_wbd_we_i (m1_wb_wr.wbd_we ), + .m1_wbd_cyc_i (m1_wb_wr.wbd_cyc ), + .m1_wbd_stb_i (m1_wb_wr.wbd_stb ), + .m1_wbd_tid_i (m1_wb_wr.wbd_tid ), + .m1_wbd_dat_o (m1_s2_wb_rd.wbd_dat ), + .m1_wbd_ack_o (m1_s2_wb_rd.wbd_ack ), + .m1_wbd_lack_o (m1_s2_wb_rd.wbd_lack ), + .m1_wbd_err_o (m1_s2_wb_rd.wbd_err ), + + // Master 2 Interface + .m2_wbd_dat_i (m2_wb_wr.wbd_dat ), + .m2_wbd_adr_i (m2_wb_wr.wbd_adr ), + .m2_wbd_sel_i (m2_wb_wr.wbd_sel ), + .m2_wbd_we_i (m2_wb_wr.wbd_we ), + .m2_wbd_cyc_i (m2_wb_wr.wbd_cyc ), + .m2_wbd_stb_i (m2_wb_wr.wbd_stb ), + .m2_wbd_tid_i (m2_wb_wr.wbd_tid ), + .m2_wbd_dat_o (m2_s2_wb_rd.wbd_dat ), + .m2_wbd_ack_o (m2_s2_wb_rd.wbd_ack ), + .m2_wbd_lack_o (m2_s2_wb_rd.wbd_lack ), + .m2_wbd_err_o (m2_s2_wb_rd.wbd_err ), + + + + // Slave Interface + .s_wbd_dat_i (s2_wb_rd.wbd_dat ), + .s_wbd_ack_i (s2_wb_rd.wbd_ack ), + .s_wbd_lack_i (s2_wb_rd.wbd_ack ), + .s_wbd_dat_o (s2_wb_wr.wbd_dat ), + .s_wbd_adr_o (s2_wb_wr.wbd_adr ), + .s_wbd_sel_o (s2_wb_wr.wbd_sel ), + .s_wbd_we_o (s2_wb_wr.wbd_we ), + .s_wbd_cyc_o (s2_wb_wr.wbd_cyc ), + .s_wbd_stb_o (s2_wb_wr.wbd_stb ) + + ); + endmodule
diff --git a/verilog/rtl/wb_interconnect/src/wb_slave_port.sv b/verilog/rtl/wb_interconnect/src/wb_slave_port.sv new file mode 100644 index 0000000..6b23e88 --- /dev/null +++ b/verilog/rtl/wb_interconnect/src/wb_slave_port.sv
@@ -0,0 +1,253 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// +////////////////////////////////////////////////////////////////////// +//// //// +//// Wishbone interconnect for slave port //// +//// //// +//// This file is part of the YIFive cores project //// +//// https://github.com/dineshannayya/riscduino.git //// +//// //// +//// Description //// +//// 1. This block implement simple round robine request //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.1 - Mar 2, 2022, Dinesh A //// +////////////////////////////////////////////////////////////////////// + + + +module wb_slave_port ( + input logic clk_i, + input logic rst_n, + + input logic [3:0] cfg_slave_id, + + + // Master 0 Interface + input logic [31:0] m0_wbd_dat_i, + input logic [31:0] m0_wbd_adr_i, + input logic [3:0] m0_wbd_sel_i, + input logic m0_wbd_we_i, + input logic m0_wbd_cyc_i, + input logic m0_wbd_stb_i, + input logic [3:0] m0_wbd_tid_i, + output logic [31:0] m0_wbd_dat_o, + output logic m0_wbd_ack_o, + output logic m0_wbd_lack_o, + output logic m0_wbd_err_o, + + // Master 1 Interface + input logic [31:0] m1_wbd_dat_i, + input logic [31:0] m1_wbd_adr_i, + input logic [3:0] m1_wbd_sel_i, + input logic m1_wbd_we_i, + input logic m1_wbd_cyc_i, + input logic m1_wbd_stb_i, + input logic [3:0] m1_wbd_tid_i, + output logic [31:0] m1_wbd_dat_o, + output logic m1_wbd_ack_o, + output logic m1_wbd_lack_o, + output logic m1_wbd_err_o, + + // Master 2 Interface + input logic [31:0] m2_wbd_dat_i, + input logic [31:0] m2_wbd_adr_i, + input logic [3:0] m2_wbd_sel_i, + input logic m2_wbd_we_i, + input logic m2_wbd_cyc_i, + input logic m2_wbd_stb_i, + input logic [3:0] m2_wbd_tid_i, + output logic [31:0] m2_wbd_dat_o, + output logic m2_wbd_ack_o, + output logic m2_wbd_lack_o, + output logic m2_wbd_err_o, + + // Slave 0 Interface + input logic [31:0] s_wbd_dat_i, + input logic s_wbd_ack_i, + input logic s_wbd_lack_i, + output logic [31:0] s_wbd_dat_o, + output logic [31:0] s_wbd_adr_o, + output logic [3:0] s_wbd_sel_o, + output logic [9:0] s_wbd_bl_o, + output logic s_wbd_bry_o, + output logic s_wbd_we_o, + output logic s_wbd_cyc_o, + output logic s_wbd_stb_o + + ); + +// WishBone Wr Interface +typedef struct packed { + logic [31:0] wbd_dat; + logic [31:0] wbd_adr; + logic [3:0] wbd_sel; + logic [9:0] wbd_bl; + logic wbd_bry; + logic wbd_we; + logic wbd_cyc; + logic wbd_stb; + logic [3:0] wbd_tid; // target id +} type_wb_wr_intf; + +// WishBone Rd Interface +typedef struct packed { + logic [31:0] wbd_dat; + logic wbd_ack; + logic wbd_lack; + logic wbd_err; +} type_wb_rd_intf; + + +// Master Write Interface +type_wb_wr_intf m0_wb_wr; +type_wb_wr_intf m1_wb_wr; +type_wb_wr_intf m2_wb_wr; + +// Master Read Interface +type_wb_rd_intf m0_wb_rd; +type_wb_rd_intf m1_wb_rd; +type_wb_rd_intf m2_wb_rd; + +wire m0_stb_i = (m0_wbd_stb_i & (m0_wbd_tid_i== cfg_slave_id)); +wire m1_stb_i = (m1_wbd_stb_i & (m1_wbd_tid_i== cfg_slave_id)); +wire m2_stb_i = (m2_wbd_stb_i & (m2_wbd_tid_i== cfg_slave_id)); + +type_wb_wr_intf m_bus_wr; // Multiplexed Master I/F +type_wb_rd_intf m_bus_rd; // Multiplexed Slave I/F + +//---------------------------------------- +// Master Mapping +// ------------------------------------- +assign m0_wb_wr.wbd_dat = m0_wbd_dat_i; +assign m0_wb_wr.wbd_adr = {m0_wbd_adr_i[31:2],2'b00}; +assign m0_wb_wr.wbd_sel = m0_wbd_sel_i; +assign m0_wb_wr.wbd_bl = 'h1; +assign m0_wb_wr.wbd_bry = 'b1; +assign m0_wb_wr.wbd_we = m0_wbd_we_i; +assign m0_wb_wr.wbd_cyc = m0_wbd_cyc_i; +assign m0_wb_wr.wbd_stb = m0_stb_i; +assign m0_wb_wr.wbd_tid = m0_wbd_tid_i; + +assign m1_wb_wr.wbd_dat = m1_wbd_dat_i; +assign m1_wb_wr.wbd_adr = {m1_wbd_adr_i[31:2],2'b00}; +assign m1_wb_wr.wbd_sel = m1_wbd_sel_i; +assign m1_wb_wr.wbd_bl = 'h1; +assign m1_wb_wr.wbd_bry = 'b1; +assign m1_wb_wr.wbd_we = m1_wbd_we_i; +assign m1_wb_wr.wbd_cyc = m1_wbd_cyc_i; +assign m1_wb_wr.wbd_stb = m1_stb_i; +assign m1_wb_wr.wbd_tid = m1_wbd_tid_i; + +assign m2_wb_wr.wbd_dat = m2_wbd_dat_i; +assign m2_wb_wr.wbd_adr = {m2_wbd_adr_i[31:2],2'b00}; +assign m2_wb_wr.wbd_sel = m2_wbd_sel_i; +assign m2_wb_wr.wbd_bl = 'h1; +assign m2_wb_wr.wbd_bry = 'b1; +assign m2_wb_wr.wbd_we = m2_wbd_we_i; +assign m2_wb_wr.wbd_cyc = m2_wbd_cyc_i; +assign m2_wb_wr.wbd_stb = m2_stb_i; +assign m2_wb_wr.wbd_tid = m2_wbd_tid_i; + +assign m0_wbd_dat_o = m0_wb_rd.wbd_dat; +assign m0_wbd_ack_o = m0_wb_rd.wbd_ack; +assign m0_wbd_lack_o = m0_wb_rd.wbd_lack; +assign m0_wbd_err_o = m0_wb_rd.wbd_err; + +assign m1_wbd_dat_o = m1_wb_rd.wbd_dat; +assign m1_wbd_ack_o = m1_wb_rd.wbd_ack; +assign m1_wbd_lack_o = m1_wb_rd.wbd_lack; +assign m1_wbd_err_o = m1_wb_rd.wbd_err; + +assign m2_wbd_dat_o = m2_wb_rd.wbd_dat; +assign m2_wbd_ack_o = m2_wb_rd.wbd_ack; +assign m2_wbd_lack_o = m2_wb_rd.wbd_lack; +assign m2_wbd_err_o = m2_wb_rd.wbd_err; + +// +// arbitor +// +logic [1:0] gnt; +wb_arb u_wb_arb( + .clk(clk_i), + .rstn(rst_n), + .req({ 1'b0, + m2_stb_i & !m2_wbd_lack_o, + m1_stb_i & !m1_wbd_lack_o, + m0_stb_i & !m0_wbd_lack_o}), + .gnt(gnt) +); + +// Generate Multiplexed Master Interface based on grant +always_comb begin + case(gnt) + 2'h0: m_bus_wr = m0_wb_wr; + 2'h1: m_bus_wr = m1_wb_wr; + 2'h2: m_bus_wr = m2_wb_wr; + default: m_bus_wr = m0_wb_wr; + endcase +end + +// Stagging FF to break write and read timing path +sync_wbb u_sync_wbb( + .clk_i (clk_i ), + .rst_n (rst_n ), + // WishBone Input master I/P + .wbm_dat_i (m_bus_wr.wbd_dat ), + .wbm_adr_i (m_bus_wr.wbd_adr ), + .wbm_sel_i (m_bus_wr.wbd_sel ), + .wbm_bl_i (m_bus_wr.wbd_bl ), + .wbm_bry_i (m_bus_wr.wbd_bry ), + .wbm_we_i (m_bus_wr.wbd_we ), + .wbm_cyc_i (m_bus_wr.wbd_cyc ), + .wbm_stb_i (m_bus_wr.wbd_stb ), + .wbm_tid_i (m_bus_wr.wbd_tid ), + .wbm_dat_o (m_bus_rd.wbd_dat ), + .wbm_ack_o (m_bus_rd.wbd_ack ), + .wbm_lack_o (m_bus_rd.wbd_lack ), + .wbm_err_o (m_bus_rd.wbd_err ), + + // Slave Interface + .wbs_dat_i (s_wbd_dat_i ), + .wbs_ack_i (s_wbd_ack_i ), + .wbs_lack_i (s_wbd_lack_i ), + .wbs_err_i (1'b0 ), + .wbs_dat_o (s_wbd_dat_o ), + .wbs_adr_o (s_wbd_adr_o ), + .wbs_sel_o (s_wbd_sel_o ), + .wbs_bl_o (s_wbd_bl_o ), + .wbs_bry_o (s_wbd_bry_o ), + .wbs_we_o (s_wbd_we_o ), + .wbs_cyc_o (s_wbd_cyc_o ), + .wbs_stb_o (s_wbd_stb_o ), + .wbs_tid_o ( ) + +); + +// Connect Slave to Master +assign m0_wb_rd = (gnt == 2'b00) ? m_bus_rd : 'h0; +assign m1_wb_rd = (gnt == 2'b01) ? m_bus_rd : 'h0; +assign m2_wb_rd = (gnt == 2'b10) ? m_bus_rd : 'h0; + +endmodule