sdc/glbl_cfg.sdc

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# Created by write_sdc
# Wed Dec 14 13:43:46 2022
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current_design glbl_cfg
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# Timing Constraints
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create_clock -name mclk -period 10.0000 [get_ports {mclk}]
set_propagated_clock [get_clocks {mclk}]
set_clock_uncertainty -from [get_clocks {mclk}] -to [get_clocks {mclk}] 0.2500
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_correct[0]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_correct[0]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_correct[1]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_correct[1]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_correct[2]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_correct[2]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_correct[3]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_correct[3]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_correct[4]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_correct[4]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_correct[5]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_correct[5]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_correct[6]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_correct[6]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_correct[7]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_correct[7]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_done[0]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_done[0]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_done[1]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_done[1]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_done[2]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_done[2]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_done[3]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_done[3]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_done[4]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_done[4]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_done[5]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_done[5]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_done[6]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_done[6]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_done[7]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_done[7]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error[0]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error[0]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error[1]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error[1]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error[2]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error[2]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error[3]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error[3]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error[4]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error[4]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error[5]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error[5]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error[6]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error[6]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error[7]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error[7]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt0[0]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt0[0]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt0[1]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt0[1]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt0[2]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt0[2]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt0[3]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt0[3]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt1[0]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt1[0]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt1[1]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt1[1]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt1[2]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt1[2]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt1[3]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt1[3]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt2[0]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt2[0]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt2[1]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt2[1]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt2[2]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt2[2]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt2[3]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt2[3]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt3[0]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt3[0]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt3[1]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt3[1]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt3[2]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt3[2]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt3[3]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt3[3]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt4[0]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt4[0]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt4[1]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt4[1]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt4[2]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt4[2]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt4[3]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt4[3]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt5[0]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt5[0]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt5[1]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt5[1]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt5[2]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt5[2]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt5[3]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt5[3]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt6[0]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt6[0]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt6[1]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt6[1]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt6[2]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt6[2]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt6[3]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt6[3]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt7[0]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt7[0]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt7[1]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt7[1]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt7[2]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt7[2]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_error_cnt7[3]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_error_cnt7[3]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_sdo[0]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_sdo[0]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_sdo[1]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_sdo[1]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_sdo[2]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_sdo[2]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_sdo[3]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_sdo[3]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_sdo[4]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_sdo[4]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_sdo[5]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_sdo[5]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_sdo[6]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_sdo[6]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_sdo[7]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_sdo[7]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[0]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[0]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[1]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[1]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[2]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[2]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[3]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[3]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[4]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[4]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[5]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[5]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[6]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[6]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[7]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[7]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[0]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[0]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[1]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[1]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[2]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[2]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[3]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[3]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_cs}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_cs}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[0]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[0]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[10]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[10]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[11]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[11]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[12]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[12]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[13]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[13]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[14]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[14]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[15]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[15]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[16]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[16]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[17]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[17]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[18]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[18]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[19]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[19]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[1]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[1]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[20]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[20]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[21]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[21]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[22]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[22]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[23]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[23]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[24]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[24]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[25]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[25]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[26]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[26]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[27]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[27]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[28]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[28]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[29]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[29]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[2]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[2]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[30]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[30]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[31]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[31]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[3]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[3]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[4]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[4]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[5]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[5]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[6]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[6]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[7]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[7]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[8]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[8]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[9]}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[9]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wr}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wr}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reset_n}]
set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reset_n}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_en[0]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_en[0]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_en[1]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_en[1]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_en[2]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_en[2]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_en[3]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_en[3]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_en[4]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_en[4]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_en[5]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_en[5]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_en[6]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_en[6]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_en[7]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_en[7]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_load[0]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_load[0]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_load[1]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_load[1]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_load[2]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_load[2]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_load[3]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_load[3]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_load[4]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_load[4]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_load[5]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_load[5]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_load[6]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_load[6]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_load[7]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_load[7]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_run[0]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_run[0]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_run[1]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_run[1]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_run[2]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_run[2]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_run[3]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_run[3]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_run[4]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_run[4]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_run[5]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_run[5]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_run[6]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_run[6]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_run[7]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_run[7]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_sdi[0]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_sdi[0]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_sdi[1]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_sdi[1]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_sdi[2]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_sdi[2]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_sdi[3]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_sdi[3]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_sdi[4]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_sdi[4]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_sdi[5]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_sdi[5]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_sdi[6]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_sdi[6]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_sdi[7]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_sdi[7]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_shift[0]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_shift[0]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_shift[1]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_shift[1]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_shift[2]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_shift[2]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_shift[3]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_shift[3]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_shift[4]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_shift[4]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_shift[5]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_shift[5]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_shift[6]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_shift[6]}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {bist_shift[7]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {bist_shift[7]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_ack}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_ack}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[0]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[0]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[10]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[10]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[11]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[11]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[12]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[12]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[13]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[13]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[14]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[14]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[15]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[15]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[16]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[16]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[17]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[17]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[18]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[18]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[19]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[19]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[1]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[1]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[20]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[20]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[21]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[21]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[22]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[22]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[23]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[23]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[24]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[24]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[25]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[25]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[26]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[26]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[27]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[27]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[28]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[28]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[29]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[29]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[2]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[2]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[30]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[30]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[31]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[31]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[3]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[3]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[4]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[4]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[5]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[5]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[6]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[6]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[7]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[7]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[8]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[8]}]
set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[9]}]
set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[9]}]
set_max_delay\
    -from [get_ports {wbd_clk_int}] 3.5000
set_max_delay\
    -from [get_ports {wbd_clk_int}]\
    -to [get_ports {wbd_clk_glbl}] 2.5000
###############################################################################
# Environment
###############################################################################
set_load -pin_load 0.0334 [get_ports {reg_ack}]
set_load -pin_load 0.0334 [get_ports {scan_en_o}]
set_load -pin_load 0.0334 [get_ports {scan_mode_o}]
set_load -pin_load 0.0334 [get_ports {wbd_clk_glbl}]
set_load -pin_load 0.0334 [get_ports {bist_en[7]}]
set_load -pin_load 0.0334 [get_ports {bist_en[6]}]
set_load -pin_load 0.0334 [get_ports {bist_en[5]}]
set_load -pin_load 0.0334 [get_ports {bist_en[4]}]
set_load -pin_load 0.0334 [get_ports {bist_en[3]}]
set_load -pin_load 0.0334 [get_ports {bist_en[2]}]
set_load -pin_load 0.0334 [get_ports {bist_en[1]}]
set_load -pin_load 0.0334 [get_ports {bist_en[0]}]
set_load -pin_load 0.0334 [get_ports {bist_load[7]}]
set_load -pin_load 0.0334 [get_ports {bist_load[6]}]
set_load -pin_load 0.0334 [get_ports {bist_load[5]}]
set_load -pin_load 0.0334 [get_ports {bist_load[4]}]
set_load -pin_load 0.0334 [get_ports {bist_load[3]}]
set_load -pin_load 0.0334 [get_ports {bist_load[2]}]
set_load -pin_load 0.0334 [get_ports {bist_load[1]}]
set_load -pin_load 0.0334 [get_ports {bist_load[0]}]
set_load -pin_load 0.0334 [get_ports {bist_run[7]}]
set_load -pin_load 0.0334 [get_ports {bist_run[6]}]
set_load -pin_load 0.0334 [get_ports {bist_run[5]}]
set_load -pin_load 0.0334 [get_ports {bist_run[4]}]
set_load -pin_load 0.0334 [get_ports {bist_run[3]}]
set_load -pin_load 0.0334 [get_ports {bist_run[2]}]
set_load -pin_load 0.0334 [get_ports {bist_run[1]}]
set_load -pin_load 0.0334 [get_ports {bist_run[0]}]
set_load -pin_load 0.0334 [get_ports {bist_sdi[7]}]
set_load -pin_load 0.0334 [get_ports {bist_sdi[6]}]
set_load -pin_load 0.0334 [get_ports {bist_sdi[5]}]
set_load -pin_load 0.0334 [get_ports {bist_sdi[4]}]
set_load -pin_load 0.0334 [get_ports {bist_sdi[3]}]
set_load -pin_load 0.0334 [get_ports {bist_sdi[2]}]
set_load -pin_load 0.0334 [get_ports {bist_sdi[1]}]
set_load -pin_load 0.0334 [get_ports {bist_sdi[0]}]
set_load -pin_load 0.0334 [get_ports {bist_shift[7]}]
set_load -pin_load 0.0334 [get_ports {bist_shift[6]}]
set_load -pin_load 0.0334 [get_ports {bist_shift[5]}]
set_load -pin_load 0.0334 [get_ports {bist_shift[4]}]
set_load -pin_load 0.0334 [get_ports {bist_shift[3]}]
set_load -pin_load 0.0334 [get_ports {bist_shift[2]}]
set_load -pin_load 0.0334 [get_ports {bist_shift[1]}]
set_load -pin_load 0.0334 [get_ports {bist_shift[0]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[31]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[30]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[29]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[28]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[27]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[26]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[25]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[24]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[23]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[22]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[21]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[20]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[19]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[18]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[17]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[16]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[15]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[14]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[13]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[12]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[11]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[10]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[9]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[8]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[7]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[6]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[5]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[4]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[3]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[2]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[1]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[0]}]
set_load -pin_load 0.0334 [get_ports {scan_so[7]}]
set_load -pin_load 0.0334 [get_ports {scan_so[6]}]
set_load -pin_load 0.0334 [get_ports {scan_so[5]}]
set_load -pin_load 0.0334 [get_ports {scan_so[4]}]
set_load -pin_load 0.0334 [get_ports {scan_so[3]}]
set_load -pin_load 0.0334 [get_ports {scan_so[2]}]
set_load -pin_load 0.0334 [get_ports {scan_so[1]}]
set_load -pin_load 0.0334 [get_ports {scan_so[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_cs}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wr}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reset_n}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_en}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_mode}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_correct[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_correct[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_correct[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_correct[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_correct[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_correct[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_correct[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_correct[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_done[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_done[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_done[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_done[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_done[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_done[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_done[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_done[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt0[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt0[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt0[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt0[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt1[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt1[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt1[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt1[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt2[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt2[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt2[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt2[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt3[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt3[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt3[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt3[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt4[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt4[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt4[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt4[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt5[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt5[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt5[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt5[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt6[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt6[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt6[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt6[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt7[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt7[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt7[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_error_cnt7[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_sdo[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_sdo[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_sdo[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_sdo[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_sdo[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_sdo[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_sdo[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_sdo[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_glbl[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_glbl[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_glbl[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_glbl[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_si[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_si[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_si[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_si[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_si[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_si[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_si[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_si[0]}]
set_case_analysis 0 [get_ports {cfg_cska_glbl[0]}]
set_case_analysis 0 [get_ports {cfg_cska_glbl[1]}]
set_case_analysis 0 [get_ports {cfg_cska_glbl[2]}]
set_case_analysis 0 [get_ports {cfg_cska_glbl[3]}]
set_case_analysis 0 [get_ports {scan_en}]
set_case_analysis 0 [get_ports {scan_mode}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
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# Design Rules
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