| module user_project_wrapper (user_clock2, |
| wb_clk_i, |
| wb_rst_i, |
| wbs_ack_o, |
| wbs_cyc_i, |
| wbs_stb_i, |
| wbs_we_i, |
| vssa2, |
| vdda2, |
| vssa1, |
| vdda1, |
| vssd2, |
| vccd2, |
| vssd1, |
| vccd1, |
| analog_io, |
| io_in, |
| io_oeb, |
| io_out, |
| la_data_in, |
| la_data_out, |
| la_oenb, |
| user_irq, |
| wbs_adr_i, |
| wbs_dat_i, |
| wbs_dat_o, |
| wbs_sel_i); |
| input user_clock2; |
| input wb_clk_i; |
| input wb_rst_i; |
| output wbs_ack_o; |
| input wbs_cyc_i; |
| input wbs_stb_i; |
| input wbs_we_i; |
| input vssa2; |
| input vdda2; |
| input vssa1; |
| input vdda1; |
| input vssd2; |
| input vccd2; |
| input vssd1; |
| input vccd1; |
| inout [28:0] analog_io; |
| input [37:0] io_in; |
| output [37:0] io_oeb; |
| output [37:0] io_out; |
| input [127:0] la_data_in; |
| output [127:0] la_data_out; |
| input [127:0] la_oenb; |
| output [2:0] user_irq; |
| input [31:0] wbs_adr_i; |
| input [31:0] wbs_dat_i; |
| output [31:0] wbs_dat_o; |
| input [3:0] wbs_sel_i; |
| |
| wire bist_rst_n; |
| wire \buf_out_north[0] ; |
| wire \buf_out_north[10] ; |
| wire \buf_out_north[11] ; |
| wire \buf_out_north[12] ; |
| wire \buf_out_north[13] ; |
| wire \buf_out_north[14] ; |
| wire \buf_out_north[15] ; |
| wire \buf_out_north[16] ; |
| wire \buf_out_north[17] ; |
| wire \buf_out_north[18] ; |
| wire \buf_out_north[19] ; |
| wire \buf_out_north[1] ; |
| wire \buf_out_north[20] ; |
| wire \buf_out_north[21] ; |
| wire \buf_out_north[22] ; |
| wire \buf_out_north[23] ; |
| wire \buf_out_north[24] ; |
| wire \buf_out_north[25] ; |
| wire \buf_out_north[26] ; |
| wire \buf_out_north[27] ; |
| wire \buf_out_north[28] ; |
| wire \buf_out_north[29] ; |
| wire \buf_out_north[2] ; |
| wire \buf_out_north[30] ; |
| wire \buf_out_north[31] ; |
| wire \buf_out_north[32] ; |
| wire \buf_out_north[33] ; |
| wire \buf_out_north[34] ; |
| wire \buf_out_north[35] ; |
| wire \buf_out_north[36] ; |
| wire \buf_out_north[37] ; |
| wire \buf_out_north[38] ; |
| wire \buf_out_north[39] ; |
| wire \buf_out_north[3] ; |
| wire \buf_out_north[40] ; |
| wire \buf_out_north[41] ; |
| wire \buf_out_north[4] ; |
| wire \buf_out_north[5] ; |
| wire \buf_out_north[6] ; |
| wire \buf_out_north[7] ; |
| wire \buf_out_north[8] ; |
| wire \buf_out_north[9] ; |
| wire \cfg_clk_ctrl1[0] ; |
| wire \cfg_clk_ctrl1[10] ; |
| wire \cfg_clk_ctrl1[11] ; |
| wire \cfg_clk_ctrl1[12] ; |
| wire \cfg_clk_ctrl1[13] ; |
| wire \cfg_clk_ctrl1[14] ; |
| wire \cfg_clk_ctrl1[15] ; |
| wire \cfg_clk_ctrl1[16] ; |
| wire \cfg_clk_ctrl1[17] ; |
| wire \cfg_clk_ctrl1[18] ; |
| wire \cfg_clk_ctrl1[19] ; |
| wire \cfg_clk_ctrl1[1] ; |
| wire \cfg_clk_ctrl1[20] ; |
| wire \cfg_clk_ctrl1[21] ; |
| wire \cfg_clk_ctrl1[22] ; |
| wire \cfg_clk_ctrl1[23] ; |
| wire \cfg_clk_ctrl1[24] ; |
| wire \cfg_clk_ctrl1[25] ; |
| wire \cfg_clk_ctrl1[26] ; |
| wire \cfg_clk_ctrl1[27] ; |
| wire \cfg_clk_ctrl1[28] ; |
| wire \cfg_clk_ctrl1[29] ; |
| wire \cfg_clk_ctrl1[2] ; |
| wire \cfg_clk_ctrl1[30] ; |
| wire \cfg_clk_ctrl1[31] ; |
| wire \cfg_clk_ctrl1[3] ; |
| wire \cfg_clk_ctrl1[4] ; |
| wire \cfg_clk_ctrl1[5] ; |
| wire \cfg_clk_ctrl1[6] ; |
| wire \cfg_clk_ctrl1[7] ; |
| wire \cfg_clk_ctrl1[8] ; |
| wire \cfg_clk_ctrl1[9] ; |
| wire \cfg_clk_ctrl2[0] ; |
| wire \cfg_clk_ctrl2[10] ; |
| wire \cfg_clk_ctrl2[11] ; |
| wire \cfg_clk_ctrl2[12] ; |
| wire \cfg_clk_ctrl2[13] ; |
| wire \cfg_clk_ctrl2[14] ; |
| wire \cfg_clk_ctrl2[15] ; |
| wire \cfg_clk_ctrl2[16] ; |
| wire \cfg_clk_ctrl2[17] ; |
| wire \cfg_clk_ctrl2[18] ; |
| wire \cfg_clk_ctrl2[19] ; |
| wire \cfg_clk_ctrl2[1] ; |
| wire \cfg_clk_ctrl2[20] ; |
| wire \cfg_clk_ctrl2[21] ; |
| wire \cfg_clk_ctrl2[22] ; |
| wire \cfg_clk_ctrl2[23] ; |
| wire \cfg_clk_ctrl2[24] ; |
| wire \cfg_clk_ctrl2[25] ; |
| wire \cfg_clk_ctrl2[26] ; |
| wire \cfg_clk_ctrl2[27] ; |
| wire \cfg_clk_ctrl2[28] ; |
| wire \cfg_clk_ctrl2[29] ; |
| wire \cfg_clk_ctrl2[2] ; |
| wire \cfg_clk_ctrl2[30] ; |
| wire \cfg_clk_ctrl2[31] ; |
| wire \cfg_clk_ctrl2[3] ; |
| wire \cfg_clk_ctrl2[4] ; |
| wire \cfg_clk_ctrl2[5] ; |
| wire \cfg_clk_ctrl2[6] ; |
| wire \cfg_clk_ctrl2[7] ; |
| wire \cfg_clk_ctrl2[8] ; |
| wire \cfg_clk_ctrl2[9] ; |
| wire \ch_out_east[11] ; |
| wire \ch_out_east[14] ; |
| wire \ch_out_east[17] ; |
| wire \ch_out_east[20] ; |
| wire \ch_out_east[23] ; |
| wire \ch_out_east[26] ; |
| wire \ch_out_east[29] ; |
| wire \ch_out_east[2] ; |
| wire \ch_out_east[32] ; |
| wire \ch_out_east[35] ; |
| wire \ch_out_east[38] ; |
| wire \ch_out_east[41] ; |
| wire \ch_out_east[44] ; |
| wire \ch_out_east[5] ; |
| wire \ch_out_east[8] ; |
| wire \ch_out_north[11] ; |
| wire \ch_out_north[14] ; |
| wire \ch_out_north[17] ; |
| wire \ch_out_north[20] ; |
| wire \ch_out_north[23] ; |
| wire \ch_out_north[26] ; |
| wire \ch_out_north[2] ; |
| wire \ch_out_north[5] ; |
| wire \ch_out_north[8] ; |
| wire \ch_out_south[0] ; |
| wire \ch_out_south[100] ; |
| wire \ch_out_south[101] ; |
| wire \ch_out_south[103] ; |
| wire \ch_out_south[104] ; |
| wire \ch_out_south[106] ; |
| wire \ch_out_south[108] ; |
| wire \ch_out_south[10] ; |
| wire \ch_out_south[110] ; |
| wire \ch_out_south[112] ; |
| wire \ch_out_south[114] ; |
| wire \ch_out_south[116] ; |
| wire \ch_out_south[118] ; |
| wire \ch_out_south[11] ; |
| wire \ch_out_south[120] ; |
| wire \ch_out_south[122] ; |
| wire \ch_out_south[124] ; |
| wire \ch_out_south[126] ; |
| wire \ch_out_south[128] ; |
| wire \ch_out_south[130] ; |
| wire \ch_out_south[132] ; |
| wire \ch_out_south[134] ; |
| wire \ch_out_south[136] ; |
| wire \ch_out_south[138] ; |
| wire \ch_out_south[13] ; |
| wire \ch_out_south[140] ; |
| wire \ch_out_south[142] ; |
| wire \ch_out_south[144] ; |
| wire \ch_out_south[146] ; |
| wire \ch_out_south[148] ; |
| wire \ch_out_south[14] ; |
| wire \ch_out_south[150] ; |
| wire \ch_out_south[152] ; |
| wire \ch_out_south[154] ; |
| wire \ch_out_south[156] ; |
| wire \ch_out_south[158] ; |
| wire \ch_out_south[15] ; |
| wire \ch_out_south[160] ; |
| wire \ch_out_south[162] ; |
| wire \ch_out_south[164] ; |
| wire \ch_out_south[166] ; |
| wire \ch_out_south[168] ; |
| wire \ch_out_south[170] ; |
| wire \ch_out_south[172] ; |
| wire \ch_out_south[174] ; |
| wire \ch_out_south[176] ; |
| wire \ch_out_south[17] ; |
| wire \ch_out_south[18] ; |
| wire \ch_out_south[19] ; |
| wire \ch_out_south[1] ; |
| wire \ch_out_south[21] ; |
| wire \ch_out_south[22] ; |
| wire \ch_out_south[23] ; |
| wire \ch_out_south[25] ; |
| wire \ch_out_south[26] ; |
| wire \ch_out_south[270] ; |
| wire \ch_out_south[28] ; |
| wire \ch_out_south[29] ; |
| wire \ch_out_south[31] ; |
| wire \ch_out_south[32] ; |
| wire \ch_out_south[34] ; |
| wire \ch_out_south[35] ; |
| wire \ch_out_south[37] ; |
| wire \ch_out_south[38] ; |
| wire \ch_out_south[3] ; |
| wire \ch_out_south[40] ; |
| wire \ch_out_south[41] ; |
| wire \ch_out_south[43] ; |
| wire \ch_out_south[44] ; |
| wire \ch_out_south[46] ; |
| wire \ch_out_south[47] ; |
| wire \ch_out_south[49] ; |
| wire \ch_out_south[4] ; |
| wire \ch_out_south[50] ; |
| wire \ch_out_south[52] ; |
| wire \ch_out_south[53] ; |
| wire \ch_out_south[55] ; |
| wire \ch_out_south[56] ; |
| wire \ch_out_south[58] ; |
| wire \ch_out_south[59] ; |
| wire \ch_out_south[5] ; |
| wire \ch_out_south[61] ; |
| wire \ch_out_south[62] ; |
| wire \ch_out_south[64] ; |
| wire \ch_out_south[65] ; |
| wire \ch_out_south[67] ; |
| wire \ch_out_south[68] ; |
| wire \ch_out_south[6] ; |
| wire \ch_out_south[70] ; |
| wire \ch_out_south[71] ; |
| wire \ch_out_south[73] ; |
| wire \ch_out_south[74] ; |
| wire \ch_out_south[76] ; |
| wire \ch_out_south[77] ; |
| wire \ch_out_south[79] ; |
| wire \ch_out_south[7] ; |
| wire \ch_out_south[80] ; |
| wire \ch_out_south[82] ; |
| wire \ch_out_south[83] ; |
| wire \ch_out_south[85] ; |
| wire \ch_out_south[86] ; |
| wire \ch_out_south[88] ; |
| wire \ch_out_south[89] ; |
| wire \ch_out_south[91] ; |
| wire \ch_out_south[92] ; |
| wire \ch_out_south[94] ; |
| wire \ch_out_south[95] ; |
| wire \ch_out_south[97] ; |
| wire \ch_out_south[98] ; |
| wire \ch_out_south[9] ; |
| wire \ch_out_west[0] ; |
| wire \ch_out_west[12] ; |
| wire \ch_out_west[15] ; |
| wire \ch_out_west[18] ; |
| wire \ch_out_west[21] ; |
| wire \ch_out_west[24] ; |
| wire \ch_out_west[27] ; |
| wire \ch_out_west[30] ; |
| wire \ch_out_west[33] ; |
| wire \ch_out_west[36] ; |
| wire \ch_out_west[39] ; |
| wire \ch_out_west[3] ; |
| wire \ch_out_west[6] ; |
| wire \ch_out_west[9] ; |
| wire \io_oeb_int[0] ; |
| wire \io_oeb_int[10] ; |
| wire \io_oeb_int[11] ; |
| wire \io_oeb_int[12] ; |
| wire \io_oeb_int[13] ; |
| wire \io_oeb_int[14] ; |
| wire \io_oeb_int[15] ; |
| wire \io_oeb_int[16] ; |
| wire \io_oeb_int[17] ; |
| wire \io_oeb_int[18] ; |
| wire \io_oeb_int[19] ; |
| wire \io_oeb_int[1] ; |
| wire \io_oeb_int[20] ; |
| wire \io_oeb_int[21] ; |
| wire \io_oeb_int[22] ; |
| wire \io_oeb_int[23] ; |
| wire \io_oeb_int[24] ; |
| wire \io_oeb_int[25] ; |
| wire \io_oeb_int[26] ; |
| wire \io_oeb_int[27] ; |
| wire \io_oeb_int[28] ; |
| wire \io_oeb_int[29] ; |
| wire \io_oeb_int[2] ; |
| wire \io_oeb_int[30] ; |
| wire \io_oeb_int[31] ; |
| wire \io_oeb_int[32] ; |
| wire \io_oeb_int[33] ; |
| wire \io_oeb_int[34] ; |
| wire \io_oeb_int[35] ; |
| wire \io_oeb_int[36] ; |
| wire \io_oeb_int[37] ; |
| wire \io_oeb_int[3] ; |
| wire \io_oeb_int[4] ; |
| wire \io_oeb_int[5] ; |
| wire \io_oeb_int[6] ; |
| wire \io_oeb_int[7] ; |
| wire \io_oeb_int[8] ; |
| wire \io_oeb_int[9] ; |
| wire \io_out_int[0] ; |
| wire \io_out_int[10] ; |
| wire \io_out_int[11] ; |
| wire \io_out_int[12] ; |
| wire \io_out_int[13] ; |
| wire \io_out_int[14] ; |
| wire \io_out_int[15] ; |
| wire \io_out_int[16] ; |
| wire \io_out_int[17] ; |
| wire \io_out_int[18] ; |
| wire \io_out_int[19] ; |
| wire \io_out_int[1] ; |
| wire \io_out_int[20] ; |
| wire \io_out_int[21] ; |
| wire \io_out_int[22] ; |
| wire \io_out_int[23] ; |
| wire \io_out_int[24] ; |
| wire \io_out_int[25] ; |
| wire \io_out_int[26] ; |
| wire \io_out_int[27] ; |
| wire \io_out_int[28] ; |
| wire \io_out_int[29] ; |
| wire \io_out_int[2] ; |
| wire \io_out_int[30] ; |
| wire \io_out_int[31] ; |
| wire \io_out_int[32] ; |
| wire \io_out_int[33] ; |
| wire \io_out_int[34] ; |
| wire \io_out_int[35] ; |
| wire \io_out_int[36] ; |
| wire \io_out_int[37] ; |
| wire \io_out_int[3] ; |
| wire \io_out_int[4] ; |
| wire \io_out_int[5] ; |
| wire \io_out_int[6] ; |
| wire \io_out_int[7] ; |
| wire \io_out_int[8] ; |
| wire \io_out_int[9] ; |
| wire \la_data_out_int[0] ; |
| wire \la_data_out_int[100] ; |
| wire \la_data_out_int[101] ; |
| wire \la_data_out_int[102] ; |
| wire \la_data_out_int[103] ; |
| wire \la_data_out_int[104] ; |
| wire \la_data_out_int[105] ; |
| wire \la_data_out_int[106] ; |
| wire \la_data_out_int[107] ; |
| wire \la_data_out_int[108] ; |
| wire \la_data_out_int[109] ; |
| wire \la_data_out_int[10] ; |
| wire \la_data_out_int[110] ; |
| wire \la_data_out_int[111] ; |
| wire \la_data_out_int[112] ; |
| wire \la_data_out_int[113] ; |
| wire \la_data_out_int[114] ; |
| wire \la_data_out_int[115] ; |
| wire \la_data_out_int[116] ; |
| wire \la_data_out_int[117] ; |
| wire \la_data_out_int[118] ; |
| wire \la_data_out_int[119] ; |
| wire \la_data_out_int[11] ; |
| wire \la_data_out_int[120] ; |
| wire \la_data_out_int[121] ; |
| wire \la_data_out_int[122] ; |
| wire \la_data_out_int[123] ; |
| wire \la_data_out_int[124] ; |
| wire \la_data_out_int[125] ; |
| wire \la_data_out_int[126] ; |
| wire \la_data_out_int[127] ; |
| wire \la_data_out_int[12] ; |
| wire \la_data_out_int[13] ; |
| wire \la_data_out_int[14] ; |
| wire \la_data_out_int[15] ; |
| wire \la_data_out_int[16] ; |
| wire \la_data_out_int[17] ; |
| wire \la_data_out_int[18] ; |
| wire \la_data_out_int[19] ; |
| wire \la_data_out_int[1] ; |
| wire \la_data_out_int[20] ; |
| wire \la_data_out_int[21] ; |
| wire \la_data_out_int[22] ; |
| wire \la_data_out_int[23] ; |
| wire \la_data_out_int[24] ; |
| wire \la_data_out_int[25] ; |
| wire \la_data_out_int[26] ; |
| wire \la_data_out_int[27] ; |
| wire \la_data_out_int[28] ; |
| wire \la_data_out_int[29] ; |
| wire \la_data_out_int[2] ; |
| wire \la_data_out_int[30] ; |
| wire \la_data_out_int[31] ; |
| wire \la_data_out_int[32] ; |
| wire \la_data_out_int[33] ; |
| wire \la_data_out_int[34] ; |
| wire \la_data_out_int[35] ; |
| wire \la_data_out_int[36] ; |
| wire \la_data_out_int[37] ; |
| wire \la_data_out_int[38] ; |
| wire \la_data_out_int[39] ; |
| wire \la_data_out_int[3] ; |
| wire \la_data_out_int[40] ; |
| wire \la_data_out_int[41] ; |
| wire \la_data_out_int[42] ; |
| wire \la_data_out_int[43] ; |
| wire \la_data_out_int[44] ; |
| wire \la_data_out_int[45] ; |
| wire \la_data_out_int[46] ; |
| wire \la_data_out_int[47] ; |
| wire \la_data_out_int[48] ; |
| wire \la_data_out_int[49] ; |
| wire \la_data_out_int[4] ; |
| wire \la_data_out_int[50] ; |
| wire \la_data_out_int[51] ; |
| wire \la_data_out_int[52] ; |
| wire \la_data_out_int[53] ; |
| wire \la_data_out_int[54] ; |
| wire \la_data_out_int[55] ; |
| wire \la_data_out_int[56] ; |
| wire \la_data_out_int[57] ; |
| wire \la_data_out_int[58] ; |
| wire \la_data_out_int[59] ; |
| wire \la_data_out_int[5] ; |
| wire \la_data_out_int[60] ; |
| wire \la_data_out_int[61] ; |
| wire \la_data_out_int[62] ; |
| wire \la_data_out_int[63] ; |
| wire \la_data_out_int[64] ; |
| wire \la_data_out_int[65] ; |
| wire \la_data_out_int[66] ; |
| wire \la_data_out_int[67] ; |
| wire \la_data_out_int[68] ; |
| wire \la_data_out_int[69] ; |
| wire \la_data_out_int[6] ; |
| wire \la_data_out_int[70] ; |
| wire \la_data_out_int[71] ; |
| wire \la_data_out_int[72] ; |
| wire \la_data_out_int[73] ; |
| wire \la_data_out_int[74] ; |
| wire \la_data_out_int[75] ; |
| wire \la_data_out_int[76] ; |
| wire \la_data_out_int[77] ; |
| wire \la_data_out_int[78] ; |
| wire \la_data_out_int[79] ; |
| wire \la_data_out_int[7] ; |
| wire \la_data_out_int[80] ; |
| wire \la_data_out_int[81] ; |
| wire \la_data_out_int[82] ; |
| wire \la_data_out_int[83] ; |
| wire \la_data_out_int[84] ; |
| wire \la_data_out_int[85] ; |
| wire \la_data_out_int[86] ; |
| wire \la_data_out_int[87] ; |
| wire \la_data_out_int[88] ; |
| wire \la_data_out_int[89] ; |
| wire \la_data_out_int[8] ; |
| wire \la_data_out_int[90] ; |
| wire \la_data_out_int[91] ; |
| wire \la_data_out_int[92] ; |
| wire \la_data_out_int[93] ; |
| wire \la_data_out_int[94] ; |
| wire \la_data_out_int[95] ; |
| wire \la_data_out_int[96] ; |
| wire \la_data_out_int[97] ; |
| wire \la_data_out_int[98] ; |
| wire \la_data_out_int[99] ; |
| wire \la_data_out_int[9] ; |
| wire lbist_clk; |
| wire mac_crs; |
| wire mac_rst_n; |
| wire mac_rx_clk; |
| wire mac_rx_dv; |
| wire mac_rx_er; |
| wire \mac_rx_qbase_addr[0] ; |
| wire \mac_rx_qbase_addr[1] ; |
| wire \mac_rx_qbase_addr[2] ; |
| wire \mac_rx_qbase_addr[3] ; |
| wire \mac_rx_qbase_addr[4] ; |
| wire \mac_rx_qbase_addr[5] ; |
| wire \mac_rx_qbase_addr[6] ; |
| wire \mac_rx_qbase_addr[7] ; |
| wire \mac_rx_qbase_addr[8] ; |
| wire \mac_rx_qbase_addr[9] ; |
| wire mac_rx_qcnt_dec; |
| wire mac_rx_qcnt_inc; |
| wire \mac_rxd[0] ; |
| wire \mac_rxd[1] ; |
| wire \mac_rxd[2] ; |
| wire \mac_rxd[3] ; |
| wire \mac_rxd[4] ; |
| wire \mac_rxd[5] ; |
| wire \mac_rxd[6] ; |
| wire \mac_rxd[7] ; |
| wire mac_tx_clk; |
| wire mac_tx_en; |
| wire mac_tx_er; |
| wire \mac_tx_qbase_addr[0] ; |
| wire \mac_tx_qbase_addr[1] ; |
| wire \mac_tx_qbase_addr[2] ; |
| wire \mac_tx_qbase_addr[3] ; |
| wire \mac_tx_qbase_addr[4] ; |
| wire \mac_tx_qbase_addr[5] ; |
| wire \mac_tx_qbase_addr[6] ; |
| wire \mac_tx_qbase_addr[7] ; |
| wire \mac_tx_qbase_addr[8] ; |
| wire \mac_tx_qbase_addr[9] ; |
| wire mac_tx_qcnt_dec; |
| wire mac_tx_qcnt_inc; |
| wire \mac_txd[0] ; |
| wire \mac_txd[1] ; |
| wire \mac_txd[2] ; |
| wire \mac_txd[3] ; |
| wire \mac_txd[4] ; |
| wire \mac_txd[5] ; |
| wire \mac_txd[6] ; |
| wire \mac_txd[7] ; |
| wire mdio_clk; |
| wire mdio_in; |
| wire mdio_out; |
| wire mdio_out_en; |
| wire \mem0_addr_a[0] ; |
| wire \mem0_addr_a[1] ; |
| wire \mem0_addr_a[2] ; |
| wire \mem0_addr_a[3] ; |
| wire \mem0_addr_a[4] ; |
| wire \mem0_addr_a[5] ; |
| wire \mem0_addr_a[6] ; |
| wire \mem0_addr_a[7] ; |
| wire \mem0_addr_a[8] ; |
| wire \mem0_addr_b[0] ; |
| wire \mem0_addr_b[1] ; |
| wire \mem0_addr_b[2] ; |
| wire \mem0_addr_b[3] ; |
| wire \mem0_addr_b[4] ; |
| wire \mem0_addr_b[5] ; |
| wire \mem0_addr_b[6] ; |
| wire \mem0_addr_b[7] ; |
| wire \mem0_addr_b[8] ; |
| wire \mem0_din_a[0] ; |
| wire \mem0_din_a[10] ; |
| wire \mem0_din_a[11] ; |
| wire \mem0_din_a[12] ; |
| wire \mem0_din_a[13] ; |
| wire \mem0_din_a[14] ; |
| wire \mem0_din_a[15] ; |
| wire \mem0_din_a[16] ; |
| wire \mem0_din_a[17] ; |
| wire \mem0_din_a[18] ; |
| wire \mem0_din_a[19] ; |
| wire \mem0_din_a[1] ; |
| wire \mem0_din_a[20] ; |
| wire \mem0_din_a[21] ; |
| wire \mem0_din_a[22] ; |
| wire \mem0_din_a[23] ; |
| wire \mem0_din_a[24] ; |
| wire \mem0_din_a[25] ; |
| wire \mem0_din_a[26] ; |
| wire \mem0_din_a[27] ; |
| wire \mem0_din_a[28] ; |
| wire \mem0_din_a[29] ; |
| wire \mem0_din_a[2] ; |
| wire \mem0_din_a[30] ; |
| wire \mem0_din_a[31] ; |
| wire \mem0_din_a[3] ; |
| wire \mem0_din_a[4] ; |
| wire \mem0_din_a[5] ; |
| wire \mem0_din_a[6] ; |
| wire \mem0_din_a[7] ; |
| wire \mem0_din_a[8] ; |
| wire \mem0_din_a[9] ; |
| wire \mem0_dout_a[0] ; |
| wire \mem0_dout_a[10] ; |
| wire \mem0_dout_a[11] ; |
| wire \mem0_dout_a[12] ; |
| wire \mem0_dout_a[13] ; |
| wire \mem0_dout_a[14] ; |
| wire \mem0_dout_a[15] ; |
| wire \mem0_dout_a[16] ; |
| wire \mem0_dout_a[17] ; |
| wire \mem0_dout_a[18] ; |
| wire \mem0_dout_a[19] ; |
| wire \mem0_dout_a[1] ; |
| wire \mem0_dout_a[20] ; |
| wire \mem0_dout_a[21] ; |
| wire \mem0_dout_a[22] ; |
| wire \mem0_dout_a[23] ; |
| wire \mem0_dout_a[24] ; |
| wire \mem0_dout_a[25] ; |
| wire \mem0_dout_a[26] ; |
| wire \mem0_dout_a[27] ; |
| wire \mem0_dout_a[28] ; |
| wire \mem0_dout_a[29] ; |
| wire \mem0_dout_a[2] ; |
| wire \mem0_dout_a[30] ; |
| wire \mem0_dout_a[31] ; |
| wire \mem0_dout_a[3] ; |
| wire \mem0_dout_a[4] ; |
| wire \mem0_dout_a[5] ; |
| wire \mem0_dout_a[6] ; |
| wire \mem0_dout_a[7] ; |
| wire \mem0_dout_a[8] ; |
| wire \mem0_dout_a[9] ; |
| wire \mem0_mask_a[0] ; |
| wire \mem0_mask_a[1] ; |
| wire \mem0_mask_a[2] ; |
| wire \mem0_mask_a[3] ; |
| wire \mem1_addr_a[0] ; |
| wire \mem1_addr_a[1] ; |
| wire \mem1_addr_a[2] ; |
| wire \mem1_addr_a[3] ; |
| wire \mem1_addr_a[4] ; |
| wire \mem1_addr_a[5] ; |
| wire \mem1_addr_a[6] ; |
| wire \mem1_addr_a[7] ; |
| wire \mem1_addr_a[8] ; |
| wire \mem1_addr_b[0] ; |
| wire \mem1_addr_b[1] ; |
| wire \mem1_addr_b[2] ; |
| wire \mem1_addr_b[3] ; |
| wire \mem1_addr_b[4] ; |
| wire \mem1_addr_b[5] ; |
| wire \mem1_addr_b[6] ; |
| wire \mem1_addr_b[7] ; |
| wire \mem1_addr_b[8] ; |
| wire \mem1_din_a[0] ; |
| wire \mem1_din_a[10] ; |
| wire \mem1_din_a[11] ; |
| wire \mem1_din_a[12] ; |
| wire \mem1_din_a[13] ; |
| wire \mem1_din_a[14] ; |
| wire \mem1_din_a[15] ; |
| wire \mem1_din_a[16] ; |
| wire \mem1_din_a[17] ; |
| wire \mem1_din_a[18] ; |
| wire \mem1_din_a[19] ; |
| wire \mem1_din_a[1] ; |
| wire \mem1_din_a[20] ; |
| wire \mem1_din_a[21] ; |
| wire \mem1_din_a[22] ; |
| wire \mem1_din_a[23] ; |
| wire \mem1_din_a[24] ; |
| wire \mem1_din_a[25] ; |
| wire \mem1_din_a[26] ; |
| wire \mem1_din_a[27] ; |
| wire \mem1_din_a[28] ; |
| wire \mem1_din_a[29] ; |
| wire \mem1_din_a[2] ; |
| wire \mem1_din_a[30] ; |
| wire \mem1_din_a[31] ; |
| wire \mem1_din_a[3] ; |
| wire \mem1_din_a[4] ; |
| wire \mem1_din_a[5] ; |
| wire \mem1_din_a[6] ; |
| wire \mem1_din_a[7] ; |
| wire \mem1_din_a[8] ; |
| wire \mem1_din_a[9] ; |
| wire \mem1_dout_a[0] ; |
| wire \mem1_dout_a[10] ; |
| wire \mem1_dout_a[11] ; |
| wire \mem1_dout_a[12] ; |
| wire \mem1_dout_a[13] ; |
| wire \mem1_dout_a[14] ; |
| wire \mem1_dout_a[15] ; |
| wire \mem1_dout_a[16] ; |
| wire \mem1_dout_a[17] ; |
| wire \mem1_dout_a[18] ; |
| wire \mem1_dout_a[19] ; |
| wire \mem1_dout_a[1] ; |
| wire \mem1_dout_a[20] ; |
| wire \mem1_dout_a[21] ; |
| wire \mem1_dout_a[22] ; |
| wire \mem1_dout_a[23] ; |
| wire \mem1_dout_a[24] ; |
| wire \mem1_dout_a[25] ; |
| wire \mem1_dout_a[26] ; |
| wire \mem1_dout_a[27] ; |
| wire \mem1_dout_a[28] ; |
| wire \mem1_dout_a[29] ; |
| wire \mem1_dout_a[2] ; |
| wire \mem1_dout_a[30] ; |
| wire \mem1_dout_a[31] ; |
| wire \mem1_dout_a[3] ; |
| wire \mem1_dout_a[4] ; |
| wire \mem1_dout_a[5] ; |
| wire \mem1_dout_a[6] ; |
| wire \mem1_dout_a[7] ; |
| wire \mem1_dout_a[8] ; |
| wire \mem1_dout_a[9] ; |
| wire \mem1_mask_a[0] ; |
| wire \mem1_mask_a[1] ; |
| wire \mem1_mask_a[2] ; |
| wire \mem1_mask_a[3] ; |
| wire \mem2_addr_a[0] ; |
| wire \mem2_addr_a[1] ; |
| wire \mem2_addr_a[2] ; |
| wire \mem2_addr_a[3] ; |
| wire \mem2_addr_a[4] ; |
| wire \mem2_addr_a[5] ; |
| wire \mem2_addr_a[6] ; |
| wire \mem2_addr_a[7] ; |
| wire \mem2_addr_a[8] ; |
| wire \mem2_addr_b[0] ; |
| wire \mem2_addr_b[1] ; |
| wire \mem2_addr_b[2] ; |
| wire \mem2_addr_b[3] ; |
| wire \mem2_addr_b[4] ; |
| wire \mem2_addr_b[5] ; |
| wire \mem2_addr_b[6] ; |
| wire \mem2_addr_b[7] ; |
| wire \mem2_addr_b[8] ; |
| wire \mem2_din_a[0] ; |
| wire \mem2_din_a[10] ; |
| wire \mem2_din_a[11] ; |
| wire \mem2_din_a[12] ; |
| wire \mem2_din_a[13] ; |
| wire \mem2_din_a[14] ; |
| wire \mem2_din_a[15] ; |
| wire \mem2_din_a[16] ; |
| wire \mem2_din_a[17] ; |
| wire \mem2_din_a[18] ; |
| wire \mem2_din_a[19] ; |
| wire \mem2_din_a[1] ; |
| wire \mem2_din_a[20] ; |
| wire \mem2_din_a[21] ; |
| wire \mem2_din_a[22] ; |
| wire \mem2_din_a[23] ; |
| wire \mem2_din_a[24] ; |
| wire \mem2_din_a[25] ; |
| wire \mem2_din_a[26] ; |
| wire \mem2_din_a[27] ; |
| wire \mem2_din_a[28] ; |
| wire \mem2_din_a[29] ; |
| wire \mem2_din_a[2] ; |
| wire \mem2_din_a[30] ; |
| wire \mem2_din_a[31] ; |
| wire \mem2_din_a[3] ; |
| wire \mem2_din_a[4] ; |
| wire \mem2_din_a[5] ; |
| wire \mem2_din_a[6] ; |
| wire \mem2_din_a[7] ; |
| wire \mem2_din_a[8] ; |
| wire \mem2_din_a[9] ; |
| wire \mem2_dout_a[0] ; |
| wire \mem2_dout_a[10] ; |
| wire \mem2_dout_a[11] ; |
| wire \mem2_dout_a[12] ; |
| wire \mem2_dout_a[13] ; |
| wire \mem2_dout_a[14] ; |
| wire \mem2_dout_a[15] ; |
| wire \mem2_dout_a[16] ; |
| wire \mem2_dout_a[17] ; |
| wire \mem2_dout_a[18] ; |
| wire \mem2_dout_a[19] ; |
| wire \mem2_dout_a[1] ; |
| wire \mem2_dout_a[20] ; |
| wire \mem2_dout_a[21] ; |
| wire \mem2_dout_a[22] ; |
| wire \mem2_dout_a[23] ; |
| wire \mem2_dout_a[24] ; |
| wire \mem2_dout_a[25] ; |
| wire \mem2_dout_a[26] ; |
| wire \mem2_dout_a[27] ; |
| wire \mem2_dout_a[28] ; |
| wire \mem2_dout_a[29] ; |
| wire \mem2_dout_a[2] ; |
| wire \mem2_dout_a[30] ; |
| wire \mem2_dout_a[31] ; |
| wire \mem2_dout_a[3] ; |
| wire \mem2_dout_a[4] ; |
| wire \mem2_dout_a[5] ; |
| wire \mem2_dout_a[6] ; |
| wire \mem2_dout_a[7] ; |
| wire \mem2_dout_a[8] ; |
| wire \mem2_dout_a[9] ; |
| wire \mem2_mask_a[0] ; |
| wire \mem2_mask_a[1] ; |
| wire \mem2_mask_a[2] ; |
| wire \mem2_mask_a[3] ; |
| wire \mem3_addr_a[0] ; |
| wire \mem3_addr_a[1] ; |
| wire \mem3_addr_a[2] ; |
| wire \mem3_addr_a[3] ; |
| wire \mem3_addr_a[4] ; |
| wire \mem3_addr_a[5] ; |
| wire \mem3_addr_a[6] ; |
| wire \mem3_addr_a[7] ; |
| wire \mem3_addr_a[8] ; |
| wire \mem3_addr_b[0] ; |
| wire \mem3_addr_b[1] ; |
| wire \mem3_addr_b[2] ; |
| wire \mem3_addr_b[3] ; |
| wire \mem3_addr_b[4] ; |
| wire \mem3_addr_b[5] ; |
| wire \mem3_addr_b[6] ; |
| wire \mem3_addr_b[7] ; |
| wire \mem3_addr_b[8] ; |
| wire \mem3_din_a[0] ; |
| wire \mem3_din_a[10] ; |
| wire \mem3_din_a[11] ; |
| wire \mem3_din_a[12] ; |
| wire \mem3_din_a[13] ; |
| wire \mem3_din_a[14] ; |
| wire \mem3_din_a[15] ; |
| wire \mem3_din_a[16] ; |
| wire \mem3_din_a[17] ; |
| wire \mem3_din_a[18] ; |
| wire \mem3_din_a[19] ; |
| wire \mem3_din_a[1] ; |
| wire \mem3_din_a[20] ; |
| wire \mem3_din_a[21] ; |
| wire \mem3_din_a[22] ; |
| wire \mem3_din_a[23] ; |
| wire \mem3_din_a[24] ; |
| wire \mem3_din_a[25] ; |
| wire \mem3_din_a[26] ; |
| wire \mem3_din_a[27] ; |
| wire \mem3_din_a[28] ; |
| wire \mem3_din_a[29] ; |
| wire \mem3_din_a[2] ; |
| wire \mem3_din_a[30] ; |
| wire \mem3_din_a[31] ; |
| wire \mem3_din_a[3] ; |
| wire \mem3_din_a[4] ; |
| wire \mem3_din_a[5] ; |
| wire \mem3_din_a[6] ; |
| wire \mem3_din_a[7] ; |
| wire \mem3_din_a[8] ; |
| wire \mem3_din_a[9] ; |
| wire \mem3_dout_a[0] ; |
| wire \mem3_dout_a[10] ; |
| wire \mem3_dout_a[11] ; |
| wire \mem3_dout_a[12] ; |
| wire \mem3_dout_a[13] ; |
| wire \mem3_dout_a[14] ; |
| wire \mem3_dout_a[15] ; |
| wire \mem3_dout_a[16] ; |
| wire \mem3_dout_a[17] ; |
| wire \mem3_dout_a[18] ; |
| wire \mem3_dout_a[19] ; |
| wire \mem3_dout_a[1] ; |
| wire \mem3_dout_a[20] ; |
| wire \mem3_dout_a[21] ; |
| wire \mem3_dout_a[22] ; |
| wire \mem3_dout_a[23] ; |
| wire \mem3_dout_a[24] ; |
| wire \mem3_dout_a[25] ; |
| wire \mem3_dout_a[26] ; |
| wire \mem3_dout_a[27] ; |
| wire \mem3_dout_a[28] ; |
| wire \mem3_dout_a[29] ; |
| wire \mem3_dout_a[2] ; |
| wire \mem3_dout_a[30] ; |
| wire \mem3_dout_a[31] ; |
| wire \mem3_dout_a[3] ; |
| wire \mem3_dout_a[4] ; |
| wire \mem3_dout_a[5] ; |
| wire \mem3_dout_a[6] ; |
| wire \mem3_dout_a[7] ; |
| wire \mem3_dout_a[8] ; |
| wire \mem3_dout_a[9] ; |
| wire \mem3_mask_a[0] ; |
| wire \mem3_mask_a[1] ; |
| wire \mem3_mask_a[2] ; |
| wire \mem3_mask_a[3] ; |
| wire \mem4_addr_a[0] ; |
| wire \mem4_addr_a[1] ; |
| wire \mem4_addr_a[2] ; |
| wire \mem4_addr_a[3] ; |
| wire \mem4_addr_a[4] ; |
| wire \mem4_addr_a[5] ; |
| wire \mem4_addr_a[6] ; |
| wire \mem4_addr_a[7] ; |
| wire \mem4_addr_a[8] ; |
| wire \mem4_addr_b[0] ; |
| wire \mem4_addr_b[1] ; |
| wire \mem4_addr_b[2] ; |
| wire \mem4_addr_b[3] ; |
| wire \mem4_addr_b[4] ; |
| wire \mem4_addr_b[5] ; |
| wire \mem4_addr_b[6] ; |
| wire \mem4_addr_b[7] ; |
| wire \mem4_addr_b[8] ; |
| wire \mem4_din_a[0] ; |
| wire \mem4_din_a[10] ; |
| wire \mem4_din_a[11] ; |
| wire \mem4_din_a[12] ; |
| wire \mem4_din_a[13] ; |
| wire \mem4_din_a[14] ; |
| wire \mem4_din_a[15] ; |
| wire \mem4_din_a[16] ; |
| wire \mem4_din_a[17] ; |
| wire \mem4_din_a[18] ; |
| wire \mem4_din_a[19] ; |
| wire \mem4_din_a[1] ; |
| wire \mem4_din_a[20] ; |
| wire \mem4_din_a[21] ; |
| wire \mem4_din_a[22] ; |
| wire \mem4_din_a[23] ; |
| wire \mem4_din_a[24] ; |
| wire \mem4_din_a[25] ; |
| wire \mem4_din_a[26] ; |
| wire \mem4_din_a[27] ; |
| wire \mem4_din_a[28] ; |
| wire \mem4_din_a[29] ; |
| wire \mem4_din_a[2] ; |
| wire \mem4_din_a[30] ; |
| wire \mem4_din_a[31] ; |
| wire \mem4_din_a[3] ; |
| wire \mem4_din_a[4] ; |
| wire \mem4_din_a[5] ; |
| wire \mem4_din_a[6] ; |
| wire \mem4_din_a[7] ; |
| wire \mem4_din_a[8] ; |
| wire \mem4_din_a[9] ; |
| wire \mem4_dout_a[0] ; |
| wire \mem4_dout_a[10] ; |
| wire \mem4_dout_a[11] ; |
| wire \mem4_dout_a[12] ; |
| wire \mem4_dout_a[13] ; |
| wire \mem4_dout_a[14] ; |
| wire \mem4_dout_a[15] ; |
| wire \mem4_dout_a[16] ; |
| wire \mem4_dout_a[17] ; |
| wire \mem4_dout_a[18] ; |
| wire \mem4_dout_a[19] ; |
| wire \mem4_dout_a[1] ; |
| wire \mem4_dout_a[20] ; |
| wire \mem4_dout_a[21] ; |
| wire \mem4_dout_a[22] ; |
| wire \mem4_dout_a[23] ; |
| wire \mem4_dout_a[24] ; |
| wire \mem4_dout_a[25] ; |
| wire \mem4_dout_a[26] ; |
| wire \mem4_dout_a[27] ; |
| wire \mem4_dout_a[28] ; |
| wire \mem4_dout_a[29] ; |
| wire \mem4_dout_a[2] ; |
| wire \mem4_dout_a[30] ; |
| wire \mem4_dout_a[31] ; |
| wire \mem4_dout_a[3] ; |
| wire \mem4_dout_a[4] ; |
| wire \mem4_dout_a[5] ; |
| wire \mem4_dout_a[6] ; |
| wire \mem4_dout_a[7] ; |
| wire \mem4_dout_a[8] ; |
| wire \mem4_dout_a[9] ; |
| wire \mem4_mask_a[0] ; |
| wire \mem4_mask_a[1] ; |
| wire \mem4_mask_a[2] ; |
| wire \mem4_mask_a[3] ; |
| wire \mem5_addr_a[0] ; |
| wire \mem5_addr_a[1] ; |
| wire \mem5_addr_a[2] ; |
| wire \mem5_addr_a[3] ; |
| wire \mem5_addr_a[4] ; |
| wire \mem5_addr_a[5] ; |
| wire \mem5_addr_a[6] ; |
| wire \mem5_addr_a[7] ; |
| wire \mem5_addr_a[8] ; |
| wire \mem5_addr_b[0] ; |
| wire \mem5_addr_b[1] ; |
| wire \mem5_addr_b[2] ; |
| wire \mem5_addr_b[3] ; |
| wire \mem5_addr_b[4] ; |
| wire \mem5_addr_b[5] ; |
| wire \mem5_addr_b[6] ; |
| wire \mem5_addr_b[7] ; |
| wire \mem5_addr_b[8] ; |
| wire \mem5_din_a[0] ; |
| wire \mem5_din_a[10] ; |
| wire \mem5_din_a[11] ; |
| wire \mem5_din_a[12] ; |
| wire \mem5_din_a[13] ; |
| wire \mem5_din_a[14] ; |
| wire \mem5_din_a[15] ; |
| wire \mem5_din_a[16] ; |
| wire \mem5_din_a[17] ; |
| wire \mem5_din_a[18] ; |
| wire \mem5_din_a[19] ; |
| wire \mem5_din_a[1] ; |
| wire \mem5_din_a[20] ; |
| wire \mem5_din_a[21] ; |
| wire \mem5_din_a[22] ; |
| wire \mem5_din_a[23] ; |
| wire \mem5_din_a[24] ; |
| wire \mem5_din_a[25] ; |
| wire \mem5_din_a[26] ; |
| wire \mem5_din_a[27] ; |
| wire \mem5_din_a[28] ; |
| wire \mem5_din_a[29] ; |
| wire \mem5_din_a[2] ; |
| wire \mem5_din_a[30] ; |
| wire \mem5_din_a[31] ; |
| wire \mem5_din_a[3] ; |
| wire \mem5_din_a[4] ; |
| wire \mem5_din_a[5] ; |
| wire \mem5_din_a[6] ; |
| wire \mem5_din_a[7] ; |
| wire \mem5_din_a[8] ; |
| wire \mem5_din_a[9] ; |
| wire \mem5_dout_a[0] ; |
| wire \mem5_dout_a[10] ; |
| wire \mem5_dout_a[11] ; |
| wire \mem5_dout_a[12] ; |
| wire \mem5_dout_a[13] ; |
| wire \mem5_dout_a[14] ; |
| wire \mem5_dout_a[15] ; |
| wire \mem5_dout_a[16] ; |
| wire \mem5_dout_a[17] ; |
| wire \mem5_dout_a[18] ; |
| wire \mem5_dout_a[19] ; |
| wire \mem5_dout_a[1] ; |
| wire \mem5_dout_a[20] ; |
| wire \mem5_dout_a[21] ; |
| wire \mem5_dout_a[22] ; |
| wire \mem5_dout_a[23] ; |
| wire \mem5_dout_a[24] ; |
| wire \mem5_dout_a[25] ; |
| wire \mem5_dout_a[26] ; |
| wire \mem5_dout_a[27] ; |
| wire \mem5_dout_a[28] ; |
| wire \mem5_dout_a[29] ; |
| wire \mem5_dout_a[2] ; |
| wire \mem5_dout_a[30] ; |
| wire \mem5_dout_a[31] ; |
| wire \mem5_dout_a[3] ; |
| wire \mem5_dout_a[4] ; |
| wire \mem5_dout_a[5] ; |
| wire \mem5_dout_a[6] ; |
| wire \mem5_dout_a[7] ; |
| wire \mem5_dout_a[8] ; |
| wire \mem5_dout_a[9] ; |
| wire \mem5_mask_a[0] ; |
| wire \mem5_mask_a[1] ; |
| wire \mem5_mask_a[2] ; |
| wire \mem5_mask_a[3] ; |
| wire \mem6_addr_a[0] ; |
| wire \mem6_addr_a[1] ; |
| wire \mem6_addr_a[2] ; |
| wire \mem6_addr_a[3] ; |
| wire \mem6_addr_a[4] ; |
| wire \mem6_addr_a[5] ; |
| wire \mem6_addr_a[6] ; |
| wire \mem6_addr_a[7] ; |
| wire \mem6_addr_a[8] ; |
| wire \mem6_addr_b[0] ; |
| wire \mem6_addr_b[1] ; |
| wire \mem6_addr_b[2] ; |
| wire \mem6_addr_b[3] ; |
| wire \mem6_addr_b[4] ; |
| wire \mem6_addr_b[5] ; |
| wire \mem6_addr_b[6] ; |
| wire \mem6_addr_b[7] ; |
| wire \mem6_addr_b[8] ; |
| wire \mem6_din_a[0] ; |
| wire \mem6_din_a[10] ; |
| wire \mem6_din_a[11] ; |
| wire \mem6_din_a[12] ; |
| wire \mem6_din_a[13] ; |
| wire \mem6_din_a[14] ; |
| wire \mem6_din_a[15] ; |
| wire \mem6_din_a[16] ; |
| wire \mem6_din_a[17] ; |
| wire \mem6_din_a[18] ; |
| wire \mem6_din_a[19] ; |
| wire \mem6_din_a[1] ; |
| wire \mem6_din_a[20] ; |
| wire \mem6_din_a[21] ; |
| wire \mem6_din_a[22] ; |
| wire \mem6_din_a[23] ; |
| wire \mem6_din_a[24] ; |
| wire \mem6_din_a[25] ; |
| wire \mem6_din_a[26] ; |
| wire \mem6_din_a[27] ; |
| wire \mem6_din_a[28] ; |
| wire \mem6_din_a[29] ; |
| wire \mem6_din_a[2] ; |
| wire \mem6_din_a[30] ; |
| wire \mem6_din_a[31] ; |
| wire \mem6_din_a[3] ; |
| wire \mem6_din_a[4] ; |
| wire \mem6_din_a[5] ; |
| wire \mem6_din_a[6] ; |
| wire \mem6_din_a[7] ; |
| wire \mem6_din_a[8] ; |
| wire \mem6_din_a[9] ; |
| wire \mem6_dout_a[0] ; |
| wire \mem6_dout_a[10] ; |
| wire \mem6_dout_a[11] ; |
| wire \mem6_dout_a[12] ; |
| wire \mem6_dout_a[13] ; |
| wire \mem6_dout_a[14] ; |
| wire \mem6_dout_a[15] ; |
| wire \mem6_dout_a[16] ; |
| wire \mem6_dout_a[17] ; |
| wire \mem6_dout_a[18] ; |
| wire \mem6_dout_a[19] ; |
| wire \mem6_dout_a[1] ; |
| wire \mem6_dout_a[20] ; |
| wire \mem6_dout_a[21] ; |
| wire \mem6_dout_a[22] ; |
| wire \mem6_dout_a[23] ; |
| wire \mem6_dout_a[24] ; |
| wire \mem6_dout_a[25] ; |
| wire \mem6_dout_a[26] ; |
| wire \mem6_dout_a[27] ; |
| wire \mem6_dout_a[28] ; |
| wire \mem6_dout_a[29] ; |
| wire \mem6_dout_a[2] ; |
| wire \mem6_dout_a[30] ; |
| wire \mem6_dout_a[31] ; |
| wire \mem6_dout_a[3] ; |
| wire \mem6_dout_a[4] ; |
| wire \mem6_dout_a[5] ; |
| wire \mem6_dout_a[6] ; |
| wire \mem6_dout_a[7] ; |
| wire \mem6_dout_a[8] ; |
| wire \mem6_dout_a[9] ; |
| wire \mem6_mask_a[0] ; |
| wire \mem6_mask_a[1] ; |
| wire \mem6_mask_a[2] ; |
| wire \mem6_mask_a[3] ; |
| wire \mem7_addr_a[0] ; |
| wire \mem7_addr_a[1] ; |
| wire \mem7_addr_a[2] ; |
| wire \mem7_addr_a[3] ; |
| wire \mem7_addr_a[4] ; |
| wire \mem7_addr_a[5] ; |
| wire \mem7_addr_a[6] ; |
| wire \mem7_addr_a[7] ; |
| wire \mem7_addr_a[8] ; |
| wire \mem7_addr_b[0] ; |
| wire \mem7_addr_b[1] ; |
| wire \mem7_addr_b[2] ; |
| wire \mem7_addr_b[3] ; |
| wire \mem7_addr_b[4] ; |
| wire \mem7_addr_b[5] ; |
| wire \mem7_addr_b[6] ; |
| wire \mem7_addr_b[7] ; |
| wire \mem7_addr_b[8] ; |
| wire \mem7_din_a[0] ; |
| wire \mem7_din_a[10] ; |
| wire \mem7_din_a[11] ; |
| wire \mem7_din_a[12] ; |
| wire \mem7_din_a[13] ; |
| wire \mem7_din_a[14] ; |
| wire \mem7_din_a[15] ; |
| wire \mem7_din_a[16] ; |
| wire \mem7_din_a[17] ; |
| wire \mem7_din_a[18] ; |
| wire \mem7_din_a[19] ; |
| wire \mem7_din_a[1] ; |
| wire \mem7_din_a[20] ; |
| wire \mem7_din_a[21] ; |
| wire \mem7_din_a[22] ; |
| wire \mem7_din_a[23] ; |
| wire \mem7_din_a[24] ; |
| wire \mem7_din_a[25] ; |
| wire \mem7_din_a[26] ; |
| wire \mem7_din_a[27] ; |
| wire \mem7_din_a[28] ; |
| wire \mem7_din_a[29] ; |
| wire \mem7_din_a[2] ; |
| wire \mem7_din_a[30] ; |
| wire \mem7_din_a[31] ; |
| wire \mem7_din_a[3] ; |
| wire \mem7_din_a[4] ; |
| wire \mem7_din_a[5] ; |
| wire \mem7_din_a[6] ; |
| wire \mem7_din_a[7] ; |
| wire \mem7_din_a[8] ; |
| wire \mem7_din_a[9] ; |
| wire \mem7_dout_a[0] ; |
| wire \mem7_dout_a[10] ; |
| wire \mem7_dout_a[11] ; |
| wire \mem7_dout_a[12] ; |
| wire \mem7_dout_a[13] ; |
| wire \mem7_dout_a[14] ; |
| wire \mem7_dout_a[15] ; |
| wire \mem7_dout_a[16] ; |
| wire \mem7_dout_a[17] ; |
| wire \mem7_dout_a[18] ; |
| wire \mem7_dout_a[19] ; |
| wire \mem7_dout_a[1] ; |
| wire \mem7_dout_a[20] ; |
| wire \mem7_dout_a[21] ; |
| wire \mem7_dout_a[22] ; |
| wire \mem7_dout_a[23] ; |
| wire \mem7_dout_a[24] ; |
| wire \mem7_dout_a[25] ; |
| wire \mem7_dout_a[26] ; |
| wire \mem7_dout_a[27] ; |
| wire \mem7_dout_a[28] ; |
| wire \mem7_dout_a[29] ; |
| wire \mem7_dout_a[2] ; |
| wire \mem7_dout_a[30] ; |
| wire \mem7_dout_a[31] ; |
| wire \mem7_dout_a[3] ; |
| wire \mem7_dout_a[4] ; |
| wire \mem7_dout_a[5] ; |
| wire \mem7_dout_a[6] ; |
| wire \mem7_dout_a[7] ; |
| wire \mem7_dout_a[8] ; |
| wire \mem7_dout_a[9] ; |
| wire \mem7_mask_a[0] ; |
| wire \mem7_mask_a[1] ; |
| wire \mem7_mask_a[2] ; |
| wire \mem7_mask_a[3] ; |
| wire \mem_cen_a[0] ; |
| wire \mem_cen_a[1] ; |
| wire \mem_cen_a[2] ; |
| wire \mem_cen_a[3] ; |
| wire \mem_cen_a[4] ; |
| wire \mem_cen_a[5] ; |
| wire \mem_cen_a[6] ; |
| wire \mem_cen_a[7] ; |
| wire \mem_cen_b[0] ; |
| wire \mem_cen_b[1] ; |
| wire \mem_cen_b[2] ; |
| wire \mem_cen_b[3] ; |
| wire \mem_cen_b[4] ; |
| wire \mem_cen_b[5] ; |
| wire \mem_cen_b[6] ; |
| wire \mem_cen_b[7] ; |
| wire \mem_clk_a[0] ; |
| wire \mem_clk_a[1] ; |
| wire \mem_clk_a[2] ; |
| wire \mem_clk_a[3] ; |
| wire \mem_clk_a[4] ; |
| wire \mem_clk_a[5] ; |
| wire \mem_clk_a[6] ; |
| wire \mem_clk_a[7] ; |
| wire \mem_clk_b[0] ; |
| wire \mem_clk_b[1] ; |
| wire \mem_clk_b[2] ; |
| wire \mem_clk_b[3] ; |
| wire \mem_clk_b[4] ; |
| wire \mem_clk_b[5] ; |
| wire \mem_clk_b[6] ; |
| wire \mem_clk_b[7] ; |
| wire \mem_web_a[0] ; |
| wire \mem_web_a[1] ; |
| wire \mem_web_a[2] ; |
| wire \mem_web_a[3] ; |
| wire \mem_web_a[4] ; |
| wire \mem_web_a[5] ; |
| wire \mem_web_a[6] ; |
| wire \mem_web_a[7] ; |
| wire scan_clk; |
| wire scan_en; |
| wire scan_en_mac; |
| wire scan_en_mbist0; |
| wire scan_en_mbist1; |
| wire scan_en_pinmux; |
| wire scan_en_wi; |
| wire \scan_in[0] ; |
| wire \scan_in[1] ; |
| wire \scan_in[2] ; |
| wire \scan_in[3] ; |
| wire \scan_in[4] ; |
| wire \scan_in[5] ; |
| wire \scan_in[6] ; |
| wire \scan_in[7] ; |
| wire scan_mode; |
| wire scan_mode_mac; |
| wire scan_mode_mbist0; |
| wire scan_mode_mbist1; |
| wire scan_mode_pinmux; |
| wire scan_mode_wi; |
| wire scan_rst_n; |
| wire \scan_so_mac[0] ; |
| wire \scan_so_mac[1] ; |
| wire \scan_so_mac[2] ; |
| wire \scan_so_mac[3] ; |
| wire \scan_so_mac[4] ; |
| wire \scan_so_mac[5] ; |
| wire \scan_so_mac[6] ; |
| wire \scan_so_mac[7] ; |
| wire \scan_so_mbist0[0] ; |
| wire \scan_so_mbist0[1] ; |
| wire \scan_so_mbist0[2] ; |
| wire \scan_so_mbist0[3] ; |
| wire \scan_so_mbist0[4] ; |
| wire \scan_so_mbist0[5] ; |
| wire \scan_so_mbist0[6] ; |
| wire \scan_so_mbist0[7] ; |
| wire \scan_so_mbist1[0] ; |
| wire \scan_so_mbist1[1] ; |
| wire \scan_so_mbist1[2] ; |
| wire \scan_so_mbist1[3] ; |
| wire \scan_so_mbist1[4] ; |
| wire \scan_so_mbist1[5] ; |
| wire \scan_so_mbist1[6] ; |
| wire \scan_so_mbist1[7] ; |
| wire \scan_so_pinmux[0] ; |
| wire \scan_so_pinmux[1] ; |
| wire \scan_so_pinmux[2] ; |
| wire \scan_so_pinmux[3] ; |
| wire \scan_so_pinmux[4] ; |
| wire \scan_so_pinmux[5] ; |
| wire \scan_so_pinmux[6] ; |
| wire \scan_so_pinmux[7] ; |
| wire \scan_so_wi[0] ; |
| wire \scan_so_wi[1] ; |
| wire \scan_so_wi[2] ; |
| wire \scan_so_wi[3] ; |
| wire \scan_so_wi[4] ; |
| wire \scan_so_wi[5] ; |
| wire \scan_so_wi[6] ; |
| wire \scan_so_wi[7] ; |
| wire sspis_sck; |
| wire sspis_si; |
| wire sspis_so; |
| wire sspis_ssn; |
| wire uartm_rxd; |
| wire uartm_txd; |
| wire wbd_clk_int; |
| wire wbd_clk_mac_rp; |
| wire wbd_clk_mac_skew; |
| wire wbd_clk_mbist0_rp; |
| wire wbd_clk_mbist0_skew; |
| wire wbd_clk_mbist1_rp; |
| wire wbd_clk_mbist1_skew; |
| wire wbd_clk_pinmux_rp; |
| wire wbd_clk_pinmux_skew; |
| wire wbd_clk_wh; |
| wire wbd_clk_wi_skew; |
| wire wbd_int_ack_o; |
| wire \wbd_int_adr_i[0] ; |
| wire \wbd_int_adr_i[10] ; |
| wire \wbd_int_adr_i[11] ; |
| wire \wbd_int_adr_i[12] ; |
| wire \wbd_int_adr_i[13] ; |
| wire \wbd_int_adr_i[14] ; |
| wire \wbd_int_adr_i[15] ; |
| wire \wbd_int_adr_i[16] ; |
| wire \wbd_int_adr_i[17] ; |
| wire \wbd_int_adr_i[18] ; |
| wire \wbd_int_adr_i[19] ; |
| wire \wbd_int_adr_i[1] ; |
| wire \wbd_int_adr_i[20] ; |
| wire \wbd_int_adr_i[21] ; |
| wire \wbd_int_adr_i[22] ; |
| wire \wbd_int_adr_i[23] ; |
| wire \wbd_int_adr_i[24] ; |
| wire \wbd_int_adr_i[25] ; |
| wire \wbd_int_adr_i[26] ; |
| wire \wbd_int_adr_i[27] ; |
| wire \wbd_int_adr_i[28] ; |
| wire \wbd_int_adr_i[29] ; |
| wire \wbd_int_adr_i[2] ; |
| wire \wbd_int_adr_i[30] ; |
| wire \wbd_int_adr_i[31] ; |
| wire \wbd_int_adr_i[3] ; |
| wire \wbd_int_adr_i[4] ; |
| wire \wbd_int_adr_i[5] ; |
| wire \wbd_int_adr_i[6] ; |
| wire \wbd_int_adr_i[7] ; |
| wire \wbd_int_adr_i[8] ; |
| wire \wbd_int_adr_i[9] ; |
| wire wbd_int_cyc_i; |
| wire \wbd_int_dat_i[0] ; |
| wire \wbd_int_dat_i[10] ; |
| wire \wbd_int_dat_i[11] ; |
| wire \wbd_int_dat_i[12] ; |
| wire \wbd_int_dat_i[13] ; |
| wire \wbd_int_dat_i[14] ; |
| wire \wbd_int_dat_i[15] ; |
| wire \wbd_int_dat_i[16] ; |
| wire \wbd_int_dat_i[17] ; |
| wire \wbd_int_dat_i[18] ; |
| wire \wbd_int_dat_i[19] ; |
| wire \wbd_int_dat_i[1] ; |
| wire \wbd_int_dat_i[20] ; |
| wire \wbd_int_dat_i[21] ; |
| wire \wbd_int_dat_i[22] ; |
| wire \wbd_int_dat_i[23] ; |
| wire \wbd_int_dat_i[24] ; |
| wire \wbd_int_dat_i[25] ; |
| wire \wbd_int_dat_i[26] ; |
| wire \wbd_int_dat_i[27] ; |
| wire \wbd_int_dat_i[28] ; |
| wire \wbd_int_dat_i[29] ; |
| wire \wbd_int_dat_i[2] ; |
| wire \wbd_int_dat_i[30] ; |
| wire \wbd_int_dat_i[31] ; |
| wire \wbd_int_dat_i[3] ; |
| wire \wbd_int_dat_i[4] ; |
| wire \wbd_int_dat_i[5] ; |
| wire \wbd_int_dat_i[6] ; |
| wire \wbd_int_dat_i[7] ; |
| wire \wbd_int_dat_i[8] ; |
| wire \wbd_int_dat_i[9] ; |
| wire \wbd_int_dat_o[0] ; |
| wire \wbd_int_dat_o[10] ; |
| wire \wbd_int_dat_o[11] ; |
| wire \wbd_int_dat_o[12] ; |
| wire \wbd_int_dat_o[13] ; |
| wire \wbd_int_dat_o[14] ; |
| wire \wbd_int_dat_o[15] ; |
| wire \wbd_int_dat_o[16] ; |
| wire \wbd_int_dat_o[17] ; |
| wire \wbd_int_dat_o[18] ; |
| wire \wbd_int_dat_o[19] ; |
| wire \wbd_int_dat_o[1] ; |
| wire \wbd_int_dat_o[20] ; |
| wire \wbd_int_dat_o[21] ; |
| wire \wbd_int_dat_o[22] ; |
| wire \wbd_int_dat_o[23] ; |
| wire \wbd_int_dat_o[24] ; |
| wire \wbd_int_dat_o[25] ; |
| wire \wbd_int_dat_o[26] ; |
| wire \wbd_int_dat_o[27] ; |
| wire \wbd_int_dat_o[28] ; |
| wire \wbd_int_dat_o[29] ; |
| wire \wbd_int_dat_o[2] ; |
| wire \wbd_int_dat_o[30] ; |
| wire \wbd_int_dat_o[31] ; |
| wire \wbd_int_dat_o[3] ; |
| wire \wbd_int_dat_o[4] ; |
| wire \wbd_int_dat_o[5] ; |
| wire \wbd_int_dat_o[6] ; |
| wire \wbd_int_dat_o[7] ; |
| wire \wbd_int_dat_o[8] ; |
| wire \wbd_int_dat_o[9] ; |
| wire wbd_int_err_o; |
| wire wbd_int_rst_n; |
| wire \wbd_int_sel_i[0] ; |
| wire \wbd_int_sel_i[1] ; |
| wire \wbd_int_sel_i[2] ; |
| wire \wbd_int_sel_i[3] ; |
| wire wbd_int_stb_i; |
| wire wbd_int_we_i; |
| wire wbd_mbist0_ack_i; |
| wire \wbd_mbist0_adr_o[0] ; |
| wire \wbd_mbist0_adr_o[10] ; |
| wire \wbd_mbist0_adr_o[11] ; |
| wire \wbd_mbist0_adr_o[12] ; |
| wire \wbd_mbist0_adr_o[13] ; |
| wire \wbd_mbist0_adr_o[14] ; |
| wire \wbd_mbist0_adr_o[1] ; |
| wire \wbd_mbist0_adr_o[2] ; |
| wire \wbd_mbist0_adr_o[3] ; |
| wire \wbd_mbist0_adr_o[4] ; |
| wire \wbd_mbist0_adr_o[5] ; |
| wire \wbd_mbist0_adr_o[6] ; |
| wire \wbd_mbist0_adr_o[7] ; |
| wire \wbd_mbist0_adr_o[8] ; |
| wire \wbd_mbist0_adr_o[9] ; |
| wire \wbd_mbist0_bl_o[0] ; |
| wire \wbd_mbist0_bl_o[1] ; |
| wire \wbd_mbist0_bl_o[2] ; |
| wire \wbd_mbist0_bl_o[3] ; |
| wire \wbd_mbist0_bl_o[4] ; |
| wire \wbd_mbist0_bl_o[5] ; |
| wire \wbd_mbist0_bl_o[6] ; |
| wire \wbd_mbist0_bl_o[7] ; |
| wire \wbd_mbist0_bl_o[8] ; |
| wire \wbd_mbist0_bl_o[9] ; |
| wire wbd_mbist0_bry_o; |
| wire wbd_mbist0_cyc_o; |
| wire \wbd_mbist0_dat_i[0] ; |
| wire \wbd_mbist0_dat_i[10] ; |
| wire \wbd_mbist0_dat_i[11] ; |
| wire \wbd_mbist0_dat_i[12] ; |
| wire \wbd_mbist0_dat_i[13] ; |
| wire \wbd_mbist0_dat_i[14] ; |
| wire \wbd_mbist0_dat_i[15] ; |
| wire \wbd_mbist0_dat_i[16] ; |
| wire \wbd_mbist0_dat_i[17] ; |
| wire \wbd_mbist0_dat_i[18] ; |
| wire \wbd_mbist0_dat_i[19] ; |
| wire \wbd_mbist0_dat_i[1] ; |
| wire \wbd_mbist0_dat_i[20] ; |
| wire \wbd_mbist0_dat_i[21] ; |
| wire \wbd_mbist0_dat_i[22] ; |
| wire \wbd_mbist0_dat_i[23] ; |
| wire \wbd_mbist0_dat_i[24] ; |
| wire \wbd_mbist0_dat_i[25] ; |
| wire \wbd_mbist0_dat_i[26] ; |
| wire \wbd_mbist0_dat_i[27] ; |
| wire \wbd_mbist0_dat_i[28] ; |
| wire \wbd_mbist0_dat_i[29] ; |
| wire \wbd_mbist0_dat_i[2] ; |
| wire \wbd_mbist0_dat_i[30] ; |
| wire \wbd_mbist0_dat_i[31] ; |
| wire \wbd_mbist0_dat_i[3] ; |
| wire \wbd_mbist0_dat_i[4] ; |
| wire \wbd_mbist0_dat_i[5] ; |
| wire \wbd_mbist0_dat_i[6] ; |
| wire \wbd_mbist0_dat_i[7] ; |
| wire \wbd_mbist0_dat_i[8] ; |
| wire \wbd_mbist0_dat_i[9] ; |
| wire \wbd_mbist0_dat_o[0] ; |
| wire \wbd_mbist0_dat_o[10] ; |
| wire \wbd_mbist0_dat_o[11] ; |
| wire \wbd_mbist0_dat_o[12] ; |
| wire \wbd_mbist0_dat_o[13] ; |
| wire \wbd_mbist0_dat_o[14] ; |
| wire \wbd_mbist0_dat_o[15] ; |
| wire \wbd_mbist0_dat_o[16] ; |
| wire \wbd_mbist0_dat_o[17] ; |
| wire \wbd_mbist0_dat_o[18] ; |
| wire \wbd_mbist0_dat_o[19] ; |
| wire \wbd_mbist0_dat_o[1] ; |
| wire \wbd_mbist0_dat_o[20] ; |
| wire \wbd_mbist0_dat_o[21] ; |
| wire \wbd_mbist0_dat_o[22] ; |
| wire \wbd_mbist0_dat_o[23] ; |
| wire \wbd_mbist0_dat_o[24] ; |
| wire \wbd_mbist0_dat_o[25] ; |
| wire \wbd_mbist0_dat_o[26] ; |
| wire \wbd_mbist0_dat_o[27] ; |
| wire \wbd_mbist0_dat_o[28] ; |
| wire \wbd_mbist0_dat_o[29] ; |
| wire \wbd_mbist0_dat_o[2] ; |
| wire \wbd_mbist0_dat_o[30] ; |
| wire \wbd_mbist0_dat_o[31] ; |
| wire \wbd_mbist0_dat_o[3] ; |
| wire \wbd_mbist0_dat_o[4] ; |
| wire \wbd_mbist0_dat_o[5] ; |
| wire \wbd_mbist0_dat_o[6] ; |
| wire \wbd_mbist0_dat_o[7] ; |
| wire \wbd_mbist0_dat_o[8] ; |
| wire \wbd_mbist0_dat_o[9] ; |
| wire \wbd_mbist0_sel_o[0] ; |
| wire \wbd_mbist0_sel_o[1] ; |
| wire \wbd_mbist0_sel_o[2] ; |
| wire \wbd_mbist0_sel_o[3] ; |
| wire wbd_mbist0_stb_o; |
| wire wbd_mbist0_we_o; |
| wire wbd_mbist1_ack_i; |
| wire \wbd_mbist1_adr_o[0] ; |
| wire \wbd_mbist1_adr_o[10] ; |
| wire \wbd_mbist1_adr_o[11] ; |
| wire \wbd_mbist1_adr_o[12] ; |
| wire \wbd_mbist1_adr_o[13] ; |
| wire \wbd_mbist1_adr_o[14] ; |
| wire \wbd_mbist1_adr_o[1] ; |
| wire \wbd_mbist1_adr_o[2] ; |
| wire \wbd_mbist1_adr_o[3] ; |
| wire \wbd_mbist1_adr_o[4] ; |
| wire \wbd_mbist1_adr_o[5] ; |
| wire \wbd_mbist1_adr_o[6] ; |
| wire \wbd_mbist1_adr_o[7] ; |
| wire \wbd_mbist1_adr_o[8] ; |
| wire \wbd_mbist1_adr_o[9] ; |
| wire \wbd_mbist1_bl_o[0] ; |
| wire \wbd_mbist1_bl_o[1] ; |
| wire \wbd_mbist1_bl_o[2] ; |
| wire \wbd_mbist1_bl_o[3] ; |
| wire \wbd_mbist1_bl_o[4] ; |
| wire \wbd_mbist1_bl_o[5] ; |
| wire \wbd_mbist1_bl_o[6] ; |
| wire \wbd_mbist1_bl_o[7] ; |
| wire \wbd_mbist1_bl_o[8] ; |
| wire \wbd_mbist1_bl_o[9] ; |
| wire wbd_mbist1_bry_o; |
| wire wbd_mbist1_cyc_o; |
| wire \wbd_mbist1_dat_i[0] ; |
| wire \wbd_mbist1_dat_i[10] ; |
| wire \wbd_mbist1_dat_i[11] ; |
| wire \wbd_mbist1_dat_i[12] ; |
| wire \wbd_mbist1_dat_i[13] ; |
| wire \wbd_mbist1_dat_i[14] ; |
| wire \wbd_mbist1_dat_i[15] ; |
| wire \wbd_mbist1_dat_i[16] ; |
| wire \wbd_mbist1_dat_i[17] ; |
| wire \wbd_mbist1_dat_i[18] ; |
| wire \wbd_mbist1_dat_i[19] ; |
| wire \wbd_mbist1_dat_i[1] ; |
| wire \wbd_mbist1_dat_i[20] ; |
| wire \wbd_mbist1_dat_i[21] ; |
| wire \wbd_mbist1_dat_i[22] ; |
| wire \wbd_mbist1_dat_i[23] ; |
| wire \wbd_mbist1_dat_i[24] ; |
| wire \wbd_mbist1_dat_i[25] ; |
| wire \wbd_mbist1_dat_i[26] ; |
| wire \wbd_mbist1_dat_i[27] ; |
| wire \wbd_mbist1_dat_i[28] ; |
| wire \wbd_mbist1_dat_i[29] ; |
| wire \wbd_mbist1_dat_i[2] ; |
| wire \wbd_mbist1_dat_i[30] ; |
| wire \wbd_mbist1_dat_i[31] ; |
| wire \wbd_mbist1_dat_i[3] ; |
| wire \wbd_mbist1_dat_i[4] ; |
| wire \wbd_mbist1_dat_i[5] ; |
| wire \wbd_mbist1_dat_i[6] ; |
| wire \wbd_mbist1_dat_i[7] ; |
| wire \wbd_mbist1_dat_i[8] ; |
| wire \wbd_mbist1_dat_i[9] ; |
| wire \wbd_mbist1_dat_o[0] ; |
| wire \wbd_mbist1_dat_o[10] ; |
| wire \wbd_mbist1_dat_o[11] ; |
| wire \wbd_mbist1_dat_o[12] ; |
| wire \wbd_mbist1_dat_o[13] ; |
| wire \wbd_mbist1_dat_o[14] ; |
| wire \wbd_mbist1_dat_o[15] ; |
| wire \wbd_mbist1_dat_o[16] ; |
| wire \wbd_mbist1_dat_o[17] ; |
| wire \wbd_mbist1_dat_o[18] ; |
| wire \wbd_mbist1_dat_o[19] ; |
| wire \wbd_mbist1_dat_o[1] ; |
| wire \wbd_mbist1_dat_o[20] ; |
| wire \wbd_mbist1_dat_o[21] ; |
| wire \wbd_mbist1_dat_o[22] ; |
| wire \wbd_mbist1_dat_o[23] ; |
| wire \wbd_mbist1_dat_o[24] ; |
| wire \wbd_mbist1_dat_o[25] ; |
| wire \wbd_mbist1_dat_o[26] ; |
| wire \wbd_mbist1_dat_o[27] ; |
| wire \wbd_mbist1_dat_o[28] ; |
| wire \wbd_mbist1_dat_o[29] ; |
| wire \wbd_mbist1_dat_o[2] ; |
| wire \wbd_mbist1_dat_o[30] ; |
| wire \wbd_mbist1_dat_o[31] ; |
| wire \wbd_mbist1_dat_o[3] ; |
| wire \wbd_mbist1_dat_o[4] ; |
| wire \wbd_mbist1_dat_o[5] ; |
| wire \wbd_mbist1_dat_o[6] ; |
| wire \wbd_mbist1_dat_o[7] ; |
| wire \wbd_mbist1_dat_o[8] ; |
| wire \wbd_mbist1_dat_o[9] ; |
| wire \wbd_mbist1_sel_o[0] ; |
| wire \wbd_mbist1_sel_o[1] ; |
| wire \wbd_mbist1_sel_o[2] ; |
| wire \wbd_mbist1_sel_o[3] ; |
| wire wbd_mbist1_stb_o; |
| wire wbd_mbist1_we_o; |
| wire wbd_pinmux_ack_i; |
| wire \wbd_pinmux_adr_o[0] ; |
| wire \wbd_pinmux_adr_o[1] ; |
| wire \wbd_pinmux_adr_o[2] ; |
| wire \wbd_pinmux_adr_o[3] ; |
| wire \wbd_pinmux_adr_o[4] ; |
| wire \wbd_pinmux_adr_o[5] ; |
| wire \wbd_pinmux_adr_o[6] ; |
| wire \wbd_pinmux_adr_o[7] ; |
| wire wbd_pinmux_cyc_o; |
| wire \wbd_pinmux_dat_i[0] ; |
| wire \wbd_pinmux_dat_i[10] ; |
| wire \wbd_pinmux_dat_i[11] ; |
| wire \wbd_pinmux_dat_i[12] ; |
| wire \wbd_pinmux_dat_i[13] ; |
| wire \wbd_pinmux_dat_i[14] ; |
| wire \wbd_pinmux_dat_i[15] ; |
| wire \wbd_pinmux_dat_i[16] ; |
| wire \wbd_pinmux_dat_i[17] ; |
| wire \wbd_pinmux_dat_i[18] ; |
| wire \wbd_pinmux_dat_i[19] ; |
| wire \wbd_pinmux_dat_i[1] ; |
| wire \wbd_pinmux_dat_i[20] ; |
| wire \wbd_pinmux_dat_i[21] ; |
| wire \wbd_pinmux_dat_i[22] ; |
| wire \wbd_pinmux_dat_i[23] ; |
| wire \wbd_pinmux_dat_i[24] ; |
| wire \wbd_pinmux_dat_i[25] ; |
| wire \wbd_pinmux_dat_i[26] ; |
| wire \wbd_pinmux_dat_i[27] ; |
| wire \wbd_pinmux_dat_i[28] ; |
| wire \wbd_pinmux_dat_i[29] ; |
| wire \wbd_pinmux_dat_i[2] ; |
| wire \wbd_pinmux_dat_i[30] ; |
| wire \wbd_pinmux_dat_i[31] ; |
| wire \wbd_pinmux_dat_i[3] ; |
| wire \wbd_pinmux_dat_i[4] ; |
| wire \wbd_pinmux_dat_i[5] ; |
| wire \wbd_pinmux_dat_i[6] ; |
| wire \wbd_pinmux_dat_i[7] ; |
| wire \wbd_pinmux_dat_i[8] ; |
| wire \wbd_pinmux_dat_i[9] ; |
| wire \wbd_pinmux_dat_o[0] ; |
| wire \wbd_pinmux_dat_o[10] ; |
| wire \wbd_pinmux_dat_o[11] ; |
| wire \wbd_pinmux_dat_o[12] ; |
| wire \wbd_pinmux_dat_o[13] ; |
| wire \wbd_pinmux_dat_o[14] ; |
| wire \wbd_pinmux_dat_o[15] ; |
| wire \wbd_pinmux_dat_o[16] ; |
| wire \wbd_pinmux_dat_o[17] ; |
| wire \wbd_pinmux_dat_o[18] ; |
| wire \wbd_pinmux_dat_o[19] ; |
| wire \wbd_pinmux_dat_o[1] ; |
| wire \wbd_pinmux_dat_o[20] ; |
| wire \wbd_pinmux_dat_o[21] ; |
| wire \wbd_pinmux_dat_o[22] ; |
| wire \wbd_pinmux_dat_o[23] ; |
| wire \wbd_pinmux_dat_o[24] ; |
| wire \wbd_pinmux_dat_o[25] ; |
| wire \wbd_pinmux_dat_o[26] ; |
| wire \wbd_pinmux_dat_o[27] ; |
| wire \wbd_pinmux_dat_o[28] ; |
| wire \wbd_pinmux_dat_o[29] ; |
| wire \wbd_pinmux_dat_o[2] ; |
| wire \wbd_pinmux_dat_o[30] ; |
| wire \wbd_pinmux_dat_o[31] ; |
| wire \wbd_pinmux_dat_o[3] ; |
| wire \wbd_pinmux_dat_o[4] ; |
| wire \wbd_pinmux_dat_o[5] ; |
| wire \wbd_pinmux_dat_o[6] ; |
| wire \wbd_pinmux_dat_o[7] ; |
| wire \wbd_pinmux_dat_o[8] ; |
| wire \wbd_pinmux_dat_o[9] ; |
| wire \wbd_pinmux_sel_o[0] ; |
| wire \wbd_pinmux_sel_o[1] ; |
| wire \wbd_pinmux_sel_o[2] ; |
| wire \wbd_pinmux_sel_o[3] ; |
| wire wbd_pinmux_stb_o; |
| wire wbd_pinmux_we_o; |
| wire wbm_grx_ack_i; |
| wire \wbm_grx_adr_o[0] ; |
| wire \wbm_grx_adr_o[10] ; |
| wire \wbm_grx_adr_o[11] ; |
| wire \wbm_grx_adr_o[12] ; |
| wire \wbm_grx_adr_o[13] ; |
| wire \wbm_grx_adr_o[14] ; |
| wire \wbm_grx_adr_o[15] ; |
| wire \wbm_grx_adr_o[1] ; |
| wire \wbm_grx_adr_o[2] ; |
| wire \wbm_grx_adr_o[3] ; |
| wire \wbm_grx_adr_o[4] ; |
| wire \wbm_grx_adr_o[5] ; |
| wire \wbm_grx_adr_o[6] ; |
| wire \wbm_grx_adr_o[7] ; |
| wire \wbm_grx_adr_o[8] ; |
| wire \wbm_grx_adr_o[9] ; |
| wire wbm_grx_cyc_o; |
| wire \wbm_grx_dat_i[0] ; |
| wire \wbm_grx_dat_i[10] ; |
| wire \wbm_grx_dat_i[11] ; |
| wire \wbm_grx_dat_i[12] ; |
| wire \wbm_grx_dat_i[13] ; |
| wire \wbm_grx_dat_i[14] ; |
| wire \wbm_grx_dat_i[15] ; |
| wire \wbm_grx_dat_i[16] ; |
| wire \wbm_grx_dat_i[17] ; |
| wire \wbm_grx_dat_i[18] ; |
| wire \wbm_grx_dat_i[19] ; |
| wire \wbm_grx_dat_i[1] ; |
| wire \wbm_grx_dat_i[20] ; |
| wire \wbm_grx_dat_i[21] ; |
| wire \wbm_grx_dat_i[22] ; |
| wire \wbm_grx_dat_i[23] ; |
| wire \wbm_grx_dat_i[24] ; |
| wire \wbm_grx_dat_i[25] ; |
| wire \wbm_grx_dat_i[26] ; |
| wire \wbm_grx_dat_i[27] ; |
| wire \wbm_grx_dat_i[28] ; |
| wire \wbm_grx_dat_i[29] ; |
| wire \wbm_grx_dat_i[2] ; |
| wire \wbm_grx_dat_i[30] ; |
| wire \wbm_grx_dat_i[31] ; |
| wire \wbm_grx_dat_i[3] ; |
| wire \wbm_grx_dat_i[4] ; |
| wire \wbm_grx_dat_i[5] ; |
| wire \wbm_grx_dat_i[6] ; |
| wire \wbm_grx_dat_i[7] ; |
| wire \wbm_grx_dat_i[8] ; |
| wire \wbm_grx_dat_i[9] ; |
| wire \wbm_grx_dat_o[0] ; |
| wire \wbm_grx_dat_o[10] ; |
| wire \wbm_grx_dat_o[11] ; |
| wire \wbm_grx_dat_o[12] ; |
| wire \wbm_grx_dat_o[13] ; |
| wire \wbm_grx_dat_o[14] ; |
| wire \wbm_grx_dat_o[15] ; |
| wire \wbm_grx_dat_o[16] ; |
| wire \wbm_grx_dat_o[17] ; |
| wire \wbm_grx_dat_o[18] ; |
| wire \wbm_grx_dat_o[19] ; |
| wire \wbm_grx_dat_o[1] ; |
| wire \wbm_grx_dat_o[20] ; |
| wire \wbm_grx_dat_o[21] ; |
| wire \wbm_grx_dat_o[22] ; |
| wire \wbm_grx_dat_o[23] ; |
| wire \wbm_grx_dat_o[24] ; |
| wire \wbm_grx_dat_o[25] ; |
| wire \wbm_grx_dat_o[26] ; |
| wire \wbm_grx_dat_o[27] ; |
| wire \wbm_grx_dat_o[28] ; |
| wire \wbm_grx_dat_o[29] ; |
| wire \wbm_grx_dat_o[2] ; |
| wire \wbm_grx_dat_o[30] ; |
| wire \wbm_grx_dat_o[31] ; |
| wire \wbm_grx_dat_o[3] ; |
| wire \wbm_grx_dat_o[4] ; |
| wire \wbm_grx_dat_o[5] ; |
| wire \wbm_grx_dat_o[6] ; |
| wire \wbm_grx_dat_o[7] ; |
| wire \wbm_grx_dat_o[8] ; |
| wire \wbm_grx_dat_o[9] ; |
| wire \wbm_grx_sel_o[0] ; |
| wire \wbm_grx_sel_o[1] ; |
| wire \wbm_grx_sel_o[2] ; |
| wire \wbm_grx_sel_o[3] ; |
| wire wbm_grx_stb_o; |
| wire wbm_grx_we_o; |
| wire wbm_gtx_ack_i; |
| wire \wbm_gtx_adr_o[0] ; |
| wire \wbm_gtx_adr_o[10] ; |
| wire \wbm_gtx_adr_o[11] ; |
| wire \wbm_gtx_adr_o[12] ; |
| wire \wbm_gtx_adr_o[13] ; |
| wire \wbm_gtx_adr_o[14] ; |
| wire \wbm_gtx_adr_o[15] ; |
| wire \wbm_gtx_adr_o[1] ; |
| wire \wbm_gtx_adr_o[2] ; |
| wire \wbm_gtx_adr_o[3] ; |
| wire \wbm_gtx_adr_o[4] ; |
| wire \wbm_gtx_adr_o[5] ; |
| wire \wbm_gtx_adr_o[6] ; |
| wire \wbm_gtx_adr_o[7] ; |
| wire \wbm_gtx_adr_o[8] ; |
| wire \wbm_gtx_adr_o[9] ; |
| wire wbm_gtx_cyc_o; |
| wire \wbm_gtx_dat_i[0] ; |
| wire \wbm_gtx_dat_i[10] ; |
| wire \wbm_gtx_dat_i[11] ; |
| wire \wbm_gtx_dat_i[12] ; |
| wire \wbm_gtx_dat_i[13] ; |
| wire \wbm_gtx_dat_i[14] ; |
| wire \wbm_gtx_dat_i[15] ; |
| wire \wbm_gtx_dat_i[16] ; |
| wire \wbm_gtx_dat_i[17] ; |
| wire \wbm_gtx_dat_i[18] ; |
| wire \wbm_gtx_dat_i[19] ; |
| wire \wbm_gtx_dat_i[1] ; |
| wire \wbm_gtx_dat_i[20] ; |
| wire \wbm_gtx_dat_i[21] ; |
| wire \wbm_gtx_dat_i[22] ; |
| wire \wbm_gtx_dat_i[23] ; |
| wire \wbm_gtx_dat_i[24] ; |
| wire \wbm_gtx_dat_i[25] ; |
| wire \wbm_gtx_dat_i[26] ; |
| wire \wbm_gtx_dat_i[27] ; |
| wire \wbm_gtx_dat_i[28] ; |
| wire \wbm_gtx_dat_i[29] ; |
| wire \wbm_gtx_dat_i[2] ; |
| wire \wbm_gtx_dat_i[30] ; |
| wire \wbm_gtx_dat_i[31] ; |
| wire \wbm_gtx_dat_i[3] ; |
| wire \wbm_gtx_dat_i[4] ; |
| wire \wbm_gtx_dat_i[5] ; |
| wire \wbm_gtx_dat_i[6] ; |
| wire \wbm_gtx_dat_i[7] ; |
| wire \wbm_gtx_dat_i[8] ; |
| wire \wbm_gtx_dat_i[9] ; |
| wire \wbm_gtx_dat_o[0] ; |
| wire \wbm_gtx_dat_o[10] ; |
| wire \wbm_gtx_dat_o[11] ; |
| wire \wbm_gtx_dat_o[12] ; |
| wire \wbm_gtx_dat_o[13] ; |
| wire \wbm_gtx_dat_o[14] ; |
| wire \wbm_gtx_dat_o[15] ; |
| wire \wbm_gtx_dat_o[16] ; |
| wire \wbm_gtx_dat_o[17] ; |
| wire \wbm_gtx_dat_o[18] ; |
| wire \wbm_gtx_dat_o[19] ; |
| wire \wbm_gtx_dat_o[1] ; |
| wire \wbm_gtx_dat_o[20] ; |
| wire \wbm_gtx_dat_o[21] ; |
| wire \wbm_gtx_dat_o[22] ; |
| wire \wbm_gtx_dat_o[23] ; |
| wire \wbm_gtx_dat_o[24] ; |
| wire \wbm_gtx_dat_o[25] ; |
| wire \wbm_gtx_dat_o[26] ; |
| wire \wbm_gtx_dat_o[27] ; |
| wire \wbm_gtx_dat_o[28] ; |
| wire \wbm_gtx_dat_o[29] ; |
| wire \wbm_gtx_dat_o[2] ; |
| wire \wbm_gtx_dat_o[30] ; |
| wire \wbm_gtx_dat_o[31] ; |
| wire \wbm_gtx_dat_o[3] ; |
| wire \wbm_gtx_dat_o[4] ; |
| wire \wbm_gtx_dat_o[5] ; |
| wire \wbm_gtx_dat_o[6] ; |
| wire \wbm_gtx_dat_o[7] ; |
| wire \wbm_gtx_dat_o[8] ; |
| wire \wbm_gtx_dat_o[9] ; |
| wire \wbm_gtx_sel_o[0] ; |
| wire \wbm_gtx_sel_o[1] ; |
| wire \wbm_gtx_sel_o[2] ; |
| wire \wbm_gtx_sel_o[3] ; |
| wire wbm_gtx_stb_o; |
| wire wbm_gtx_we_o; |
| wire wbs_ack_int_o; |
| wire \wbs_dat_int_o[0] ; |
| wire \wbs_dat_int_o[10] ; |
| wire \wbs_dat_int_o[11] ; |
| wire \wbs_dat_int_o[12] ; |
| wire \wbs_dat_int_o[13] ; |
| wire \wbs_dat_int_o[14] ; |
| wire \wbs_dat_int_o[15] ; |
| wire \wbs_dat_int_o[16] ; |
| wire \wbs_dat_int_o[17] ; |
| wire \wbs_dat_int_o[18] ; |
| wire \wbs_dat_int_o[19] ; |
| wire \wbs_dat_int_o[1] ; |
| wire \wbs_dat_int_o[20] ; |
| wire \wbs_dat_int_o[21] ; |
| wire \wbs_dat_int_o[22] ; |
| wire \wbs_dat_int_o[23] ; |
| wire \wbs_dat_int_o[24] ; |
| wire \wbs_dat_int_o[25] ; |
| wire \wbs_dat_int_o[26] ; |
| wire \wbs_dat_int_o[27] ; |
| wire \wbs_dat_int_o[28] ; |
| wire \wbs_dat_int_o[29] ; |
| wire \wbs_dat_int_o[2] ; |
| wire \wbs_dat_int_o[30] ; |
| wire \wbs_dat_int_o[31] ; |
| wire \wbs_dat_int_o[3] ; |
| wire \wbs_dat_int_o[4] ; |
| wire \wbs_dat_int_o[5] ; |
| wire \wbs_dat_int_o[6] ; |
| wire \wbs_dat_int_o[7] ; |
| wire \wbs_dat_int_o[8] ; |
| wire \wbs_dat_int_o[9] ; |
| wire wbs_grg_ack_o; |
| wire \wbs_grg_adr_i[0] ; |
| wire \wbs_grg_adr_i[10] ; |
| wire \wbs_grg_adr_i[11] ; |
| wire \wbs_grg_adr_i[12] ; |
| wire \wbs_grg_adr_i[1] ; |
| wire \wbs_grg_adr_i[2] ; |
| wire \wbs_grg_adr_i[3] ; |
| wire \wbs_grg_adr_i[4] ; |
| wire \wbs_grg_adr_i[5] ; |
| wire \wbs_grg_adr_i[6] ; |
| wire \wbs_grg_adr_i[7] ; |
| wire \wbs_grg_adr_i[8] ; |
| wire \wbs_grg_adr_i[9] ; |
| wire wbs_grg_cyc_i; |
| wire \wbs_grg_dat_i[0] ; |
| wire \wbs_grg_dat_i[10] ; |
| wire \wbs_grg_dat_i[11] ; |
| wire \wbs_grg_dat_i[12] ; |
| wire \wbs_grg_dat_i[13] ; |
| wire \wbs_grg_dat_i[14] ; |
| wire \wbs_grg_dat_i[15] ; |
| wire \wbs_grg_dat_i[16] ; |
| wire \wbs_grg_dat_i[17] ; |
| wire \wbs_grg_dat_i[18] ; |
| wire \wbs_grg_dat_i[19] ; |
| wire \wbs_grg_dat_i[1] ; |
| wire \wbs_grg_dat_i[20] ; |
| wire \wbs_grg_dat_i[21] ; |
| wire \wbs_grg_dat_i[22] ; |
| wire \wbs_grg_dat_i[23] ; |
| wire \wbs_grg_dat_i[24] ; |
| wire \wbs_grg_dat_i[25] ; |
| wire \wbs_grg_dat_i[26] ; |
| wire \wbs_grg_dat_i[27] ; |
| wire \wbs_grg_dat_i[28] ; |
| wire \wbs_grg_dat_i[29] ; |
| wire \wbs_grg_dat_i[2] ; |
| wire \wbs_grg_dat_i[30] ; |
| wire \wbs_grg_dat_i[31] ; |
| wire \wbs_grg_dat_i[3] ; |
| wire \wbs_grg_dat_i[4] ; |
| wire \wbs_grg_dat_i[5] ; |
| wire \wbs_grg_dat_i[6] ; |
| wire \wbs_grg_dat_i[7] ; |
| wire \wbs_grg_dat_i[8] ; |
| wire \wbs_grg_dat_i[9] ; |
| wire \wbs_grg_dat_o[0] ; |
| wire \wbs_grg_dat_o[10] ; |
| wire \wbs_grg_dat_o[11] ; |
| wire \wbs_grg_dat_o[12] ; |
| wire \wbs_grg_dat_o[13] ; |
| wire \wbs_grg_dat_o[14] ; |
| wire \wbs_grg_dat_o[15] ; |
| wire \wbs_grg_dat_o[16] ; |
| wire \wbs_grg_dat_o[17] ; |
| wire \wbs_grg_dat_o[18] ; |
| wire \wbs_grg_dat_o[19] ; |
| wire \wbs_grg_dat_o[1] ; |
| wire \wbs_grg_dat_o[20] ; |
| wire \wbs_grg_dat_o[21] ; |
| wire \wbs_grg_dat_o[22] ; |
| wire \wbs_grg_dat_o[23] ; |
| wire \wbs_grg_dat_o[24] ; |
| wire \wbs_grg_dat_o[25] ; |
| wire \wbs_grg_dat_o[26] ; |
| wire \wbs_grg_dat_o[27] ; |
| wire \wbs_grg_dat_o[28] ; |
| wire \wbs_grg_dat_o[29] ; |
| wire \wbs_grg_dat_o[2] ; |
| wire \wbs_grg_dat_o[30] ; |
| wire \wbs_grg_dat_o[31] ; |
| wire \wbs_grg_dat_o[3] ; |
| wire \wbs_grg_dat_o[4] ; |
| wire \wbs_grg_dat_o[5] ; |
| wire \wbs_grg_dat_o[6] ; |
| wire \wbs_grg_dat_o[7] ; |
| wire \wbs_grg_dat_o[8] ; |
| wire \wbs_grg_dat_o[9] ; |
| wire \wbs_grg_sel_i[0] ; |
| wire \wbs_grg_sel_i[1] ; |
| wire \wbs_grg_sel_i[2] ; |
| wire \wbs_grg_sel_i[3] ; |
| wire wbs_grg_stb_i; |
| wire wbs_grg_we_i; |
| |
| wb_interconnect u_intercon (.clk_i(wbd_clk_wi_skew), |
| .m0_wbd_ack_o(wbd_int_ack_o), |
| .m0_wbd_cyc_i(wbd_int_cyc_i), |
| .m0_wbd_err_o(wbd_int_err_o), |
| .m0_wbd_stb_i(wbd_int_stb_i), |
| .m0_wbd_we_i(wbd_int_we_i), |
| .m1_wbd_ack_o(wbm_gtx_ack_i), |
| .m1_wbd_cyc_i(wbm_gtx_cyc_o), |
| .m1_wbd_stb_i(wbm_gtx_stb_o), |
| .m1_wbd_we_i(wbm_gtx_we_o), |
| .m2_wbd_ack_o(wbm_grx_ack_i), |
| .m2_wbd_cyc_i(wbm_grx_cyc_o), |
| .m2_wbd_stb_i(wbm_grx_stb_o), |
| .m2_wbd_we_i(wbm_grx_we_o), |
| .mac_rx_qcnt_dec(mac_rx_qcnt_dec), |
| .mac_rx_qcnt_inc(mac_rx_qcnt_inc), |
| .mac_tx_qcnt_dec(mac_tx_qcnt_dec), |
| .mac_tx_qcnt_inc(mac_tx_qcnt_inc), |
| .rst_n(wbd_int_rst_n), |
| .s0_wbd_ack_i(wbd_pinmux_ack_i), |
| .s0_wbd_cyc_o(wbd_pinmux_cyc_o), |
| .s0_wbd_stb_o(wbd_pinmux_stb_o), |
| .s0_wbd_we_o(wbd_pinmux_we_o), |
| .s1_wbd_ack_i(wbs_grg_ack_o), |
| .s1_wbd_cyc_o(wbs_grg_cyc_i), |
| .s1_wbd_stb_o(wbs_grg_stb_i), |
| .s1_wbd_we_o(wbs_grg_we_i), |
| .s2_wbd_ack_i(wbd_mbist0_ack_i), |
| .s2_wbd_bry_o(wbd_mbist0_bry_o), |
| .s2_wbd_cyc_o(wbd_mbist0_cyc_o), |
| .s2_wbd_stb_o(wbd_mbist0_stb_o), |
| .s2_wbd_we_o(wbd_mbist0_we_o), |
| .s3_wbd_ack_i(wbd_mbist1_ack_i), |
| .s3_wbd_bry_o(wbd_mbist1_bry_o), |
| .s3_wbd_cyc_o(wbd_mbist1_cyc_o), |
| .s3_wbd_stb_o(wbd_mbist1_stb_o), |
| .s3_wbd_we_o(wbd_mbist1_we_o), |
| .scan_en(scan_en_mbist1), |
| .scan_en_o(scan_en_wi), |
| .scan_mode(scan_mode_mbist1), |
| .scan_mode_o(scan_mode_wi), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .wbd_clk_int(wbd_clk_int), |
| .wbd_clk_skew(wbd_clk_wi_skew), |
| .cfg_cska_wi({\cfg_clk_ctrl1[7] , |
| \cfg_clk_ctrl1[6] , |
| \cfg_clk_ctrl1[5] , |
| \cfg_clk_ctrl1[4] }), |
| .ch_clk_in({wbd_clk_int, |
| wbd_clk_int, |
| wbd_clk_int, |
| wbd_clk_int}), |
| .ch_clk_out({wbd_clk_mac_rp, |
| wbd_clk_mbist1_rp, |
| wbd_clk_mbist0_rp, |
| wbd_clk_pinmux_rp}), |
| .m0_wbd_adr_i({\wbd_int_adr_i[31] , |
| \wbd_int_adr_i[30] , |
| \wbd_int_adr_i[29] , |
| \wbd_int_adr_i[28] , |
| \wbd_int_adr_i[27] , |
| \wbd_int_adr_i[26] , |
| \wbd_int_adr_i[25] , |
| \wbd_int_adr_i[24] , |
| \wbd_int_adr_i[23] , |
| \wbd_int_adr_i[22] , |
| \wbd_int_adr_i[21] , |
| \wbd_int_adr_i[20] , |
| \wbd_int_adr_i[19] , |
| \wbd_int_adr_i[18] , |
| \wbd_int_adr_i[17] , |
| \wbd_int_adr_i[16] , |
| \wbd_int_adr_i[15] , |
| \wbd_int_adr_i[14] , |
| \wbd_int_adr_i[13] , |
| \wbd_int_adr_i[12] , |
| \wbd_int_adr_i[11] , |
| \wbd_int_adr_i[10] , |
| \wbd_int_adr_i[9] , |
| \wbd_int_adr_i[8] , |
| \wbd_int_adr_i[7] , |
| \wbd_int_adr_i[6] , |
| \wbd_int_adr_i[5] , |
| \wbd_int_adr_i[4] , |
| \wbd_int_adr_i[3] , |
| \wbd_int_adr_i[2] , |
| \wbd_int_adr_i[1] , |
| \wbd_int_adr_i[0] }), |
| .m0_wbd_dat_i({\wbd_int_dat_i[31] , |
| \wbd_int_dat_i[30] , |
| \wbd_int_dat_i[29] , |
| \wbd_int_dat_i[28] , |
| \wbd_int_dat_i[27] , |
| \wbd_int_dat_i[26] , |
| \wbd_int_dat_i[25] , |
| \wbd_int_dat_i[24] , |
| \wbd_int_dat_i[23] , |
| \wbd_int_dat_i[22] , |
| \wbd_int_dat_i[21] , |
| \wbd_int_dat_i[20] , |
| \wbd_int_dat_i[19] , |
| \wbd_int_dat_i[18] , |
| \wbd_int_dat_i[17] , |
| \wbd_int_dat_i[16] , |
| \wbd_int_dat_i[15] , |
| \wbd_int_dat_i[14] , |
| \wbd_int_dat_i[13] , |
| \wbd_int_dat_i[12] , |
| \wbd_int_dat_i[11] , |
| \wbd_int_dat_i[10] , |
| \wbd_int_dat_i[9] , |
| \wbd_int_dat_i[8] , |
| \wbd_int_dat_i[7] , |
| \wbd_int_dat_i[6] , |
| \wbd_int_dat_i[5] , |
| \wbd_int_dat_i[4] , |
| \wbd_int_dat_i[3] , |
| \wbd_int_dat_i[2] , |
| \wbd_int_dat_i[1] , |
| \wbd_int_dat_i[0] }), |
| .m0_wbd_dat_o({\wbd_int_dat_o[31] , |
| \wbd_int_dat_o[30] , |
| \wbd_int_dat_o[29] , |
| \wbd_int_dat_o[28] , |
| \wbd_int_dat_o[27] , |
| \wbd_int_dat_o[26] , |
| \wbd_int_dat_o[25] , |
| \wbd_int_dat_o[24] , |
| \wbd_int_dat_o[23] , |
| \wbd_int_dat_o[22] , |
| \wbd_int_dat_o[21] , |
| \wbd_int_dat_o[20] , |
| \wbd_int_dat_o[19] , |
| \wbd_int_dat_o[18] , |
| \wbd_int_dat_o[17] , |
| \wbd_int_dat_o[16] , |
| \wbd_int_dat_o[15] , |
| \wbd_int_dat_o[14] , |
| \wbd_int_dat_o[13] , |
| \wbd_int_dat_o[12] , |
| \wbd_int_dat_o[11] , |
| \wbd_int_dat_o[10] , |
| \wbd_int_dat_o[9] , |
| \wbd_int_dat_o[8] , |
| \wbd_int_dat_o[7] , |
| \wbd_int_dat_o[6] , |
| \wbd_int_dat_o[5] , |
| \wbd_int_dat_o[4] , |
| \wbd_int_dat_o[3] , |
| \wbd_int_dat_o[2] , |
| \wbd_int_dat_o[1] , |
| \wbd_int_dat_o[0] }), |
| .m0_wbd_sel_i({\wbd_int_sel_i[3] , |
| \wbd_int_sel_i[2] , |
| \wbd_int_sel_i[1] , |
| \wbd_int_sel_i[0] }), |
| .m1_wbd_adr_i({\wbm_gtx_adr_o[15] , |
| \wbm_gtx_adr_o[14] , |
| \wbm_gtx_adr_o[13] , |
| \wbm_gtx_adr_o[12] , |
| \wbm_gtx_adr_o[11] , |
| \wbm_gtx_adr_o[10] , |
| \wbm_gtx_adr_o[9] , |
| \wbm_gtx_adr_o[8] , |
| \wbm_gtx_adr_o[7] , |
| \wbm_gtx_adr_o[6] , |
| \wbm_gtx_adr_o[5] , |
| \wbm_gtx_adr_o[4] , |
| \wbm_gtx_adr_o[3] , |
| \wbm_gtx_adr_o[2] , |
| \wbm_gtx_adr_o[1] , |
| \wbm_gtx_adr_o[0] }), |
| .m1_wbd_dat_i({\wbm_gtx_dat_o[31] , |
| \wbm_gtx_dat_o[30] , |
| \wbm_gtx_dat_o[29] , |
| \wbm_gtx_dat_o[28] , |
| \wbm_gtx_dat_o[27] , |
| \wbm_gtx_dat_o[26] , |
| \wbm_gtx_dat_o[25] , |
| \wbm_gtx_dat_o[24] , |
| \wbm_gtx_dat_o[23] , |
| \wbm_gtx_dat_o[22] , |
| \wbm_gtx_dat_o[21] , |
| \wbm_gtx_dat_o[20] , |
| \wbm_gtx_dat_o[19] , |
| \wbm_gtx_dat_o[18] , |
| \wbm_gtx_dat_o[17] , |
| \wbm_gtx_dat_o[16] , |
| \wbm_gtx_dat_o[15] , |
| \wbm_gtx_dat_o[14] , |
| \wbm_gtx_dat_o[13] , |
| \wbm_gtx_dat_o[12] , |
| \wbm_gtx_dat_o[11] , |
| \wbm_gtx_dat_o[10] , |
| \wbm_gtx_dat_o[9] , |
| \wbm_gtx_dat_o[8] , |
| \wbm_gtx_dat_o[7] , |
| \wbm_gtx_dat_o[6] , |
| \wbm_gtx_dat_o[5] , |
| \wbm_gtx_dat_o[4] , |
| \wbm_gtx_dat_o[3] , |
| \wbm_gtx_dat_o[2] , |
| \wbm_gtx_dat_o[1] , |
| \wbm_gtx_dat_o[0] }), |
| .m1_wbd_dat_o({\wbm_gtx_dat_i[31] , |
| \wbm_gtx_dat_i[30] , |
| \wbm_gtx_dat_i[29] , |
| \wbm_gtx_dat_i[28] , |
| \wbm_gtx_dat_i[27] , |
| \wbm_gtx_dat_i[26] , |
| \wbm_gtx_dat_i[25] , |
| \wbm_gtx_dat_i[24] , |
| \wbm_gtx_dat_i[23] , |
| \wbm_gtx_dat_i[22] , |
| \wbm_gtx_dat_i[21] , |
| \wbm_gtx_dat_i[20] , |
| \wbm_gtx_dat_i[19] , |
| \wbm_gtx_dat_i[18] , |
| \wbm_gtx_dat_i[17] , |
| \wbm_gtx_dat_i[16] , |
| \wbm_gtx_dat_i[15] , |
| \wbm_gtx_dat_i[14] , |
| \wbm_gtx_dat_i[13] , |
| \wbm_gtx_dat_i[12] , |
| \wbm_gtx_dat_i[11] , |
| \wbm_gtx_dat_i[10] , |
| \wbm_gtx_dat_i[9] , |
| \wbm_gtx_dat_i[8] , |
| \wbm_gtx_dat_i[7] , |
| \wbm_gtx_dat_i[6] , |
| \wbm_gtx_dat_i[5] , |
| \wbm_gtx_dat_i[4] , |
| \wbm_gtx_dat_i[3] , |
| \wbm_gtx_dat_i[2] , |
| \wbm_gtx_dat_i[1] , |
| \wbm_gtx_dat_i[0] }), |
| .m1_wbd_sel_i({\wbm_gtx_sel_o[3] , |
| \wbm_gtx_sel_o[2] , |
| \wbm_gtx_sel_o[1] , |
| \wbm_gtx_sel_o[0] }), |
| .m2_wbd_adr_i({\wbm_grx_adr_o[15] , |
| \wbm_grx_adr_o[14] , |
| \wbm_grx_adr_o[13] , |
| \wbm_grx_adr_o[12] , |
| \wbm_grx_adr_o[11] , |
| \wbm_grx_adr_o[10] , |
| \wbm_grx_adr_o[9] , |
| \wbm_grx_adr_o[8] , |
| \wbm_grx_adr_o[7] , |
| \wbm_grx_adr_o[6] , |
| \wbm_grx_adr_o[5] , |
| \wbm_grx_adr_o[4] , |
| \wbm_grx_adr_o[3] , |
| \wbm_grx_adr_o[2] , |
| \wbm_grx_adr_o[1] , |
| \wbm_grx_adr_o[0] }), |
| .m2_wbd_dat_i({\wbm_grx_dat_o[31] , |
| \wbm_grx_dat_o[30] , |
| \wbm_grx_dat_o[29] , |
| \wbm_grx_dat_o[28] , |
| \wbm_grx_dat_o[27] , |
| \wbm_grx_dat_o[26] , |
| \wbm_grx_dat_o[25] , |
| \wbm_grx_dat_o[24] , |
| \wbm_grx_dat_o[23] , |
| \wbm_grx_dat_o[22] , |
| \wbm_grx_dat_o[21] , |
| \wbm_grx_dat_o[20] , |
| \wbm_grx_dat_o[19] , |
| \wbm_grx_dat_o[18] , |
| \wbm_grx_dat_o[17] , |
| \wbm_grx_dat_o[16] , |
| \wbm_grx_dat_o[15] , |
| \wbm_grx_dat_o[14] , |
| \wbm_grx_dat_o[13] , |
| \wbm_grx_dat_o[12] , |
| \wbm_grx_dat_o[11] , |
| \wbm_grx_dat_o[10] , |
| \wbm_grx_dat_o[9] , |
| \wbm_grx_dat_o[8] , |
| \wbm_grx_dat_o[7] , |
| \wbm_grx_dat_o[6] , |
| \wbm_grx_dat_o[5] , |
| \wbm_grx_dat_o[4] , |
| \wbm_grx_dat_o[3] , |
| \wbm_grx_dat_o[2] , |
| \wbm_grx_dat_o[1] , |
| \wbm_grx_dat_o[0] }), |
| .m2_wbd_dat_o({\wbm_grx_dat_i[31] , |
| \wbm_grx_dat_i[30] , |
| \wbm_grx_dat_i[29] , |
| \wbm_grx_dat_i[28] , |
| \wbm_grx_dat_i[27] , |
| \wbm_grx_dat_i[26] , |
| \wbm_grx_dat_i[25] , |
| \wbm_grx_dat_i[24] , |
| \wbm_grx_dat_i[23] , |
| \wbm_grx_dat_i[22] , |
| \wbm_grx_dat_i[21] , |
| \wbm_grx_dat_i[20] , |
| \wbm_grx_dat_i[19] , |
| \wbm_grx_dat_i[18] , |
| \wbm_grx_dat_i[17] , |
| \wbm_grx_dat_i[16] , |
| \wbm_grx_dat_i[15] , |
| \wbm_grx_dat_i[14] , |
| \wbm_grx_dat_i[13] , |
| \wbm_grx_dat_i[12] , |
| \wbm_grx_dat_i[11] , |
| \wbm_grx_dat_i[10] , |
| \wbm_grx_dat_i[9] , |
| \wbm_grx_dat_i[8] , |
| \wbm_grx_dat_i[7] , |
| \wbm_grx_dat_i[6] , |
| \wbm_grx_dat_i[5] , |
| \wbm_grx_dat_i[4] , |
| \wbm_grx_dat_i[3] , |
| \wbm_grx_dat_i[2] , |
| \wbm_grx_dat_i[1] , |
| \wbm_grx_dat_i[0] }), |
| .m2_wbd_sel_i({\wbm_grx_sel_o[3] , |
| \wbm_grx_sel_o[2] , |
| \wbm_grx_sel_o[1] , |
| \wbm_grx_sel_o[0] }), |
| .mac_rx_qbase_addr({\mac_rx_qbase_addr[9] , |
| \mac_rx_qbase_addr[8] , |
| \mac_rx_qbase_addr[7] , |
| \mac_rx_qbase_addr[6] , |
| \mac_rx_qbase_addr[5] , |
| \mac_rx_qbase_addr[4] , |
| \mac_rx_qbase_addr[3] , |
| \mac_rx_qbase_addr[2] , |
| \mac_rx_qbase_addr[1] , |
| \mac_rx_qbase_addr[0] }), |
| .mac_tx_qbase_addr({\mac_tx_qbase_addr[9] , |
| \mac_tx_qbase_addr[8] , |
| \mac_tx_qbase_addr[7] , |
| \mac_tx_qbase_addr[6] , |
| \mac_tx_qbase_addr[5] , |
| \mac_tx_qbase_addr[4] , |
| \mac_tx_qbase_addr[3] , |
| \mac_tx_qbase_addr[2] , |
| \mac_tx_qbase_addr[1] , |
| \mac_tx_qbase_addr[0] }), |
| .s0_wbd_adr_o({\wbd_pinmux_adr_o[7] , |
| \wbd_pinmux_adr_o[6] , |
| \wbd_pinmux_adr_o[5] , |
| \wbd_pinmux_adr_o[4] , |
| \wbd_pinmux_adr_o[3] , |
| \wbd_pinmux_adr_o[2] , |
| \wbd_pinmux_adr_o[1] , |
| \wbd_pinmux_adr_o[0] }), |
| .s0_wbd_dat_i({\wbd_pinmux_dat_i[31] , |
| \wbd_pinmux_dat_i[30] , |
| \wbd_pinmux_dat_i[29] , |
| \wbd_pinmux_dat_i[28] , |
| \wbd_pinmux_dat_i[27] , |
| \wbd_pinmux_dat_i[26] , |
| \wbd_pinmux_dat_i[25] , |
| \wbd_pinmux_dat_i[24] , |
| \wbd_pinmux_dat_i[23] , |
| \wbd_pinmux_dat_i[22] , |
| \wbd_pinmux_dat_i[21] , |
| \wbd_pinmux_dat_i[20] , |
| \wbd_pinmux_dat_i[19] , |
| \wbd_pinmux_dat_i[18] , |
| \wbd_pinmux_dat_i[17] , |
| \wbd_pinmux_dat_i[16] , |
| \wbd_pinmux_dat_i[15] , |
| \wbd_pinmux_dat_i[14] , |
| \wbd_pinmux_dat_i[13] , |
| \wbd_pinmux_dat_i[12] , |
| \wbd_pinmux_dat_i[11] , |
| \wbd_pinmux_dat_i[10] , |
| \wbd_pinmux_dat_i[9] , |
| \wbd_pinmux_dat_i[8] , |
| \wbd_pinmux_dat_i[7] , |
| \wbd_pinmux_dat_i[6] , |
| \wbd_pinmux_dat_i[5] , |
| \wbd_pinmux_dat_i[4] , |
| \wbd_pinmux_dat_i[3] , |
| \wbd_pinmux_dat_i[2] , |
| \wbd_pinmux_dat_i[1] , |
| \wbd_pinmux_dat_i[0] }), |
| .s0_wbd_dat_o({\wbd_pinmux_dat_o[31] , |
| \wbd_pinmux_dat_o[30] , |
| \wbd_pinmux_dat_o[29] , |
| \wbd_pinmux_dat_o[28] , |
| \wbd_pinmux_dat_o[27] , |
| \wbd_pinmux_dat_o[26] , |
| \wbd_pinmux_dat_o[25] , |
| \wbd_pinmux_dat_o[24] , |
| \wbd_pinmux_dat_o[23] , |
| \wbd_pinmux_dat_o[22] , |
| \wbd_pinmux_dat_o[21] , |
| \wbd_pinmux_dat_o[20] , |
| \wbd_pinmux_dat_o[19] , |
| \wbd_pinmux_dat_o[18] , |
| \wbd_pinmux_dat_o[17] , |
| \wbd_pinmux_dat_o[16] , |
| \wbd_pinmux_dat_o[15] , |
| \wbd_pinmux_dat_o[14] , |
| \wbd_pinmux_dat_o[13] , |
| \wbd_pinmux_dat_o[12] , |
| \wbd_pinmux_dat_o[11] , |
| \wbd_pinmux_dat_o[10] , |
| \wbd_pinmux_dat_o[9] , |
| \wbd_pinmux_dat_o[8] , |
| \wbd_pinmux_dat_o[7] , |
| \wbd_pinmux_dat_o[6] , |
| \wbd_pinmux_dat_o[5] , |
| \wbd_pinmux_dat_o[4] , |
| \wbd_pinmux_dat_o[3] , |
| \wbd_pinmux_dat_o[2] , |
| \wbd_pinmux_dat_o[1] , |
| \wbd_pinmux_dat_o[0] }), |
| .s0_wbd_sel_o({\wbd_pinmux_sel_o[3] , |
| \wbd_pinmux_sel_o[2] , |
| \wbd_pinmux_sel_o[1] , |
| \wbd_pinmux_sel_o[0] }), |
| .s1_wbd_adr_o({\wbs_grg_adr_i[12] , |
| \wbs_grg_adr_i[11] , |
| \wbs_grg_adr_i[10] , |
| \wbs_grg_adr_i[9] , |
| \wbs_grg_adr_i[8] , |
| \wbs_grg_adr_i[7] , |
| \wbs_grg_adr_i[6] , |
| \wbs_grg_adr_i[5] , |
| \wbs_grg_adr_i[4] , |
| \wbs_grg_adr_i[3] , |
| \wbs_grg_adr_i[2] , |
| \wbs_grg_adr_i[1] , |
| \wbs_grg_adr_i[0] }), |
| .s1_wbd_dat_i({\wbs_grg_dat_o[31] , |
| \wbs_grg_dat_o[30] , |
| \wbs_grg_dat_o[29] , |
| \wbs_grg_dat_o[28] , |
| \wbs_grg_dat_o[27] , |
| \wbs_grg_dat_o[26] , |
| \wbs_grg_dat_o[25] , |
| \wbs_grg_dat_o[24] , |
| \wbs_grg_dat_o[23] , |
| \wbs_grg_dat_o[22] , |
| \wbs_grg_dat_o[21] , |
| \wbs_grg_dat_o[20] , |
| \wbs_grg_dat_o[19] , |
| \wbs_grg_dat_o[18] , |
| \wbs_grg_dat_o[17] , |
| \wbs_grg_dat_o[16] , |
| \wbs_grg_dat_o[15] , |
| \wbs_grg_dat_o[14] , |
| \wbs_grg_dat_o[13] , |
| \wbs_grg_dat_o[12] , |
| \wbs_grg_dat_o[11] , |
| \wbs_grg_dat_o[10] , |
| \wbs_grg_dat_o[9] , |
| \wbs_grg_dat_o[8] , |
| \wbs_grg_dat_o[7] , |
| \wbs_grg_dat_o[6] , |
| \wbs_grg_dat_o[5] , |
| \wbs_grg_dat_o[4] , |
| \wbs_grg_dat_o[3] , |
| \wbs_grg_dat_o[2] , |
| \wbs_grg_dat_o[1] , |
| \wbs_grg_dat_o[0] }), |
| .s1_wbd_dat_o({\wbs_grg_dat_i[31] , |
| \wbs_grg_dat_i[30] , |
| \wbs_grg_dat_i[29] , |
| \wbs_grg_dat_i[28] , |
| \wbs_grg_dat_i[27] , |
| \wbs_grg_dat_i[26] , |
| \wbs_grg_dat_i[25] , |
| \wbs_grg_dat_i[24] , |
| \wbs_grg_dat_i[23] , |
| \wbs_grg_dat_i[22] , |
| \wbs_grg_dat_i[21] , |
| \wbs_grg_dat_i[20] , |
| \wbs_grg_dat_i[19] , |
| \wbs_grg_dat_i[18] , |
| \wbs_grg_dat_i[17] , |
| \wbs_grg_dat_i[16] , |
| \wbs_grg_dat_i[15] , |
| \wbs_grg_dat_i[14] , |
| \wbs_grg_dat_i[13] , |
| \wbs_grg_dat_i[12] , |
| \wbs_grg_dat_i[11] , |
| \wbs_grg_dat_i[10] , |
| \wbs_grg_dat_i[9] , |
| \wbs_grg_dat_i[8] , |
| \wbs_grg_dat_i[7] , |
| \wbs_grg_dat_i[6] , |
| \wbs_grg_dat_i[5] , |
| \wbs_grg_dat_i[4] , |
| \wbs_grg_dat_i[3] , |
| \wbs_grg_dat_i[2] , |
| \wbs_grg_dat_i[1] , |
| \wbs_grg_dat_i[0] }), |
| .s1_wbd_sel_o({\wbs_grg_sel_i[3] , |
| \wbs_grg_sel_i[2] , |
| \wbs_grg_sel_i[1] , |
| \wbs_grg_sel_i[0] }), |
| .s2_wbd_adr_o({\wbd_mbist0_adr_o[14] , |
| \wbd_mbist0_adr_o[13] , |
| \wbd_mbist0_adr_o[12] , |
| \wbd_mbist0_adr_o[11] , |
| \wbd_mbist0_adr_o[10] , |
| \wbd_mbist0_adr_o[9] , |
| \wbd_mbist0_adr_o[8] , |
| \wbd_mbist0_adr_o[7] , |
| \wbd_mbist0_adr_o[6] , |
| \wbd_mbist0_adr_o[5] , |
| \wbd_mbist0_adr_o[4] , |
| \wbd_mbist0_adr_o[3] , |
| \wbd_mbist0_adr_o[2] , |
| \wbd_mbist0_adr_o[1] , |
| \wbd_mbist0_adr_o[0] }), |
| .s2_wbd_bl_o({\wbd_mbist0_bl_o[9] , |
| \wbd_mbist0_bl_o[8] , |
| \wbd_mbist0_bl_o[7] , |
| \wbd_mbist0_bl_o[6] , |
| \wbd_mbist0_bl_o[5] , |
| \wbd_mbist0_bl_o[4] , |
| \wbd_mbist0_bl_o[3] , |
| \wbd_mbist0_bl_o[2] , |
| \wbd_mbist0_bl_o[1] , |
| \wbd_mbist0_bl_o[0] }), |
| .s2_wbd_dat_i({\wbd_mbist0_dat_i[31] , |
| \wbd_mbist0_dat_i[30] , |
| \wbd_mbist0_dat_i[29] , |
| \wbd_mbist0_dat_i[28] , |
| \wbd_mbist0_dat_i[27] , |
| \wbd_mbist0_dat_i[26] , |
| \wbd_mbist0_dat_i[25] , |
| \wbd_mbist0_dat_i[24] , |
| \wbd_mbist0_dat_i[23] , |
| \wbd_mbist0_dat_i[22] , |
| \wbd_mbist0_dat_i[21] , |
| \wbd_mbist0_dat_i[20] , |
| \wbd_mbist0_dat_i[19] , |
| \wbd_mbist0_dat_i[18] , |
| \wbd_mbist0_dat_i[17] , |
| \wbd_mbist0_dat_i[16] , |
| \wbd_mbist0_dat_i[15] , |
| \wbd_mbist0_dat_i[14] , |
| \wbd_mbist0_dat_i[13] , |
| \wbd_mbist0_dat_i[12] , |
| \wbd_mbist0_dat_i[11] , |
| \wbd_mbist0_dat_i[10] , |
| \wbd_mbist0_dat_i[9] , |
| \wbd_mbist0_dat_i[8] , |
| \wbd_mbist0_dat_i[7] , |
| \wbd_mbist0_dat_i[6] , |
| \wbd_mbist0_dat_i[5] , |
| \wbd_mbist0_dat_i[4] , |
| \wbd_mbist0_dat_i[3] , |
| \wbd_mbist0_dat_i[2] , |
| \wbd_mbist0_dat_i[1] , |
| \wbd_mbist0_dat_i[0] }), |
| .s2_wbd_dat_o({\wbd_mbist0_dat_o[31] , |
| \wbd_mbist0_dat_o[30] , |
| \wbd_mbist0_dat_o[29] , |
| \wbd_mbist0_dat_o[28] , |
| \wbd_mbist0_dat_o[27] , |
| \wbd_mbist0_dat_o[26] , |
| \wbd_mbist0_dat_o[25] , |
| \wbd_mbist0_dat_o[24] , |
| \wbd_mbist0_dat_o[23] , |
| \wbd_mbist0_dat_o[22] , |
| \wbd_mbist0_dat_o[21] , |
| \wbd_mbist0_dat_o[20] , |
| \wbd_mbist0_dat_o[19] , |
| \wbd_mbist0_dat_o[18] , |
| \wbd_mbist0_dat_o[17] , |
| \wbd_mbist0_dat_o[16] , |
| \wbd_mbist0_dat_o[15] , |
| \wbd_mbist0_dat_o[14] , |
| \wbd_mbist0_dat_o[13] , |
| \wbd_mbist0_dat_o[12] , |
| \wbd_mbist0_dat_o[11] , |
| \wbd_mbist0_dat_o[10] , |
| \wbd_mbist0_dat_o[9] , |
| \wbd_mbist0_dat_o[8] , |
| \wbd_mbist0_dat_o[7] , |
| \wbd_mbist0_dat_o[6] , |
| \wbd_mbist0_dat_o[5] , |
| \wbd_mbist0_dat_o[4] , |
| \wbd_mbist0_dat_o[3] , |
| \wbd_mbist0_dat_o[2] , |
| \wbd_mbist0_dat_o[1] , |
| \wbd_mbist0_dat_o[0] }), |
| .s2_wbd_sel_o({\wbd_mbist0_sel_o[3] , |
| \wbd_mbist0_sel_o[2] , |
| \wbd_mbist0_sel_o[1] , |
| \wbd_mbist0_sel_o[0] }), |
| .s3_wbd_adr_o({\wbd_mbist1_adr_o[14] , |
| \wbd_mbist1_adr_o[13] , |
| \wbd_mbist1_adr_o[12] , |
| \wbd_mbist1_adr_o[11] , |
| \wbd_mbist1_adr_o[10] , |
| \wbd_mbist1_adr_o[9] , |
| \wbd_mbist1_adr_o[8] , |
| \wbd_mbist1_adr_o[7] , |
| \wbd_mbist1_adr_o[6] , |
| \wbd_mbist1_adr_o[5] , |
| \wbd_mbist1_adr_o[4] , |
| \wbd_mbist1_adr_o[3] , |
| \wbd_mbist1_adr_o[2] , |
| \wbd_mbist1_adr_o[1] , |
| \wbd_mbist1_adr_o[0] }), |
| .s3_wbd_bl_o({\wbd_mbist1_bl_o[9] , |
| \wbd_mbist1_bl_o[8] , |
| \wbd_mbist1_bl_o[7] , |
| \wbd_mbist1_bl_o[6] , |
| \wbd_mbist1_bl_o[5] , |
| \wbd_mbist1_bl_o[4] , |
| \wbd_mbist1_bl_o[3] , |
| \wbd_mbist1_bl_o[2] , |
| \wbd_mbist1_bl_o[1] , |
| \wbd_mbist1_bl_o[0] }), |
| .s3_wbd_dat_i({\wbd_mbist1_dat_i[31] , |
| \wbd_mbist1_dat_i[30] , |
| \wbd_mbist1_dat_i[29] , |
| \wbd_mbist1_dat_i[28] , |
| \wbd_mbist1_dat_i[27] , |
| \wbd_mbist1_dat_i[26] , |
| \wbd_mbist1_dat_i[25] , |
| \wbd_mbist1_dat_i[24] , |
| \wbd_mbist1_dat_i[23] , |
| \wbd_mbist1_dat_i[22] , |
| \wbd_mbist1_dat_i[21] , |
| \wbd_mbist1_dat_i[20] , |
| \wbd_mbist1_dat_i[19] , |
| \wbd_mbist1_dat_i[18] , |
| \wbd_mbist1_dat_i[17] , |
| \wbd_mbist1_dat_i[16] , |
| \wbd_mbist1_dat_i[15] , |
| \wbd_mbist1_dat_i[14] , |
| \wbd_mbist1_dat_i[13] , |
| \wbd_mbist1_dat_i[12] , |
| \wbd_mbist1_dat_i[11] , |
| \wbd_mbist1_dat_i[10] , |
| \wbd_mbist1_dat_i[9] , |
| \wbd_mbist1_dat_i[8] , |
| \wbd_mbist1_dat_i[7] , |
| \wbd_mbist1_dat_i[6] , |
| \wbd_mbist1_dat_i[5] , |
| \wbd_mbist1_dat_i[4] , |
| \wbd_mbist1_dat_i[3] , |
| \wbd_mbist1_dat_i[2] , |
| \wbd_mbist1_dat_i[1] , |
| \wbd_mbist1_dat_i[0] }), |
| .s3_wbd_dat_o({\wbd_mbist1_dat_o[31] , |
| \wbd_mbist1_dat_o[30] , |
| \wbd_mbist1_dat_o[29] , |
| \wbd_mbist1_dat_o[28] , |
| \wbd_mbist1_dat_o[27] , |
| \wbd_mbist1_dat_o[26] , |
| \wbd_mbist1_dat_o[25] , |
| \wbd_mbist1_dat_o[24] , |
| \wbd_mbist1_dat_o[23] , |
| \wbd_mbist1_dat_o[22] , |
| \wbd_mbist1_dat_o[21] , |
| \wbd_mbist1_dat_o[20] , |
| \wbd_mbist1_dat_o[19] , |
| \wbd_mbist1_dat_o[18] , |
| \wbd_mbist1_dat_o[17] , |
| \wbd_mbist1_dat_o[16] , |
| \wbd_mbist1_dat_o[15] , |
| \wbd_mbist1_dat_o[14] , |
| \wbd_mbist1_dat_o[13] , |
| \wbd_mbist1_dat_o[12] , |
| \wbd_mbist1_dat_o[11] , |
| \wbd_mbist1_dat_o[10] , |
| \wbd_mbist1_dat_o[9] , |
| \wbd_mbist1_dat_o[8] , |
| \wbd_mbist1_dat_o[7] , |
| \wbd_mbist1_dat_o[6] , |
| \wbd_mbist1_dat_o[5] , |
| \wbd_mbist1_dat_o[4] , |
| \wbd_mbist1_dat_o[3] , |
| \wbd_mbist1_dat_o[2] , |
| \wbd_mbist1_dat_o[1] , |
| \wbd_mbist1_dat_o[0] }), |
| .s3_wbd_sel_o({\wbd_mbist1_sel_o[3] , |
| \wbd_mbist1_sel_o[2] , |
| \wbd_mbist1_sel_o[1] , |
| \wbd_mbist1_sel_o[0] }), |
| .scan_si({\scan_so_mbist1[7] , |
| \scan_so_mbist1[6] , |
| \scan_so_mbist1[5] , |
| \scan_so_mbist1[4] , |
| \scan_so_mbist1[3] , |
| \scan_so_mbist1[2] , |
| \scan_so_mbist1[1] , |
| \scan_so_mbist1[0] }), |
| .scan_so({\scan_so_wi[7] , |
| \scan_so_wi[6] , |
| \scan_so_wi[5] , |
| \scan_so_wi[4] , |
| \scan_so_wi[3] , |
| \scan_so_wi[2] , |
| \scan_so_wi[1] , |
| \scan_so_wi[0] })); |
| mac_wrapper u_mac_wrap (.app_clk(wbd_clk_mac_skew), |
| .mac_rx_qcnt_dec(mac_rx_qcnt_dec), |
| .mac_rx_qcnt_inc(mac_rx_qcnt_inc), |
| .mac_tx_qcnt_dec(mac_tx_qcnt_dec), |
| .mac_tx_qcnt_inc(mac_tx_qcnt_inc), |
| .mdio_clk(mdio_clk), |
| .mdio_in(mdio_in), |
| .mdio_out(mdio_out), |
| .mdio_out_en(mdio_out_en), |
| .phy_crs(mac_crs), |
| .phy_rx_clk(mac_rx_clk), |
| .phy_rx_dv(mac_rx_dv), |
| .phy_rx_er(mac_rx_er), |
| .phy_tx_clk(mac_tx_clk), |
| .phy_tx_en(mac_tx_en), |
| .phy_tx_er(mac_tx_er), |
| .reset_n(mac_rst_n), |
| .scan_en(scan_en_pinmux), |
| .scan_en_o(scan_en_mac), |
| .scan_mode(scan_mode_pinmux), |
| .scan_mode_o(scan_mode_mac), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .wbd_clk_int(wbd_clk_mac_rp), |
| .wbd_clk_skew(wbd_clk_mac_skew), |
| .wbm_grx_ack_i(wbm_grx_ack_i), |
| .wbm_grx_cyc_o(wbm_grx_cyc_o), |
| .wbm_grx_stb_o(wbm_grx_stb_o), |
| .wbm_grx_we_o(wbm_grx_we_o), |
| .wbm_gtx_ack_i(wbm_gtx_ack_i), |
| .wbm_gtx_cyc_o(wbm_gtx_cyc_o), |
| .wbm_gtx_stb_o(wbm_gtx_stb_o), |
| .wbm_gtx_we_o(wbm_gtx_we_o), |
| .wbs_grg_ack_o(wbs_grg_ack_o), |
| .wbs_grg_cyc_i(wbs_grg_cyc_i), |
| .wbs_grg_stb_i(wbs_grg_stb_i), |
| .wbs_grg_we_i(wbs_grg_we_i), |
| .cfg_cska_mac({\cfg_clk_ctrl1[27] , |
| \cfg_clk_ctrl1[26] , |
| \cfg_clk_ctrl1[25] , |
| \cfg_clk_ctrl1[24] }), |
| .cfg_rx_qbase_addr({\mac_rx_qbase_addr[9] , |
| \mac_rx_qbase_addr[8] , |
| \mac_rx_qbase_addr[7] , |
| \mac_rx_qbase_addr[6] , |
| \mac_rx_qbase_addr[5] , |
| \mac_rx_qbase_addr[4] , |
| \mac_rx_qbase_addr[3] , |
| \mac_rx_qbase_addr[2] , |
| \mac_rx_qbase_addr[1] , |
| \mac_rx_qbase_addr[0] }), |
| .cfg_tx_qbase_addr({\mac_tx_qbase_addr[9] , |
| \mac_tx_qbase_addr[8] , |
| \mac_tx_qbase_addr[7] , |
| \mac_tx_qbase_addr[6] , |
| \mac_tx_qbase_addr[5] , |
| \mac_tx_qbase_addr[4] , |
| \mac_tx_qbase_addr[3] , |
| \mac_tx_qbase_addr[2] , |
| \mac_tx_qbase_addr[1] , |
| \mac_tx_qbase_addr[0] }), |
| .phy_rxd({\mac_rxd[7] , |
| \mac_rxd[6] , |
| \mac_rxd[5] , |
| \mac_rxd[4] , |
| \mac_rxd[3] , |
| \mac_rxd[2] , |
| \mac_rxd[1] , |
| \mac_rxd[0] }), |
| .phy_txd({\mac_txd[7] , |
| \mac_txd[6] , |
| \mac_txd[5] , |
| \mac_txd[4] , |
| \mac_txd[3] , |
| \mac_txd[2] , |
| \mac_txd[1] , |
| \mac_txd[0] }), |
| .scan_si({\scan_so_pinmux[7] , |
| \scan_so_pinmux[6] , |
| \scan_so_pinmux[5] , |
| \scan_so_pinmux[4] , |
| \scan_so_pinmux[3] , |
| \scan_so_pinmux[2] , |
| \scan_so_pinmux[1] , |
| \scan_so_pinmux[0] }), |
| .scan_so({\scan_so_mac[7] , |
| \scan_so_mac[6] , |
| \scan_so_mac[5] , |
| \scan_so_mac[4] , |
| \scan_so_mac[3] , |
| \scan_so_mac[2] , |
| \scan_so_mac[1] , |
| \scan_so_mac[0] }), |
| .wbm_grx_adr_o({\wbm_grx_adr_o[15] , |
| \wbm_grx_adr_o[14] , |
| \wbm_grx_adr_o[13] , |
| \wbm_grx_adr_o[12] , |
| \wbm_grx_adr_o[11] , |
| \wbm_grx_adr_o[10] , |
| \wbm_grx_adr_o[9] , |
| \wbm_grx_adr_o[8] , |
| \wbm_grx_adr_o[7] , |
| \wbm_grx_adr_o[6] , |
| \wbm_grx_adr_o[5] , |
| \wbm_grx_adr_o[4] , |
| \wbm_grx_adr_o[3] , |
| \wbm_grx_adr_o[2] , |
| \wbm_grx_adr_o[1] , |
| \wbm_grx_adr_o[0] }), |
| .wbm_grx_dat_i({\wbm_grx_dat_i[31] , |
| \wbm_grx_dat_i[30] , |
| \wbm_grx_dat_i[29] , |
| \wbm_grx_dat_i[28] , |
| \wbm_grx_dat_i[27] , |
| \wbm_grx_dat_i[26] , |
| \wbm_grx_dat_i[25] , |
| \wbm_grx_dat_i[24] , |
| \wbm_grx_dat_i[23] , |
| \wbm_grx_dat_i[22] , |
| \wbm_grx_dat_i[21] , |
| \wbm_grx_dat_i[20] , |
| \wbm_grx_dat_i[19] , |
| \wbm_grx_dat_i[18] , |
| \wbm_grx_dat_i[17] , |
| \wbm_grx_dat_i[16] , |
| \wbm_grx_dat_i[15] , |
| \wbm_grx_dat_i[14] , |
| \wbm_grx_dat_i[13] , |
| \wbm_grx_dat_i[12] , |
| \wbm_grx_dat_i[11] , |
| \wbm_grx_dat_i[10] , |
| \wbm_grx_dat_i[9] , |
| \wbm_grx_dat_i[8] , |
| \wbm_grx_dat_i[7] , |
| \wbm_grx_dat_i[6] , |
| \wbm_grx_dat_i[5] , |
| \wbm_grx_dat_i[4] , |
| \wbm_grx_dat_i[3] , |
| \wbm_grx_dat_i[2] , |
| \wbm_grx_dat_i[1] , |
| \wbm_grx_dat_i[0] }), |
| .wbm_grx_dat_o({\wbm_grx_dat_o[31] , |
| \wbm_grx_dat_o[30] , |
| \wbm_grx_dat_o[29] , |
| \wbm_grx_dat_o[28] , |
| \wbm_grx_dat_o[27] , |
| \wbm_grx_dat_o[26] , |
| \wbm_grx_dat_o[25] , |
| \wbm_grx_dat_o[24] , |
| \wbm_grx_dat_o[23] , |
| \wbm_grx_dat_o[22] , |
| \wbm_grx_dat_o[21] , |
| \wbm_grx_dat_o[20] , |
| \wbm_grx_dat_o[19] , |
| \wbm_grx_dat_o[18] , |
| \wbm_grx_dat_o[17] , |
| \wbm_grx_dat_o[16] , |
| \wbm_grx_dat_o[15] , |
| \wbm_grx_dat_o[14] , |
| \wbm_grx_dat_o[13] , |
| \wbm_grx_dat_o[12] , |
| \wbm_grx_dat_o[11] , |
| \wbm_grx_dat_o[10] , |
| \wbm_grx_dat_o[9] , |
| \wbm_grx_dat_o[8] , |
| \wbm_grx_dat_o[7] , |
| \wbm_grx_dat_o[6] , |
| \wbm_grx_dat_o[5] , |
| \wbm_grx_dat_o[4] , |
| \wbm_grx_dat_o[3] , |
| \wbm_grx_dat_o[2] , |
| \wbm_grx_dat_o[1] , |
| \wbm_grx_dat_o[0] }), |
| .wbm_grx_sel_o({\wbm_grx_sel_o[3] , |
| \wbm_grx_sel_o[2] , |
| \wbm_grx_sel_o[1] , |
| \wbm_grx_sel_o[0] }), |
| .wbm_gtx_adr_o({\wbm_gtx_adr_o[15] , |
| \wbm_gtx_adr_o[14] , |
| \wbm_gtx_adr_o[13] , |
| \wbm_gtx_adr_o[12] , |
| \wbm_gtx_adr_o[11] , |
| \wbm_gtx_adr_o[10] , |
| \wbm_gtx_adr_o[9] , |
| \wbm_gtx_adr_o[8] , |
| \wbm_gtx_adr_o[7] , |
| \wbm_gtx_adr_o[6] , |
| \wbm_gtx_adr_o[5] , |
| \wbm_gtx_adr_o[4] , |
| \wbm_gtx_adr_o[3] , |
| \wbm_gtx_adr_o[2] , |
| \wbm_gtx_adr_o[1] , |
| \wbm_gtx_adr_o[0] }), |
| .wbm_gtx_dat_i({\wbm_gtx_dat_i[31] , |
| \wbm_gtx_dat_i[30] , |
| \wbm_gtx_dat_i[29] , |
| \wbm_gtx_dat_i[28] , |
| \wbm_gtx_dat_i[27] , |
| \wbm_gtx_dat_i[26] , |
| \wbm_gtx_dat_i[25] , |
| \wbm_gtx_dat_i[24] , |
| \wbm_gtx_dat_i[23] , |
| \wbm_gtx_dat_i[22] , |
| \wbm_gtx_dat_i[21] , |
| \wbm_gtx_dat_i[20] , |
| \wbm_gtx_dat_i[19] , |
| \wbm_gtx_dat_i[18] , |
| \wbm_gtx_dat_i[17] , |
| \wbm_gtx_dat_i[16] , |
| \wbm_gtx_dat_i[15] , |
| \wbm_gtx_dat_i[14] , |
| \wbm_gtx_dat_i[13] , |
| \wbm_gtx_dat_i[12] , |
| \wbm_gtx_dat_i[11] , |
| \wbm_gtx_dat_i[10] , |
| \wbm_gtx_dat_i[9] , |
| \wbm_gtx_dat_i[8] , |
| \wbm_gtx_dat_i[7] , |
| \wbm_gtx_dat_i[6] , |
| \wbm_gtx_dat_i[5] , |
| \wbm_gtx_dat_i[4] , |
| \wbm_gtx_dat_i[3] , |
| \wbm_gtx_dat_i[2] , |
| \wbm_gtx_dat_i[1] , |
| \wbm_gtx_dat_i[0] }), |
| .wbm_gtx_dat_o({\wbm_gtx_dat_o[31] , |
| \wbm_gtx_dat_o[30] , |
| \wbm_gtx_dat_o[29] , |
| \wbm_gtx_dat_o[28] , |
| \wbm_gtx_dat_o[27] , |
| \wbm_gtx_dat_o[26] , |
| \wbm_gtx_dat_o[25] , |
| \wbm_gtx_dat_o[24] , |
| \wbm_gtx_dat_o[23] , |
| \wbm_gtx_dat_o[22] , |
| \wbm_gtx_dat_o[21] , |
| \wbm_gtx_dat_o[20] , |
| \wbm_gtx_dat_o[19] , |
| \wbm_gtx_dat_o[18] , |
| \wbm_gtx_dat_o[17] , |
| \wbm_gtx_dat_o[16] , |
| \wbm_gtx_dat_o[15] , |
| \wbm_gtx_dat_o[14] , |
| \wbm_gtx_dat_o[13] , |
| \wbm_gtx_dat_o[12] , |
| \wbm_gtx_dat_o[11] , |
| \wbm_gtx_dat_o[10] , |
| \wbm_gtx_dat_o[9] , |
| \wbm_gtx_dat_o[8] , |
| \wbm_gtx_dat_o[7] , |
| \wbm_gtx_dat_o[6] , |
| \wbm_gtx_dat_o[5] , |
| \wbm_gtx_dat_o[4] , |
| \wbm_gtx_dat_o[3] , |
| \wbm_gtx_dat_o[2] , |
| \wbm_gtx_dat_o[1] , |
| \wbm_gtx_dat_o[0] }), |
| .wbm_gtx_sel_o({\wbm_gtx_sel_o[3] , |
| \wbm_gtx_sel_o[2] , |
| \wbm_gtx_sel_o[1] , |
| \wbm_gtx_sel_o[0] }), |
| .wbs_grg_adr_i({\wbs_grg_adr_i[12] , |
| \wbs_grg_adr_i[11] , |
| \wbs_grg_adr_i[10] , |
| \wbs_grg_adr_i[9] , |
| \wbs_grg_adr_i[8] , |
| \wbs_grg_adr_i[7] , |
| \wbs_grg_adr_i[6] , |
| \wbs_grg_adr_i[5] , |
| \wbs_grg_adr_i[4] , |
| \wbs_grg_adr_i[3] , |
| \wbs_grg_adr_i[2] , |
| \wbs_grg_adr_i[1] , |
| \wbs_grg_adr_i[0] }), |
| .wbs_grg_dat_i({\wbs_grg_dat_i[31] , |
| \wbs_grg_dat_i[30] , |
| \wbs_grg_dat_i[29] , |
| \wbs_grg_dat_i[28] , |
| \wbs_grg_dat_i[27] , |
| \wbs_grg_dat_i[26] , |
| \wbs_grg_dat_i[25] , |
| \wbs_grg_dat_i[24] , |
| \wbs_grg_dat_i[23] , |
| \wbs_grg_dat_i[22] , |
| \wbs_grg_dat_i[21] , |
| \wbs_grg_dat_i[20] , |
| \wbs_grg_dat_i[19] , |
| \wbs_grg_dat_i[18] , |
| \wbs_grg_dat_i[17] , |
| \wbs_grg_dat_i[16] , |
| \wbs_grg_dat_i[15] , |
| \wbs_grg_dat_i[14] , |
| \wbs_grg_dat_i[13] , |
| \wbs_grg_dat_i[12] , |
| \wbs_grg_dat_i[11] , |
| \wbs_grg_dat_i[10] , |
| \wbs_grg_dat_i[9] , |
| \wbs_grg_dat_i[8] , |
| \wbs_grg_dat_i[7] , |
| \wbs_grg_dat_i[6] , |
| \wbs_grg_dat_i[5] , |
| \wbs_grg_dat_i[4] , |
| \wbs_grg_dat_i[3] , |
| \wbs_grg_dat_i[2] , |
| \wbs_grg_dat_i[1] , |
| \wbs_grg_dat_i[0] }), |
| .wbs_grg_dat_o({\wbs_grg_dat_o[31] , |
| \wbs_grg_dat_o[30] , |
| \wbs_grg_dat_o[29] , |
| \wbs_grg_dat_o[28] , |
| \wbs_grg_dat_o[27] , |
| \wbs_grg_dat_o[26] , |
| \wbs_grg_dat_o[25] , |
| \wbs_grg_dat_o[24] , |
| \wbs_grg_dat_o[23] , |
| \wbs_grg_dat_o[22] , |
| \wbs_grg_dat_o[21] , |
| \wbs_grg_dat_o[20] , |
| \wbs_grg_dat_o[19] , |
| \wbs_grg_dat_o[18] , |
| \wbs_grg_dat_o[17] , |
| \wbs_grg_dat_o[16] , |
| \wbs_grg_dat_o[15] , |
| \wbs_grg_dat_o[14] , |
| \wbs_grg_dat_o[13] , |
| \wbs_grg_dat_o[12] , |
| \wbs_grg_dat_o[11] , |
| \wbs_grg_dat_o[10] , |
| \wbs_grg_dat_o[9] , |
| \wbs_grg_dat_o[8] , |
| \wbs_grg_dat_o[7] , |
| \wbs_grg_dat_o[6] , |
| \wbs_grg_dat_o[5] , |
| \wbs_grg_dat_o[4] , |
| \wbs_grg_dat_o[3] , |
| \wbs_grg_dat_o[2] , |
| \wbs_grg_dat_o[1] , |
| \wbs_grg_dat_o[0] }), |
| .wbs_grg_sel_i({\wbs_grg_sel_i[3] , |
| \wbs_grg_sel_i[2] , |
| \wbs_grg_sel_i[1] , |
| \wbs_grg_sel_i[0] })); |
| mbist_wrapper u_mbist0 (.rst_n(bist_rst_n), |
| .scan_en(scan_en), |
| .scan_en_o(scan_en_mbist0), |
| .scan_mode(scan_mode), |
| .scan_mode_o(scan_mode_mbist0), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .wb_ack_o(wbd_mbist0_ack_i), |
| .wb_bry_i(wbd_mbist0_bry_o), |
| .wb_clk2_i(wbd_clk_mbist0_skew), |
| .wb_clk_i(wbd_clk_mbist0_skew), |
| .wb_cyc_i(wbd_mbist0_cyc_o), |
| .wb_stb_i(wbd_mbist0_stb_o), |
| .wb_we_i(wbd_mbist0_we_o), |
| .wbd_clk_int(wbd_clk_mbist0_rp), |
| .wbd_clk_skew(wbd_clk_mbist0_skew), |
| .cfg_cska_mbist({\cfg_clk_ctrl1[19] , |
| \cfg_clk_ctrl1[18] , |
| \cfg_clk_ctrl1[17] , |
| \cfg_clk_ctrl1[16] }), |
| .mem_addr_a0({\mem0_addr_a[8] , |
| \mem0_addr_a[7] , |
| \mem0_addr_a[6] , |
| \mem0_addr_a[5] , |
| \mem0_addr_a[4] , |
| \mem0_addr_a[3] , |
| \mem0_addr_a[2] , |
| \mem0_addr_a[1] , |
| \mem0_addr_a[0] }), |
| .mem_addr_a1({\mem1_addr_a[8] , |
| \mem1_addr_a[7] , |
| \mem1_addr_a[6] , |
| \mem1_addr_a[5] , |
| \mem1_addr_a[4] , |
| \mem1_addr_a[3] , |
| \mem1_addr_a[2] , |
| \mem1_addr_a[1] , |
| \mem1_addr_a[0] }), |
| .mem_addr_a2({\mem2_addr_a[8] , |
| \mem2_addr_a[7] , |
| \mem2_addr_a[6] , |
| \mem2_addr_a[5] , |
| \mem2_addr_a[4] , |
| \mem2_addr_a[3] , |
| \mem2_addr_a[2] , |
| \mem2_addr_a[1] , |
| \mem2_addr_a[0] }), |
| .mem_addr_a3({\mem3_addr_a[8] , |
| \mem3_addr_a[7] , |
| \mem3_addr_a[6] , |
| \mem3_addr_a[5] , |
| \mem3_addr_a[4] , |
| \mem3_addr_a[3] , |
| \mem3_addr_a[2] , |
| \mem3_addr_a[1] , |
| \mem3_addr_a[0] }), |
| .mem_addr_b0({\mem0_addr_b[8] , |
| \mem0_addr_b[7] , |
| \mem0_addr_b[6] , |
| \mem0_addr_b[5] , |
| \mem0_addr_b[4] , |
| \mem0_addr_b[3] , |
| \mem0_addr_b[2] , |
| \mem0_addr_b[1] , |
| \mem0_addr_b[0] }), |
| .mem_addr_b1({\mem1_addr_b[8] , |
| \mem1_addr_b[7] , |
| \mem1_addr_b[6] , |
| \mem1_addr_b[5] , |
| \mem1_addr_b[4] , |
| \mem1_addr_b[3] , |
| \mem1_addr_b[2] , |
| \mem1_addr_b[1] , |
| \mem1_addr_b[0] }), |
| .mem_addr_b2({\mem2_addr_b[8] , |
| \mem2_addr_b[7] , |
| \mem2_addr_b[6] , |
| \mem2_addr_b[5] , |
| \mem2_addr_b[4] , |
| \mem2_addr_b[3] , |
| \mem2_addr_b[2] , |
| \mem2_addr_b[1] , |
| \mem2_addr_b[0] }), |
| .mem_addr_b3({\mem3_addr_b[8] , |
| \mem3_addr_b[7] , |
| \mem3_addr_b[6] , |
| \mem3_addr_b[5] , |
| \mem3_addr_b[4] , |
| \mem3_addr_b[3] , |
| \mem3_addr_b[2] , |
| \mem3_addr_b[1] , |
| \mem3_addr_b[0] }), |
| .mem_cen_a({\mem_cen_a[3] , |
| \mem_cen_a[2] , |
| \mem_cen_a[1] , |
| \mem_cen_a[0] }), |
| .mem_cen_b({\mem_cen_b[3] , |
| \mem_cen_b[2] , |
| \mem_cen_b[1] , |
| \mem_cen_b[0] }), |
| .mem_clk_a({\mem_clk_a[3] , |
| \mem_clk_a[2] , |
| \mem_clk_a[1] , |
| \mem_clk_a[0] }), |
| .mem_clk_b({\mem_clk_b[3] , |
| \mem_clk_b[2] , |
| \mem_clk_b[1] , |
| \mem_clk_b[0] }), |
| .mem_din_a0({\mem0_din_a[31] , |
| \mem0_din_a[30] , |
| \mem0_din_a[29] , |
| \mem0_din_a[28] , |
| \mem0_din_a[27] , |
| \mem0_din_a[26] , |
| \mem0_din_a[25] , |
| \mem0_din_a[24] , |
| \mem0_din_a[23] , |
| \mem0_din_a[22] , |
| \mem0_din_a[21] , |
| \mem0_din_a[20] , |
| \mem0_din_a[19] , |
| \mem0_din_a[18] , |
| \mem0_din_a[17] , |
| \mem0_din_a[16] , |
| \mem0_din_a[15] , |
| \mem0_din_a[14] , |
| \mem0_din_a[13] , |
| \mem0_din_a[12] , |
| \mem0_din_a[11] , |
| \mem0_din_a[10] , |
| \mem0_din_a[9] , |
| \mem0_din_a[8] , |
| \mem0_din_a[7] , |
| \mem0_din_a[6] , |
| \mem0_din_a[5] , |
| \mem0_din_a[4] , |
| \mem0_din_a[3] , |
| \mem0_din_a[2] , |
| \mem0_din_a[1] , |
| \mem0_din_a[0] }), |
| .mem_din_a1({\mem1_din_a[31] , |
| \mem1_din_a[30] , |
| \mem1_din_a[29] , |
| \mem1_din_a[28] , |
| \mem1_din_a[27] , |
| \mem1_din_a[26] , |
| \mem1_din_a[25] , |
| \mem1_din_a[24] , |
| \mem1_din_a[23] , |
| \mem1_din_a[22] , |
| \mem1_din_a[21] , |
| \mem1_din_a[20] , |
| \mem1_din_a[19] , |
| \mem1_din_a[18] , |
| \mem1_din_a[17] , |
| \mem1_din_a[16] , |
| \mem1_din_a[15] , |
| \mem1_din_a[14] , |
| \mem1_din_a[13] , |
| \mem1_din_a[12] , |
| \mem1_din_a[11] , |
| \mem1_din_a[10] , |
| \mem1_din_a[9] , |
| \mem1_din_a[8] , |
| \mem1_din_a[7] , |
| \mem1_din_a[6] , |
| \mem1_din_a[5] , |
| \mem1_din_a[4] , |
| \mem1_din_a[3] , |
| \mem1_din_a[2] , |
| \mem1_din_a[1] , |
| \mem1_din_a[0] }), |
| .mem_din_a2({\mem2_din_a[31] , |
| \mem2_din_a[30] , |
| \mem2_din_a[29] , |
| \mem2_din_a[28] , |
| \mem2_din_a[27] , |
| \mem2_din_a[26] , |
| \mem2_din_a[25] , |
| \mem2_din_a[24] , |
| \mem2_din_a[23] , |
| \mem2_din_a[22] , |
| \mem2_din_a[21] , |
| \mem2_din_a[20] , |
| \mem2_din_a[19] , |
| \mem2_din_a[18] , |
| \mem2_din_a[17] , |
| \mem2_din_a[16] , |
| \mem2_din_a[15] , |
| \mem2_din_a[14] , |
| \mem2_din_a[13] , |
| \mem2_din_a[12] , |
| \mem2_din_a[11] , |
| \mem2_din_a[10] , |
| \mem2_din_a[9] , |
| \mem2_din_a[8] , |
| \mem2_din_a[7] , |
| \mem2_din_a[6] , |
| \mem2_din_a[5] , |
| \mem2_din_a[4] , |
| \mem2_din_a[3] , |
| \mem2_din_a[2] , |
| \mem2_din_a[1] , |
| \mem2_din_a[0] }), |
| .mem_din_a3({\mem3_din_a[31] , |
| \mem3_din_a[30] , |
| \mem3_din_a[29] , |
| \mem3_din_a[28] , |
| \mem3_din_a[27] , |
| \mem3_din_a[26] , |
| \mem3_din_a[25] , |
| \mem3_din_a[24] , |
| \mem3_din_a[23] , |
| \mem3_din_a[22] , |
| \mem3_din_a[21] , |
| \mem3_din_a[20] , |
| \mem3_din_a[19] , |
| \mem3_din_a[18] , |
| \mem3_din_a[17] , |
| \mem3_din_a[16] , |
| \mem3_din_a[15] , |
| \mem3_din_a[14] , |
| \mem3_din_a[13] , |
| \mem3_din_a[12] , |
| \mem3_din_a[11] , |
| \mem3_din_a[10] , |
| \mem3_din_a[9] , |
| \mem3_din_a[8] , |
| \mem3_din_a[7] , |
| \mem3_din_a[6] , |
| \mem3_din_a[5] , |
| \mem3_din_a[4] , |
| \mem3_din_a[3] , |
| \mem3_din_a[2] , |
| \mem3_din_a[1] , |
| \mem3_din_a[0] }), |
| .mem_dout_a0({\mem0_dout_a[31] , |
| \mem0_dout_a[30] , |
| \mem0_dout_a[29] , |
| \mem0_dout_a[28] , |
| \mem0_dout_a[27] , |
| \mem0_dout_a[26] , |
| \mem0_dout_a[25] , |
| \mem0_dout_a[24] , |
| \mem0_dout_a[23] , |
| \mem0_dout_a[22] , |
| \mem0_dout_a[21] , |
| \mem0_dout_a[20] , |
| \mem0_dout_a[19] , |
| \mem0_dout_a[18] , |
| \mem0_dout_a[17] , |
| \mem0_dout_a[16] , |
| \mem0_dout_a[15] , |
| \mem0_dout_a[14] , |
| \mem0_dout_a[13] , |
| \mem0_dout_a[12] , |
| \mem0_dout_a[11] , |
| \mem0_dout_a[10] , |
| \mem0_dout_a[9] , |
| \mem0_dout_a[8] , |
| \mem0_dout_a[7] , |
| \mem0_dout_a[6] , |
| \mem0_dout_a[5] , |
| \mem0_dout_a[4] , |
| \mem0_dout_a[3] , |
| \mem0_dout_a[2] , |
| \mem0_dout_a[1] , |
| \mem0_dout_a[0] }), |
| .mem_dout_a1({\mem1_dout_a[31] , |
| \mem1_dout_a[30] , |
| \mem1_dout_a[29] , |
| \mem1_dout_a[28] , |
| \mem1_dout_a[27] , |
| \mem1_dout_a[26] , |
| \mem1_dout_a[25] , |
| \mem1_dout_a[24] , |
| \mem1_dout_a[23] , |
| \mem1_dout_a[22] , |
| \mem1_dout_a[21] , |
| \mem1_dout_a[20] , |
| \mem1_dout_a[19] , |
| \mem1_dout_a[18] , |
| \mem1_dout_a[17] , |
| \mem1_dout_a[16] , |
| \mem1_dout_a[15] , |
| \mem1_dout_a[14] , |
| \mem1_dout_a[13] , |
| \mem1_dout_a[12] , |
| \mem1_dout_a[11] , |
| \mem1_dout_a[10] , |
| \mem1_dout_a[9] , |
| \mem1_dout_a[8] , |
| \mem1_dout_a[7] , |
| \mem1_dout_a[6] , |
| \mem1_dout_a[5] , |
| \mem1_dout_a[4] , |
| \mem1_dout_a[3] , |
| \mem1_dout_a[2] , |
| \mem1_dout_a[1] , |
| \mem1_dout_a[0] }), |
| .mem_dout_a2({\mem2_dout_a[31] , |
| \mem2_dout_a[30] , |
| \mem2_dout_a[29] , |
| \mem2_dout_a[28] , |
| \mem2_dout_a[27] , |
| \mem2_dout_a[26] , |
| \mem2_dout_a[25] , |
| \mem2_dout_a[24] , |
| \mem2_dout_a[23] , |
| \mem2_dout_a[22] , |
| \mem2_dout_a[21] , |
| \mem2_dout_a[20] , |
| \mem2_dout_a[19] , |
| \mem2_dout_a[18] , |
| \mem2_dout_a[17] , |
| \mem2_dout_a[16] , |
| \mem2_dout_a[15] , |
| \mem2_dout_a[14] , |
| \mem2_dout_a[13] , |
| \mem2_dout_a[12] , |
| \mem2_dout_a[11] , |
| \mem2_dout_a[10] , |
| \mem2_dout_a[9] , |
| \mem2_dout_a[8] , |
| \mem2_dout_a[7] , |
| \mem2_dout_a[6] , |
| \mem2_dout_a[5] , |
| \mem2_dout_a[4] , |
| \mem2_dout_a[3] , |
| \mem2_dout_a[2] , |
| \mem2_dout_a[1] , |
| \mem2_dout_a[0] }), |
| .mem_dout_a3({\mem3_dout_a[31] , |
| \mem3_dout_a[30] , |
| \mem3_dout_a[29] , |
| \mem3_dout_a[28] , |
| \mem3_dout_a[27] , |
| \mem3_dout_a[26] , |
| \mem3_dout_a[25] , |
| \mem3_dout_a[24] , |
| \mem3_dout_a[23] , |
| \mem3_dout_a[22] , |
| \mem3_dout_a[21] , |
| \mem3_dout_a[20] , |
| \mem3_dout_a[19] , |
| \mem3_dout_a[18] , |
| \mem3_dout_a[17] , |
| \mem3_dout_a[16] , |
| \mem3_dout_a[15] , |
| \mem3_dout_a[14] , |
| \mem3_dout_a[13] , |
| \mem3_dout_a[12] , |
| \mem3_dout_a[11] , |
| \mem3_dout_a[10] , |
| \mem3_dout_a[9] , |
| \mem3_dout_a[8] , |
| \mem3_dout_a[7] , |
| \mem3_dout_a[6] , |
| \mem3_dout_a[5] , |
| \mem3_dout_a[4] , |
| \mem3_dout_a[3] , |
| \mem3_dout_a[2] , |
| \mem3_dout_a[1] , |
| \mem3_dout_a[0] }), |
| .mem_mask_a0({\mem0_mask_a[3] , |
| \mem0_mask_a[2] , |
| \mem0_mask_a[1] , |
| \mem0_mask_a[0] }), |
| .mem_mask_a1({\mem1_mask_a[3] , |
| \mem1_mask_a[2] , |
| \mem1_mask_a[1] , |
| \mem1_mask_a[0] }), |
| .mem_mask_a2({\mem2_mask_a[3] , |
| \mem2_mask_a[2] , |
| \mem2_mask_a[1] , |
| \mem2_mask_a[0] }), |
| .mem_mask_a3({\mem3_mask_a[3] , |
| \mem3_mask_a[2] , |
| \mem3_mask_a[1] , |
| \mem3_mask_a[0] }), |
| .mem_web_a({\mem_web_a[3] , |
| \mem_web_a[2] , |
| \mem_web_a[1] , |
| \mem_web_a[0] }), |
| .scan_si({\scan_in[7] , |
| \scan_in[6] , |
| \scan_in[5] , |
| \scan_in[4] , |
| \scan_in[3] , |
| \scan_in[2] , |
| \scan_in[1] , |
| \scan_in[0] }), |
| .scan_so({\scan_so_mbist0[7] , |
| \scan_so_mbist0[6] , |
| \scan_so_mbist0[5] , |
| \scan_so_mbist0[4] , |
| \scan_so_mbist0[3] , |
| \scan_so_mbist0[2] , |
| \scan_so_mbist0[1] , |
| \scan_so_mbist0[0] }), |
| .wb_adr_i({\wbd_mbist0_adr_o[14] , |
| \wbd_mbist0_adr_o[13] , |
| \wbd_mbist0_adr_o[12] , |
| \wbd_mbist0_adr_o[11] , |
| \wbd_mbist0_adr_o[10] , |
| \wbd_mbist0_adr_o[9] , |
| \wbd_mbist0_adr_o[8] , |
| \wbd_mbist0_adr_o[7] , |
| \wbd_mbist0_adr_o[6] , |
| \wbd_mbist0_adr_o[5] , |
| \wbd_mbist0_adr_o[4] , |
| \wbd_mbist0_adr_o[3] , |
| \wbd_mbist0_adr_o[2] , |
| \wbd_mbist0_adr_o[1] , |
| \wbd_mbist0_adr_o[0] }), |
| .wb_bl_i({\wbd_mbist0_bl_o[9] , |
| \wbd_mbist0_bl_o[8] , |
| \wbd_mbist0_bl_o[7] , |
| \wbd_mbist0_bl_o[6] , |
| \wbd_mbist0_bl_o[5] , |
| \wbd_mbist0_bl_o[4] , |
| \wbd_mbist0_bl_o[3] , |
| \wbd_mbist0_bl_o[2] , |
| \wbd_mbist0_bl_o[1] , |
| \wbd_mbist0_bl_o[0] }), |
| .wb_dat_i({\wbd_mbist0_dat_o[31] , |
| \wbd_mbist0_dat_o[30] , |
| \wbd_mbist0_dat_o[29] , |
| \wbd_mbist0_dat_o[28] , |
| \wbd_mbist0_dat_o[27] , |
| \wbd_mbist0_dat_o[26] , |
| \wbd_mbist0_dat_o[25] , |
| \wbd_mbist0_dat_o[24] , |
| \wbd_mbist0_dat_o[23] , |
| \wbd_mbist0_dat_o[22] , |
| \wbd_mbist0_dat_o[21] , |
| \wbd_mbist0_dat_o[20] , |
| \wbd_mbist0_dat_o[19] , |
| \wbd_mbist0_dat_o[18] , |
| \wbd_mbist0_dat_o[17] , |
| \wbd_mbist0_dat_o[16] , |
| \wbd_mbist0_dat_o[15] , |
| \wbd_mbist0_dat_o[14] , |
| \wbd_mbist0_dat_o[13] , |
| \wbd_mbist0_dat_o[12] , |
| \wbd_mbist0_dat_o[11] , |
| \wbd_mbist0_dat_o[10] , |
| \wbd_mbist0_dat_o[9] , |
| \wbd_mbist0_dat_o[8] , |
| \wbd_mbist0_dat_o[7] , |
| \wbd_mbist0_dat_o[6] , |
| \wbd_mbist0_dat_o[5] , |
| \wbd_mbist0_dat_o[4] , |
| \wbd_mbist0_dat_o[3] , |
| \wbd_mbist0_dat_o[2] , |
| \wbd_mbist0_dat_o[1] , |
| \wbd_mbist0_dat_o[0] }), |
| .wb_dat_o({\wbd_mbist0_dat_i[31] , |
| \wbd_mbist0_dat_i[30] , |
| \wbd_mbist0_dat_i[29] , |
| \wbd_mbist0_dat_i[28] , |
| \wbd_mbist0_dat_i[27] , |
| \wbd_mbist0_dat_i[26] , |
| \wbd_mbist0_dat_i[25] , |
| \wbd_mbist0_dat_i[24] , |
| \wbd_mbist0_dat_i[23] , |
| \wbd_mbist0_dat_i[22] , |
| \wbd_mbist0_dat_i[21] , |
| \wbd_mbist0_dat_i[20] , |
| \wbd_mbist0_dat_i[19] , |
| \wbd_mbist0_dat_i[18] , |
| \wbd_mbist0_dat_i[17] , |
| \wbd_mbist0_dat_i[16] , |
| \wbd_mbist0_dat_i[15] , |
| \wbd_mbist0_dat_i[14] , |
| \wbd_mbist0_dat_i[13] , |
| \wbd_mbist0_dat_i[12] , |
| \wbd_mbist0_dat_i[11] , |
| \wbd_mbist0_dat_i[10] , |
| \wbd_mbist0_dat_i[9] , |
| \wbd_mbist0_dat_i[8] , |
| \wbd_mbist0_dat_i[7] , |
| \wbd_mbist0_dat_i[6] , |
| \wbd_mbist0_dat_i[5] , |
| \wbd_mbist0_dat_i[4] , |
| \wbd_mbist0_dat_i[3] , |
| \wbd_mbist0_dat_i[2] , |
| \wbd_mbist0_dat_i[1] , |
| \wbd_mbist0_dat_i[0] }), |
| .wb_sel_i({\wbd_mbist0_sel_o[3] , |
| \wbd_mbist0_sel_o[2] , |
| \wbd_mbist0_sel_o[1] , |
| \wbd_mbist0_sel_o[0] })); |
| mbist_wrapper u_mbist1 (.rst_n(bist_rst_n), |
| .scan_en(scan_en_mbist0), |
| .scan_en_o(scan_en_mbist1), |
| .scan_mode(scan_mode_mbist0), |
| .scan_mode_o(scan_mode_mbist1), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .wb_ack_o(wbd_mbist1_ack_i), |
| .wb_bry_i(wbd_mbist1_bry_o), |
| .wb_clk2_i(wbd_clk_mbist1_skew), |
| .wb_clk_i(wbd_clk_mbist1_skew), |
| .wb_cyc_i(wbd_mbist1_cyc_o), |
| .wb_stb_i(wbd_mbist1_stb_o), |
| .wb_we_i(wbd_mbist1_we_o), |
| .wbd_clk_int(wbd_clk_mbist1_rp), |
| .wbd_clk_skew(wbd_clk_mbist1_skew), |
| .cfg_cska_mbist({\cfg_clk_ctrl1[23] , |
| \cfg_clk_ctrl1[22] , |
| \cfg_clk_ctrl1[21] , |
| \cfg_clk_ctrl1[20] }), |
| .mem_addr_a0({\mem4_addr_a[8] , |
| \mem4_addr_a[7] , |
| \mem4_addr_a[6] , |
| \mem4_addr_a[5] , |
| \mem4_addr_a[4] , |
| \mem4_addr_a[3] , |
| \mem4_addr_a[2] , |
| \mem4_addr_a[1] , |
| \mem4_addr_a[0] }), |
| .mem_addr_a1({\mem5_addr_a[8] , |
| \mem5_addr_a[7] , |
| \mem5_addr_a[6] , |
| \mem5_addr_a[5] , |
| \mem5_addr_a[4] , |
| \mem5_addr_a[3] , |
| \mem5_addr_a[2] , |
| \mem5_addr_a[1] , |
| \mem5_addr_a[0] }), |
| .mem_addr_a2({\mem6_addr_a[8] , |
| \mem6_addr_a[7] , |
| \mem6_addr_a[6] , |
| \mem6_addr_a[5] , |
| \mem6_addr_a[4] , |
| \mem6_addr_a[3] , |
| \mem6_addr_a[2] , |
| \mem6_addr_a[1] , |
| \mem6_addr_a[0] }), |
| .mem_addr_a3({\mem7_addr_a[8] , |
| \mem7_addr_a[7] , |
| \mem7_addr_a[6] , |
| \mem7_addr_a[5] , |
| \mem7_addr_a[4] , |
| \mem7_addr_a[3] , |
| \mem7_addr_a[2] , |
| \mem7_addr_a[1] , |
| \mem7_addr_a[0] }), |
| .mem_addr_b0({\mem4_addr_b[8] , |
| \mem4_addr_b[7] , |
| \mem4_addr_b[6] , |
| \mem4_addr_b[5] , |
| \mem4_addr_b[4] , |
| \mem4_addr_b[3] , |
| \mem4_addr_b[2] , |
| \mem4_addr_b[1] , |
| \mem4_addr_b[0] }), |
| .mem_addr_b1({\mem5_addr_b[8] , |
| \mem5_addr_b[7] , |
| \mem5_addr_b[6] , |
| \mem5_addr_b[5] , |
| \mem5_addr_b[4] , |
| \mem5_addr_b[3] , |
| \mem5_addr_b[2] , |
| \mem5_addr_b[1] , |
| \mem5_addr_b[0] }), |
| .mem_addr_b2({\mem6_addr_b[8] , |
| \mem6_addr_b[7] , |
| \mem6_addr_b[6] , |
| \mem6_addr_b[5] , |
| \mem6_addr_b[4] , |
| \mem6_addr_b[3] , |
| \mem6_addr_b[2] , |
| \mem6_addr_b[1] , |
| \mem6_addr_b[0] }), |
| .mem_addr_b3({\mem7_addr_b[8] , |
| \mem7_addr_b[7] , |
| \mem7_addr_b[6] , |
| \mem7_addr_b[5] , |
| \mem7_addr_b[4] , |
| \mem7_addr_b[3] , |
| \mem7_addr_b[2] , |
| \mem7_addr_b[1] , |
| \mem7_addr_b[0] }), |
| .mem_cen_a({\mem_cen_a[7] , |
| \mem_cen_a[6] , |
| \mem_cen_a[5] , |
| \mem_cen_a[4] }), |
| .mem_cen_b({\mem_cen_b[7] , |
| \mem_cen_b[6] , |
| \mem_cen_b[5] , |
| \mem_cen_b[4] }), |
| .mem_clk_a({\mem_clk_a[7] , |
| \mem_clk_a[6] , |
| \mem_clk_a[5] , |
| \mem_clk_a[4] }), |
| .mem_clk_b({\mem_clk_b[7] , |
| \mem_clk_b[6] , |
| \mem_clk_b[5] , |
| \mem_clk_b[4] }), |
| .mem_din_a0({\mem4_din_a[31] , |
| \mem4_din_a[30] , |
| \mem4_din_a[29] , |
| \mem4_din_a[28] , |
| \mem4_din_a[27] , |
| \mem4_din_a[26] , |
| \mem4_din_a[25] , |
| \mem4_din_a[24] , |
| \mem4_din_a[23] , |
| \mem4_din_a[22] , |
| \mem4_din_a[21] , |
| \mem4_din_a[20] , |
| \mem4_din_a[19] , |
| \mem4_din_a[18] , |
| \mem4_din_a[17] , |
| \mem4_din_a[16] , |
| \mem4_din_a[15] , |
| \mem4_din_a[14] , |
| \mem4_din_a[13] , |
| \mem4_din_a[12] , |
| \mem4_din_a[11] , |
| \mem4_din_a[10] , |
| \mem4_din_a[9] , |
| \mem4_din_a[8] , |
| \mem4_din_a[7] , |
| \mem4_din_a[6] , |
| \mem4_din_a[5] , |
| \mem4_din_a[4] , |
| \mem4_din_a[3] , |
| \mem4_din_a[2] , |
| \mem4_din_a[1] , |
| \mem4_din_a[0] }), |
| .mem_din_a1({\mem5_din_a[31] , |
| \mem5_din_a[30] , |
| \mem5_din_a[29] , |
| \mem5_din_a[28] , |
| \mem5_din_a[27] , |
| \mem5_din_a[26] , |
| \mem5_din_a[25] , |
| \mem5_din_a[24] , |
| \mem5_din_a[23] , |
| \mem5_din_a[22] , |
| \mem5_din_a[21] , |
| \mem5_din_a[20] , |
| \mem5_din_a[19] , |
| \mem5_din_a[18] , |
| \mem5_din_a[17] , |
| \mem5_din_a[16] , |
| \mem5_din_a[15] , |
| \mem5_din_a[14] , |
| \mem5_din_a[13] , |
| \mem5_din_a[12] , |
| \mem5_din_a[11] , |
| \mem5_din_a[10] , |
| \mem5_din_a[9] , |
| \mem5_din_a[8] , |
| \mem5_din_a[7] , |
| \mem5_din_a[6] , |
| \mem5_din_a[5] , |
| \mem5_din_a[4] , |
| \mem5_din_a[3] , |
| \mem5_din_a[2] , |
| \mem5_din_a[1] , |
| \mem5_din_a[0] }), |
| .mem_din_a2({\mem6_din_a[31] , |
| \mem6_din_a[30] , |
| \mem6_din_a[29] , |
| \mem6_din_a[28] , |
| \mem6_din_a[27] , |
| \mem6_din_a[26] , |
| \mem6_din_a[25] , |
| \mem6_din_a[24] , |
| \mem6_din_a[23] , |
| \mem6_din_a[22] , |
| \mem6_din_a[21] , |
| \mem6_din_a[20] , |
| \mem6_din_a[19] , |
| \mem6_din_a[18] , |
| \mem6_din_a[17] , |
| \mem6_din_a[16] , |
| \mem6_din_a[15] , |
| \mem6_din_a[14] , |
| \mem6_din_a[13] , |
| \mem6_din_a[12] , |
| \mem6_din_a[11] , |
| \mem6_din_a[10] , |
| \mem6_din_a[9] , |
| \mem6_din_a[8] , |
| \mem6_din_a[7] , |
| \mem6_din_a[6] , |
| \mem6_din_a[5] , |
| \mem6_din_a[4] , |
| \mem6_din_a[3] , |
| \mem6_din_a[2] , |
| \mem6_din_a[1] , |
| \mem6_din_a[0] }), |
| .mem_din_a3({\mem7_din_a[31] , |
| \mem7_din_a[30] , |
| \mem7_din_a[29] , |
| \mem7_din_a[28] , |
| \mem7_din_a[27] , |
| \mem7_din_a[26] , |
| \mem7_din_a[25] , |
| \mem7_din_a[24] , |
| \mem7_din_a[23] , |
| \mem7_din_a[22] , |
| \mem7_din_a[21] , |
| \mem7_din_a[20] , |
| \mem7_din_a[19] , |
| \mem7_din_a[18] , |
| \mem7_din_a[17] , |
| \mem7_din_a[16] , |
| \mem7_din_a[15] , |
| \mem7_din_a[14] , |
| \mem7_din_a[13] , |
| \mem7_din_a[12] , |
| \mem7_din_a[11] , |
| \mem7_din_a[10] , |
| \mem7_din_a[9] , |
| \mem7_din_a[8] , |
| \mem7_din_a[7] , |
| \mem7_din_a[6] , |
| \mem7_din_a[5] , |
| \mem7_din_a[4] , |
| \mem7_din_a[3] , |
| \mem7_din_a[2] , |
| \mem7_din_a[1] , |
| \mem7_din_a[0] }), |
| .mem_dout_a0({\mem4_dout_a[31] , |
| \mem4_dout_a[30] , |
| \mem4_dout_a[29] , |
| \mem4_dout_a[28] , |
| \mem4_dout_a[27] , |
| \mem4_dout_a[26] , |
| \mem4_dout_a[25] , |
| \mem4_dout_a[24] , |
| \mem4_dout_a[23] , |
| \mem4_dout_a[22] , |
| \mem4_dout_a[21] , |
| \mem4_dout_a[20] , |
| \mem4_dout_a[19] , |
| \mem4_dout_a[18] , |
| \mem4_dout_a[17] , |
| \mem4_dout_a[16] , |
| \mem4_dout_a[15] , |
| \mem4_dout_a[14] , |
| \mem4_dout_a[13] , |
| \mem4_dout_a[12] , |
| \mem4_dout_a[11] , |
| \mem4_dout_a[10] , |
| \mem4_dout_a[9] , |
| \mem4_dout_a[8] , |
| \mem4_dout_a[7] , |
| \mem4_dout_a[6] , |
| \mem4_dout_a[5] , |
| \mem4_dout_a[4] , |
| \mem4_dout_a[3] , |
| \mem4_dout_a[2] , |
| \mem4_dout_a[1] , |
| \mem4_dout_a[0] }), |
| .mem_dout_a1({\mem5_dout_a[31] , |
| \mem5_dout_a[30] , |
| \mem5_dout_a[29] , |
| \mem5_dout_a[28] , |
| \mem5_dout_a[27] , |
| \mem5_dout_a[26] , |
| \mem5_dout_a[25] , |
| \mem5_dout_a[24] , |
| \mem5_dout_a[23] , |
| \mem5_dout_a[22] , |
| \mem5_dout_a[21] , |
| \mem5_dout_a[20] , |
| \mem5_dout_a[19] , |
| \mem5_dout_a[18] , |
| \mem5_dout_a[17] , |
| \mem5_dout_a[16] , |
| \mem5_dout_a[15] , |
| \mem5_dout_a[14] , |
| \mem5_dout_a[13] , |
| \mem5_dout_a[12] , |
| \mem5_dout_a[11] , |
| \mem5_dout_a[10] , |
| \mem5_dout_a[9] , |
| \mem5_dout_a[8] , |
| \mem5_dout_a[7] , |
| \mem5_dout_a[6] , |
| \mem5_dout_a[5] , |
| \mem5_dout_a[4] , |
| \mem5_dout_a[3] , |
| \mem5_dout_a[2] , |
| \mem5_dout_a[1] , |
| \mem5_dout_a[0] }), |
| .mem_dout_a2({\mem6_dout_a[31] , |
| \mem6_dout_a[30] , |
| \mem6_dout_a[29] , |
| \mem6_dout_a[28] , |
| \mem6_dout_a[27] , |
| \mem6_dout_a[26] , |
| \mem6_dout_a[25] , |
| \mem6_dout_a[24] , |
| \mem6_dout_a[23] , |
| \mem6_dout_a[22] , |
| \mem6_dout_a[21] , |
| \mem6_dout_a[20] , |
| \mem6_dout_a[19] , |
| \mem6_dout_a[18] , |
| \mem6_dout_a[17] , |
| \mem6_dout_a[16] , |
| \mem6_dout_a[15] , |
| \mem6_dout_a[14] , |
| \mem6_dout_a[13] , |
| \mem6_dout_a[12] , |
| \mem6_dout_a[11] , |
| \mem6_dout_a[10] , |
| \mem6_dout_a[9] , |
| \mem6_dout_a[8] , |
| \mem6_dout_a[7] , |
| \mem6_dout_a[6] , |
| \mem6_dout_a[5] , |
| \mem6_dout_a[4] , |
| \mem6_dout_a[3] , |
| \mem6_dout_a[2] , |
| \mem6_dout_a[1] , |
| \mem6_dout_a[0] }), |
| .mem_dout_a3({\mem7_dout_a[31] , |
| \mem7_dout_a[30] , |
| \mem7_dout_a[29] , |
| \mem7_dout_a[28] , |
| \mem7_dout_a[27] , |
| \mem7_dout_a[26] , |
| \mem7_dout_a[25] , |
| \mem7_dout_a[24] , |
| \mem7_dout_a[23] , |
| \mem7_dout_a[22] , |
| \mem7_dout_a[21] , |
| \mem7_dout_a[20] , |
| \mem7_dout_a[19] , |
| \mem7_dout_a[18] , |
| \mem7_dout_a[17] , |
| \mem7_dout_a[16] , |
| \mem7_dout_a[15] , |
| \mem7_dout_a[14] , |
| \mem7_dout_a[13] , |
| \mem7_dout_a[12] , |
| \mem7_dout_a[11] , |
| \mem7_dout_a[10] , |
| \mem7_dout_a[9] , |
| \mem7_dout_a[8] , |
| \mem7_dout_a[7] , |
| \mem7_dout_a[6] , |
| \mem7_dout_a[5] , |
| \mem7_dout_a[4] , |
| \mem7_dout_a[3] , |
| \mem7_dout_a[2] , |
| \mem7_dout_a[1] , |
| \mem7_dout_a[0] }), |
| .mem_mask_a0({\mem4_mask_a[3] , |
| \mem4_mask_a[2] , |
| \mem4_mask_a[1] , |
| \mem4_mask_a[0] }), |
| .mem_mask_a1({\mem5_mask_a[3] , |
| \mem5_mask_a[2] , |
| \mem5_mask_a[1] , |
| \mem5_mask_a[0] }), |
| .mem_mask_a2({\mem6_mask_a[3] , |
| \mem6_mask_a[2] , |
| \mem6_mask_a[1] , |
| \mem6_mask_a[0] }), |
| .mem_mask_a3({\mem7_mask_a[3] , |
| \mem7_mask_a[2] , |
| \mem7_mask_a[1] , |
| \mem7_mask_a[0] }), |
| .mem_web_a({\mem_web_a[7] , |
| \mem_web_a[6] , |
| \mem_web_a[5] , |
| \mem_web_a[4] }), |
| .scan_si({\scan_so_mbist0[7] , |
| \scan_so_mbist0[6] , |
| \scan_so_mbist0[5] , |
| \scan_so_mbist0[4] , |
| \scan_so_mbist0[3] , |
| \scan_so_mbist0[2] , |
| \scan_so_mbist0[1] , |
| \scan_so_mbist0[0] }), |
| .scan_so({\scan_so_mbist1[7] , |
| \scan_so_mbist1[6] , |
| \scan_so_mbist1[5] , |
| \scan_so_mbist1[4] , |
| \scan_so_mbist1[3] , |
| \scan_so_mbist1[2] , |
| \scan_so_mbist1[1] , |
| \scan_so_mbist1[0] }), |
| .wb_adr_i({\wbd_mbist1_adr_o[14] , |
| \wbd_mbist1_adr_o[13] , |
| \wbd_mbist1_adr_o[12] , |
| \wbd_mbist1_adr_o[11] , |
| \wbd_mbist1_adr_o[10] , |
| \wbd_mbist1_adr_o[9] , |
| \wbd_mbist1_adr_o[8] , |
| \wbd_mbist1_adr_o[7] , |
| \wbd_mbist1_adr_o[6] , |
| \wbd_mbist1_adr_o[5] , |
| \wbd_mbist1_adr_o[4] , |
| \wbd_mbist1_adr_o[3] , |
| \wbd_mbist1_adr_o[2] , |
| \wbd_mbist1_adr_o[1] , |
| \wbd_mbist1_adr_o[0] }), |
| .wb_bl_i({\wbd_mbist1_bl_o[9] , |
| \wbd_mbist1_bl_o[8] , |
| \wbd_mbist1_bl_o[7] , |
| \wbd_mbist1_bl_o[6] , |
| \wbd_mbist1_bl_o[5] , |
| \wbd_mbist1_bl_o[4] , |
| \wbd_mbist1_bl_o[3] , |
| \wbd_mbist1_bl_o[2] , |
| \wbd_mbist1_bl_o[1] , |
| \wbd_mbist1_bl_o[0] }), |
| .wb_dat_i({\wbd_mbist1_dat_o[31] , |
| \wbd_mbist1_dat_o[30] , |
| \wbd_mbist1_dat_o[29] , |
| \wbd_mbist1_dat_o[28] , |
| \wbd_mbist1_dat_o[27] , |
| \wbd_mbist1_dat_o[26] , |
| \wbd_mbist1_dat_o[25] , |
| \wbd_mbist1_dat_o[24] , |
| \wbd_mbist1_dat_o[23] , |
| \wbd_mbist1_dat_o[22] , |
| \wbd_mbist1_dat_o[21] , |
| \wbd_mbist1_dat_o[20] , |
| \wbd_mbist1_dat_o[19] , |
| \wbd_mbist1_dat_o[18] , |
| \wbd_mbist1_dat_o[17] , |
| \wbd_mbist1_dat_o[16] , |
| \wbd_mbist1_dat_o[15] , |
| \wbd_mbist1_dat_o[14] , |
| \wbd_mbist1_dat_o[13] , |
| \wbd_mbist1_dat_o[12] , |
| \wbd_mbist1_dat_o[11] , |
| \wbd_mbist1_dat_o[10] , |
| \wbd_mbist1_dat_o[9] , |
| \wbd_mbist1_dat_o[8] , |
| \wbd_mbist1_dat_o[7] , |
| \wbd_mbist1_dat_o[6] , |
| \wbd_mbist1_dat_o[5] , |
| \wbd_mbist1_dat_o[4] , |
| \wbd_mbist1_dat_o[3] , |
| \wbd_mbist1_dat_o[2] , |
| \wbd_mbist1_dat_o[1] , |
| \wbd_mbist1_dat_o[0] }), |
| .wb_dat_o({\wbd_mbist1_dat_i[31] , |
| \wbd_mbist1_dat_i[30] , |
| \wbd_mbist1_dat_i[29] , |
| \wbd_mbist1_dat_i[28] , |
| \wbd_mbist1_dat_i[27] , |
| \wbd_mbist1_dat_i[26] , |
| \wbd_mbist1_dat_i[25] , |
| \wbd_mbist1_dat_i[24] , |
| \wbd_mbist1_dat_i[23] , |
| \wbd_mbist1_dat_i[22] , |
| \wbd_mbist1_dat_i[21] , |
| \wbd_mbist1_dat_i[20] , |
| \wbd_mbist1_dat_i[19] , |
| \wbd_mbist1_dat_i[18] , |
| \wbd_mbist1_dat_i[17] , |
| \wbd_mbist1_dat_i[16] , |
| \wbd_mbist1_dat_i[15] , |
| \wbd_mbist1_dat_i[14] , |
| \wbd_mbist1_dat_i[13] , |
| \wbd_mbist1_dat_i[12] , |
| \wbd_mbist1_dat_i[11] , |
| \wbd_mbist1_dat_i[10] , |
| \wbd_mbist1_dat_i[9] , |
| \wbd_mbist1_dat_i[8] , |
| \wbd_mbist1_dat_i[7] , |
| \wbd_mbist1_dat_i[6] , |
| \wbd_mbist1_dat_i[5] , |
| \wbd_mbist1_dat_i[4] , |
| \wbd_mbist1_dat_i[3] , |
| \wbd_mbist1_dat_i[2] , |
| \wbd_mbist1_dat_i[1] , |
| \wbd_mbist1_dat_i[0] }), |
| .wb_sel_i({\wbd_mbist1_sel_o[3] , |
| \wbd_mbist1_sel_o[2] , |
| \wbd_mbist1_sel_o[1] , |
| \wbd_mbist1_sel_o[0] })); |
| pinmux_top u_pinmux (.mac_crs(mac_crs), |
| .mac_rx_clk(mac_rx_clk), |
| .mac_rx_dv(mac_rx_dv), |
| .mac_rx_er(mac_rx_er), |
| .mac_tx_clk(mac_tx_clk), |
| .mac_tx_en(mac_tx_en), |
| .mac_tx_er(mac_tx_er), |
| .mclk(wbd_clk_pinmux_skew), |
| .mdio_clk(mdio_clk), |
| .mdio_in(mdio_in), |
| .mdio_out(mdio_out), |
| .mdio_out_en(mdio_out_en), |
| .reg_ack(wbd_pinmux_ack_i), |
| .reg_cs(wbd_pinmux_stb_o), |
| .reg_wr(wbd_pinmux_we_o), |
| .reset_n(wbd_int_rst_n), |
| .scan_en(scan_en_wi), |
| .scan_en_o(scan_en_pinmux), |
| .scan_mode(scan_mode_wi), |
| .scan_mode_o(scan_mode_pinmux), |
| .spis_miso(sspis_so), |
| .spis_mosi(sspis_si), |
| .spis_sck(sspis_sck), |
| .spis_ssn(sspis_ssn), |
| .uartm_rxd(uartm_rxd), |
| .uartm_txd(uartm_txd), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .wbd_clk_int(wbd_clk_pinmux_rp), |
| .wbd_clk_skew(wbd_clk_pinmux_skew), |
| .cfg_cska_pinmux({\cfg_clk_ctrl1[11] , |
| \cfg_clk_ctrl1[10] , |
| \cfg_clk_ctrl1[9] , |
| \cfg_clk_ctrl1[8] }), |
| .io_in({\buf_out_north[39] , |
| \buf_out_north[36] , |
| \buf_out_north[33] , |
| \buf_out_north[30] , |
| \buf_out_north[27] , |
| \buf_out_north[24] , |
| \buf_out_north[21] , |
| \buf_out_north[18] , |
| \buf_out_north[15] , |
| \buf_out_north[12] , |
| \buf_out_north[9] , |
| \buf_out_north[6] , |
| \buf_out_north[3] , |
| \buf_out_north[0] , |
| \ch_out_north[2] , |
| \ch_out_north[5] , |
| \ch_out_north[8] , |
| \ch_out_north[11] , |
| \ch_out_north[14] , |
| \ch_out_north[17] , |
| \ch_out_north[20] , |
| \ch_out_north[23] , |
| \ch_out_north[26] , |
| \ch_out_east[2] , |
| \ch_out_east[5] , |
| \ch_out_east[8] , |
| \ch_out_east[11] , |
| \ch_out_east[14] , |
| \ch_out_east[17] , |
| \ch_out_east[20] , |
| \ch_out_east[23] , |
| \ch_out_east[26] , |
| \ch_out_east[29] , |
| \ch_out_east[32] , |
| \ch_out_east[35] , |
| \ch_out_east[38] , |
| \ch_out_east[41] , |
| \ch_out_east[44] }), |
| .io_oeb({\io_oeb_int[37] , |
| \io_oeb_int[36] , |
| \io_oeb_int[35] , |
| \io_oeb_int[34] , |
| \io_oeb_int[33] , |
| \io_oeb_int[32] , |
| \io_oeb_int[31] , |
| \io_oeb_int[30] , |
| \io_oeb_int[29] , |
| \io_oeb_int[28] , |
| \io_oeb_int[27] , |
| \io_oeb_int[26] , |
| \io_oeb_int[25] , |
| \io_oeb_int[24] , |
| \io_oeb_int[23] , |
| \io_oeb_int[22] , |
| \io_oeb_int[21] , |
| \io_oeb_int[20] , |
| \io_oeb_int[19] , |
| \io_oeb_int[18] , |
| \io_oeb_int[17] , |
| \io_oeb_int[16] , |
| \io_oeb_int[15] , |
| \io_oeb_int[14] , |
| \io_oeb_int[13] , |
| \io_oeb_int[12] , |
| \io_oeb_int[11] , |
| \io_oeb_int[10] , |
| \io_oeb_int[9] , |
| \io_oeb_int[8] , |
| \io_oeb_int[7] , |
| \io_oeb_int[6] , |
| \io_oeb_int[5] , |
| \io_oeb_int[4] , |
| \io_oeb_int[3] , |
| \io_oeb_int[2] , |
| \io_oeb_int[1] , |
| \io_oeb_int[0] }), |
| .io_out({\io_out_int[37] , |
| \io_out_int[36] , |
| \io_out_int[35] , |
| \io_out_int[34] , |
| \io_out_int[33] , |
| \io_out_int[32] , |
| \io_out_int[31] , |
| \io_out_int[30] , |
| \io_out_int[29] , |
| \io_out_int[28] , |
| \io_out_int[27] , |
| \io_out_int[26] , |
| \io_out_int[25] , |
| \io_out_int[24] , |
| \io_out_int[23] , |
| \io_out_int[22] , |
| \io_out_int[21] , |
| \io_out_int[20] , |
| \io_out_int[19] , |
| \io_out_int[18] , |
| \io_out_int[17] , |
| \io_out_int[16] , |
| \io_out_int[15] , |
| \io_out_int[14] , |
| \io_out_int[13] , |
| \io_out_int[12] , |
| \io_out_int[11] , |
| \io_out_int[10] , |
| \io_out_int[9] , |
| \io_out_int[8] , |
| \io_out_int[7] , |
| \io_out_int[6] , |
| \io_out_int[5] , |
| \io_out_int[4] , |
| \io_out_int[3] , |
| \io_out_int[2] , |
| \io_out_int[1] , |
| \io_out_int[0] }), |
| .mac_rxd({\mac_rxd[7] , |
| \mac_rxd[6] , |
| \mac_rxd[5] , |
| \mac_rxd[4] , |
| \mac_rxd[3] , |
| \mac_rxd[2] , |
| \mac_rxd[1] , |
| \mac_rxd[0] }), |
| .mac_txd({\mac_txd[7] , |
| \mac_txd[6] , |
| \mac_txd[5] , |
| \mac_txd[4] , |
| \mac_txd[3] , |
| \mac_txd[2] , |
| \mac_txd[1] , |
| \mac_txd[0] }), |
| .reg_addr({\wbd_pinmux_adr_o[7] , |
| \wbd_pinmux_adr_o[6] , |
| \wbd_pinmux_adr_o[5] , |
| \wbd_pinmux_adr_o[4] , |
| \wbd_pinmux_adr_o[3] , |
| \wbd_pinmux_adr_o[2] , |
| \wbd_pinmux_adr_o[1] , |
| \wbd_pinmux_adr_o[0] }), |
| .reg_be({\wbd_pinmux_sel_o[3] , |
| \wbd_pinmux_sel_o[2] , |
| \wbd_pinmux_sel_o[1] , |
| \wbd_pinmux_sel_o[0] }), |
| .reg_rdata({\wbd_pinmux_dat_i[31] , |
| \wbd_pinmux_dat_i[30] , |
| \wbd_pinmux_dat_i[29] , |
| \wbd_pinmux_dat_i[28] , |
| \wbd_pinmux_dat_i[27] , |
| \wbd_pinmux_dat_i[26] , |
| \wbd_pinmux_dat_i[25] , |
| \wbd_pinmux_dat_i[24] , |
| \wbd_pinmux_dat_i[23] , |
| \wbd_pinmux_dat_i[22] , |
| \wbd_pinmux_dat_i[21] , |
| \wbd_pinmux_dat_i[20] , |
| \wbd_pinmux_dat_i[19] , |
| \wbd_pinmux_dat_i[18] , |
| \wbd_pinmux_dat_i[17] , |
| \wbd_pinmux_dat_i[16] , |
| \wbd_pinmux_dat_i[15] , |
| \wbd_pinmux_dat_i[14] , |
| \wbd_pinmux_dat_i[13] , |
| \wbd_pinmux_dat_i[12] , |
| \wbd_pinmux_dat_i[11] , |
| \wbd_pinmux_dat_i[10] , |
| \wbd_pinmux_dat_i[9] , |
| \wbd_pinmux_dat_i[8] , |
| \wbd_pinmux_dat_i[7] , |
| \wbd_pinmux_dat_i[6] , |
| \wbd_pinmux_dat_i[5] , |
| \wbd_pinmux_dat_i[4] , |
| \wbd_pinmux_dat_i[3] , |
| \wbd_pinmux_dat_i[2] , |
| \wbd_pinmux_dat_i[1] , |
| \wbd_pinmux_dat_i[0] }), |
| .reg_wdata({\wbd_pinmux_dat_o[31] , |
| \wbd_pinmux_dat_o[30] , |
| \wbd_pinmux_dat_o[29] , |
| \wbd_pinmux_dat_o[28] , |
| \wbd_pinmux_dat_o[27] , |
| \wbd_pinmux_dat_o[26] , |
| \wbd_pinmux_dat_o[25] , |
| \wbd_pinmux_dat_o[24] , |
| \wbd_pinmux_dat_o[23] , |
| \wbd_pinmux_dat_o[22] , |
| \wbd_pinmux_dat_o[21] , |
| \wbd_pinmux_dat_o[20] , |
| \wbd_pinmux_dat_o[19] , |
| \wbd_pinmux_dat_o[18] , |
| \wbd_pinmux_dat_o[17] , |
| \wbd_pinmux_dat_o[16] , |
| \wbd_pinmux_dat_o[15] , |
| \wbd_pinmux_dat_o[14] , |
| \wbd_pinmux_dat_o[13] , |
| \wbd_pinmux_dat_o[12] , |
| \wbd_pinmux_dat_o[11] , |
| \wbd_pinmux_dat_o[10] , |
| \wbd_pinmux_dat_o[9] , |
| \wbd_pinmux_dat_o[8] , |
| \wbd_pinmux_dat_o[7] , |
| \wbd_pinmux_dat_o[6] , |
| \wbd_pinmux_dat_o[5] , |
| \wbd_pinmux_dat_o[4] , |
| \wbd_pinmux_dat_o[3] , |
| \wbd_pinmux_dat_o[2] , |
| \wbd_pinmux_dat_o[1] , |
| \wbd_pinmux_dat_o[0] }), |
| .scan_si({\scan_so_wi[7] , |
| \scan_so_wi[6] , |
| \scan_so_wi[5] , |
| \scan_so_wi[4] , |
| \scan_so_wi[3] , |
| \scan_so_wi[2] , |
| \scan_so_wi[1] , |
| \scan_so_wi[0] }), |
| .scan_so({\scan_so_pinmux[7] , |
| \scan_so_pinmux[6] , |
| \scan_so_pinmux[5] , |
| \scan_so_pinmux[4] , |
| \scan_so_pinmux[3] , |
| \scan_so_pinmux[2] , |
| \scan_so_pinmux[1] , |
| \scan_so_pinmux[0] })); |
| bus_rep_east u_rp_east (.vccd1(vccd1), |
| .vssd1(vssd1), |
| .ch_in({io_in[0], |
| \io_out_int[0] , |
| \io_oeb_int[0] , |
| io_in[1], |
| \io_out_int[1] , |
| \io_oeb_int[1] , |
| io_in[2], |
| \io_out_int[2] , |
| \io_oeb_int[2] , |
| io_in[3], |
| \io_out_int[3] , |
| \io_oeb_int[3] , |
| io_in[4], |
| \io_out_int[4] , |
| \io_oeb_int[4] , |
| io_in[5], |
| \io_out_int[5] , |
| \io_oeb_int[5] , |
| io_in[6], |
| \io_out_int[6] , |
| \io_oeb_int[6] , |
| io_in[7], |
| \io_out_int[7] , |
| \io_oeb_int[7] , |
| io_in[8], |
| \io_out_int[8] , |
| \io_oeb_int[8] , |
| io_in[9], |
| \io_out_int[9] , |
| \io_oeb_int[9] , |
| io_in[10], |
| \io_out_int[10] , |
| \io_oeb_int[10] , |
| io_in[11], |
| \io_out_int[11] , |
| \io_oeb_int[11] , |
| io_in[12], |
| \io_out_int[12] , |
| \io_oeb_int[12] , |
| io_in[13], |
| \io_out_int[13] , |
| \io_oeb_int[13] , |
| io_in[14], |
| \io_out_int[14] , |
| \io_oeb_int[14] }), |
| .ch_out({\ch_out_east[44] , |
| io_out[0], |
| io_oeb[0], |
| \ch_out_east[41] , |
| io_out[1], |
| io_oeb[1], |
| \ch_out_east[38] , |
| io_out[2], |
| io_oeb[2], |
| \ch_out_east[35] , |
| io_out[3], |
| io_oeb[3], |
| \ch_out_east[32] , |
| io_out[4], |
| io_oeb[4], |
| \ch_out_east[29] , |
| io_out[5], |
| io_oeb[5], |
| \ch_out_east[26] , |
| io_out[6], |
| io_oeb[6], |
| \ch_out_east[23] , |
| io_out[7], |
| io_oeb[7], |
| \ch_out_east[20] , |
| io_out[8], |
| io_oeb[8], |
| \ch_out_east[17] , |
| io_out[9], |
| io_oeb[9], |
| \ch_out_east[14] , |
| io_out[10], |
| io_oeb[10], |
| \ch_out_east[11] , |
| io_out[11], |
| io_oeb[11], |
| \ch_out_east[8] , |
| io_out[12], |
| io_oeb[12], |
| \ch_out_east[5] , |
| io_out[13], |
| io_oeb[13], |
| \ch_out_east[2] , |
| io_out[14], |
| io_oeb[14]})); |
| bus_rep_north u_rp_north (.vccd1(vccd1), |
| .vssd1(vssd1), |
| .buf_in({\io_oeb_int[37] , |
| \io_out_int[37] , |
| \ch_out_west[39] , |
| \io_oeb_int[36] , |
| \io_out_int[36] , |
| \ch_out_west[36] , |
| \io_oeb_int[35] , |
| \io_out_int[35] , |
| \ch_out_west[33] , |
| \io_oeb_int[34] , |
| \io_out_int[34] , |
| \ch_out_west[30] , |
| \io_oeb_int[33] , |
| \io_out_int[33] , |
| \ch_out_west[27] , |
| \io_oeb_int[32] , |
| \io_out_int[32] , |
| \ch_out_west[24] , |
| \io_oeb_int[31] , |
| \io_out_int[31] , |
| \ch_out_west[21] , |
| \io_oeb_int[30] , |
| \io_out_int[30] , |
| \ch_out_west[18] , |
| \io_oeb_int[29] , |
| \io_out_int[29] , |
| \ch_out_west[15] , |
| \io_oeb_int[28] , |
| \io_out_int[28] , |
| \ch_out_west[12] , |
| \io_oeb_int[27] , |
| \io_out_int[27] , |
| \ch_out_west[9] , |
| \io_oeb_int[26] , |
| \io_out_int[26] , |
| \ch_out_west[6] , |
| \io_oeb_int[25] , |
| \io_out_int[25] , |
| \ch_out_west[3] , |
| \io_oeb_int[24] , |
| \io_out_int[24] , |
| \ch_out_west[0] }), |
| .buf_out({\buf_out_north[41] , |
| \buf_out_north[40] , |
| \buf_out_north[39] , |
| \buf_out_north[38] , |
| \buf_out_north[37] , |
| \buf_out_north[36] , |
| \buf_out_north[35] , |
| \buf_out_north[34] , |
| \buf_out_north[33] , |
| \buf_out_north[32] , |
| \buf_out_north[31] , |
| \buf_out_north[30] , |
| \buf_out_north[29] , |
| \buf_out_north[28] , |
| \buf_out_north[27] , |
| \buf_out_north[26] , |
| \buf_out_north[25] , |
| \buf_out_north[24] , |
| \buf_out_north[23] , |
| \buf_out_north[22] , |
| \buf_out_north[21] , |
| \buf_out_north[20] , |
| \buf_out_north[19] , |
| \buf_out_north[18] , |
| \buf_out_north[17] , |
| \buf_out_north[16] , |
| \buf_out_north[15] , |
| \buf_out_north[14] , |
| \buf_out_north[13] , |
| \buf_out_north[12] , |
| \buf_out_north[11] , |
| \buf_out_north[10] , |
| \buf_out_north[9] , |
| \buf_out_north[8] , |
| \buf_out_north[7] , |
| \buf_out_north[6] , |
| \buf_out_north[5] , |
| \buf_out_north[4] , |
| \buf_out_north[3] , |
| \buf_out_north[2] , |
| \buf_out_north[1] , |
| \buf_out_north[0] }), |
| .ch_in({io_in[15], |
| \io_out_int[15] , |
| \io_oeb_int[15] , |
| io_in[16], |
| \io_out_int[16] , |
| \io_oeb_int[16] , |
| io_in[17], |
| \io_out_int[17] , |
| \io_oeb_int[17] , |
| io_in[18], |
| \io_out_int[18] , |
| \io_oeb_int[18] , |
| io_in[19], |
| \io_out_int[19] , |
| \io_oeb_int[19] , |
| io_in[20], |
| \io_out_int[20] , |
| \io_oeb_int[20] , |
| io_in[21], |
| \io_out_int[21] , |
| \io_oeb_int[21] , |
| io_in[22], |
| \io_out_int[22] , |
| \io_oeb_int[22] , |
| io_in[23], |
| \io_out_int[23] , |
| \io_oeb_int[23] }), |
| .ch_out({\ch_out_north[26] , |
| io_out[15], |
| io_oeb[15], |
| \ch_out_north[23] , |
| io_out[16], |
| io_oeb[16], |
| \ch_out_north[20] , |
| io_out[17], |
| io_oeb[17], |
| \ch_out_north[17] , |
| io_out[18], |
| io_oeb[18], |
| \ch_out_north[14] , |
| io_out[19], |
| io_oeb[19], |
| \ch_out_north[11] , |
| io_out[20], |
| io_oeb[20], |
| \ch_out_north[8] , |
| io_out[21], |
| io_oeb[21], |
| \ch_out_north[5] , |
| io_out[22], |
| io_oeb[22], |
| \ch_out_north[2] , |
| io_out[23], |
| io_oeb[23]})); |
| bus_rep_south u_rp_south (.vccd1(vccd1), |
| .vssd1(vssd1), |
| .ch_in({user_clock2, |
| \la_data_out_int[127] , |
| \la_data_out_int[126] , |
| \la_data_out_int[125] , |
| \la_data_out_int[124] , |
| \la_data_out_int[123] , |
| \la_data_out_int[122] , |
| \la_data_out_int[121] , |
| \la_data_out_int[120] , |
| \la_data_out_int[119] , |
| \la_data_out_int[118] , |
| \la_data_out_int[117] , |
| \la_data_out_int[116] , |
| \la_data_out_int[115] , |
| \la_data_out_int[114] , |
| \la_data_out_int[113] , |
| \la_data_out_int[112] , |
| \la_data_out_int[111] , |
| \la_data_out_int[110] , |
| \la_data_out_int[109] , |
| \la_data_out_int[108] , |
| \la_data_out_int[107] , |
| \la_data_out_int[106] , |
| \la_data_out_int[105] , |
| \la_data_out_int[104] , |
| \la_data_out_int[103] , |
| \la_data_out_int[102] , |
| \la_data_out_int[101] , |
| \la_data_out_int[100] , |
| \la_data_out_int[99] , |
| \la_data_out_int[98] , |
| \la_data_out_int[97] , |
| \la_data_out_int[96] , |
| \la_data_out_int[95] , |
| \la_data_out_int[94] , |
| \la_data_out_int[93] , |
| \la_data_out_int[92] , |
| \la_data_out_int[91] , |
| \la_data_out_int[90] , |
| \la_data_out_int[89] , |
| \la_data_out_int[88] , |
| \la_data_out_int[87] , |
| \la_data_out_int[86] , |
| \la_data_out_int[85] , |
| \la_data_out_int[84] , |
| \la_data_out_int[83] , |
| \la_data_out_int[82] , |
| \la_data_out_int[81] , |
| \la_data_out_int[80] , |
| \la_data_out_int[79] , |
| \la_data_out_int[78] , |
| \la_data_out_int[77] , |
| \la_data_out_int[76] , |
| \la_data_out_int[75] , |
| \la_data_out_int[74] , |
| \la_data_out_int[73] , |
| \la_data_out_int[72] , |
| \la_data_out_int[71] , |
| \la_data_out_int[70] , |
| \la_data_out_int[69] , |
| \la_data_out_int[68] , |
| \la_data_out_int[67] , |
| \la_data_out_int[66] , |
| \la_data_out_int[65] , |
| \la_data_out_int[64] , |
| \la_data_out_int[63] , |
| \la_data_out_int[62] , |
| \la_data_out_int[61] , |
| \la_data_out_int[60] , |
| \la_data_out_int[59] , |
| \la_data_out_int[58] , |
| \la_data_out_int[57] , |
| \la_data_out_int[56] , |
| \la_data_out_int[55] , |
| \la_data_out_int[54] , |
| \la_data_out_int[53] , |
| \la_data_out_int[52] , |
| \la_data_out_int[51] , |
| \la_data_out_int[50] , |
| \la_data_out_int[49] , |
| \la_data_out_int[48] , |
| \la_data_out_int[47] , |
| \la_data_out_int[46] , |
| \la_data_out_int[45] , |
| \la_data_out_int[44] , |
| \la_data_out_int[43] , |
| \la_data_out_int[42] , |
| \la_data_out_int[41] , |
| \la_data_out_int[40] , |
| \la_data_out_int[39] , |
| \la_data_out_int[38] , |
| \la_data_out_int[37] , |
| \la_data_out_int[36] , |
| \la_data_out_int[35] , |
| la_data_in[35], |
| \la_data_out_int[34] , |
| la_data_in[34], |
| \la_data_out_int[33] , |
| la_data_in[33], |
| \la_data_out_int[32] , |
| la_data_in[32], |
| \la_data_out_int[31] , |
| la_data_in[31], |
| \la_data_out_int[30] , |
| la_data_in[30], |
| \la_data_out_int[29] , |
| la_data_in[29], |
| \la_data_out_int[28] , |
| la_data_in[28], |
| \la_data_out_int[27] , |
| la_data_in[27], |
| \la_data_out_int[26] , |
| la_data_in[26], |
| \la_data_out_int[25] , |
| la_data_in[25], |
| \la_data_out_int[24] , |
| la_data_in[24], |
| \la_data_out_int[23] , |
| la_data_in[23], |
| \la_data_out_int[22] , |
| la_data_in[22], |
| \la_data_out_int[21] , |
| la_data_in[21], |
| \la_data_out_int[20] , |
| la_data_in[20], |
| \la_data_out_int[19] , |
| la_data_in[19], |
| \la_data_out_int[18] , |
| la_data_in[18], |
| \la_data_out_int[17] , |
| la_data_in[17], |
| \la_data_out_int[16] , |
| la_data_in[16], |
| \la_data_out_int[15] , |
| la_data_in[15], |
| \la_data_out_int[14] , |
| la_data_in[14], |
| \la_data_out_int[13] , |
| la_data_in[13], |
| \la_data_out_int[12] , |
| la_data_in[12], |
| \la_data_out_int[11] , |
| la_data_in[11], |
| \la_data_out_int[10] , |
| la_data_in[10], |
| \la_data_out_int[9] , |
| la_data_in[9], |
| \la_data_out_int[8] , |
| la_data_in[8], |
| \la_data_out_int[7] , |
| la_data_in[7], |
| \la_data_out_int[6] , |
| la_data_in[6], |
| \la_data_out_int[5] , |
| la_data_in[5], |
| \la_data_out_int[4] , |
| la_data_in[4], |
| \la_data_out_int[3] , |
| la_data_in[3], |
| \la_data_out_int[2] , |
| la_data_in[2], |
| \la_data_out_int[1] , |
| la_data_in[1], |
| \la_data_out_int[0] , |
| la_data_in[0], |
| \wbs_dat_int_o[31] , |
| wbs_dat_i[31], |
| wbs_adr_i[31], |
| \wbs_dat_int_o[30] , |
| wbs_dat_i[30], |
| wbs_adr_i[30], |
| \wbs_dat_int_o[29] , |
| wbs_dat_i[29], |
| wbs_adr_i[29], |
| \wbs_dat_int_o[28] , |
| wbs_dat_i[28], |
| wbs_adr_i[28], |
| \wbs_dat_int_o[27] , |
| wbs_dat_i[27], |
| wbs_adr_i[27], |
| \wbs_dat_int_o[26] , |
| wbs_dat_i[26], |
| wbs_adr_i[26], |
| \wbs_dat_int_o[25] , |
| wbs_dat_i[25], |
| wbs_adr_i[25], |
| \wbs_dat_int_o[24] , |
| wbs_dat_i[24], |
| wbs_adr_i[24], |
| \wbs_dat_int_o[23] , |
| wbs_dat_i[23], |
| wbs_adr_i[23], |
| \wbs_dat_int_o[22] , |
| wbs_dat_i[22], |
| wbs_adr_i[22], |
| \wbs_dat_int_o[21] , |
| wbs_dat_i[21], |
| wbs_adr_i[21], |
| \wbs_dat_int_o[20] , |
| wbs_dat_i[20], |
| wbs_adr_i[20], |
| \wbs_dat_int_o[19] , |
| wbs_dat_i[19], |
| wbs_adr_i[19], |
| \wbs_dat_int_o[18] , |
| wbs_dat_i[18], |
| wbs_adr_i[18], |
| \wbs_dat_int_o[17] , |
| wbs_dat_i[17], |
| wbs_adr_i[17], |
| \wbs_dat_int_o[16] , |
| wbs_dat_i[16], |
| wbs_adr_i[16], |
| \wbs_dat_int_o[15] , |
| wbs_dat_i[15], |
| wbs_adr_i[15], |
| \wbs_dat_int_o[14] , |
| wbs_dat_i[14], |
| wbs_adr_i[14], |
| \wbs_dat_int_o[13] , |
| wbs_dat_i[13], |
| wbs_adr_i[13], |
| \wbs_dat_int_o[12] , |
| wbs_dat_i[12], |
| wbs_adr_i[12], |
| \wbs_dat_int_o[11] , |
| wbs_dat_i[11], |
| wbs_adr_i[11], |
| \wbs_dat_int_o[10] , |
| wbs_dat_i[10], |
| wbs_adr_i[10], |
| \wbs_dat_int_o[9] , |
| wbs_dat_i[9], |
| wbs_adr_i[9], |
| \wbs_dat_int_o[8] , |
| wbs_dat_i[8], |
| wbs_adr_i[8], |
| \wbs_dat_int_o[7] , |
| wbs_dat_i[7], |
| wbs_adr_i[7], |
| \wbs_dat_int_o[6] , |
| wbs_dat_i[6], |
| wbs_adr_i[6], |
| \wbs_dat_int_o[5] , |
| wbs_dat_i[5], |
| wbs_adr_i[5], |
| \wbs_dat_int_o[4] , |
| wbs_dat_i[4], |
| wbs_adr_i[4], |
| wbs_sel_i[3], |
| \wbs_dat_int_o[3] , |
| wbs_dat_i[3], |
| wbs_adr_i[3], |
| wbs_sel_i[2], |
| \wbs_dat_int_o[2] , |
| wbs_dat_i[2], |
| wbs_adr_i[2], |
| wbs_sel_i[1], |
| \wbs_dat_int_o[1] , |
| wbs_dat_i[1], |
| wbs_adr_i[1], |
| wbs_sel_i[0], |
| \wbs_dat_int_o[0] , |
| wbs_dat_i[0], |
| wbs_adr_i[0], |
| wbs_we_i, |
| wbs_stb_i, |
| wbs_cyc_i, |
| wbs_ack_int_o, |
| wb_rst_i, |
| wb_clk_i}), |
| .ch_out({\ch_out_south[270] , |
| la_data_out[127], |
| la_data_out[126], |
| la_data_out[125], |
| la_data_out[124], |
| la_data_out[123], |
| la_data_out[122], |
| la_data_out[121], |
| la_data_out[120], |
| la_data_out[119], |
| la_data_out[118], |
| la_data_out[117], |
| la_data_out[116], |
| la_data_out[115], |
| la_data_out[114], |
| la_data_out[113], |
| la_data_out[112], |
| la_data_out[111], |
| la_data_out[110], |
| la_data_out[109], |
| la_data_out[108], |
| la_data_out[107], |
| la_data_out[106], |
| la_data_out[105], |
| la_data_out[104], |
| la_data_out[103], |
| la_data_out[102], |
| la_data_out[101], |
| la_data_out[100], |
| la_data_out[99], |
| la_data_out[98], |
| la_data_out[97], |
| la_data_out[96], |
| la_data_out[95], |
| la_data_out[94], |
| la_data_out[93], |
| la_data_out[92], |
| la_data_out[91], |
| la_data_out[90], |
| la_data_out[89], |
| la_data_out[88], |
| la_data_out[87], |
| la_data_out[86], |
| la_data_out[85], |
| la_data_out[84], |
| la_data_out[83], |
| la_data_out[82], |
| la_data_out[81], |
| la_data_out[80], |
| la_data_out[79], |
| la_data_out[78], |
| la_data_out[77], |
| la_data_out[76], |
| la_data_out[75], |
| la_data_out[74], |
| la_data_out[73], |
| la_data_out[72], |
| la_data_out[71], |
| la_data_out[70], |
| la_data_out[69], |
| la_data_out[68], |
| la_data_out[67], |
| la_data_out[66], |
| la_data_out[65], |
| la_data_out[64], |
| la_data_out[63], |
| la_data_out[62], |
| la_data_out[61], |
| la_data_out[60], |
| la_data_out[59], |
| la_data_out[58], |
| la_data_out[57], |
| la_data_out[56], |
| la_data_out[55], |
| la_data_out[54], |
| la_data_out[53], |
| la_data_out[52], |
| la_data_out[51], |
| la_data_out[50], |
| la_data_out[49], |
| la_data_out[48], |
| la_data_out[47], |
| la_data_out[46], |
| la_data_out[45], |
| la_data_out[44], |
| la_data_out[43], |
| la_data_out[42], |
| la_data_out[41], |
| la_data_out[40], |
| la_data_out[39], |
| la_data_out[38], |
| la_data_out[37], |
| la_data_out[36], |
| la_data_out[35], |
| \ch_out_south[176] , |
| la_data_out[34], |
| \ch_out_south[174] , |
| la_data_out[33], |
| \ch_out_south[172] , |
| la_data_out[32], |
| \ch_out_south[170] , |
| la_data_out[31], |
| \ch_out_south[168] , |
| la_data_out[30], |
| \ch_out_south[166] , |
| la_data_out[29], |
| \ch_out_south[164] , |
| la_data_out[28], |
| \ch_out_south[162] , |
| la_data_out[27], |
| \ch_out_south[160] , |
| la_data_out[26], |
| \ch_out_south[158] , |
| la_data_out[25], |
| \ch_out_south[156] , |
| la_data_out[24], |
| \ch_out_south[154] , |
| la_data_out[23], |
| \ch_out_south[152] , |
| la_data_out[22], |
| \ch_out_south[150] , |
| la_data_out[21], |
| \ch_out_south[148] , |
| la_data_out[20], |
| \ch_out_south[146] , |
| la_data_out[19], |
| \ch_out_south[144] , |
| la_data_out[18], |
| \ch_out_south[142] , |
| la_data_out[17], |
| \ch_out_south[140] , |
| la_data_out[16], |
| \ch_out_south[138] , |
| la_data_out[15], |
| \ch_out_south[136] , |
| la_data_out[14], |
| \ch_out_south[134] , |
| la_data_out[13], |
| \ch_out_south[132] , |
| la_data_out[12], |
| \ch_out_south[130] , |
| la_data_out[11], |
| \ch_out_south[128] , |
| la_data_out[10], |
| \ch_out_south[126] , |
| la_data_out[9], |
| \ch_out_south[124] , |
| la_data_out[8], |
| \ch_out_south[122] , |
| la_data_out[7], |
| \ch_out_south[120] , |
| la_data_out[6], |
| \ch_out_south[118] , |
| la_data_out[5], |
| \ch_out_south[116] , |
| la_data_out[4], |
| \ch_out_south[114] , |
| la_data_out[3], |
| \ch_out_south[112] , |
| la_data_out[2], |
| \ch_out_south[110] , |
| la_data_out[1], |
| \ch_out_south[108] , |
| la_data_out[0], |
| \ch_out_south[106] , |
| wbs_dat_o[31], |
| \ch_out_south[104] , |
| \ch_out_south[103] , |
| wbs_dat_o[30], |
| \ch_out_south[101] , |
| \ch_out_south[100] , |
| wbs_dat_o[29], |
| \ch_out_south[98] , |
| \ch_out_south[97] , |
| wbs_dat_o[28], |
| \ch_out_south[95] , |
| \ch_out_south[94] , |
| wbs_dat_o[27], |
| \ch_out_south[92] , |
| \ch_out_south[91] , |
| wbs_dat_o[26], |
| \ch_out_south[89] , |
| \ch_out_south[88] , |
| wbs_dat_o[25], |
| \ch_out_south[86] , |
| \ch_out_south[85] , |
| wbs_dat_o[24], |
| \ch_out_south[83] , |
| \ch_out_south[82] , |
| wbs_dat_o[23], |
| \ch_out_south[80] , |
| \ch_out_south[79] , |
| wbs_dat_o[22], |
| \ch_out_south[77] , |
| \ch_out_south[76] , |
| wbs_dat_o[21], |
| \ch_out_south[74] , |
| \ch_out_south[73] , |
| wbs_dat_o[20], |
| \ch_out_south[71] , |
| \ch_out_south[70] , |
| wbs_dat_o[19], |
| \ch_out_south[68] , |
| \ch_out_south[67] , |
| wbs_dat_o[18], |
| \ch_out_south[65] , |
| \ch_out_south[64] , |
| wbs_dat_o[17], |
| \ch_out_south[62] , |
| \ch_out_south[61] , |
| wbs_dat_o[16], |
| \ch_out_south[59] , |
| \ch_out_south[58] , |
| wbs_dat_o[15], |
| \ch_out_south[56] , |
| \ch_out_south[55] , |
| wbs_dat_o[14], |
| \ch_out_south[53] , |
| \ch_out_south[52] , |
| wbs_dat_o[13], |
| \ch_out_south[50] , |
| \ch_out_south[49] , |
| wbs_dat_o[12], |
| \ch_out_south[47] , |
| \ch_out_south[46] , |
| wbs_dat_o[11], |
| \ch_out_south[44] , |
| \ch_out_south[43] , |
| wbs_dat_o[10], |
| \ch_out_south[41] , |
| \ch_out_south[40] , |
| wbs_dat_o[9], |
| \ch_out_south[38] , |
| \ch_out_south[37] , |
| wbs_dat_o[8], |
| \ch_out_south[35] , |
| \ch_out_south[34] , |
| wbs_dat_o[7], |
| \ch_out_south[32] , |
| \ch_out_south[31] , |
| wbs_dat_o[6], |
| \ch_out_south[29] , |
| \ch_out_south[28] , |
| wbs_dat_o[5], |
| \ch_out_south[26] , |
| \ch_out_south[25] , |
| wbs_dat_o[4], |
| \ch_out_south[23] , |
| \ch_out_south[22] , |
| \ch_out_south[21] , |
| wbs_dat_o[3], |
| \ch_out_south[19] , |
| \ch_out_south[18] , |
| \ch_out_south[17] , |
| wbs_dat_o[2], |
| \ch_out_south[15] , |
| \ch_out_south[14] , |
| \ch_out_south[13] , |
| wbs_dat_o[1], |
| \ch_out_south[11] , |
| \ch_out_south[10] , |
| \ch_out_south[9] , |
| wbs_dat_o[0], |
| \ch_out_south[7] , |
| \ch_out_south[6] , |
| \ch_out_south[5] , |
| \ch_out_south[4] , |
| \ch_out_south[3] , |
| wbs_ack_o, |
| \ch_out_south[1] , |
| \ch_out_south[0] })); |
| bus_rep_west u_rp_west (.vccd1(vccd1), |
| .vssd1(vssd1), |
| .ch_in({\buf_out_north[41] , |
| \buf_out_north[40] , |
| io_in[37], |
| \buf_out_north[38] , |
| \buf_out_north[37] , |
| io_in[36], |
| \buf_out_north[35] , |
| \buf_out_north[34] , |
| io_in[35], |
| \buf_out_north[32] , |
| \buf_out_north[31] , |
| io_in[34], |
| \buf_out_north[29] , |
| \buf_out_north[28] , |
| io_in[33], |
| \buf_out_north[26] , |
| \buf_out_north[25] , |
| io_in[32], |
| \buf_out_north[23] , |
| \buf_out_north[22] , |
| io_in[31], |
| \buf_out_north[20] , |
| \buf_out_north[19] , |
| io_in[30], |
| \buf_out_north[17] , |
| \buf_out_north[16] , |
| io_in[29], |
| \buf_out_north[14] , |
| \buf_out_north[13] , |
| io_in[28], |
| \buf_out_north[11] , |
| \buf_out_north[10] , |
| io_in[27], |
| \buf_out_north[8] , |
| \buf_out_north[7] , |
| io_in[26], |
| \buf_out_north[5] , |
| \buf_out_north[4] , |
| io_in[25], |
| \buf_out_north[2] , |
| \buf_out_north[1] , |
| io_in[24]}), |
| .ch_out({io_oeb[37], |
| io_out[37], |
| \ch_out_west[39] , |
| io_oeb[36], |
| io_out[36], |
| \ch_out_west[36] , |
| io_oeb[35], |
| io_out[35], |
| \ch_out_west[33] , |
| io_oeb[34], |
| io_out[34], |
| \ch_out_west[30] , |
| io_oeb[33], |
| io_out[33], |
| \ch_out_west[27] , |
| io_oeb[32], |
| io_out[32], |
| \ch_out_west[24] , |
| io_oeb[31], |
| io_out[31], |
| \ch_out_west[21] , |
| io_oeb[30], |
| io_out[30], |
| \ch_out_west[18] , |
| io_oeb[29], |
| io_out[29], |
| \ch_out_west[15] , |
| io_oeb[28], |
| io_out[28], |
| \ch_out_west[12] , |
| io_oeb[27], |
| io_out[27], |
| \ch_out_west[9] , |
| io_oeb[26], |
| io_out[26], |
| \ch_out_west[6] , |
| io_oeb[25], |
| io_out[25], |
| \ch_out_west[3] , |
| io_oeb[24], |
| io_out[24], |
| \ch_out_west[0] })); |
| sky130_sram_2kbyte_1rw1r_32x512_8 u_sram0_2kb (.csb0(\mem_cen_a[0] ), |
| .csb1(\mem_cen_b[0] ), |
| .web0(\mem_web_a[0] ), |
| .clk0(\mem_clk_a[0] ), |
| .clk1(\mem_clk_b[0] ), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .addr0({\mem0_addr_a[8] , |
| \mem0_addr_a[7] , |
| \mem0_addr_a[6] , |
| \mem0_addr_a[5] , |
| \mem0_addr_a[4] , |
| \mem0_addr_a[3] , |
| \mem0_addr_a[2] , |
| \mem0_addr_a[1] , |
| \mem0_addr_a[0] }), |
| .addr1({\mem0_addr_b[8] , |
| \mem0_addr_b[7] , |
| \mem0_addr_b[6] , |
| \mem0_addr_b[5] , |
| \mem0_addr_b[4] , |
| \mem0_addr_b[3] , |
| \mem0_addr_b[2] , |
| \mem0_addr_b[1] , |
| \mem0_addr_b[0] }), |
| .din0({\mem0_din_a[31] , |
| \mem0_din_a[30] , |
| \mem0_din_a[29] , |
| \mem0_din_a[28] , |
| \mem0_din_a[27] , |
| \mem0_din_a[26] , |
| \mem0_din_a[25] , |
| \mem0_din_a[24] , |
| \mem0_din_a[23] , |
| \mem0_din_a[22] , |
| \mem0_din_a[21] , |
| \mem0_din_a[20] , |
| \mem0_din_a[19] , |
| \mem0_din_a[18] , |
| \mem0_din_a[17] , |
| \mem0_din_a[16] , |
| \mem0_din_a[15] , |
| \mem0_din_a[14] , |
| \mem0_din_a[13] , |
| \mem0_din_a[12] , |
| \mem0_din_a[11] , |
| \mem0_din_a[10] , |
| \mem0_din_a[9] , |
| \mem0_din_a[8] , |
| \mem0_din_a[7] , |
| \mem0_din_a[6] , |
| \mem0_din_a[5] , |
| \mem0_din_a[4] , |
| \mem0_din_a[3] , |
| \mem0_din_a[2] , |
| \mem0_din_a[1] , |
| \mem0_din_a[0] }), |
| .dout0({\mem0_dout_a[31] , |
| \mem0_dout_a[30] , |
| \mem0_dout_a[29] , |
| \mem0_dout_a[28] , |
| \mem0_dout_a[27] , |
| \mem0_dout_a[26] , |
| \mem0_dout_a[25] , |
| \mem0_dout_a[24] , |
| \mem0_dout_a[23] , |
| \mem0_dout_a[22] , |
| \mem0_dout_a[21] , |
| \mem0_dout_a[20] , |
| \mem0_dout_a[19] , |
| \mem0_dout_a[18] , |
| \mem0_dout_a[17] , |
| \mem0_dout_a[16] , |
| \mem0_dout_a[15] , |
| \mem0_dout_a[14] , |
| \mem0_dout_a[13] , |
| \mem0_dout_a[12] , |
| \mem0_dout_a[11] , |
| \mem0_dout_a[10] , |
| \mem0_dout_a[9] , |
| \mem0_dout_a[8] , |
| \mem0_dout_a[7] , |
| \mem0_dout_a[6] , |
| \mem0_dout_a[5] , |
| \mem0_dout_a[4] , |
| \mem0_dout_a[3] , |
| \mem0_dout_a[2] , |
| \mem0_dout_a[1] , |
| \mem0_dout_a[0] }), |
| .dout1({_NC1, |
| _NC2, |
| _NC3, |
| _NC4, |
| _NC5, |
| _NC6, |
| _NC7, |
| _NC8, |
| _NC9, |
| _NC10, |
| _NC11, |
| _NC12, |
| _NC13, |
| _NC14, |
| _NC15, |
| _NC16, |
| _NC17, |
| _NC18, |
| _NC19, |
| _NC20, |
| _NC21, |
| _NC22, |
| _NC23, |
| _NC24, |
| _NC25, |
| _NC26, |
| _NC27, |
| _NC28, |
| _NC29, |
| _NC30, |
| _NC31, |
| _NC32}), |
| .wmask0({\mem0_mask_a[3] , |
| \mem0_mask_a[2] , |
| \mem0_mask_a[1] , |
| \mem0_mask_a[0] })); |
| sky130_sram_2kbyte_1rw1r_32x512_8 u_sram1_2kb (.csb0(\mem_cen_a[1] ), |
| .csb1(\mem_cen_b[1] ), |
| .web0(\mem_web_a[1] ), |
| .clk0(\mem_clk_a[1] ), |
| .clk1(\mem_clk_b[1] ), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .addr0({\mem1_addr_a[8] , |
| \mem1_addr_a[7] , |
| \mem1_addr_a[6] , |
| \mem1_addr_a[5] , |
| \mem1_addr_a[4] , |
| \mem1_addr_a[3] , |
| \mem1_addr_a[2] , |
| \mem1_addr_a[1] , |
| \mem1_addr_a[0] }), |
| .addr1({\mem1_addr_b[8] , |
| \mem1_addr_b[7] , |
| \mem1_addr_b[6] , |
| \mem1_addr_b[5] , |
| \mem1_addr_b[4] , |
| \mem1_addr_b[3] , |
| \mem1_addr_b[2] , |
| \mem1_addr_b[1] , |
| \mem1_addr_b[0] }), |
| .din0({\mem1_din_a[31] , |
| \mem1_din_a[30] , |
| \mem1_din_a[29] , |
| \mem1_din_a[28] , |
| \mem1_din_a[27] , |
| \mem1_din_a[26] , |
| \mem1_din_a[25] , |
| \mem1_din_a[24] , |
| \mem1_din_a[23] , |
| \mem1_din_a[22] , |
| \mem1_din_a[21] , |
| \mem1_din_a[20] , |
| \mem1_din_a[19] , |
| \mem1_din_a[18] , |
| \mem1_din_a[17] , |
| \mem1_din_a[16] , |
| \mem1_din_a[15] , |
| \mem1_din_a[14] , |
| \mem1_din_a[13] , |
| \mem1_din_a[12] , |
| \mem1_din_a[11] , |
| \mem1_din_a[10] , |
| \mem1_din_a[9] , |
| \mem1_din_a[8] , |
| \mem1_din_a[7] , |
| \mem1_din_a[6] , |
| \mem1_din_a[5] , |
| \mem1_din_a[4] , |
| \mem1_din_a[3] , |
| \mem1_din_a[2] , |
| \mem1_din_a[1] , |
| \mem1_din_a[0] }), |
| .dout0({\mem1_dout_a[31] , |
| \mem1_dout_a[30] , |
| \mem1_dout_a[29] , |
| \mem1_dout_a[28] , |
| \mem1_dout_a[27] , |
| \mem1_dout_a[26] , |
| \mem1_dout_a[25] , |
| \mem1_dout_a[24] , |
| \mem1_dout_a[23] , |
| \mem1_dout_a[22] , |
| \mem1_dout_a[21] , |
| \mem1_dout_a[20] , |
| \mem1_dout_a[19] , |
| \mem1_dout_a[18] , |
| \mem1_dout_a[17] , |
| \mem1_dout_a[16] , |
| \mem1_dout_a[15] , |
| \mem1_dout_a[14] , |
| \mem1_dout_a[13] , |
| \mem1_dout_a[12] , |
| \mem1_dout_a[11] , |
| \mem1_dout_a[10] , |
| \mem1_dout_a[9] , |
| \mem1_dout_a[8] , |
| \mem1_dout_a[7] , |
| \mem1_dout_a[6] , |
| \mem1_dout_a[5] , |
| \mem1_dout_a[4] , |
| \mem1_dout_a[3] , |
| \mem1_dout_a[2] , |
| \mem1_dout_a[1] , |
| \mem1_dout_a[0] }), |
| .dout1({_NC33, |
| _NC34, |
| _NC35, |
| _NC36, |
| _NC37, |
| _NC38, |
| _NC39, |
| _NC40, |
| _NC41, |
| _NC42, |
| _NC43, |
| _NC44, |
| _NC45, |
| _NC46, |
| _NC47, |
| _NC48, |
| _NC49, |
| _NC50, |
| _NC51, |
| _NC52, |
| _NC53, |
| _NC54, |
| _NC55, |
| _NC56, |
| _NC57, |
| _NC58, |
| _NC59, |
| _NC60, |
| _NC61, |
| _NC62, |
| _NC63, |
| _NC64}), |
| .wmask0({\mem1_mask_a[3] , |
| \mem1_mask_a[2] , |
| \mem1_mask_a[1] , |
| \mem1_mask_a[0] })); |
| sky130_sram_2kbyte_1rw1r_32x512_8 u_sram2_2kb (.csb0(\mem_cen_a[2] ), |
| .csb1(\mem_cen_b[2] ), |
| .web0(\mem_web_a[2] ), |
| .clk0(\mem_clk_a[2] ), |
| .clk1(\mem_clk_b[2] ), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .addr0({\mem2_addr_a[8] , |
| \mem2_addr_a[7] , |
| \mem2_addr_a[6] , |
| \mem2_addr_a[5] , |
| \mem2_addr_a[4] , |
| \mem2_addr_a[3] , |
| \mem2_addr_a[2] , |
| \mem2_addr_a[1] , |
| \mem2_addr_a[0] }), |
| .addr1({\mem2_addr_b[8] , |
| \mem2_addr_b[7] , |
| \mem2_addr_b[6] , |
| \mem2_addr_b[5] , |
| \mem2_addr_b[4] , |
| \mem2_addr_b[3] , |
| \mem2_addr_b[2] , |
| \mem2_addr_b[1] , |
| \mem2_addr_b[0] }), |
| .din0({\mem2_din_a[31] , |
| \mem2_din_a[30] , |
| \mem2_din_a[29] , |
| \mem2_din_a[28] , |
| \mem2_din_a[27] , |
| \mem2_din_a[26] , |
| \mem2_din_a[25] , |
| \mem2_din_a[24] , |
| \mem2_din_a[23] , |
| \mem2_din_a[22] , |
| \mem2_din_a[21] , |
| \mem2_din_a[20] , |
| \mem2_din_a[19] , |
| \mem2_din_a[18] , |
| \mem2_din_a[17] , |
| \mem2_din_a[16] , |
| \mem2_din_a[15] , |
| \mem2_din_a[14] , |
| \mem2_din_a[13] , |
| \mem2_din_a[12] , |
| \mem2_din_a[11] , |
| \mem2_din_a[10] , |
| \mem2_din_a[9] , |
| \mem2_din_a[8] , |
| \mem2_din_a[7] , |
| \mem2_din_a[6] , |
| \mem2_din_a[5] , |
| \mem2_din_a[4] , |
| \mem2_din_a[3] , |
| \mem2_din_a[2] , |
| \mem2_din_a[1] , |
| \mem2_din_a[0] }), |
| .dout0({\mem2_dout_a[31] , |
| \mem2_dout_a[30] , |
| \mem2_dout_a[29] , |
| \mem2_dout_a[28] , |
| \mem2_dout_a[27] , |
| \mem2_dout_a[26] , |
| \mem2_dout_a[25] , |
| \mem2_dout_a[24] , |
| \mem2_dout_a[23] , |
| \mem2_dout_a[22] , |
| \mem2_dout_a[21] , |
| \mem2_dout_a[20] , |
| \mem2_dout_a[19] , |
| \mem2_dout_a[18] , |
| \mem2_dout_a[17] , |
| \mem2_dout_a[16] , |
| \mem2_dout_a[15] , |
| \mem2_dout_a[14] , |
| \mem2_dout_a[13] , |
| \mem2_dout_a[12] , |
| \mem2_dout_a[11] , |
| \mem2_dout_a[10] , |
| \mem2_dout_a[9] , |
| \mem2_dout_a[8] , |
| \mem2_dout_a[7] , |
| \mem2_dout_a[6] , |
| \mem2_dout_a[5] , |
| \mem2_dout_a[4] , |
| \mem2_dout_a[3] , |
| \mem2_dout_a[2] , |
| \mem2_dout_a[1] , |
| \mem2_dout_a[0] }), |
| .dout1({_NC65, |
| _NC66, |
| _NC67, |
| _NC68, |
| _NC69, |
| _NC70, |
| _NC71, |
| _NC72, |
| _NC73, |
| _NC74, |
| _NC75, |
| _NC76, |
| _NC77, |
| _NC78, |
| _NC79, |
| _NC80, |
| _NC81, |
| _NC82, |
| _NC83, |
| _NC84, |
| _NC85, |
| _NC86, |
| _NC87, |
| _NC88, |
| _NC89, |
| _NC90, |
| _NC91, |
| _NC92, |
| _NC93, |
| _NC94, |
| _NC95, |
| _NC96}), |
| .wmask0({\mem2_mask_a[3] , |
| \mem2_mask_a[2] , |
| \mem2_mask_a[1] , |
| \mem2_mask_a[0] })); |
| sky130_sram_2kbyte_1rw1r_32x512_8 u_sram3_2kb (.csb0(\mem_cen_a[3] ), |
| .csb1(\mem_cen_b[3] ), |
| .web0(\mem_web_a[3] ), |
| .clk0(\mem_clk_a[3] ), |
| .clk1(\mem_clk_b[3] ), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .addr0({\mem3_addr_a[8] , |
| \mem3_addr_a[7] , |
| \mem3_addr_a[6] , |
| \mem3_addr_a[5] , |
| \mem3_addr_a[4] , |
| \mem3_addr_a[3] , |
| \mem3_addr_a[2] , |
| \mem3_addr_a[1] , |
| \mem3_addr_a[0] }), |
| .addr1({\mem3_addr_b[8] , |
| \mem3_addr_b[7] , |
| \mem3_addr_b[6] , |
| \mem3_addr_b[5] , |
| \mem3_addr_b[4] , |
| \mem3_addr_b[3] , |
| \mem3_addr_b[2] , |
| \mem3_addr_b[1] , |
| \mem3_addr_b[0] }), |
| .din0({\mem3_din_a[31] , |
| \mem3_din_a[30] , |
| \mem3_din_a[29] , |
| \mem3_din_a[28] , |
| \mem3_din_a[27] , |
| \mem3_din_a[26] , |
| \mem3_din_a[25] , |
| \mem3_din_a[24] , |
| \mem3_din_a[23] , |
| \mem3_din_a[22] , |
| \mem3_din_a[21] , |
| \mem3_din_a[20] , |
| \mem3_din_a[19] , |
| \mem3_din_a[18] , |
| \mem3_din_a[17] , |
| \mem3_din_a[16] , |
| \mem3_din_a[15] , |
| \mem3_din_a[14] , |
| \mem3_din_a[13] , |
| \mem3_din_a[12] , |
| \mem3_din_a[11] , |
| \mem3_din_a[10] , |
| \mem3_din_a[9] , |
| \mem3_din_a[8] , |
| \mem3_din_a[7] , |
| \mem3_din_a[6] , |
| \mem3_din_a[5] , |
| \mem3_din_a[4] , |
| \mem3_din_a[3] , |
| \mem3_din_a[2] , |
| \mem3_din_a[1] , |
| \mem3_din_a[0] }), |
| .dout0({\mem3_dout_a[31] , |
| \mem3_dout_a[30] , |
| \mem3_dout_a[29] , |
| \mem3_dout_a[28] , |
| \mem3_dout_a[27] , |
| \mem3_dout_a[26] , |
| \mem3_dout_a[25] , |
| \mem3_dout_a[24] , |
| \mem3_dout_a[23] , |
| \mem3_dout_a[22] , |
| \mem3_dout_a[21] , |
| \mem3_dout_a[20] , |
| \mem3_dout_a[19] , |
| \mem3_dout_a[18] , |
| \mem3_dout_a[17] , |
| \mem3_dout_a[16] , |
| \mem3_dout_a[15] , |
| \mem3_dout_a[14] , |
| \mem3_dout_a[13] , |
| \mem3_dout_a[12] , |
| \mem3_dout_a[11] , |
| \mem3_dout_a[10] , |
| \mem3_dout_a[9] , |
| \mem3_dout_a[8] , |
| \mem3_dout_a[7] , |
| \mem3_dout_a[6] , |
| \mem3_dout_a[5] , |
| \mem3_dout_a[4] , |
| \mem3_dout_a[3] , |
| \mem3_dout_a[2] , |
| \mem3_dout_a[1] , |
| \mem3_dout_a[0] }), |
| .dout1({_NC97, |
| _NC98, |
| _NC99, |
| _NC100, |
| _NC101, |
| _NC102, |
| _NC103, |
| _NC104, |
| _NC105, |
| _NC106, |
| _NC107, |
| _NC108, |
| _NC109, |
| _NC110, |
| _NC111, |
| _NC112, |
| _NC113, |
| _NC114, |
| _NC115, |
| _NC116, |
| _NC117, |
| _NC118, |
| _NC119, |
| _NC120, |
| _NC121, |
| _NC122, |
| _NC123, |
| _NC124, |
| _NC125, |
| _NC126, |
| _NC127, |
| _NC128}), |
| .wmask0({\mem3_mask_a[3] , |
| \mem3_mask_a[2] , |
| \mem3_mask_a[1] , |
| \mem3_mask_a[0] })); |
| sky130_sram_2kbyte_1rw1r_32x512_8 u_sram4_2kb (.csb0(\mem_cen_a[4] ), |
| .csb1(\mem_cen_b[4] ), |
| .web0(\mem_web_a[4] ), |
| .clk0(\mem_clk_a[4] ), |
| .clk1(\mem_clk_b[4] ), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .addr0({\mem4_addr_a[8] , |
| \mem4_addr_a[7] , |
| \mem4_addr_a[6] , |
| \mem4_addr_a[5] , |
| \mem4_addr_a[4] , |
| \mem4_addr_a[3] , |
| \mem4_addr_a[2] , |
| \mem4_addr_a[1] , |
| \mem4_addr_a[0] }), |
| .addr1({\mem4_addr_b[8] , |
| \mem4_addr_b[7] , |
| \mem4_addr_b[6] , |
| \mem4_addr_b[5] , |
| \mem4_addr_b[4] , |
| \mem4_addr_b[3] , |
| \mem4_addr_b[2] , |
| \mem4_addr_b[1] , |
| \mem4_addr_b[0] }), |
| .din0({\mem4_din_a[31] , |
| \mem4_din_a[30] , |
| \mem4_din_a[29] , |
| \mem4_din_a[28] , |
| \mem4_din_a[27] , |
| \mem4_din_a[26] , |
| \mem4_din_a[25] , |
| \mem4_din_a[24] , |
| \mem4_din_a[23] , |
| \mem4_din_a[22] , |
| \mem4_din_a[21] , |
| \mem4_din_a[20] , |
| \mem4_din_a[19] , |
| \mem4_din_a[18] , |
| \mem4_din_a[17] , |
| \mem4_din_a[16] , |
| \mem4_din_a[15] , |
| \mem4_din_a[14] , |
| \mem4_din_a[13] , |
| \mem4_din_a[12] , |
| \mem4_din_a[11] , |
| \mem4_din_a[10] , |
| \mem4_din_a[9] , |
| \mem4_din_a[8] , |
| \mem4_din_a[7] , |
| \mem4_din_a[6] , |
| \mem4_din_a[5] , |
| \mem4_din_a[4] , |
| \mem4_din_a[3] , |
| \mem4_din_a[2] , |
| \mem4_din_a[1] , |
| \mem4_din_a[0] }), |
| .dout0({\mem4_dout_a[31] , |
| \mem4_dout_a[30] , |
| \mem4_dout_a[29] , |
| \mem4_dout_a[28] , |
| \mem4_dout_a[27] , |
| \mem4_dout_a[26] , |
| \mem4_dout_a[25] , |
| \mem4_dout_a[24] , |
| \mem4_dout_a[23] , |
| \mem4_dout_a[22] , |
| \mem4_dout_a[21] , |
| \mem4_dout_a[20] , |
| \mem4_dout_a[19] , |
| \mem4_dout_a[18] , |
| \mem4_dout_a[17] , |
| \mem4_dout_a[16] , |
| \mem4_dout_a[15] , |
| \mem4_dout_a[14] , |
| \mem4_dout_a[13] , |
| \mem4_dout_a[12] , |
| \mem4_dout_a[11] , |
| \mem4_dout_a[10] , |
| \mem4_dout_a[9] , |
| \mem4_dout_a[8] , |
| \mem4_dout_a[7] , |
| \mem4_dout_a[6] , |
| \mem4_dout_a[5] , |
| \mem4_dout_a[4] , |
| \mem4_dout_a[3] , |
| \mem4_dout_a[2] , |
| \mem4_dout_a[1] , |
| \mem4_dout_a[0] }), |
| .dout1({_NC129, |
| _NC130, |
| _NC131, |
| _NC132, |
| _NC133, |
| _NC134, |
| _NC135, |
| _NC136, |
| _NC137, |
| _NC138, |
| _NC139, |
| _NC140, |
| _NC141, |
| _NC142, |
| _NC143, |
| _NC144, |
| _NC145, |
| _NC146, |
| _NC147, |
| _NC148, |
| _NC149, |
| _NC150, |
| _NC151, |
| _NC152, |
| _NC153, |
| _NC154, |
| _NC155, |
| _NC156, |
| _NC157, |
| _NC158, |
| _NC159, |
| _NC160}), |
| .wmask0({\mem4_mask_a[3] , |
| \mem4_mask_a[2] , |
| \mem4_mask_a[1] , |
| \mem4_mask_a[0] })); |
| sky130_sram_2kbyte_1rw1r_32x512_8 u_sram5_2kb (.csb0(\mem_cen_a[5] ), |
| .csb1(\mem_cen_b[5] ), |
| .web0(\mem_web_a[5] ), |
| .clk0(\mem_clk_a[5] ), |
| .clk1(\mem_clk_b[5] ), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .addr0({\mem5_addr_a[8] , |
| \mem5_addr_a[7] , |
| \mem5_addr_a[6] , |
| \mem5_addr_a[5] , |
| \mem5_addr_a[4] , |
| \mem5_addr_a[3] , |
| \mem5_addr_a[2] , |
| \mem5_addr_a[1] , |
| \mem5_addr_a[0] }), |
| .addr1({\mem5_addr_b[8] , |
| \mem5_addr_b[7] , |
| \mem5_addr_b[6] , |
| \mem5_addr_b[5] , |
| \mem5_addr_b[4] , |
| \mem5_addr_b[3] , |
| \mem5_addr_b[2] , |
| \mem5_addr_b[1] , |
| \mem5_addr_b[0] }), |
| .din0({\mem5_din_a[31] , |
| \mem5_din_a[30] , |
| \mem5_din_a[29] , |
| \mem5_din_a[28] , |
| \mem5_din_a[27] , |
| \mem5_din_a[26] , |
| \mem5_din_a[25] , |
| \mem5_din_a[24] , |
| \mem5_din_a[23] , |
| \mem5_din_a[22] , |
| \mem5_din_a[21] , |
| \mem5_din_a[20] , |
| \mem5_din_a[19] , |
| \mem5_din_a[18] , |
| \mem5_din_a[17] , |
| \mem5_din_a[16] , |
| \mem5_din_a[15] , |
| \mem5_din_a[14] , |
| \mem5_din_a[13] , |
| \mem5_din_a[12] , |
| \mem5_din_a[11] , |
| \mem5_din_a[10] , |
| \mem5_din_a[9] , |
| \mem5_din_a[8] , |
| \mem5_din_a[7] , |
| \mem5_din_a[6] , |
| \mem5_din_a[5] , |
| \mem5_din_a[4] , |
| \mem5_din_a[3] , |
| \mem5_din_a[2] , |
| \mem5_din_a[1] , |
| \mem5_din_a[0] }), |
| .dout0({\mem5_dout_a[31] , |
| \mem5_dout_a[30] , |
| \mem5_dout_a[29] , |
| \mem5_dout_a[28] , |
| \mem5_dout_a[27] , |
| \mem5_dout_a[26] , |
| \mem5_dout_a[25] , |
| \mem5_dout_a[24] , |
| \mem5_dout_a[23] , |
| \mem5_dout_a[22] , |
| \mem5_dout_a[21] , |
| \mem5_dout_a[20] , |
| \mem5_dout_a[19] , |
| \mem5_dout_a[18] , |
| \mem5_dout_a[17] , |
| \mem5_dout_a[16] , |
| \mem5_dout_a[15] , |
| \mem5_dout_a[14] , |
| \mem5_dout_a[13] , |
| \mem5_dout_a[12] , |
| \mem5_dout_a[11] , |
| \mem5_dout_a[10] , |
| \mem5_dout_a[9] , |
| \mem5_dout_a[8] , |
| \mem5_dout_a[7] , |
| \mem5_dout_a[6] , |
| \mem5_dout_a[5] , |
| \mem5_dout_a[4] , |
| \mem5_dout_a[3] , |
| \mem5_dout_a[2] , |
| \mem5_dout_a[1] , |
| \mem5_dout_a[0] }), |
| .dout1({_NC161, |
| _NC162, |
| _NC163, |
| _NC164, |
| _NC165, |
| _NC166, |
| _NC167, |
| _NC168, |
| _NC169, |
| _NC170, |
| _NC171, |
| _NC172, |
| _NC173, |
| _NC174, |
| _NC175, |
| _NC176, |
| _NC177, |
| _NC178, |
| _NC179, |
| _NC180, |
| _NC181, |
| _NC182, |
| _NC183, |
| _NC184, |
| _NC185, |
| _NC186, |
| _NC187, |
| _NC188, |
| _NC189, |
| _NC190, |
| _NC191, |
| _NC192}), |
| .wmask0({\mem5_mask_a[3] , |
| \mem5_mask_a[2] , |
| \mem5_mask_a[1] , |
| \mem5_mask_a[0] })); |
| sky130_sram_2kbyte_1rw1r_32x512_8 u_sram6_2kb (.csb0(\mem_cen_a[6] ), |
| .csb1(\mem_cen_b[6] ), |
| .web0(\mem_web_a[6] ), |
| .clk0(\mem_clk_a[6] ), |
| .clk1(\mem_clk_b[6] ), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .addr0({\mem6_addr_a[8] , |
| \mem6_addr_a[7] , |
| \mem6_addr_a[6] , |
| \mem6_addr_a[5] , |
| \mem6_addr_a[4] , |
| \mem6_addr_a[3] , |
| \mem6_addr_a[2] , |
| \mem6_addr_a[1] , |
| \mem6_addr_a[0] }), |
| .addr1({\mem6_addr_b[8] , |
| \mem6_addr_b[7] , |
| \mem6_addr_b[6] , |
| \mem6_addr_b[5] , |
| \mem6_addr_b[4] , |
| \mem6_addr_b[3] , |
| \mem6_addr_b[2] , |
| \mem6_addr_b[1] , |
| \mem6_addr_b[0] }), |
| .din0({\mem6_din_a[31] , |
| \mem6_din_a[30] , |
| \mem6_din_a[29] , |
| \mem6_din_a[28] , |
| \mem6_din_a[27] , |
| \mem6_din_a[26] , |
| \mem6_din_a[25] , |
| \mem6_din_a[24] , |
| \mem6_din_a[23] , |
| \mem6_din_a[22] , |
| \mem6_din_a[21] , |
| \mem6_din_a[20] , |
| \mem6_din_a[19] , |
| \mem6_din_a[18] , |
| \mem6_din_a[17] , |
| \mem6_din_a[16] , |
| \mem6_din_a[15] , |
| \mem6_din_a[14] , |
| \mem6_din_a[13] , |
| \mem6_din_a[12] , |
| \mem6_din_a[11] , |
| \mem6_din_a[10] , |
| \mem6_din_a[9] , |
| \mem6_din_a[8] , |
| \mem6_din_a[7] , |
| \mem6_din_a[6] , |
| \mem6_din_a[5] , |
| \mem6_din_a[4] , |
| \mem6_din_a[3] , |
| \mem6_din_a[2] , |
| \mem6_din_a[1] , |
| \mem6_din_a[0] }), |
| .dout0({\mem6_dout_a[31] , |
| \mem6_dout_a[30] , |
| \mem6_dout_a[29] , |
| \mem6_dout_a[28] , |
| \mem6_dout_a[27] , |
| \mem6_dout_a[26] , |
| \mem6_dout_a[25] , |
| \mem6_dout_a[24] , |
| \mem6_dout_a[23] , |
| \mem6_dout_a[22] , |
| \mem6_dout_a[21] , |
| \mem6_dout_a[20] , |
| \mem6_dout_a[19] , |
| \mem6_dout_a[18] , |
| \mem6_dout_a[17] , |
| \mem6_dout_a[16] , |
| \mem6_dout_a[15] , |
| \mem6_dout_a[14] , |
| \mem6_dout_a[13] , |
| \mem6_dout_a[12] , |
| \mem6_dout_a[11] , |
| \mem6_dout_a[10] , |
| \mem6_dout_a[9] , |
| \mem6_dout_a[8] , |
| \mem6_dout_a[7] , |
| \mem6_dout_a[6] , |
| \mem6_dout_a[5] , |
| \mem6_dout_a[4] , |
| \mem6_dout_a[3] , |
| \mem6_dout_a[2] , |
| \mem6_dout_a[1] , |
| \mem6_dout_a[0] }), |
| .dout1({_NC193, |
| _NC194, |
| _NC195, |
| _NC196, |
| _NC197, |
| _NC198, |
| _NC199, |
| _NC200, |
| _NC201, |
| _NC202, |
| _NC203, |
| _NC204, |
| _NC205, |
| _NC206, |
| _NC207, |
| _NC208, |
| _NC209, |
| _NC210, |
| _NC211, |
| _NC212, |
| _NC213, |
| _NC214, |
| _NC215, |
| _NC216, |
| _NC217, |
| _NC218, |
| _NC219, |
| _NC220, |
| _NC221, |
| _NC222, |
| _NC223, |
| _NC224}), |
| .wmask0({\mem6_mask_a[3] , |
| \mem6_mask_a[2] , |
| \mem6_mask_a[1] , |
| \mem6_mask_a[0] })); |
| sky130_sram_2kbyte_1rw1r_32x512_8 u_sram7_2kb (.csb0(\mem_cen_a[7] ), |
| .csb1(\mem_cen_b[7] ), |
| .web0(\mem_web_a[7] ), |
| .clk0(\mem_clk_a[7] ), |
| .clk1(\mem_clk_b[7] ), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .addr0({\mem7_addr_a[8] , |
| \mem7_addr_a[7] , |
| \mem7_addr_a[6] , |
| \mem7_addr_a[5] , |
| \mem7_addr_a[4] , |
| \mem7_addr_a[3] , |
| \mem7_addr_a[2] , |
| \mem7_addr_a[1] , |
| \mem7_addr_a[0] }), |
| .addr1({\mem7_addr_b[8] , |
| \mem7_addr_b[7] , |
| \mem7_addr_b[6] , |
| \mem7_addr_b[5] , |
| \mem7_addr_b[4] , |
| \mem7_addr_b[3] , |
| \mem7_addr_b[2] , |
| \mem7_addr_b[1] , |
| \mem7_addr_b[0] }), |
| .din0({\mem7_din_a[31] , |
| \mem7_din_a[30] , |
| \mem7_din_a[29] , |
| \mem7_din_a[28] , |
| \mem7_din_a[27] , |
| \mem7_din_a[26] , |
| \mem7_din_a[25] , |
| \mem7_din_a[24] , |
| \mem7_din_a[23] , |
| \mem7_din_a[22] , |
| \mem7_din_a[21] , |
| \mem7_din_a[20] , |
| \mem7_din_a[19] , |
| \mem7_din_a[18] , |
| \mem7_din_a[17] , |
| \mem7_din_a[16] , |
| \mem7_din_a[15] , |
| \mem7_din_a[14] , |
| \mem7_din_a[13] , |
| \mem7_din_a[12] , |
| \mem7_din_a[11] , |
| \mem7_din_a[10] , |
| \mem7_din_a[9] , |
| \mem7_din_a[8] , |
| \mem7_din_a[7] , |
| \mem7_din_a[6] , |
| \mem7_din_a[5] , |
| \mem7_din_a[4] , |
| \mem7_din_a[3] , |
| \mem7_din_a[2] , |
| \mem7_din_a[1] , |
| \mem7_din_a[0] }), |
| .dout0({\mem7_dout_a[31] , |
| \mem7_dout_a[30] , |
| \mem7_dout_a[29] , |
| \mem7_dout_a[28] , |
| \mem7_dout_a[27] , |
| \mem7_dout_a[26] , |
| \mem7_dout_a[25] , |
| \mem7_dout_a[24] , |
| \mem7_dout_a[23] , |
| \mem7_dout_a[22] , |
| \mem7_dout_a[21] , |
| \mem7_dout_a[20] , |
| \mem7_dout_a[19] , |
| \mem7_dout_a[18] , |
| \mem7_dout_a[17] , |
| \mem7_dout_a[16] , |
| \mem7_dout_a[15] , |
| \mem7_dout_a[14] , |
| \mem7_dout_a[13] , |
| \mem7_dout_a[12] , |
| \mem7_dout_a[11] , |
| \mem7_dout_a[10] , |
| \mem7_dout_a[9] , |
| \mem7_dout_a[8] , |
| \mem7_dout_a[7] , |
| \mem7_dout_a[6] , |
| \mem7_dout_a[5] , |
| \mem7_dout_a[4] , |
| \mem7_dout_a[3] , |
| \mem7_dout_a[2] , |
| \mem7_dout_a[1] , |
| \mem7_dout_a[0] }), |
| .dout1({_NC225, |
| _NC226, |
| _NC227, |
| _NC228, |
| _NC229, |
| _NC230, |
| _NC231, |
| _NC232, |
| _NC233, |
| _NC234, |
| _NC235, |
| _NC236, |
| _NC237, |
| _NC238, |
| _NC239, |
| _NC240, |
| _NC241, |
| _NC242, |
| _NC243, |
| _NC244, |
| _NC245, |
| _NC246, |
| _NC247, |
| _NC248, |
| _NC249, |
| _NC250, |
| _NC251, |
| _NC252, |
| _NC253, |
| _NC254, |
| _NC255, |
| _NC256}), |
| .wmask0({\mem7_mask_a[3] , |
| \mem7_mask_a[2] , |
| \mem7_mask_a[1] , |
| \mem7_mask_a[0] })); |
| wb_host u_wb_host (.bist_rst_n(bist_rst_n), |
| .lbist_clk_int(lbist_clk), |
| .lbist_clk_out(lbist_clk), |
| .mac_rst_n(mac_rst_n), |
| .scan_clk(scan_clk), |
| .scan_en(scan_en), |
| .scan_mode(scan_mode), |
| .scan_rst_n(scan_rst_n), |
| .sclk(sspis_sck), |
| .sdin(sspis_si), |
| .sdout(sspis_so), |
| .ssn(sspis_ssn), |
| .uartm_rxd(uartm_rxd), |
| .uartm_txd(uartm_txd), |
| .user_clock1(wb_clk_i), |
| .user_clock2(user_clock2), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .wbd_clk_int(wbd_clk_int), |
| .wbd_clk_wh(wbd_clk_wh), |
| .wbd_int_rst_n(wbd_int_rst_n), |
| .wbm_ack_o(wbs_ack_int_o), |
| .wbm_clk_i(\ch_out_south[0] ), |
| .wbm_cyc_i(\ch_out_south[3] ), |
| .wbm_rst_i(\ch_out_south[1] ), |
| .wbm_stb_i(\ch_out_south[4] ), |
| .wbm_we_i(\ch_out_south[5] ), |
| .wbs_ack_i(wbd_int_ack_o), |
| .wbs_clk_i(wbd_clk_wh), |
| .wbs_clk_out(wbd_clk_int), |
| .wbs_cyc_o(wbd_int_cyc_i), |
| .wbs_err_i(wbd_int_err_o), |
| .wbs_stb_o(wbd_int_stb_i), |
| .wbs_we_o(wbd_int_we_i), |
| .cfg_clk_ctrl1({\cfg_clk_ctrl1[31] , |
| \cfg_clk_ctrl1[30] , |
| \cfg_clk_ctrl1[29] , |
| \cfg_clk_ctrl1[28] , |
| \cfg_clk_ctrl1[27] , |
| \cfg_clk_ctrl1[26] , |
| \cfg_clk_ctrl1[25] , |
| \cfg_clk_ctrl1[24] , |
| \cfg_clk_ctrl1[23] , |
| \cfg_clk_ctrl1[22] , |
| \cfg_clk_ctrl1[21] , |
| \cfg_clk_ctrl1[20] , |
| \cfg_clk_ctrl1[19] , |
| \cfg_clk_ctrl1[18] , |
| \cfg_clk_ctrl1[17] , |
| \cfg_clk_ctrl1[16] , |
| \cfg_clk_ctrl1[15] , |
| \cfg_clk_ctrl1[14] , |
| \cfg_clk_ctrl1[13] , |
| \cfg_clk_ctrl1[12] , |
| \cfg_clk_ctrl1[11] , |
| \cfg_clk_ctrl1[10] , |
| \cfg_clk_ctrl1[9] , |
| \cfg_clk_ctrl1[8] , |
| \cfg_clk_ctrl1[7] , |
| \cfg_clk_ctrl1[6] , |
| \cfg_clk_ctrl1[5] , |
| \cfg_clk_ctrl1[4] , |
| \cfg_clk_ctrl1[3] , |
| \cfg_clk_ctrl1[2] , |
| \cfg_clk_ctrl1[1] , |
| \cfg_clk_ctrl1[0] }), |
| .cfg_clk_ctrl2({\cfg_clk_ctrl2[31] , |
| \cfg_clk_ctrl2[30] , |
| \cfg_clk_ctrl2[29] , |
| \cfg_clk_ctrl2[28] , |
| \cfg_clk_ctrl2[27] , |
| \cfg_clk_ctrl2[26] , |
| \cfg_clk_ctrl2[25] , |
| \cfg_clk_ctrl2[24] , |
| \cfg_clk_ctrl2[23] , |
| \cfg_clk_ctrl2[22] , |
| \cfg_clk_ctrl2[21] , |
| \cfg_clk_ctrl2[20] , |
| \cfg_clk_ctrl2[19] , |
| \cfg_clk_ctrl2[18] , |
| \cfg_clk_ctrl2[17] , |
| \cfg_clk_ctrl2[16] , |
| \cfg_clk_ctrl2[15] , |
| \cfg_clk_ctrl2[14] , |
| \cfg_clk_ctrl2[13] , |
| \cfg_clk_ctrl2[12] , |
| \cfg_clk_ctrl2[11] , |
| \cfg_clk_ctrl2[10] , |
| \cfg_clk_ctrl2[9] , |
| \cfg_clk_ctrl2[8] , |
| \cfg_clk_ctrl2[7] , |
| \cfg_clk_ctrl2[6] , |
| \cfg_clk_ctrl2[5] , |
| \cfg_clk_ctrl2[4] , |
| \cfg_clk_ctrl2[3] , |
| \cfg_clk_ctrl2[2] , |
| \cfg_clk_ctrl2[1] , |
| \cfg_clk_ctrl2[0] }), |
| .cfg_cska_lbist({\cfg_clk_ctrl1[15] , |
| \cfg_clk_ctrl1[14] , |
| \cfg_clk_ctrl1[13] , |
| \cfg_clk_ctrl1[12] }), |
| .cfg_cska_wh({\cfg_clk_ctrl1[3] , |
| \cfg_clk_ctrl1[2] , |
| \cfg_clk_ctrl1[1] , |
| \cfg_clk_ctrl1[0] }), |
| .la_data_in({\ch_out_south[176] , |
| \ch_out_south[174] , |
| \ch_out_south[172] , |
| \ch_out_south[170] , |
| \ch_out_south[168] , |
| \ch_out_south[166] , |
| \ch_out_south[164] , |
| \ch_out_south[162] , |
| \ch_out_south[160] , |
| \ch_out_south[158] , |
| \ch_out_south[156] , |
| \ch_out_south[154] , |
| \ch_out_south[152] , |
| \ch_out_south[150] , |
| \ch_out_south[148] , |
| \ch_out_south[146] , |
| \ch_out_south[144] , |
| \ch_out_south[142] , |
| \ch_out_south[140] , |
| \ch_out_south[138] , |
| \ch_out_south[136] , |
| \ch_out_south[134] , |
| \ch_out_south[132] , |
| \ch_out_south[130] , |
| \ch_out_south[128] , |
| \ch_out_south[126] , |
| \ch_out_south[124] , |
| \ch_out_south[122] , |
| \ch_out_south[120] , |
| \ch_out_south[118] , |
| \ch_out_south[116] , |
| \ch_out_south[114] , |
| \ch_out_south[112] , |
| \ch_out_south[110] , |
| \ch_out_south[108] , |
| \ch_out_south[106] }), |
| .la_data_out({\la_data_out_int[127] , |
| \la_data_out_int[126] , |
| \la_data_out_int[125] , |
| \la_data_out_int[124] , |
| \la_data_out_int[123] , |
| \la_data_out_int[122] , |
| \la_data_out_int[121] , |
| \la_data_out_int[120] , |
| \la_data_out_int[119] , |
| \la_data_out_int[118] , |
| \la_data_out_int[117] , |
| \la_data_out_int[116] , |
| \la_data_out_int[115] , |
| \la_data_out_int[114] , |
| \la_data_out_int[113] , |
| \la_data_out_int[112] , |
| \la_data_out_int[111] , |
| \la_data_out_int[110] , |
| \la_data_out_int[109] , |
| \la_data_out_int[108] , |
| \la_data_out_int[107] , |
| \la_data_out_int[106] , |
| \la_data_out_int[105] , |
| \la_data_out_int[104] , |
| \la_data_out_int[103] , |
| \la_data_out_int[102] , |
| \la_data_out_int[101] , |
| \la_data_out_int[100] , |
| \la_data_out_int[99] , |
| \la_data_out_int[98] , |
| \la_data_out_int[97] , |
| \la_data_out_int[96] , |
| \la_data_out_int[95] , |
| \la_data_out_int[94] , |
| \la_data_out_int[93] , |
| \la_data_out_int[92] , |
| \la_data_out_int[91] , |
| \la_data_out_int[90] , |
| \la_data_out_int[89] , |
| \la_data_out_int[88] , |
| \la_data_out_int[87] , |
| \la_data_out_int[86] , |
| \la_data_out_int[85] , |
| \la_data_out_int[84] , |
| \la_data_out_int[83] , |
| \la_data_out_int[82] , |
| \la_data_out_int[81] , |
| \la_data_out_int[80] , |
| \la_data_out_int[79] , |
| \la_data_out_int[78] , |
| \la_data_out_int[77] , |
| \la_data_out_int[76] , |
| \la_data_out_int[75] , |
| \la_data_out_int[74] , |
| \la_data_out_int[73] , |
| \la_data_out_int[72] , |
| \la_data_out_int[71] , |
| \la_data_out_int[70] , |
| \la_data_out_int[69] , |
| \la_data_out_int[68] , |
| \la_data_out_int[67] , |
| \la_data_out_int[66] , |
| \la_data_out_int[65] , |
| \la_data_out_int[64] , |
| \la_data_out_int[63] , |
| \la_data_out_int[62] , |
| \la_data_out_int[61] , |
| \la_data_out_int[60] , |
| \la_data_out_int[59] , |
| \la_data_out_int[58] , |
| \la_data_out_int[57] , |
| \la_data_out_int[56] , |
| \la_data_out_int[55] , |
| \la_data_out_int[54] , |
| \la_data_out_int[53] , |
| \la_data_out_int[52] , |
| \la_data_out_int[51] , |
| \la_data_out_int[50] , |
| \la_data_out_int[49] , |
| \la_data_out_int[48] , |
| \la_data_out_int[47] , |
| \la_data_out_int[46] , |
| \la_data_out_int[45] , |
| \la_data_out_int[44] , |
| \la_data_out_int[43] , |
| \la_data_out_int[42] , |
| \la_data_out_int[41] , |
| \la_data_out_int[40] , |
| \la_data_out_int[39] , |
| \la_data_out_int[38] , |
| \la_data_out_int[37] , |
| \la_data_out_int[36] , |
| \la_data_out_int[35] , |
| \la_data_out_int[34] , |
| \la_data_out_int[33] , |
| \la_data_out_int[32] , |
| \la_data_out_int[31] , |
| \la_data_out_int[30] , |
| \la_data_out_int[29] , |
| \la_data_out_int[28] , |
| \la_data_out_int[27] , |
| \la_data_out_int[26] , |
| \la_data_out_int[25] , |
| \la_data_out_int[24] , |
| \la_data_out_int[23] , |
| \la_data_out_int[22] , |
| \la_data_out_int[21] , |
| \la_data_out_int[20] , |
| \la_data_out_int[19] , |
| \la_data_out_int[18] , |
| \la_data_out_int[17] , |
| \la_data_out_int[16] , |
| \la_data_out_int[15] , |
| \la_data_out_int[14] , |
| \la_data_out_int[13] , |
| \la_data_out_int[12] , |
| \la_data_out_int[11] , |
| \la_data_out_int[10] , |
| \la_data_out_int[9] , |
| \la_data_out_int[8] , |
| \la_data_out_int[7] , |
| \la_data_out_int[6] , |
| \la_data_out_int[5] , |
| \la_data_out_int[4] , |
| \la_data_out_int[3] , |
| \la_data_out_int[2] , |
| \la_data_out_int[1] , |
| \la_data_out_int[0] }), |
| .scan_in({\scan_in[7] , |
| \scan_in[6] , |
| \scan_in[5] , |
| \scan_in[4] , |
| \scan_in[3] , |
| \scan_in[2] , |
| \scan_in[1] , |
| \scan_in[0] }), |
| .scan_out({\scan_so_mac[7] , |
| \scan_so_mac[6] , |
| \scan_so_mac[5] , |
| \scan_so_mac[4] , |
| \scan_so_mac[3] , |
| \scan_so_mac[2] , |
| \scan_so_mac[1] , |
| \scan_so_mac[0] }), |
| .user_irq({user_irq[2], |
| user_irq[1], |
| user_irq[0]}), |
| .wbm_adr_i({\ch_out_south[103] , |
| \ch_out_south[100] , |
| \ch_out_south[97] , |
| \ch_out_south[94] , |
| \ch_out_south[91] , |
| \ch_out_south[88] , |
| \ch_out_south[85] , |
| \ch_out_south[82] , |
| \ch_out_south[79] , |
| \ch_out_south[76] , |
| \ch_out_south[73] , |
| \ch_out_south[70] , |
| \ch_out_south[67] , |
| \ch_out_south[64] , |
| \ch_out_south[61] , |
| \ch_out_south[58] , |
| \ch_out_south[55] , |
| \ch_out_south[52] , |
| \ch_out_south[49] , |
| \ch_out_south[46] , |
| \ch_out_south[43] , |
| \ch_out_south[40] , |
| \ch_out_south[37] , |
| \ch_out_south[34] , |
| \ch_out_south[31] , |
| \ch_out_south[28] , |
| \ch_out_south[25] , |
| \ch_out_south[22] , |
| \ch_out_south[18] , |
| \ch_out_south[14] , |
| \ch_out_south[10] , |
| \ch_out_south[6] }), |
| .wbm_dat_i({\ch_out_south[104] , |
| \ch_out_south[101] , |
| \ch_out_south[98] , |
| \ch_out_south[95] , |
| \ch_out_south[92] , |
| \ch_out_south[89] , |
| \ch_out_south[86] , |
| \ch_out_south[83] , |
| \ch_out_south[80] , |
| \ch_out_south[77] , |
| \ch_out_south[74] , |
| \ch_out_south[71] , |
| \ch_out_south[68] , |
| \ch_out_south[65] , |
| \ch_out_south[62] , |
| \ch_out_south[59] , |
| \ch_out_south[56] , |
| \ch_out_south[53] , |
| \ch_out_south[50] , |
| \ch_out_south[47] , |
| \ch_out_south[44] , |
| \ch_out_south[41] , |
| \ch_out_south[38] , |
| \ch_out_south[35] , |
| \ch_out_south[32] , |
| \ch_out_south[29] , |
| \ch_out_south[26] , |
| \ch_out_south[23] , |
| \ch_out_south[19] , |
| \ch_out_south[15] , |
| \ch_out_south[11] , |
| \ch_out_south[7] }), |
| .wbm_dat_o({\wbs_dat_int_o[31] , |
| \wbs_dat_int_o[30] , |
| \wbs_dat_int_o[29] , |
| \wbs_dat_int_o[28] , |
| \wbs_dat_int_o[27] , |
| \wbs_dat_int_o[26] , |
| \wbs_dat_int_o[25] , |
| \wbs_dat_int_o[24] , |
| \wbs_dat_int_o[23] , |
| \wbs_dat_int_o[22] , |
| \wbs_dat_int_o[21] , |
| \wbs_dat_int_o[20] , |
| \wbs_dat_int_o[19] , |
| \wbs_dat_int_o[18] , |
| \wbs_dat_int_o[17] , |
| \wbs_dat_int_o[16] , |
| \wbs_dat_int_o[15] , |
| \wbs_dat_int_o[14] , |
| \wbs_dat_int_o[13] , |
| \wbs_dat_int_o[12] , |
| \wbs_dat_int_o[11] , |
| \wbs_dat_int_o[10] , |
| \wbs_dat_int_o[9] , |
| \wbs_dat_int_o[8] , |
| \wbs_dat_int_o[7] , |
| \wbs_dat_int_o[6] , |
| \wbs_dat_int_o[5] , |
| \wbs_dat_int_o[4] , |
| \wbs_dat_int_o[3] , |
| \wbs_dat_int_o[2] , |
| \wbs_dat_int_o[1] , |
| \wbs_dat_int_o[0] }), |
| .wbm_sel_i({\ch_out_south[21] , |
| \ch_out_south[17] , |
| \ch_out_south[13] , |
| \ch_out_south[9] }), |
| .wbs_adr_o({\wbd_int_adr_i[31] , |
| \wbd_int_adr_i[30] , |
| \wbd_int_adr_i[29] , |
| \wbd_int_adr_i[28] , |
| \wbd_int_adr_i[27] , |
| \wbd_int_adr_i[26] , |
| \wbd_int_adr_i[25] , |
| \wbd_int_adr_i[24] , |
| \wbd_int_adr_i[23] , |
| \wbd_int_adr_i[22] , |
| \wbd_int_adr_i[21] , |
| \wbd_int_adr_i[20] , |
| \wbd_int_adr_i[19] , |
| \wbd_int_adr_i[18] , |
| \wbd_int_adr_i[17] , |
| \wbd_int_adr_i[16] , |
| \wbd_int_adr_i[15] , |
| \wbd_int_adr_i[14] , |
| \wbd_int_adr_i[13] , |
| \wbd_int_adr_i[12] , |
| \wbd_int_adr_i[11] , |
| \wbd_int_adr_i[10] , |
| \wbd_int_adr_i[9] , |
| \wbd_int_adr_i[8] , |
| \wbd_int_adr_i[7] , |
| \wbd_int_adr_i[6] , |
| \wbd_int_adr_i[5] , |
| \wbd_int_adr_i[4] , |
| \wbd_int_adr_i[3] , |
| \wbd_int_adr_i[2] , |
| \wbd_int_adr_i[1] , |
| \wbd_int_adr_i[0] }), |
| .wbs_dat_i({\wbd_int_dat_o[31] , |
| \wbd_int_dat_o[30] , |
| \wbd_int_dat_o[29] , |
| \wbd_int_dat_o[28] , |
| \wbd_int_dat_o[27] , |
| \wbd_int_dat_o[26] , |
| \wbd_int_dat_o[25] , |
| \wbd_int_dat_o[24] , |
| \wbd_int_dat_o[23] , |
| \wbd_int_dat_o[22] , |
| \wbd_int_dat_o[21] , |
| \wbd_int_dat_o[20] , |
| \wbd_int_dat_o[19] , |
| \wbd_int_dat_o[18] , |
| \wbd_int_dat_o[17] , |
| \wbd_int_dat_o[16] , |
| \wbd_int_dat_o[15] , |
| \wbd_int_dat_o[14] , |
| \wbd_int_dat_o[13] , |
| \wbd_int_dat_o[12] , |
| \wbd_int_dat_o[11] , |
| \wbd_int_dat_o[10] , |
| \wbd_int_dat_o[9] , |
| \wbd_int_dat_o[8] , |
| \wbd_int_dat_o[7] , |
| \wbd_int_dat_o[6] , |
| \wbd_int_dat_o[5] , |
| \wbd_int_dat_o[4] , |
| \wbd_int_dat_o[3] , |
| \wbd_int_dat_o[2] , |
| \wbd_int_dat_o[1] , |
| \wbd_int_dat_o[0] }), |
| .wbs_dat_o({\wbd_int_dat_i[31] , |
| \wbd_int_dat_i[30] , |
| \wbd_int_dat_i[29] , |
| \wbd_int_dat_i[28] , |
| \wbd_int_dat_i[27] , |
| \wbd_int_dat_i[26] , |
| \wbd_int_dat_i[25] , |
| \wbd_int_dat_i[24] , |
| \wbd_int_dat_i[23] , |
| \wbd_int_dat_i[22] , |
| \wbd_int_dat_i[21] , |
| \wbd_int_dat_i[20] , |
| \wbd_int_dat_i[19] , |
| \wbd_int_dat_i[18] , |
| \wbd_int_dat_i[17] , |
| \wbd_int_dat_i[16] , |
| \wbd_int_dat_i[15] , |
| \wbd_int_dat_i[14] , |
| \wbd_int_dat_i[13] , |
| \wbd_int_dat_i[12] , |
| \wbd_int_dat_i[11] , |
| \wbd_int_dat_i[10] , |
| \wbd_int_dat_i[9] , |
| \wbd_int_dat_i[8] , |
| \wbd_int_dat_i[7] , |
| \wbd_int_dat_i[6] , |
| \wbd_int_dat_i[5] , |
| \wbd_int_dat_i[4] , |
| \wbd_int_dat_i[3] , |
| \wbd_int_dat_i[2] , |
| \wbd_int_dat_i[1] , |
| \wbd_int_dat_i[0] }), |
| .wbs_sel_o({\wbd_int_sel_i[3] , |
| \wbd_int_sel_i[2] , |
| \wbd_int_sel_i[1] , |
| \wbd_int_sel_i[0] })); |
| endmodule |
