mpw_precheck/logs/spdx_compliance_report.log

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/root/riscduino-pxt1/openlane/scripts/scan_connect.tcl
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/root/riscduino-pxt1/openlane/user_project_wrapper/interactive.tcl
/root/riscduino-pxt1/openlane/user_project_wrapper/pdn_cfg.tcl
/root/riscduino-pxt1/openlane/wb_host/base.sdc
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/root/riscduino-pxt1/openlane/wb_interconnect/base.sdc
/root/riscduino-pxt1/sdc/bus_rep_east.sdc
/root/riscduino-pxt1/sdc/bus_rep_north.sdc
/root/riscduino-pxt1/sdc/bus_rep_south.sdc
/root/riscduino-pxt1/sdc/bus_rep_west.sdc
/root/riscduino-pxt1/sdc/caravel.sdc
/root/riscduino-pxt1/sdc/glbl_cfg.sdc
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/root/riscduino-pxt1/sdc/mbist_top1.sdc
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/root/riscduino-pxt1/sdc/mbist_wrapper.sdc
/root/riscduino-pxt1/sdc/pinmux_top.sdc
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/root/riscduino-pxt1/sdc/wb_host.sdc
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/root/riscduino-pxt1/verilog/rtl/gmac/crc32/g_rx_crc32.v
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/root/riscduino-pxt1/verilog/rtl/gmac/ctrl/eth_parser.v
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/root/riscduino-pxt1/verilog/rtl/gmac/mac/g_tx_top.v
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/root/riscduino-pxt1/verilog/rtl/gmac/top/g_mac_top.v
/root/riscduino-pxt1/verilog/rtl/lbist/src/lbist_top.sv
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/root/riscduino-pxt1/verilog/rtl/lib/async_fifo.v
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/root/riscduino-pxt1/verilog/rtl/lib/dble_reg.v
/root/riscduino-pxt1/verilog/rtl/lib/g_dpath_ctrl.v
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/root/riscduino-pxt1/verilog/rtl/lib/stat_counter.v
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/root/riscduino-pxt1/verilog/rtl/lib/wb_crossbar.v
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/root/riscduino-pxt1/verilog/rtl/mac_wrapper/src/mac_wrapper.sv
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/root/riscduino-pxt1/verilog/rtl/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v
/root/riscduino-pxt1/verilog/rtl/uart2wb/src/run_verilog
/root/riscduino-pxt1/verilog/rtl/uart2wb/src/uart_auto_det.sv
/root/riscduino-pxt1/verilog/rtl/uart2wb/src/uart_msg_handler.v
/root/riscduino-pxt1/verilog/rtl/wb_host/src/run_iverilog
/root/riscduino-pxt1/verilog/rtl/wb_host/src/run_verilator
/root/riscduino-pxt1/verilog/rtl/wb_interconnect/src/run_iverilog
/root/riscduino-pxt1/verilog/rtl/wb_interconnect/src/run_verilator