first version
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..2090a6a
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,337 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+MAKEFLAGS+=--warn-undefined-variables
+
+export CARAVEL_ROOT?=$(PWD)/caravel
+PRECHECK_ROOT?=${HOME}/mpw_precheck
+export MCW_ROOT?=$(PWD)/mgmt_core_wrapper
+SIM?=RTL
+DUMP?=OFF
+RISC_CORE ?=0
+
+# Install lite version of caravel, (1): caravel-lite, (0): caravel
+CARAVEL_LITE?=1
+
+# PDK switch varient
+export PDK?=sky130A
+#export PDK?=gf180mcuC
+export PDKPATH?=$(PDK_ROOT)/$(PDK)
+
+
+
+ifeq ($(PDK),sky130A)
+ SKYWATER_COMMIT=f70d8ca46961ff92719d8870a18a076370b85f6c
+ export OPEN_PDKS_COMMIT?=0059588eebfc704681dc2368bd1d33d96281d10f
+ export OPENLANE_TAG?=2022.10.20
+ MPW_TAG ?= mpw-7g
+
+ifeq ($(CARAVEL_LITE),1)
+ CARAVEL_NAME := caravel-lite
+ CARAVEL_REPO := https://github.com/efabless/caravel-lite
+ CARAVEL_TAG := $(MPW_TAG)
+else
+ CARAVEL_NAME := caravel
+ CARAVEL_REPO := https://github.com/efabless/caravel
+ CARAVEL_TAG := $(MPW_TAG)
+endif
+
+endif
+
+#RISCV COMPLIANCE test Environment
+COREMARK_DIR = verilog/dv/riscv_regress/dependencies/coremark
+RISCV_COMP_DIR = verilog/dv/riscv_regress/dependencies/riscv-compliance
+RISCV_TEST_DIR = verilog/dv/riscv_regress/dependencies/riscv-tests
+
+COREMARK_REPO = https://github.com/eembc/coremark
+RISCV_COMP_REPO = https://github.com/riscv/riscv-compliance
+RISCV_TEST_REPO = https://github.com/riscv/riscv-tests
+
+COREMARK_BRANCH = 7f420b6bdbff436810ef75381059944e2b0d79e8
+RISCV_COMP_BRANCH = d51259b2a949be3af02e776c39e135402675ac9b
+RISCV_TEST_BRANCH = e30978a71921159aec38eeefd848fca4ed39a826
+
+ifeq ($(PDK),sky130B)
+ SKYWATER_COMMIT=f70d8ca46961ff92719d8870a18a076370b85f6c
+ export OPEN_PDKS_COMMIT?=0059588eebfc704681dc2368bd1d33d96281d10f
+ export OPENLANE_TAG?=2022.10.20
+ MPW_TAG ?= mpw-7g
+
+ifeq ($(CARAVEL_LITE),1)
+ CARAVEL_NAME := caravel-lite
+ CARAVEL_REPO := https://github.com/efabless/caravel-lite
+ CARAVEL_TAG := $(MPW_TAG)
+else
+ CARAVEL_NAME := caravel
+ CARAVEL_REPO := https://github.com/efabless/caravel
+ CARAVEL_TAG := $(MPW_TAG)
+endif
+
+endif
+
+ifeq ($(PDK),gf180mcuC)
+
+ MPW_TAG ?= gfmpw-0a
+ CARAVEL_NAME := caravel
+ CARAVEL_REPO := https://github.com/efabless/caravel-gf180mcu
+ CARAVEL_TAG := $(MPW_TAG)
+ #OPENLANE_TAG=ddfeab57e3e8769ea3d40dda12be0460e09bb6d9
+ export OPEN_PDKS_COMMIT?=0059588eebfc704681dc2368bd1d33d96281d10f
+ export OPENLANE_TAG?=2022.11.17
+
+endif
+
+# Include Caravel Makefile Targets
+.PHONY: % : check-caravel
+%:
+ export CARAVEL_ROOT=$(CARAVEL_ROOT) && $(MAKE) -f $(CARAVEL_ROOT)/Makefile $@
+
+.PHONY: install
+install:
+ if [ -d "$(CARAVEL_ROOT)" ]; then\
+ echo "Deleting exisiting $(CARAVEL_ROOT)" && \
+ rm -rf $(CARAVEL_ROOT) && sleep 2;\
+ fi
+ echo "Installing $(CARAVEL_NAME).."
+ git clone -b $(CARAVEL_TAG) $(CARAVEL_REPO) $(CARAVEL_ROOT) --depth=1
+
+# Install DV setup
+.PHONY: simenv
+simenv:
+ docker pull riscduino/dv_setup:mpw7
+
+.PHONY: setup
+setup: install check-env install_mcw openlane pdk-with-volare setup-timing-scripts
+
+# Openlane
+blocks=$(shell cd openlane && find * -maxdepth 0 -type d)
+.PHONY: $(blocks)
+$(blocks): % :
+ $(MAKE) -C openlane $*
+
+
+PATTERNS=$(shell cd verilog/dv && find * -maxdepth 0 -type d)
+DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
+TARGET_PATH=$(shell pwd)
+verify_command="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} DUMP=${DUMP} RISC_CORE=${RISC_CORE} && make"
+$(DV_PATTERNS): verify-% : ./verilog/dv/% check-coremark_repo check-riscv_comp_repo check-riscv_test_repo
+ docker run -v ${TARGET_PATH}:${TARGET_PATH} \
+ -e TARGET_PATH=${TARGET_PATH} \
+ -e TOOLS=/opt/riscv32i \
+ -e DESIGNS=$(TARGET_PATH) \
+ -e GCC_PREFIX=riscv32-unknown-elf \
+ -u $$(id -u $$USER):$$(id -g $$USER) riscduino/dv_setup:mpw7 \
+ sh -c $(verify_command)
+
+
+.PHONY: verify
+verify:
+ cd ./verilog/dv/ && \
+ export SIM=${SIM} DUMP=${DUMP} && \
+ $(MAKE) -j$(THREADS)
+
+
+# Install Openlane
+.PHONY: openlane
+openlane:
+ @if [ "$$(realpath $${OPENLANE_ROOT})" = "$$(realpath $$(pwd)/openlane)" ]; then\
+ echo "OPENLANE_ROOT is set to '$$(pwd)/openlane' which contains openlane config files"; \
+ echo "Please set it to a different directory"; \
+ exit 1; \
+ fi
+ cd openlane && $(MAKE) openlane
+
+#### Not sure if the targets following are of any use
+
+# Create symbolic links to caravel's main files
+.PHONY: simlink
+simlink: check-caravel
+### Symbolic links relative path to $CARAVEL_ROOT
+ $(eval MAKEFILE_PATH := $(shell realpath --relative-to=openlane $(CARAVEL_ROOT)/openlane/Makefile))
+ $(eval PIN_CFG_PATH := $(shell realpath --relative-to=openlane/user_project_wrapper $(CARAVEL_ROOT)/openlane/user_project_wrapper_empty/pin_order.cfg))
+ mkdir -p openlane
+ mkdir -p openlane/user_project_wrapper
+ cd openlane &&\
+ ln -sf $(MAKEFILE_PATH) Makefile
+ cd openlane/user_project_wrapper &&\
+ ln -sf $(PIN_CFG_PATH) pin_order.cfg
+
+# Update Caravel
+.PHONY: update_caravel
+update_caravel: check-caravel
+ cd $(CARAVEL_ROOT)/ && git checkout $(CARAVEL_TAG) && git pull
+
+# Uninstall Caravel
+.PHONY: uninstall
+uninstall:
+ rm -rf $(CARAVEL_ROOT)
+
+
+# Install Pre-check
+# Default installs to the user home directory, override by "export PRECHECK_ROOT=<precheck-installation-path>"
+.PHONY: precheck
+precheck:
+ @git clone --depth=1 --branch $(MPW_TAG) https://github.com/efabless/mpw_precheck.git $(PRECHECK_ROOT)
+ @docker pull efabless/mpw_precheck:latest
+
+.PHONY: run-precheck
+run-precheck: check-pdk check-precheck
+ $(eval INPUT_DIRECTORY := $(shell pwd))
+ cd $(PRECHECK_ROOT) && \
+ docker run -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) \
+ -v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) \
+ -v $(PDK_ROOT):$(PDK_ROOT) \
+ -e INPUT_DIRECTORY=$(INPUT_DIRECTORY) \
+ -e PDK_PATH=$(PDK_ROOT)/$(PDK) \
+ -e PDK_ROOT=$(PDK_ROOT) \
+ -e PDKPATH=$(PDKPATH) \
+ -u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+ efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_path $(PDK_ROOT)/$(PDK)"
+
+
+
+.PHONY: clean
+clean:
+ cd ./verilog/dv/ && \
+ $(MAKE) -j$(THREADS) clean
+
+check-caravel:
+ @if [ ! -d "$(CARAVEL_ROOT)" ]; then \
+ echo "Caravel Root: "$(CARAVEL_ROOT)" doesn't exists, please export the correct path before running make. "; \
+ exit 1; \
+ fi
+
+check-precheck:
+ @if [ ! -d "$(PRECHECK_ROOT)" ]; then \
+ echo "Pre-check Root: "$(PRECHECK_ROOT)" doesn't exists, please export the correct path before running make. "; \
+ exit 1; \
+ fi
+
+check-pdk:
+ @if [ ! -d "$(PDK_ROOT)" ]; then \
+ echo "PDK Root: "$(PDK_ROOT)" doesn't exists, please export the correct path before running make. "; \
+ exit 1; \
+ fi
+
+check-coremark_repo:
+ @if [ ! -d "$(COREMARK_DIR)" ]; then \
+ echo "Installing Core Mark Repo.."; \
+ git clone $(COREMARK_REPO) $(COREMARK_DIR); \
+ cd $(COREMARK_DIR); git checkout $(COREMARK_BRANCH); \
+ fi
+
+check-riscv_comp_repo:
+ @if [ ! -d "$(RISCV_COMP_DIR)" ]; then \
+ echo "Installing Risc V Complance Repo.."; \
+ git clone $(RISCV_COMP_REPO) $(RISCV_COMP_DIR); \
+ cd $(RISCV_COMP_DIR); git checkout $(RISCV_COMP_BRANCH); \
+ fi
+
+check-riscv_test_repo:
+ @if [ ! -d "$(RISCV_TEST_DIR)" ]; then \
+ echo "Installing RiscV Test Repo.."; \
+ git clone $(RISCV_TEST_REPO) $(RISCV_TEST_DIR); \
+ cd $(RISCV_TEST_DIR); git checkout $(RISCV_TEST_BRANCH); \
+ fi
+
+zip:
+ gzip -f -r lef/*
+ gzip -f -r gds/*
+ gzip -f -r spef/*
+ gzip -f -r spi/lvs/*
+ gzip -f -r verilog/gl/*
+
+unzip:
+ gzip -d -r lef/*
+ gzip -d -r gds/*
+ gzip -d -r spef/*
+ gzip -d -r spi/lvs/*
+ gzip -d -r verilog/gl/*
+
+.PHONY: help
+help:
+ cd $(CARAVEL_ROOT) && $(MAKE) help
+ @$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$'
+
+
+export CUP_ROOT=$(shell pwd)
+export TIMING_ROOT?=$(shell pwd)/deps/timing-scripts
+export PROJECT_ROOT=$(CUP_ROOT)
+timing-scripts-repo=https://github.com/efabless/timing-scripts.git
+
+$(TIMING_ROOT):
+ @mkdir -p $(CUP_ROOT)/deps
+ @git clone $(timing-scripts-repo) $(TIMING_ROOT)
+
+.PHONY: setup-timing-scripts
+setup-timing-scripts: $(TIMING_ROOT)
+ @( cd $(TIMING_ROOT) && git pull )
+ @#( cd $(TIMING_ROOT) && git fetch && git checkout $(MPW_TAG); )
+ @python3 -m venv ./venv
+ . ./venv/bin/activate && \
+ python3 -m pip install --upgrade pip && \
+ python3 -m pip install -r $(TIMING_ROOT)/requirements.txt && \
+ deactivate
+
+./verilog/gl/user_project_wrapper.v:
+ $(error you don't have $@)
+
+./env/spef-mapping.tcl:
+ @echo "run the following:"
+ @echo "make extract-parasitics"
+ @echo "make create-spef-mapping"
+ exit 1
+
+.PHONY: create-spef-mapping
+create-spef-mapping: ./verilog/gl/user_project_wrapper.v
+ @. ./venv/bin/activate && \
+ python3 $(TIMING_ROOT)/scripts/generate_spef_mapping.py \
+ -i ./verilog/gl/user_project_wrapper.v \
+ -o ./env/spef-mapping.tcl \
+ --pdk-path $(PDK_ROOT)/$(PDK) \
+ --macro-parent mprj \
+ --project-root "$(CUP_ROOT)" && \
+ deactivate
+
+.PHONY: extract-parasitics
+extract-parasitics: ./verilog/gl/user_project_wrapper.v
+ @. ./venv/bin/activate && \
+ python3 $(TIMING_ROOT)/scripts/get_macros.py \
+ -i ./verilog/gl/user_project_wrapper.v \
+ -o ./tmp-macros-list \
+ --project-root "$(CUP_ROOT)" \
+ --pdk-path $(PDK_ROOT)/$(PDK) && \
+ deactivate
+ @cat ./tmp-macros-list | cut -d " " -f2 \
+ | xargs -I % bash -c "$(MAKE) -C $(TIMING_ROOT) \
+ -f $(TIMING_ROOT)/timing.mk rcx-% || echo 'Cannot extract %. Probably no def for this macro'"
+ @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk rcx-user_project_wrapper
+ @cat ./tmp-macros-list
+ @rm ./tmp-macros-list
+
+.PHONY: caravel-sta
+caravel-sta: ./env/spef-mapping.tcl
+ @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-typ
+ @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-fast
+ @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-slow
+ @echo "You can find results for all corners in $(CUP_ROOT)/signoff/caravel/openlane-signoff/timing/"
+
+#Added by Dinesh-A for Klayout Based DRC check
+.PHONY: run-drc
+run-drc:
+ @echo "run kalyout DRC checks"
+ mkdir -p signoff/user_project_wrapper/openlane-signoff/drc
+ docker run -ti --rm -v $(PROJECT_ROOT):/project riscduino/openlane:mpw7 sh -c "cd /project && ./scripts/klayout_drc.sh user_project_wrapper "
+
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
new file mode 100644
index 0000000..7977ac7
--- /dev/null
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz
new file mode 100644
index 0000000..cceffca
--- /dev/null
+++ b/lef/user_project_wrapper.lef.gz
Binary files differ
diff --git a/openlane/Makefile b/openlane/Makefile
new file mode 100644
index 0000000..3c48c94
--- /dev/null
+++ b/openlane/Makefile
@@ -0,0 +1,95 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+#SHELL = sh -xv
+
+BLOCKS = $(shell find * -maxdepth 0 -type d)
+CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl)
+CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
+
+OPENLANE_TAG = mpw7
+OPENLANE_IMAGE_NAME = riscduino/openlane:$(OPENLANE_TAG)
+OPENLANE_BASIC_COMMAND = "cd $(PWD)/../openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
+OPENLANE_INTERACTIVE_COMMAND = "cd $(PWD)/../openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite -it -file ./$*/interactive.tcl"
+
+all: $(BLOCKS)
+
+$(CONFIG) :
+ @echo "Missing $@. Please create a configuration for that design"
+ @exit 1
+
+.PHONY: $(BLOCKS)
+$(BLOCKS) : % : ./%/config.tcl
+ifeq ($(OPENLANE_ROOT),)
+ @echo "Please export OPENLANE_ROOT"
+ @exit 1
+endif
+ifeq ($(PDK_ROOT),)
+ @echo "Please export PDK_ROOT"
+ @exit 1
+endif
+ @echo "###############################################"
+ @sleep 1
+
+ @if [ -f ./$*/interactive.tcl ]; then\
+ docker run --rm \
+ -v $(PWD)/..:$(PWD)/.. \
+ -e TEST_MISMATCHES=tools \
+ -e MISMATCHES_OK=1 \
+ -u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+ $(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_INTERACTIVE_COMMAND);\
+ else\
+ docker run --rm \
+ -v $(PWD)/..:$(PWD)/.. \
+ -e TEST_MISMATCHES=tools \
+ -e MISMATCHES_OK=1 \
+ -u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+ $(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_BASIC_COMMAND);\
+ fi
+ mkdir -p ../signoff/$*/
+ cp $*/runs/$*/OPENLANE_VERSION ../signoff/$*/
+ cp $*/runs/$*/PDK_SOURCES ../signoff/$*/
+ cp $*/runs/$*/reports/final_summary_report.csv ../signoff/$*/
+
+.PHONY: openlane
+openlane: check-openlane-env
+ if [ -d "$(OPENLANE_ROOT)" ]; then\
+ echo "Deleting exisiting $(OPENLANE_ROOT)" && \
+ rm -rf $(OPENLANE_ROOT) && sleep 2; \
+ fi
+ git clone https://github.com/The-OpenROAD-Project/OpenLane --branch=$(OPENLANE_TAG) --depth=1 $(OPENLANE_ROOT) && \
+ cd $(OPENLANE_ROOT) && \
+ export OPENLANE_IMAGE_NAME=efabless/openlane:$(OPENLANE_TAG) && \
+ export IMAGE_NAME=efabless/openlane:$(OPENLANE_TAG) && \
+ $(MAKE) pull-openlane
+
+.PHONY: check-openlane-env
+check-openlane-env:
+ifeq ($(OPENLANE_ROOT),)
+ @echo "Please export OPENLANE_ROOT"
+ @exit 1
+endif
+
+FORCE:
+
+clean:
+ @echo "Use clean_all to clean everything :)"
+
+clean_all: $(CLEAN)
+
+$(CLEAN): clean-% :
+ rm -rf runs/$*
+ rm -rf ../gds/$**
+ rm -rf ../mag/$**
+ rm -rf ../lef/$**
diff --git a/openlane/glbl_cfg/base.sdc b/openlane/glbl_cfg/base.sdc
new file mode 100644
index 0000000..33f7cc8
--- /dev/null
+++ b/openlane/glbl_cfg/base.sdc
@@ -0,0 +1,112 @@
+###############################################################################
+# Created by write_sdc
+# Sat Nov 13 06:33:41 2021
+###############################################################################
+current_design glbl_cfg
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -hold 0.2500
+set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -setup 0.2500
+set_clock_uncertainty -rise_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -hold 0.2500
+set_clock_uncertainty -rise_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -hold 0.2500
+set_clock_uncertainty -fall_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -hold 0.2500
+set_clock_uncertainty -fall_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -setup 0.2500
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_cs}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wr}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reset_n}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_cs}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wr}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reset_n}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[*]}]
+
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[*]}]
+
+
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_done[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_error[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_correct[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_done[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_error_cnt0[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_error_cnt1[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_error_cnt2[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_error_cnt3[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_error_cnt4[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_error_cnt5[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_error_cnt6[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_error_cnt7[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_sdo[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_done[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_error[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_correct[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_done[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_error_cnt0[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_error_cnt1[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_error_cnt2[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_error_cnt3[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_error_cnt4[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_error_cnt5[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_error_cnt6[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_error_cnt7[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_sdo[*]}]
+
+
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_en}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_run[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_load[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_sdi[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_shift[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_en}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_run[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_load[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_sdi[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {bist_shift[*]}]
+
+# Set max delay for clock skew
+set_max_delay 3.5 -from [get_ports {wbd_clk_int}]
+set_max_delay 2.5 -from wbd_clk_int -to wbd_clk_glbl
+
+set_case_analysis 0 [get_ports {cfg_cska_glbl[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_glbl[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_glbl[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_glbl[3]}]
+
+set_case_analysis 0 [get_ports {scan_en}]
+set_case_analysis 0 [get_ports {scan_mode}]
+set_false_path -from [get_ports {scan_in[*]}]
+set_false_path -to [get_ports {scan_out[*]}]
+
+###############################################################################
+# Environment
+###############################################################################
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
+
+
+###############################################################################
+# Design Rules
+###############################################################################
diff --git a/openlane/glbl_cfg/config.tcl b/openlane/glbl_cfg/config.tcl
new file mode 100755
index 0000000..cc03862
--- /dev/null
+++ b/openlane/glbl_cfg/config.tcl
@@ -0,0 +1,117 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+set ::env(DESIGN_NAME) glbl_cfg
+
+set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "mclk"
+
+set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+ $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/registers.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_ctl.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/ser_inf_32b.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/glbl/src/glbl_cfg.sv \
+ "
+
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+set ::env(SDC_FILE) "$::env(DESIGN_DIR)/base.sdc"
+set ::env(BASE_SDC_FILE) "$::env(DESIGN_DIR)/base.sdc"
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+set ::env(SCAN_TOTAL_CHAINS) 8
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 250 300"
+
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
+
+#set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_TARGET_DENSITY) "0.35"
+
+# helps in anteena fix
+set ::env(USE_ARC_ANTENNA_CHECK) "1"
+
+set ::env(FP_IO_VEXTEND) 4
+set ::env(FP_IO_HEXTEND) 4
+
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 6.2
+set ::env(FP_PDN_HWIDTH) 6.2
+
+#set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
+
+#Lef
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
+
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
+
+set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {0.25}
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) {0.25}
+
+set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {500}
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {500}
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "1"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/glbl_cfg/pdn.tcl b/openlane/glbl_cfg/pdn.tcl
new file mode 100644
index 0000000..1fe689b
--- /dev/null
+++ b/openlane/glbl_cfg/pdn.tcl
@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+ name grid
+ rails {
+ met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+ }
+ straps {
+ met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+ met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+ }
+ connect {{met1 met4} {met4 met5}}
+}
+
+pdngen::specify_grid macro {
+ power_pins "VPWR"
+ ground_pins "VGND"
+ blockages "li1 met1 met2 met3 met4"
+ straps {
+ }
+ connect {{met4_PIN_ver met5}}
+}
+
+set ::halo 5
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
diff --git a/openlane/glbl_cfg/pin_order.cfg b/openlane/glbl_cfg/pin_order.cfg
new file mode 100644
index 0000000..d31edcc
--- /dev/null
+++ b/openlane/glbl_cfg/pin_order.cfg
@@ -0,0 +1,231 @@
+#BUS_SORT
+
+#MANUAL_PLACE
+
+
+#S
+scan_en_o 0100 0 2
+scan_mode_o
+scan_so\[7\]
+scan_so\[6\]
+scan_so\[5\]
+scan_so\[4\]
+scan_so\[3\]
+scan_so\[2\]
+scan_so\[1\]
+scan_so\[0\]
+
+
+#N
+reset_n 0000 0
+scan_en 0100 0 2
+scan_mode
+scan_si\[7\]
+scan_si\[6\]
+scan_si\[5\]
+scan_si\[4\]
+scan_si\[3\]
+scan_si\[2\]
+scan_si\[1\]
+scan_si\[0\]
+
+
+#E
+cfg_cska_glbl\[3\] 0000 0 4
+cfg_cska_glbl\[2\]
+cfg_cska_glbl\[1\]
+cfg_cska_glbl\[0\]
+mclk
+wbd_clk_glbl
+wbd_clk_int 0025 0 2
+reg_cs
+reg_wr
+reg_addr\[7\]
+reg_addr\[6\]
+reg_addr\[5\]
+reg_addr\[4\]
+reg_addr\[3\]
+reg_addr\[2\]
+reg_addr\[1\]
+reg_addr\[0\]
+reg_be\[3\]
+reg_be\[2\]
+reg_be\[1\]
+reg_be\[0\]
+reg_wdata\[31\]
+reg_wdata\[30\]
+reg_wdata\[29\]
+reg_wdata\[28\]
+reg_wdata\[27\]
+reg_wdata\[26\]
+reg_wdata\[25\]
+reg_wdata\[24\]
+reg_wdata\[23\]
+reg_wdata\[22\]
+reg_wdata\[21\]
+reg_wdata\[20\]
+reg_wdata\[19\]
+reg_wdata\[18\]
+reg_wdata\[17\]
+reg_wdata\[16\]
+reg_wdata\[15\]
+reg_wdata\[14\]
+reg_wdata\[13\]
+reg_wdata\[12\]
+reg_wdata\[11\]
+reg_wdata\[10\]
+reg_wdata\[9\]
+reg_wdata\[8\]
+reg_wdata\[7\]
+reg_wdata\[6\]
+reg_wdata\[5\]
+reg_wdata\[4\]
+reg_wdata\[3\]
+reg_wdata\[2\]
+reg_wdata\[1\]
+reg_wdata\[0\]
+reg_rdata\[31\]
+reg_rdata\[30\]
+reg_rdata\[29\]
+reg_rdata\[28\]
+reg_rdata\[27\]
+reg_rdata\[26\]
+reg_rdata\[25\]
+reg_rdata\[24\]
+reg_rdata\[23\]
+reg_rdata\[22\]
+reg_rdata\[21\]
+reg_rdata\[20\]
+reg_rdata\[19\]
+reg_rdata\[18\]
+reg_rdata\[17\]
+reg_rdata\[16\]
+reg_rdata\[15\]
+reg_rdata\[14\]
+reg_rdata\[13\]
+reg_rdata\[12\]
+reg_rdata\[11\]
+reg_rdata\[10\]
+reg_rdata\[9\]
+reg_rdata\[8\]
+reg_rdata\[7\]
+reg_rdata\[6\]
+reg_rdata\[5\]
+reg_rdata\[4\]
+reg_rdata\[3\]
+reg_rdata\[2\]
+reg_rdata\[1\]
+reg_rdata\[0\]
+reg_ack
+
+bist_en\[0\] 0150 0 2
+bist_run\[0\]
+bist_shift\[0\]
+bist_load\[0\]
+bist_sdi\[0\]
+bist_sdo\[0\]
+bist_done\[0\]
+bist_error\[0\]
+bist_correct\[0\]
+bist_error_cnt0\[0\]
+bist_error_cnt0\[1\]
+bist_error_cnt0\[2\]
+bist_error_cnt0\[3\]
+
+bist_en\[1\]
+bist_run\[1\]
+bist_shift\[1\]
+bist_load\[1\]
+bist_sdi\[1\]
+bist_sdo\[1\]
+bist_done\[1\]
+bist_error\[1\]
+bist_correct\[1\]
+bist_error_cnt1\[0\]
+bist_error_cnt1\[1\]
+bist_error_cnt1\[2\]
+bist_error_cnt1\[3\]
+
+bist_en\[2\]
+bist_run\[2\]
+bist_shift\[2\]
+bist_load\[2\]
+bist_sdi\[2\]
+bist_sdo\[2\]
+bist_done\[2\]
+bist_error\[2\]
+bist_correct\[2\]
+bist_error_cnt2\[0\]
+bist_error_cnt2\[1\]
+bist_error_cnt2\[2\]
+bist_error_cnt2\[3\]
+
+bist_en\[3\]
+bist_run\[3\]
+bist_shift\[3\]
+bist_load\[3\]
+bist_sdi\[3\]
+bist_sdo\[3\]
+bist_done\[3\]
+bist_error\[3\]
+bist_correct\[3\]
+bist_error_cnt3\[0\]
+bist_error_cnt3\[1\]
+bist_error_cnt3\[2\]
+bist_error_cnt3\[3\]
+
+bist_en\[4\]
+bist_run\[4\]
+bist_shift\[4\]
+bist_load\[4\]
+bist_sdi\[4\]
+bist_sdo\[4\]
+bist_done\[4\]
+bist_error\[4\]
+bist_correct\[4\]
+bist_error_cnt4\[0\]
+bist_error_cnt4\[1\]
+bist_error_cnt4\[2\]
+bist_error_cnt4\[3\]
+
+bist_en\[5\]
+bist_run\[5\]
+bist_shift\[5\]
+bist_load\[5\]
+bist_sdi\[5\]
+bist_sdo\[5\]
+bist_done\[5\]
+bist_error\[5\]
+bist_correct\[5\]
+bist_error_cnt5\[0\]
+bist_error_cnt5\[1\]
+bist_error_cnt5\[2\]
+bist_error_cnt5\[3\]
+
+bist_en\[6\]
+bist_run\[6\]
+bist_shift\[6\]
+bist_load\[6\]
+bist_sdi\[6\]
+bist_sdo\[6\]
+bist_done\[6\]
+bist_error\[6\]
+bist_correct\[6\]
+bist_error_cnt6\[0\]
+bist_error_cnt6\[1\]
+bist_error_cnt6\[2\]
+bist_error_cnt6\[3\]
+
+bist_en\[7\]
+bist_run\[7\]
+bist_shift\[7\]
+bist_load\[7\]
+bist_sdi\[7\]
+bist_sdo\[7\]
+bist_done\[7\]
+bist_error\[7\]
+bist_correct\[7\]
+bist_error_cnt7\[0\]
+bist_error_cnt7\[1\]
+bist_error_cnt7\[2\]
+bist_error_cnt7\[3\]
diff --git a/openlane/mbist_top1/base.sdc b/openlane/mbist_top1/base.sdc
new file mode 100644
index 0000000..8ae25b1
--- /dev/null
+++ b/openlane/mbist_top1/base.sdc
@@ -0,0 +1,163 @@
+###############################################################################
+# Created by write_sdc
+# Sun Nov 14 09:33:23 2021
+###############################################################################
+current_design mbist_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name wb_clk_i -period 10.0000 [get_ports {wb_clk_i}]
+create_generated_clock -name bist_mem_clk_a -add -source [get_ports {wb_clk_i}] -master_clock [get_clocks wb_clk_i] -divide_by 1 -comment {Mem Clock A} [get_ports mem_clk_a]
+create_generated_clock -name bist_mem_clk_b -add -source [get_ports {wb_clk_i}] -master_clock [get_clocks wb_clk_i] -divide_by 1 -comment {Mem Clock B} [get_ports mem_clk_b]
+
+set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks {wb_clk_i bist_mem_clk_a bist_mem_clk_b}]
+
+set_clock_transition 0.1500 [get_clocks {wb_clk_i}]
+set_clock_uncertainty -setup 0.2500 wb_clk_i
+set_clock_uncertainty -setup 0.2500 mem_clk_a
+set_clock_uncertainty -setup 0.2500 mem_clk_b
+
+set_clock_uncertainty -hold 0.2500 wb_clk_i
+set_clock_uncertainty -hold 0.2500 mem_clk_a
+set_clock_uncertainty -hold 0.2500 mem_clk_b
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+set_input_delay -max 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rst_n}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rst_n}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_correct}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_done}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[0]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[1]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[2]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[3]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdo}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_correct}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_done}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[0]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[1]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[2]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[3]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdo}]
+
+set_false_path -from [get_ports {bist_en}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_load}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_run}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdi}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_shift}]
+
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_en}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_load}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_run}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdi}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_shift}]
+
+## Functional Inputs
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[*]}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_stb_i}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_cyc_i}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_we_i}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbd_mbist1_dat_o[*]}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[*]}]
+
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[*]}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_stb_i}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_cyc_i}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_we_i}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbd_mbist1_dat_o[*]}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[*]}]
+
+set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[*]}]
+set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_ack_o}]
+set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_err_o}]
+
+set_output_delay -min 1 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[*]}]
+set_output_delay -min 1 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_ack_o}]
+set_output_delay -min 1 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_err_o}]
+
+## Towards MEMORY from MBIST CLOCK
+## PORT-A
+set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[*]}]
+set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[*]}]
+
+
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[*]}]
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_a}]
+
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[*]}]
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_a}]
+
+
+
+## PORT-B
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_cen_b}]
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_din_b[*]}]
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_mask_b[*]}]
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_web_b}]
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_addr_b[*]}]
+
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_cen_b}]
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_din_b[*]}]
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_mask_b[*]}]
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_web_b}]
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_addr_b[*]}]
+
+
+# Set max delay for clock skew
+
+set_max_delay 3.5 -from [get_ports {wbd_clk_int}]
+set_max_delay 2 -to [get_ports {wbd_clk_mbist}]
+set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_mbist
+
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {bist_correct}]
+set_load -pin_load 0.0334 [get_ports {bist_done}]
+set_load -pin_load 0.0334 [get_ports {bist_error}]
+set_load -pin_load 0.0334 [get_ports {bist_sdo}]
+set_load -pin_load 0.0334 [get_ports {mem_cen_a}]
+set_load -pin_load 0.0334 [get_ports {mem_cen_b}]
+set_load -pin_load 0.0334 [get_ports {mem_clk_a}]
+set_load -pin_load 0.0334 [get_ports {mem_clk_b}]
+set_load -pin_load 0.0334 [get_ports {mem_web_b}]
+set_load -pin_load 0.0334 [get_ports {bist_error_cnt[3]}]
+set_load -pin_load 0.0334 [get_ports {bist_error_cnt[2]}]
+set_load -pin_load 0.0334 [get_ports {bist_error_cnt[1]}]
+set_load -pin_load 0.0334 [get_ports {bist_error_cnt[0]}]
+set_load -pin_load 0.0334 [get_ports {wb_cyc_i}]
+set_load -pin_load 0.0334 [get_ports {wb_stb_i}]
+set_load -pin_load 0.0334 [get_ports {wb_adr_i[*]}]
+set_load -pin_load 0.0334 [get_ports {wb_we_i}]
+set_load -pin_load 0.0334 [get_ports {wb_dat_i[*]}]
+set_load -pin_load 0.0334 [get_ports {wb_sel_i[*]}]
+set_load -pin_load 0.0334 [get_ports {mem_addr_a[*]}]
+set_load -pin_load 0.0334 [get_ports {mem_addr_b[*]}]
+set_load -pin_load 0.0334 [get_ports {mem_din_b[*]}]
+set_load -pin_load 0.0334 [get_ports {mem_mask_b[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_en}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_load}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_run}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_sdi}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_shift}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[*]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/openlane/mbist_top1/config.tcl b/openlane/mbist_top1/config.tcl
new file mode 100755
index 0000000..cce3320
--- /dev/null
+++ b/openlane/mbist_top1/config.tcl
@@ -0,0 +1,138 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+
+set ::env(DESIGN_NAME) mbist_top1
+
+set ::env(DESIGN_IS_CORE) "0"
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "u_cts_wb_clk_b1.u_buf/X u_cts_wb_clk_b2.u_buf/X u_mem_sel.u_cts_mem_clk_a.u_buf/X u_mem_sel.u_cts_mem_clk_b.u_buf/X"
+
+set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+ $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/mbist/src/core/mbist_addr_gen.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/mbist/src/core/mbist_fsm.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/mbist/src/core/mbist_op_sel.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/mbist/src/core/mbist_repair_addr.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/mbist/src/core/mbist_sti_sel.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/mbist/src/core/mbist_pat_sel.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/mbist/src/core/mbist_mux.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/mbist/src/core/mbist_data_cmp.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/mbist/src/top/mbist_top1.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/reset_sync.sv \
+ "
+
+set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/../../verilog/rtl/mbist/include ]
+
+
+set ::env(SYNTH_PARAMETERS) "SCW=8 \
+ BIST_ADDR_WD=9\
+ BIST_DATA_WD=32 \
+ BIST_ADDR_START=9'h000,\
+ BIST_ADDR_END=9'h1FB,\
+ BIST_REPAIR_ADDR_START=9'h1FC,\
+ BIST_RAD_WD_I=9,\
+ BIST_RAD_WD_O=9\
+ "
+
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+set ::env(SDC_FILE) "$::env(DESIGN_DIR)/base.sdc"
+set ::env(BASE_SDC_FILE) "$::env(DESIGN_DIR)/base.sdc"
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+set ::env(SCAN_TOTAL_CHAINS) 8
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 250 350"
+
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
+
+#set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_TARGET_DENSITY) "0.35"
+
+# helps in anteena fix
+set ::env(USE_ARC_ANTENNA_CHECK) "1"
+
+set ::env(FP_IO_VEXTEND) 4
+set ::env(FP_IO_HEXTEND) 4
+
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 6.2
+set ::env(FP_PDN_HWIDTH) 6.2
+
+#set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
+
+#Lef
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
+
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
+
+set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {0.25}
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) {0.25}
+
+set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {500}
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {500}
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "1"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/mbist_top1/pin_order.cfg b/openlane/mbist_top1/pin_order.cfg
new file mode 100644
index 0000000..76d9147
--- /dev/null
+++ b/openlane/mbist_top1/pin_order.cfg
@@ -0,0 +1,235 @@
+#BUS_SORT
+
+#MANUAL_PLACE
+
+
+#S
+rst_n 0000 0
+cfg_mem_lphase
+
+scan_en 0100 0 2
+scan_mode
+scan_si\[7\]
+scan_si\[6\]
+scan_si\[5\]
+scan_si\[4\]
+scan_si\[3\]
+scan_si\[2\]
+scan_si\[1\]
+scan_si\[0\]
+
+#N
+scan_en_o 0100 0 2
+scan_mode_o
+scan_so\[7\]
+scan_so\[6\]
+scan_so\[5\]
+scan_so\[4\]
+scan_so\[3\]
+scan_so\[2\]
+scan_so\[1\]
+scan_so\[0\]
+
+
+#W
+cfg_cska_mbist\[3\] 0000 0 4
+cfg_cska_mbist\[2\]
+cfg_cska_mbist\[1\]
+cfg_cska_mbist\[0\]
+wb_clk_i
+wbd_clk_mbist
+wbd_clk_int 0025 0 2
+wb_cyc_i
+wb_stb_i
+wb_we_i
+wb_adr_i\[8\]
+wb_adr_i\[7\]
+wb_adr_i\[6\]
+wb_adr_i\[5\]
+wb_adr_i\[4\]
+wb_adr_i\[3\]
+wb_adr_i\[2\]
+wb_adr_i\[1\]
+wb_adr_i\[0\]
+wb_dat_i\[31\]
+wb_dat_i\[30\]
+wb_dat_i\[29\]
+wb_dat_i\[28\]
+wb_dat_i\[27\]
+wb_dat_i\[26\]
+wb_dat_i\[25\]
+wb_dat_i\[24\]
+wb_dat_i\[23\]
+wb_dat_i\[22\]
+wb_dat_i\[21\]
+wb_dat_i\[20\]
+wb_dat_i\[19\]
+wb_dat_i\[18\]
+wb_dat_i\[17\]
+wb_dat_i\[16\]
+wb_dat_i\[15\]
+wb_dat_i\[14\]
+wb_dat_i\[13\]
+wb_dat_i\[12\]
+wb_dat_i\[11\]
+wb_dat_i\[10\]
+wb_dat_i\[9\]
+wb_dat_i\[8\]
+wb_dat_i\[7\]
+wb_dat_i\[6\]
+wb_dat_i\[5\]
+wb_dat_i\[4\]
+wb_dat_i\[3\]
+wb_dat_i\[2\]
+wb_dat_i\[1\]
+wb_dat_i\[0\]
+wb_sel_i\[3\]
+wb_sel_i\[2\]
+wb_sel_i\[1\]
+wb_sel_i\[0\]
+wb_dat_o\[31\]
+wb_dat_o\[30\]
+wb_dat_o\[29\]
+wb_dat_o\[28\]
+wb_dat_o\[27\]
+wb_dat_o\[26\]
+wb_dat_o\[25\]
+wb_dat_o\[24\]
+wb_dat_o\[23\]
+wb_dat_o\[22\]
+wb_dat_o\[21\]
+wb_dat_o\[20\]
+wb_dat_o\[19\]
+wb_dat_o\[18\]
+wb_dat_o\[17\]
+wb_dat_o\[16\]
+wb_dat_o\[15\]
+wb_dat_o\[14\]
+wb_dat_o\[13\]
+wb_dat_o\[12\]
+wb_dat_o\[11\]
+wb_dat_o\[10\]
+wb_dat_o\[9\]
+wb_dat_o\[8\]
+wb_dat_o\[7\]
+wb_dat_o\[6\]
+wb_dat_o\[5\]
+wb_dat_o\[4\]
+wb_dat_o\[3\]
+wb_dat_o\[2\]
+wb_dat_o\[1\]
+wb_dat_o\[0\]
+wb_ack_o
+wb_err_o
+
+
+bist_en 0150 0 2
+bist_run
+bist_shift
+bist_load
+bist_sdi
+bist_done
+bist_sdo
+bist_error
+bist_correct
+bist_error_cnt\[0\]
+bist_error_cnt\[1\]
+bist_error_cnt\[2\]
+bist_error_cnt\[3\]
+
+#E
+mem_clk_b 0000 0 2
+mem_cen_b
+mem_web_b
+mem_mask_b\[0\]
+mem_mask_b\[1\]
+mem_mask_b\[2\]
+mem_mask_b\[3\]
+mem_addr_b\[0\]
+mem_addr_b\[1\]
+mem_addr_b\[2\]
+mem_addr_b\[3\]
+mem_addr_b\[4\]
+mem_addr_b\[5\]
+mem_addr_b\[6\]
+mem_addr_b\[7\]
+mem_addr_b\[8\]
+mem_din_b\[0\]
+mem_din_b\[1\]
+mem_din_b\[2\]
+mem_din_b\[3\]
+mem_din_b\[4\]
+mem_din_b\[5\]
+mem_din_b\[6\]
+mem_din_b\[7\]
+mem_din_b\[8\]
+mem_din_b\[9\]
+mem_din_b\[10\]
+mem_din_b\[11\]
+mem_din_b\[12\]
+mem_din_b\[13\]
+mem_din_b\[14\]
+mem_din_b\[15\]
+mem_din_b\[16\]
+mem_din_b\[17\]
+mem_din_b\[18\]
+mem_din_b\[19\]
+mem_din_b\[20\]
+mem_din_b\[21\]
+mem_din_b\[22\]
+mem_din_b\[23\]
+mem_din_b\[24\]
+mem_din_b\[25\]
+mem_din_b\[26\]
+mem_din_b\[27\]
+mem_din_b\[28\]
+mem_din_b\[29\]
+mem_din_b\[30\]
+mem_din_b\[31\]
+
+
+mem_dout_a\[0\] 0100 0 2
+mem_dout_a\[1\]
+mem_dout_a\[2\]
+mem_dout_a\[3\]
+mem_dout_a\[4\]
+mem_dout_a\[5\]
+mem_dout_a\[6\]
+mem_dout_a\[7\]
+mem_dout_a\[8\]
+mem_dout_a\[9\]
+mem_dout_a\[10\]
+mem_dout_a\[11\]
+mem_dout_a\[12\]
+mem_dout_a\[13\]
+mem_dout_a\[14\]
+mem_dout_a\[15\]
+mem_dout_a\[16\]
+mem_dout_a\[17\]
+mem_dout_a\[18\]
+mem_dout_a\[19\]
+mem_dout_a\[20\]
+mem_dout_a\[21\]
+mem_dout_a\[22\]
+mem_dout_a\[23\]
+mem_dout_a\[24\]
+mem_dout_a\[25\]
+mem_dout_a\[26\]
+mem_dout_a\[27\]
+mem_dout_a\[28\]
+mem_dout_a\[29\]
+mem_dout_a\[30\]
+mem_dout_a\[31\]
+
+
+mem_clk_a 0200 0 2
+mem_cen_a
+mem_addr_a\[8\]
+mem_addr_a\[7\]
+mem_addr_a\[6\]
+mem_addr_a\[5\]
+mem_addr_a\[4\]
+mem_addr_a\[3\]
+mem_addr_a\[2\]
+mem_addr_a\[1\]
+mem_addr_a\[0\]
diff --git a/openlane/mbist_top1/sta.tcl b/openlane/mbist_top1/sta.tcl
new file mode 100644
index 0000000..57a6c35
--- /dev/null
+++ b/openlane/mbist_top1/sta.tcl
@@ -0,0 +1,88 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+
+set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
+set ::env(LIB_TYPICAL) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"
+set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
+set ::env(DESIGN_NAME) "mbist_top"
+set ::env(BASE_SDC_FILE) "base.sdc"
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
+set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
+set ::env(SYNTH_CAP_LOAD) "17.65"
+set ::env(WIRE_RC_LAYER) "met1"
+
+#To disable empty filler cell black box get created
+#set link_make_black_boxes 0
+
+
+set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
+define_corners wc bc tt
+read_liberty -corner bc $::env(LIB_FASTEST)
+read_liberty -corner wc $::env(LIB_SLOWEST)
+read_liberty -corner tt $::env(LIB_TYPICAL)
+
+
+read_verilog ../user_project_wrapper/netlist/mbist.v
+link_design $::env(DESIGN_NAME)
+
+
+read_spef ../../spef/mbist_top.spef
+
+
+read_sdc -echo $::env(BASE_SDC_FILE)
+
+# check for missing constraints
+check_setup -verbose > unconstraints.rpt
+
+set_operating_conditions -analysis_type single
+# Propgate the clock
+set_propagated_clock [all_clocks]
+
+report_tns
+report_wns
+#report_power
+echo "################ CORNER : WC (SLOW) TIMING Report ###################" > timing_ss_max.rpt
+report_checks -unique -path_delay max -slack_max -0.0 -group_count 100 -corner wc >> timing_ss_max.rpt
+report_checks -group_count 100 -path_delay max -path_group bist_clk -corner wc >> timing_ss_max.rpt
+report_checks -group_count 100 -path_delay max -path_group mem_clk_a -corner wc >> timing_ss_max.rpt
+report_checks -group_count 100 -path_delay max -path_group mem_clk_b -corner wc >> timing_ss_max.rpt
+report_checks -path_delay max -corner wc >> timing_ss_max.rpt
+
+echo "################ CORNER : BC (SLOW) TIMING Report ###################" > timing_ff_min.rpt
+report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner bc >> timing_ff_min.rpt
+report_checks -group_count 100 -path_delay min -path_group bist_clk -corner bc >> timing_ff_min.rpt
+report_checks -group_count 100 -path_delay min -path_group mem_clk_a -corner bc >> timing_ff_min.rpt
+report_checks -group_count 100 -path_delay min -path_group mem_clk_b -corner bc >> timing_ff_min.rpt
+report_checks -path_delay min -corner bc >> timing_ff_min.rpt
+
+echo "################ CORNER : TT (MAX) TIMING Report ###################" > timing_tt_max.rpt
+report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner tt >> timing_tt_max.rpt
+report_checks -group_count 100 -path_delay max -path_group bist_clk -corner tt >> timing_tt_max.rpt
+report_checks -group_count 100 -path_delay max -path_group mem_clk_a -corner tt >> timing_tt_max.rpt
+report_checks -group_count 100 -path_delay max -path_group mem_clk_b -corner tt >> timing_tt_max.rpt
+report_checks -path_delay min -corner tt >> timing_tt_min.rpt
+
+echo "################ CORNER : TT (MIN) TIMING Report ###################" > timing_tt_min.rpt
+report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner tt >> timing_tt_min.rpt
+report_checks -group_count 100 -path_delay min -path_group bist_clk -corner tt >> timing_tt_min.rpt
+report_checks -group_count 100 -path_delay min -path_group mem_clk_a -corner tt >> timing_tt_min.rpt
+report_checks -group_count 100 -path_delay min -path_group mem_clk_b -corner tt >> timing_tt_min.rpt
+report_checks -path_delay min -corner tt >> timing_tt_min.rpt
+
+report_checks -path_delay min
+
+#exit
diff --git a/openlane/mbist_top2/base.sdc b/openlane/mbist_top2/base.sdc
new file mode 100644
index 0000000..8ae25b1
--- /dev/null
+++ b/openlane/mbist_top2/base.sdc
@@ -0,0 +1,163 @@
+###############################################################################
+# Created by write_sdc
+# Sun Nov 14 09:33:23 2021
+###############################################################################
+current_design mbist_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name wb_clk_i -period 10.0000 [get_ports {wb_clk_i}]
+create_generated_clock -name bist_mem_clk_a -add -source [get_ports {wb_clk_i}] -master_clock [get_clocks wb_clk_i] -divide_by 1 -comment {Mem Clock A} [get_ports mem_clk_a]
+create_generated_clock -name bist_mem_clk_b -add -source [get_ports {wb_clk_i}] -master_clock [get_clocks wb_clk_i] -divide_by 1 -comment {Mem Clock B} [get_ports mem_clk_b]
+
+set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks {wb_clk_i bist_mem_clk_a bist_mem_clk_b}]
+
+set_clock_transition 0.1500 [get_clocks {wb_clk_i}]
+set_clock_uncertainty -setup 0.2500 wb_clk_i
+set_clock_uncertainty -setup 0.2500 mem_clk_a
+set_clock_uncertainty -setup 0.2500 mem_clk_b
+
+set_clock_uncertainty -hold 0.2500 wb_clk_i
+set_clock_uncertainty -hold 0.2500 mem_clk_a
+set_clock_uncertainty -hold 0.2500 mem_clk_b
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+set_input_delay -max 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rst_n}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rst_n}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_correct}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_done}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[0]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[1]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[2]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[3]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdo}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_correct}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_done}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[0]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[1]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[2]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[3]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdo}]
+
+set_false_path -from [get_ports {bist_en}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_load}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_run}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdi}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_shift}]
+
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_en}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_load}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_run}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdi}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_shift}]
+
+## Functional Inputs
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[*]}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_stb_i}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_cyc_i}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_we_i}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbd_mbist1_dat_o[*]}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[*]}]
+
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[*]}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_stb_i}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_cyc_i}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_we_i}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbd_mbist1_dat_o[*]}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[*]}]
+
+set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[*]}]
+set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_ack_o}]
+set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_err_o}]
+
+set_output_delay -min 1 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[*]}]
+set_output_delay -min 1 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_ack_o}]
+set_output_delay -min 1 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_err_o}]
+
+## Towards MEMORY from MBIST CLOCK
+## PORT-A
+set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[*]}]
+set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[*]}]
+
+
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[*]}]
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_a}]
+
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[*]}]
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_a}]
+
+
+
+## PORT-B
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_cen_b}]
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_din_b[*]}]
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_mask_b[*]}]
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_web_b}]
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_addr_b[*]}]
+
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_cen_b}]
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_din_b[*]}]
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_mask_b[*]}]
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_web_b}]
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_addr_b[*]}]
+
+
+# Set max delay for clock skew
+
+set_max_delay 3.5 -from [get_ports {wbd_clk_int}]
+set_max_delay 2 -to [get_ports {wbd_clk_mbist}]
+set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_mbist
+
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {bist_correct}]
+set_load -pin_load 0.0334 [get_ports {bist_done}]
+set_load -pin_load 0.0334 [get_ports {bist_error}]
+set_load -pin_load 0.0334 [get_ports {bist_sdo}]
+set_load -pin_load 0.0334 [get_ports {mem_cen_a}]
+set_load -pin_load 0.0334 [get_ports {mem_cen_b}]
+set_load -pin_load 0.0334 [get_ports {mem_clk_a}]
+set_load -pin_load 0.0334 [get_ports {mem_clk_b}]
+set_load -pin_load 0.0334 [get_ports {mem_web_b}]
+set_load -pin_load 0.0334 [get_ports {bist_error_cnt[3]}]
+set_load -pin_load 0.0334 [get_ports {bist_error_cnt[2]}]
+set_load -pin_load 0.0334 [get_ports {bist_error_cnt[1]}]
+set_load -pin_load 0.0334 [get_ports {bist_error_cnt[0]}]
+set_load -pin_load 0.0334 [get_ports {wb_cyc_i}]
+set_load -pin_load 0.0334 [get_ports {wb_stb_i}]
+set_load -pin_load 0.0334 [get_ports {wb_adr_i[*]}]
+set_load -pin_load 0.0334 [get_ports {wb_we_i}]
+set_load -pin_load 0.0334 [get_ports {wb_dat_i[*]}]
+set_load -pin_load 0.0334 [get_ports {wb_sel_i[*]}]
+set_load -pin_load 0.0334 [get_ports {mem_addr_a[*]}]
+set_load -pin_load 0.0334 [get_ports {mem_addr_b[*]}]
+set_load -pin_load 0.0334 [get_ports {mem_din_b[*]}]
+set_load -pin_load 0.0334 [get_ports {mem_mask_b[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_en}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_load}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_run}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_sdi}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_shift}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[*]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/openlane/mbist_top2/config.tcl b/openlane/mbist_top2/config.tcl
new file mode 100755
index 0000000..a11b5e2
--- /dev/null
+++ b/openlane/mbist_top2/config.tcl
@@ -0,0 +1,138 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+
+set ::env(DESIGN_NAME) mbist_top2
+
+set ::env(DESIGN_IS_CORE) "0"
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "u_cts_wb_clk_b1.u_buf/X u_cts_wb_clk_b2.u_buf/X u_mem_sel.u_cts_mem_clk_a.u_buf/X u_mem_sel.u_cts_mem_clk_b.u_buf/X"
+
+set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+ $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/mbist/src/core/mbist_addr_gen.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/mbist/src/core/mbist_fsm.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/mbist/src/core/mbist_op_sel.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/mbist/src/core/mbist_repair_addr.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/mbist/src/core/mbist_sti_sel.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/mbist/src/core/mbist_pat_sel.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/mbist/src/core/mbist_mux.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/mbist/src/core/mbist_data_cmp.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/mbist/src/top/mbist_top2.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/reset_sync.sv \
+ "
+
+set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/../../verilog/rtl/mbist/include ]
+
+
+set ::env(SYNTH_PARAMETERS) "SCW=8 \
+ BIST_ADDR_WD=8\
+ BIST_DATA_WD=32\
+ BIST_ADDR_START=8'h000\
+ BIST_ADDR_END=8'h0FB\
+ BIST_REPAIR_ADDR_START=8'h0FC\
+ BIST_RAD_WD_I=8\
+ BIST_RAD_WD_O=8\
+ "
+
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+set ::env(SDC_FILE) "$::env(DESIGN_DIR)/base.sdc"
+set ::env(BASE_SDC_FILE) "$::env(DESIGN_DIR)/base.sdc"
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+set ::env(SCAN_TOTAL_CHAINS) 8
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 250 250"
+
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
+
+#set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_TARGET_DENSITY) "0.35"
+
+# helps in anteena fix
+set ::env(USE_ARC_ANTENNA_CHECK) "1"
+
+set ::env(FP_IO_VEXTEND) 4
+set ::env(FP_IO_HEXTEND) 4
+
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 6.2
+set ::env(FP_PDN_HWIDTH) 6.2
+
+#set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
+
+#Lef
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
+
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
+
+set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {0.25}
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) {0.25}
+
+set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {500}
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {500}
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "1"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/mbist_top2/pin_order.cfg b/openlane/mbist_top2/pin_order.cfg
new file mode 100644
index 0000000..b15dd5a
--- /dev/null
+++ b/openlane/mbist_top2/pin_order.cfg
@@ -0,0 +1,232 @@
+#BUS_SORT
+
+#MANUAL_PLACE
+
+
+#S
+scan_en_o 0100 0 2
+scan_mode_o
+scan_so\[7\]
+scan_so\[6\]
+scan_so\[5\]
+scan_so\[4\]
+scan_so\[3\]
+scan_so\[2\]
+scan_so\[1\]
+scan_so\[0\]
+
+
+#N
+rst_n 0000 0
+cfg_mem_lphase
+
+scan_en 0100 0 2
+scan_mode
+scan_si\[7\]
+scan_si\[6\]
+scan_si\[5\]
+scan_si\[4\]
+scan_si\[3\]
+scan_si\[2\]
+scan_si\[1\]
+scan_si\[0\]
+
+
+#E
+cfg_cska_mbist\[3\] 0000 0 4
+cfg_cska_mbist\[2\]
+cfg_cska_mbist\[1\]
+cfg_cska_mbist\[0\]
+wb_clk_i
+wbd_clk_mbist
+wbd_clk_int 0025 0 2
+wb_cyc_i
+wb_stb_i
+wb_we_i
+wb_adr_i\[7\]
+wb_adr_i\[6\]
+wb_adr_i\[5\]
+wb_adr_i\[4\]
+wb_adr_i\[3\]
+wb_adr_i\[2\]
+wb_adr_i\[1\]
+wb_adr_i\[0\]
+wb_dat_i\[31\]
+wb_dat_i\[30\]
+wb_dat_i\[29\]
+wb_dat_i\[28\]
+wb_dat_i\[27\]
+wb_dat_i\[26\]
+wb_dat_i\[25\]
+wb_dat_i\[24\]
+wb_dat_i\[23\]
+wb_dat_i\[22\]
+wb_dat_i\[21\]
+wb_dat_i\[20\]
+wb_dat_i\[19\]
+wb_dat_i\[18\]
+wb_dat_i\[17\]
+wb_dat_i\[16\]
+wb_dat_i\[15\]
+wb_dat_i\[14\]
+wb_dat_i\[13\]
+wb_dat_i\[12\]
+wb_dat_i\[11\]
+wb_dat_i\[10\]
+wb_dat_i\[9\]
+wb_dat_i\[8\]
+wb_dat_i\[7\]
+wb_dat_i\[6\]
+wb_dat_i\[5\]
+wb_dat_i\[4\]
+wb_dat_i\[3\]
+wb_dat_i\[2\]
+wb_dat_i\[1\]
+wb_dat_i\[0\]
+wb_sel_i\[3\]
+wb_sel_i\[2\]
+wb_sel_i\[1\]
+wb_sel_i\[0\]
+wb_dat_o\[31\]
+wb_dat_o\[30\]
+wb_dat_o\[29\]
+wb_dat_o\[28\]
+wb_dat_o\[27\]
+wb_dat_o\[26\]
+wb_dat_o\[25\]
+wb_dat_o\[24\]
+wb_dat_o\[23\]
+wb_dat_o\[22\]
+wb_dat_o\[21\]
+wb_dat_o\[20\]
+wb_dat_o\[19\]
+wb_dat_o\[18\]
+wb_dat_o\[17\]
+wb_dat_o\[16\]
+wb_dat_o\[15\]
+wb_dat_o\[14\]
+wb_dat_o\[13\]
+wb_dat_o\[12\]
+wb_dat_o\[11\]
+wb_dat_o\[10\]
+wb_dat_o\[9\]
+wb_dat_o\[8\]
+wb_dat_o\[7\]
+wb_dat_o\[6\]
+wb_dat_o\[5\]
+wb_dat_o\[4\]
+wb_dat_o\[3\]
+wb_dat_o\[2\]
+wb_dat_o\[1\]
+wb_dat_o\[0\]
+wb_ack_o
+wb_err_o
+
+bist_en 0150 0 2
+bist_run
+bist_shift
+bist_load
+bist_sdi
+bist_done
+bist_sdo
+bist_error
+bist_correct
+bist_error_cnt\[0\]
+bist_error_cnt\[1\]
+bist_error_cnt\[2\]
+bist_error_cnt\[3\]
+
+#W
+mem_clk_b 0000 0 2
+mem_cen_b
+mem_web_b
+mem_mask_b\[0\]
+mem_mask_b\[1\]
+mem_mask_b\[2\]
+mem_mask_b\[3\]
+mem_addr_b\[0\]
+mem_addr_b\[1\]
+mem_addr_b\[2\]
+mem_addr_b\[3\]
+mem_addr_b\[4\]
+mem_addr_b\[5\]
+mem_addr_b\[6\]
+mem_addr_b\[7\]
+mem_din_b\[0\]
+mem_din_b\[1\]
+mem_din_b\[2\]
+mem_din_b\[3\]
+mem_din_b\[4\]
+mem_din_b\[5\]
+mem_din_b\[6\]
+mem_din_b\[7\]
+mem_din_b\[8\]
+mem_din_b\[9\]
+mem_din_b\[10\]
+mem_din_b\[11\]
+mem_din_b\[12\]
+mem_din_b\[13\]
+mem_din_b\[14\]
+mem_din_b\[15\]
+mem_din_b\[16\]
+mem_din_b\[17\]
+mem_din_b\[18\]
+mem_din_b\[19\]
+mem_din_b\[20\]
+mem_din_b\[21\]
+mem_din_b\[22\]
+mem_din_b\[23\]
+mem_din_b\[24\]
+mem_din_b\[25\]
+mem_din_b\[26\]
+mem_din_b\[27\]
+mem_din_b\[28\]
+mem_din_b\[29\]
+mem_din_b\[30\]
+mem_din_b\[31\]
+
+
+mem_dout_a\[0\] 0100 0 2
+mem_dout_a\[1\]
+mem_dout_a\[2\]
+mem_dout_a\[3\]
+mem_dout_a\[4\]
+mem_dout_a\[5\]
+mem_dout_a\[6\]
+mem_dout_a\[7\]
+mem_dout_a\[8\]
+mem_dout_a\[9\]
+mem_dout_a\[10\]
+mem_dout_a\[11\]
+mem_dout_a\[12\]
+mem_dout_a\[13\]
+mem_dout_a\[14\]
+mem_dout_a\[15\]
+mem_dout_a\[16\]
+mem_dout_a\[17\]
+mem_dout_a\[18\]
+mem_dout_a\[19\]
+mem_dout_a\[20\]
+mem_dout_a\[21\]
+mem_dout_a\[22\]
+mem_dout_a\[23\]
+mem_dout_a\[24\]
+mem_dout_a\[25\]
+mem_dout_a\[26\]
+mem_dout_a\[27\]
+mem_dout_a\[28\]
+mem_dout_a\[29\]
+mem_dout_a\[30\]
+mem_dout_a\[31\]
+
+
+mem_clk_a 0200 0 2
+mem_cen_a
+mem_addr_a\[7\]
+mem_addr_a\[6\]
+mem_addr_a\[5\]
+mem_addr_a\[4\]
+mem_addr_a\[3\]
+mem_addr_a\[2\]
+mem_addr_a\[1\]
+mem_addr_a\[0\]
diff --git a/openlane/mbist_top2/sta.tcl b/openlane/mbist_top2/sta.tcl
new file mode 100644
index 0000000..57a6c35
--- /dev/null
+++ b/openlane/mbist_top2/sta.tcl
@@ -0,0 +1,88 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+
+set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
+set ::env(LIB_TYPICAL) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"
+set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
+set ::env(DESIGN_NAME) "mbist_top"
+set ::env(BASE_SDC_FILE) "base.sdc"
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
+set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
+set ::env(SYNTH_CAP_LOAD) "17.65"
+set ::env(WIRE_RC_LAYER) "met1"
+
+#To disable empty filler cell black box get created
+#set link_make_black_boxes 0
+
+
+set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
+define_corners wc bc tt
+read_liberty -corner bc $::env(LIB_FASTEST)
+read_liberty -corner wc $::env(LIB_SLOWEST)
+read_liberty -corner tt $::env(LIB_TYPICAL)
+
+
+read_verilog ../user_project_wrapper/netlist/mbist.v
+link_design $::env(DESIGN_NAME)
+
+
+read_spef ../../spef/mbist_top.spef
+
+
+read_sdc -echo $::env(BASE_SDC_FILE)
+
+# check for missing constraints
+check_setup -verbose > unconstraints.rpt
+
+set_operating_conditions -analysis_type single
+# Propgate the clock
+set_propagated_clock [all_clocks]
+
+report_tns
+report_wns
+#report_power
+echo "################ CORNER : WC (SLOW) TIMING Report ###################" > timing_ss_max.rpt
+report_checks -unique -path_delay max -slack_max -0.0 -group_count 100 -corner wc >> timing_ss_max.rpt
+report_checks -group_count 100 -path_delay max -path_group bist_clk -corner wc >> timing_ss_max.rpt
+report_checks -group_count 100 -path_delay max -path_group mem_clk_a -corner wc >> timing_ss_max.rpt
+report_checks -group_count 100 -path_delay max -path_group mem_clk_b -corner wc >> timing_ss_max.rpt
+report_checks -path_delay max -corner wc >> timing_ss_max.rpt
+
+echo "################ CORNER : BC (SLOW) TIMING Report ###################" > timing_ff_min.rpt
+report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner bc >> timing_ff_min.rpt
+report_checks -group_count 100 -path_delay min -path_group bist_clk -corner bc >> timing_ff_min.rpt
+report_checks -group_count 100 -path_delay min -path_group mem_clk_a -corner bc >> timing_ff_min.rpt
+report_checks -group_count 100 -path_delay min -path_group mem_clk_b -corner bc >> timing_ff_min.rpt
+report_checks -path_delay min -corner bc >> timing_ff_min.rpt
+
+echo "################ CORNER : TT (MAX) TIMING Report ###################" > timing_tt_max.rpt
+report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner tt >> timing_tt_max.rpt
+report_checks -group_count 100 -path_delay max -path_group bist_clk -corner tt >> timing_tt_max.rpt
+report_checks -group_count 100 -path_delay max -path_group mem_clk_a -corner tt >> timing_tt_max.rpt
+report_checks -group_count 100 -path_delay max -path_group mem_clk_b -corner tt >> timing_tt_max.rpt
+report_checks -path_delay min -corner tt >> timing_tt_min.rpt
+
+echo "################ CORNER : TT (MIN) TIMING Report ###################" > timing_tt_min.rpt
+report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner tt >> timing_tt_min.rpt
+report_checks -group_count 100 -path_delay min -path_group bist_clk -corner tt >> timing_tt_min.rpt
+report_checks -group_count 100 -path_delay min -path_group mem_clk_a -corner tt >> timing_tt_min.rpt
+report_checks -group_count 100 -path_delay min -path_group mem_clk_b -corner tt >> timing_tt_min.rpt
+report_checks -path_delay min -corner tt >> timing_tt_min.rpt
+
+report_checks -path_delay min
+
+#exit
diff --git a/openlane/user_project_wrapper/base.sdc b/openlane/user_project_wrapper/base.sdc
new file mode 100644
index 0000000..689e7e8
--- /dev/null
+++ b/openlane/user_project_wrapper/base.sdc
@@ -0,0 +1,896 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+
+set_units -time ns
+set ::env(WBM_CLOCK_PERIOD) "10"
+set ::env(WBM_CLOCK_PORT) "wb_clk_i"
+set ::env(WBM_CLOCK_NAME) "wbm_clk_i"
+
+set ::env(WBS_CLOCK_PERIOD) "10"
+set ::env(WBS_CLOCK_PORT) "u_wb_host*mem_clk"
+set ::env(WBS_CLOCK_NAME) "mem_clk"
+
+set ::env(BIST_CLOCK_PERIOD) "20"
+set ::env(BIST_CLOCK_PORT) "u_wb_host*bist_clk"
+set ::env(BIST_CLOCK_NAME) "bist_clk"
+
+######################################
+# WB MASTER Clock domain input output
+######################################
+create_clock -name user_clock2 -period 100.0000 [get_ports {user_clock2}]
+create_clock -name wbm_clk_i -period 10.0000 [get_ports {wb_clk_i}]
+create_clock -name wbs_clk_i -period 10.0000 [get_pins {u_wb_host/wbs_clk_out}]
+
+set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}] -setup 0.2000
+
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}] -setup 0.2000
+
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}] -setup 0.2000
+
+set_clock_groups -name async_clock -asynchronous \
+ -group [get_clocks {user_clock2}]\
+ -group [get_clocks {wbm_clk_i}]\
+ -group [get_clocks {wbs_clk_i}] -comment {Async Clock group}
+
+set_input_delay 2.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wb_rst_i}]
+
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[*]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_cyc_i}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[*]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_sel_i[*]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_stb_i}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_we_i}]
+
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[*]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_cyc_i}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[*]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_sel_i[*]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_stb_i}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_we_i}]
+
+
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_ack_o}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[0]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[10]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[11]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[12]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[13]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[14]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[15]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[16]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[17]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[18]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[19]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[1]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[20]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[21]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[22]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[23]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[24]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[25]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[26]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[27]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[28]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[29]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[2]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[30]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[31]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[3]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[4]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[5]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[6]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[7]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[8]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[9]}]
+
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_ack_o}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[0]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[10]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[11]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[12]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[13]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[14]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[15]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[16]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[17]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[18]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[19]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[1]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[20]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[21]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[22]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[23]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[24]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[25]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[26]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[27]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[28]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[29]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[2]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[30]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[31]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[3]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[4]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[5]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[6]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[7]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[8]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[9]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {wbs_ack_o}]
+set_load -pin_load 0.0334 [get_ports {analog_io[28]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[27]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[26]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[25]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[24]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[23]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[22]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[21]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[20]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[19]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[18]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[17]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[16]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[15]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[14]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[13]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[12]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[11]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[10]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[9]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[8]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[7]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[6]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[5]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[4]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[3]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[2]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[1]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[0]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[37]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[36]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[35]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[34]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[33]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[32]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[31]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[30]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[29]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[28]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[27]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[26]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[25]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[24]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[23]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[22]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[21]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[20]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[19]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[18]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[17]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[16]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[15]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[14]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[13]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[12]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[11]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[10]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[9]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[8]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[7]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[6]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[5]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[4]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[3]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[2]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[1]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[0]}]
+set_load -pin_load 0.0334 [get_ports {io_out[37]}]
+set_load -pin_load 0.0334 [get_ports {io_out[36]}]
+set_load -pin_load 0.0334 [get_ports {io_out[35]}]
+set_load -pin_load 0.0334 [get_ports {io_out[34]}]
+set_load -pin_load 0.0334 [get_ports {io_out[33]}]
+set_load -pin_load 0.0334 [get_ports {io_out[32]}]
+set_load -pin_load 0.0334 [get_ports {io_out[31]}]
+set_load -pin_load 0.0334 [get_ports {io_out[30]}]
+set_load -pin_load 0.0334 [get_ports {io_out[29]}]
+set_load -pin_load 0.0334 [get_ports {io_out[28]}]
+set_load -pin_load 0.0334 [get_ports {io_out[27]}]
+set_load -pin_load 0.0334 [get_ports {io_out[26]}]
+set_load -pin_load 0.0334 [get_ports {io_out[25]}]
+set_load -pin_load 0.0334 [get_ports {io_out[24]}]
+set_load -pin_load 0.0334 [get_ports {io_out[23]}]
+set_load -pin_load 0.0334 [get_ports {io_out[22]}]
+set_load -pin_load 0.0334 [get_ports {io_out[21]}]
+set_load -pin_load 0.0334 [get_ports {io_out[20]}]
+set_load -pin_load 0.0334 [get_ports {io_out[19]}]
+set_load -pin_load 0.0334 [get_ports {io_out[18]}]
+set_load -pin_load 0.0334 [get_ports {io_out[17]}]
+set_load -pin_load 0.0334 [get_ports {io_out[16]}]
+set_load -pin_load 0.0334 [get_ports {io_out[15]}]
+set_load -pin_load 0.0334 [get_ports {io_out[14]}]
+set_load -pin_load 0.0334 [get_ports {io_out[13]}]
+set_load -pin_load 0.0334 [get_ports {io_out[12]}]
+set_load -pin_load 0.0334 [get_ports {io_out[11]}]
+set_load -pin_load 0.0334 [get_ports {io_out[10]}]
+set_load -pin_load 0.0334 [get_ports {io_out[9]}]
+set_load -pin_load 0.0334 [get_ports {io_out[8]}]
+set_load -pin_load 0.0334 [get_ports {io_out[7]}]
+set_load -pin_load 0.0334 [get_ports {io_out[6]}]
+set_load -pin_load 0.0334 [get_ports {io_out[5]}]
+set_load -pin_load 0.0334 [get_ports {io_out[4]}]
+set_load -pin_load 0.0334 [get_ports {io_out[3]}]
+set_load -pin_load 0.0334 [get_ports {io_out[2]}]
+set_load -pin_load 0.0334 [get_ports {io_out[1]}]
+set_load -pin_load 0.0334 [get_ports {io_out[0]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[127]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[126]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[125]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[124]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[123]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[122]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[121]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[120]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[119]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[118]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[117]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[116]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[115]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[114]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[113]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[112]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[111]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[110]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[109]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[108]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[107]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[106]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[105]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[104]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[103]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[102]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[101]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[100]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[99]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[98]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[97]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[96]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[95]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[94]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[93]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[92]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[91]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[90]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[89]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[88]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[87]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[86]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[85]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[84]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[83]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[82]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[81]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[80]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[79]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[78]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[77]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[76]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[75]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[74]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[73]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[72]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[71]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[70]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[69]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[68]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[67]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[66]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[65]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[64]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[63]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[62]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[61]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[60]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[59]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[58]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[57]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[56]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[55]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[54]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[53]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[52]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[51]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[50]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[49]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[48]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[47]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[46]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[45]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[44]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[43]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[42]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[41]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[40]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[39]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[38]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[37]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[36]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[35]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[34]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[33]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[32]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[31]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[30]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[29]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[28]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[27]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[26]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[25]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[24]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[23]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[22]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[21]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[20]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[19]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[18]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[17]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[16]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[15]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[14]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[13]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[12]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[11]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[10]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[9]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[8]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[7]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[6]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[5]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[4]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[3]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[2]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[1]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[0]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[2]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[1]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[0]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_clock2}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_stb_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[127]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[126]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[125]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[124]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[123]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[122]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[121]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[120]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[119]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[118]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[117]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[116]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[115]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[114]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[113]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[112]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[111]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[110]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[109]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[108]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[107]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[106]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[105]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[104]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[103]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[102]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[101]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[100]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[99]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[98]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[97]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[96]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[95]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[94]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[93]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[92]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[91]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[90]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[89]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[88]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[87]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[86]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[85]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[84]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[83]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[82]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[81]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[80]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[79]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[78]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[77]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[76]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[75]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[74]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[73]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[72]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[71]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[70]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[69]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[68]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[67]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[66]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[65]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[64]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[63]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[62]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[61]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[60]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[59]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[58]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[57]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[56]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[55]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[54]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[53]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[52]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[51]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[50]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[49]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[48]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[47]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[46]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[45]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[44]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[43]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[42]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[127]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[126]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[125]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[124]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[123]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[122]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[121]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[120]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[119]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[118]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[117]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[116]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[115]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[114]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[113]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[112]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[111]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[110]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[109]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[108]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[107]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[106]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[105]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[104]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[103]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[102]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[101]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[100]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[99]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[98]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[97]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[96]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[95]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[94]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[93]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[92]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[91]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[90]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[89]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[88]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[87]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[86]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[85]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[84]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[83]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[82]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[81]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[80]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[79]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[78]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[77]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[76]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[75]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[74]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[73]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[72]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[71]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[70]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[69]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[68]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[67]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[66]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[65]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[64]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[63]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[62]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[61]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[60]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[59]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[58]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[57]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[56]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[55]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[54]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[53]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[52]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[51]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[50]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[49]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[48]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[47]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[46]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[45]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[44]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[43]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[42]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[0]}]
+
+## Case analysis
+set_case_analysis 0 [get_pins {u_intercon/cfg_cska_wi[0]}]
+set_case_analysis 0 [get_pins {u_intercon/cfg_cska_wi[1]}]
+set_case_analysis 0 [get_pins {u_intercon/cfg_cska_wi[2]}]
+set_case_analysis 1 [get_pins {u_intercon/cfg_cska_wi[3]}]
+
+set_case_analysis 1 [get_pins {u_glbl/cfg_cska_glbl[0]}]
+set_case_analysis 1 [get_pins {u_glbl/cfg_cska_glbl[1]}]
+set_case_analysis 1 [get_pins {u_glbl/cfg_cska_glbl[2]}]
+set_case_analysis 0 [get_pins {u_glbl/cfg_cska_glbl[3]}]
+
+set_case_analysis 1 [get_pins {u_mbist1/cfg_cska_mbist[0]}]
+set_case_analysis 1 [get_pins {u_mbist1/cfg_cska_mbist[1]}]
+set_case_analysis 1 [get_pins {u_mbist1/cfg_cska_mbist[2]}]
+set_case_analysis 0 [get_pins {u_mbist1/cfg_cska_mbist[3]}]
+
+set_case_analysis 1 [get_pins {u_mbist2/cfg_cska_mbist[0]}]
+set_case_analysis 1 [get_pins {u_mbist2/cfg_cska_mbist[1]}]
+set_case_analysis 1 [get_pins {u_mbist2/cfg_cska_mbist[2]}]
+set_case_analysis 0 [get_pins {u_mbist2/cfg_cska_mbist[3]}]
+
+set_case_analysis 1 [get_pins {u_mbist3/cfg_cska_mbist[0]}]
+set_case_analysis 1 [get_pins {u_mbist3/cfg_cska_mbist[1]}]
+set_case_analysis 1 [get_pins {u_mbist3/cfg_cska_mbist[2]}]
+set_case_analysis 0 [get_pins {u_mbist3/cfg_cska_mbist[3]}]
+
+set_case_analysis 1 [get_pins {u_mbist4/cfg_cska_mbist[0]}]
+set_case_analysis 1 [get_pins {u_mbist4/cfg_cska_mbist[1]}]
+set_case_analysis 1 [get_pins {u_mbist4/cfg_cska_mbist[2]}]
+set_case_analysis 0 [get_pins {u_mbist4/cfg_cska_mbist[3]}]
+
+set_case_analysis 1 [get_pins {u_mbist5/cfg_cska_mbist[0]}]
+set_case_analysis 1 [get_pins {u_mbist5/cfg_cska_mbist[1]}]
+set_case_analysis 1 [get_pins {u_mbist5/cfg_cska_mbist[2]}]
+set_case_analysis 0 [get_pins {u_mbist5/cfg_cska_mbist[3]}]
+
+set_case_analysis 1 [get_pins {u_mbist6/cfg_cska_mbist[0]}]
+set_case_analysis 1 [get_pins {u_mbist6/cfg_cska_mbist[1]}]
+set_case_analysis 1 [get_pins {u_mbist6/cfg_cska_mbist[2]}]
+set_case_analysis 0 [get_pins {u_mbist6/cfg_cska_mbist[3]}]
+
+set_case_analysis 1 [get_pins {u_mbist7/cfg_cska_mbist[0]}]
+set_case_analysis 1 [get_pins {u_mbist7/cfg_cska_mbist[1]}]
+set_case_analysis 1 [get_pins {u_mbist7/cfg_cska_mbist[2]}]
+set_case_analysis 0 [get_pins {u_mbist7/cfg_cska_mbist[3]}]
+
+set_case_analysis 1 [get_pins {u_mbist8/cfg_cska_mbist[0]}]
+set_case_analysis 1 [get_pins {u_mbist8/cfg_cska_mbist[1]}]
+set_case_analysis 1 [get_pins {u_mbist8/cfg_cska_mbist[2]}]
+set_case_analysis 0 [get_pins {u_mbist8/cfg_cska_mbist[3]}]
+
+set_case_analysis 0 [get_pins {u_wb_host/cfg_cska_wh[0]}]
+set_case_analysis 1 [get_pins {u_wb_host/cfg_cska_wh[1]}]
+set_case_analysis 1 [get_pins {u_wb_host/cfg_cska_wh[2]}]
+set_case_analysis 0 [get_pins {u_wb_host/cfg_cska_wh[3]}]
+
+#disable clock gating check at static clock select pins
+set_false_path -through [get_pins u_wb_host/u_wbs_clk_sel.u_mux/S]
+
+#Strobe is registered inside the wb_host before generating chip select
+# So wbm_adr_i wbm_we_i wbm_sel_i wbm_dat_i are having 2 cycle setup
+
+set_multicycle_path -setup -from [get_ports {wbs_adr_i[*]}] 2
+set_multicycle_path -setup -from [get_ports {wbs_cyc_i}] 2
+set_multicycle_path -setup -from [get_ports {wbs_dat_i[*]}] 2
+set_multicycle_path -setup -from [get_ports {wbs_sel_i[*]}] 2
+set_multicycle_path -setup -from [get_ports {wbs_we_i}] 2
+
+set_multicycle_path -hold -from [get_ports {wbs_adr_i[*]}] 2
+set_multicycle_path -hold -from [get_ports {wbs_cyc_i}] 2
+set_multicycle_path -hold -from [get_ports {wbs_dat_i[*]}] 2
+set_multicycle_path -hold -from [get_ports {wbs_sel_i[*]}] 2
+set_multicycle_path -hold -from [get_ports {wbs_we_i}] 2
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
new file mode 100755
index 0000000..3632430
--- /dev/null
+++ b/openlane/user_project_wrapper/config.tcl
@@ -0,0 +1,198 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Base Configurations. Don't Touch
+# section begin
+
+set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
+
+# YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS
+source $::env(DESIGN_DIR)/fixed_dont_change/fixed_wrapper_cfgs.tcl
+
+
+# YOU CAN CHANGE ANY VARIABLES DEFINED IN THE DEFAULT WRAPPER CFGS BY OVERRIDING THEM IN THIS CONFIG.TCL
+source $::env(DESIGN_DIR)/fixed_dont_change/default_wrapper_cfgs.tcl
+
+
+set script_dir [file dirname [file normalize [info script]]]
+set proj_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) user_project_wrapper
+set verilog_root $::env(DESIGN_DIR)/../../verilog/
+set lef_root $::env(DESIGN_DIR)/../../lef/
+set gds_root $::env(DESIGN_DIR)/../../gds/
+#section end
+
+# User Configurations
+#
+set ::env(DESIGN_IS_CORE) 1
+
+
+## Source Verilog Files
+set ::env(VERILOG_FILES) "\
+ $::env(DESIGN_DIR)/../../verilog/rtl/user_project_wrapper.v"
+
+
+## Clock configurations
+set ::env(CLOCK_PORT) "user_clock2 wb_clk_i"
+#set ::env(CLOCK_NET) "mprj.clk"
+
+set ::env(CLOCK_PERIOD) "10"
+
+## Internal Macros
+### Macro Placement
+set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
+
+set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn_cfg.tcl
+
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+
+### Black-box verilog and views
+set ::env(VERILOG_FILES_BLACKBOX) "\
+ $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
+ $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/wb_interconnect.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/wb_host.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/glbl_cfg.v\
+ $::env(DESIGN_DIR)/../../verilog/gl/mbist_top1.v\
+ $::env(DESIGN_DIR)/../../verilog/gl/mbist_top2.v\
+ "
+
+set ::env(EXTRA_LEFS) "\
+ $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
+ $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef \
+ $::env(DESIGN_DIR)/../../lef/glbl_cfg.lef \
+ $::env(DESIGN_DIR)/../../lef/mbist_top1.lef \
+ $::env(DESIGN_DIR)/../../lef/mbist_top2.lef \
+ $::env(DESIGN_DIR)/../../lef/wb_interconnect.lef \
+ $::env(DESIGN_DIR)/../../lef/wb_host.lef"
+
+set ::env(EXTRA_GDS_FILES) "\
+ $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
+ $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds \
+ $::env(DESIGN_DIR)/../../gds/glbl_cfg.gds \
+ $::env(DESIGN_DIR)/../../gds/mbist_top1.gds \
+ $::env(DESIGN_DIR)/../../gds/mbist_top2.gds \
+ $::env(DESIGN_DIR)/../../gds/wb_interconnect.gds \
+ $::env(DESIGN_DIR)/../../gds/wb_host.gds"
+
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+
+#set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/includes ]
+
+#set ::env(GLB_RT_MAXLAYER) 6
+set ::env(RT_MAX_LAYER) {met5}
+
+## Internal Macros
+### Macro PDN Connections
+set ::env(FP_PDN_CHECK_NODES) 1
+set ::env(FP_PDN_IRDROP) "1"
+set ::env(RUN_IRDROP_REPORT) "1"
+####################
+
+set ::env(FP_PDN_ENABLE_MACROS_GRID) {1}
+set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "0"
+set ::env(FP_PDN_CHECK_NODES) 1
+set ::env(FP_PDN_ENABLE_RAILS) 0
+set ::env(FP_PDN_IRDROP) "1"
+
+set ::env(VDD_NETS) {vccd1 vccd2 vdda1 vdda2}
+set ::env(GND_NETS) {vssd1 vssd2 vssa1 vssa2}
+#
+set ::env(VDD_NET) {vccd1}
+set ::env(GND_NET) {vssd1}
+set ::env(VDD_PIN) {vccd1}
+set ::env(GND_PIN) {vssd1}
+
+set ::env(PDN_STRIPE) {vccd1 vssd1 }
+set ::env(DRT_OPT_ITERS) {32}
+
+# Add Blockage arond the SRAM to avoid Magic DRC &
+# add signal routing blockage for met5
+set ::env(GLB_RT_OBS) "met1 2000.00 800.00 2683.10 1216.54, \
+ met2 2000.00 800.00 2683.10 1216.54, \
+ met3 2000.00 800.00 2683.10 1216.54, \
+ met1 2000.00 1400.00 2683.10 1816.54, \
+ met2 2000.00 1400.00 2683.10 1816.54, \
+ met3 2000.00 1400.00 2683.10 1816.54, \
+ met1 2000.00 2000.00 2683.10 2416.54, \
+ met2 2000.00 2000.00 2683.10 2416.54, \
+ met3 2000.00 2000.00 2683.10 2416.54, \
+ met1 2000.00 2600.00 2683.10 3016.54, \
+ met2 2000.00 2600.00 2683.10 3016.54, \
+ met3 2000.00 2600.00 2683.10 3016.54, \
+ met1 200.00 1200.00 679.78 1597.5, \
+ met2 200.00 1200.00 679.78 1597.5, \
+ met3 200.00 1200.00 679.78 1597.5, \
+ met1 200.00 1800.00 679.78 2197.5, \
+ met2 200.00 1800.00 679.78 2197.5, \
+ met3 200.00 1800.00 679.78 2197.5, \
+ met1 200.00 2400.00 679.78 2797.5, \
+ met2 200.00 2400.00 679.78 2797.5, \
+ met3 200.00 2400.00 679.78 2797.5, \
+ met1 200.00 3000.00 679.78 3397.5, \
+ met2 200.00 3000.00 679.78 3397.5, \
+ met3 200.00 3000.00 679.78 3397.5, \
+ met5 0 0 2920 3520"
+
+
+set ::env(FP_PDN_MACRO_HOOKS) "\
+ u_wb_host vccd1 vssd1 vccd1 vssd1,\
+ u_intercon vccd1 vssd1 vccd1 vssd1,\
+ u_glbl vccd1 vssd1 vccd1 vssd1,\
+ u_mbist1 vccd1 vssd1 vccd1 vssd1,\
+ u_mbist2 vccd1 vssd1 vccd1 vssd1,\
+ u_mbist3 vccd1 vssd1 vccd1 vssd1,\
+ u_mbist4 vccd1 vssd1 vccd1 vssd1,\
+ u_mbist5 vccd1 vssd1 vccd1 vssd1,\
+ u_mbist6 vccd1 vssd1 vccd1 vssd1,\
+ u_mbist7 vccd1 vssd1 vccd1 vssd1,\
+ u_mbist8 vccd1 vssd1 vccd1 vssd1,\
+ u_sram1_2kb vccd1 vssd1 vccd1 vssd1,\
+ u_sram2_2kb vccd1 vssd1 vccd1 vssd1,\
+ u_sram3_2kb vccd1 vssd1 vccd1 vssd1,\
+ u_sram4_2kb vccd1 vssd1 vccd1 vssd1,\
+ u_sram5_1kb vccd1 vssd1 vccd1 vssd1,\
+ u_sram6_1kb vccd1 vssd1 vccd1 vssd1,\
+ u_sram7_1kb vccd1 vssd1 vccd1 vssd1,\
+ u_sram8_1kb vccd1 vssd1 vccd1 vssd1\
+ "
+
+
+# The following is because there are no std cells in the example wrapper project.
+set ::env(SYNTH_TOP_LEVEL) 0
+set ::env(PL_RANDOM_GLB_PLACEMENT) 1
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {0}
+set ::env(GLB_OPTIMIZE_MIRRORING) {0}
+set ::env(DIODE_INSERTION_STRATEGY) 0
+set ::env(RUN_FILL_INSERTION) 0
+set ::env(RUN_TAP_DECAP_INSERTION) 0
+set ::env(CLOCK_TREE_SYNTH) 0
+set ::env(QUIT_ON_LVS_ERROR) "1"
+set ::env(QUIT_ON_MAGIC_DRC) "0"
+set ::env(QUIT_ON_NEGATIVE_WNS) "0"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+
+## Temp Masked due to long Run Time
+set ::env(RUN_KLAYOUT_XOR) {0}
+
diff --git a/openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl b/openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl
new file mode 100644
index 0000000..4a4f8a2
--- /dev/null
+++ b/openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl
@@ -0,0 +1,24 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# THE FOLLOWING SECTIONS CAN BE CHANGED IF NEEDED
+
+# PDN Pitch
+set ::env(FP_PDN_VPITCH) 180
+set ::env(FP_PDN_HPITCH) $::env(FP_PDN_VPITCH)
+
+# PDN Offset
+set ::env(FP_PDN_VOFFSET) 5
+set ::env(FP_PDN_HOFFSET) $::env(FP_PDN_VOFFSET)
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl b/openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl
new file mode 100644
index 0000000..e602da7
--- /dev/null
+++ b/openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl
@@ -0,0 +1,57 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# DON'T TOUCH THE FOLLOWING SECTIONS
+set script_dir [file dirname [file normalize [info script]]]
+
+# This makes sure that the core rings are outside the boundaries
+# of your block.
+set ::env(MAGIC_ZEROIZE_ORIGIN) 0
+
+# Area Configurations. DON'T TOUCH.
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 2920 3520"
+
+set ::env(RUN_CVC) 0
+
+set ::unit 2.4
+set ::env(FP_IO_VEXTEND) [expr 2*$::unit]
+set ::env(FP_IO_HEXTEND) [expr 2*$::unit]
+set ::env(FP_IO_VLENGTH) $::unit
+set ::env(FP_IO_HLENGTH) $::unit
+
+set ::env(FP_IO_VTHICKNESS_MULT) 4
+set ::env(FP_IO_HTHICKNESS_MULT) 4
+
+# Power & Pin Configurations. DON'T TOUCH.
+set ::env(FP_PDN_CORE_RING) 1
+set ::env(FP_PDN_CORE_RING_VWIDTH) 3.1
+set ::env(FP_PDN_CORE_RING_HWIDTH) 3.1
+set ::env(FP_PDN_CORE_RING_VOFFSET) 12.45
+set ::env(FP_PDN_CORE_RING_HOFFSET) $::env(FP_PDN_CORE_RING_VOFFSET)
+set ::env(FP_PDN_CORE_RING_VSPACING) 1.7
+set ::env(FP_PDN_CORE_RING_HSPACING) $::env(FP_PDN_CORE_RING_VSPACING)
+
+set ::env(FP_PDN_VWIDTH) 3.1
+set ::env(FP_PDN_HWIDTH) 3.1
+set ::env(FP_PDN_VSPACING) [expr 5*$::env(FP_PDN_CORE_RING_VWIDTH)]
+set ::env(FP_PDN_HSPACING) [expr 5*$::env(FP_PDN_CORE_RING_HWIDTH)]
+
+set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
+set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
+set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
+
+# Pin placement template
+set ::env(FP_DEF_TEMPLATE) $::env(DESIGN_DIR)/fixed_dont_change/user_project_wrapper.def
diff --git a/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper.def b/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper.def
new file mode 100644
index 0000000..0647d54
--- /dev/null
+++ b/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper.def
@@ -0,0 +1,7656 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN user_project_wrapper ;
+UNITS DISTANCE MICRONS 1000 ;
+DIEAREA ( 0 0 ) ( 2920000 3520000 ) ;
+ROW ROW_0 unithd 5520 10880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1 unithd 5520 13600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_2 unithd 5520 16320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_3 unithd 5520 19040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_4 unithd 5520 21760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_5 unithd 5520 24480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_6 unithd 5520 27200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_7 unithd 5520 29920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_8 unithd 5520 32640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_9 unithd 5520 35360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_10 unithd 5520 38080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_11 unithd 5520 40800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_12 unithd 5520 43520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_13 unithd 5520 46240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_14 unithd 5520 48960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_15 unithd 5520 51680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_16 unithd 5520 54400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_17 unithd 5520 57120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_18 unithd 5520 59840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_19 unithd 5520 62560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_20 unithd 5520 65280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_21 unithd 5520 68000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_22 unithd 5520 70720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_23 unithd 5520 73440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_24 unithd 5520 76160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_25 unithd 5520 78880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_26 unithd 5520 81600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_27 unithd 5520 84320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_28 unithd 5520 87040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_29 unithd 5520 89760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_30 unithd 5520 92480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_31 unithd 5520 95200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_32 unithd 5520 97920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_33 unithd 5520 100640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_34 unithd 5520 103360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_35 unithd 5520 106080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_36 unithd 5520 108800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_37 unithd 5520 111520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_38 unithd 5520 114240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_39 unithd 5520 116960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_40 unithd 5520 119680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_41 unithd 5520 122400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_42 unithd 5520 125120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_43 unithd 5520 127840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_44 unithd 5520 130560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_45 unithd 5520 133280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_46 unithd 5520 136000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_47 unithd 5520 138720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_48 unithd 5520 141440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_49 unithd 5520 144160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_50 unithd 5520 146880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_51 unithd 5520 149600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_52 unithd 5520 152320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_53 unithd 5520 155040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_54 unithd 5520 157760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_55 unithd 5520 160480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_56 unithd 5520 163200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_57 unithd 5520 165920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_58 unithd 5520 168640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_59 unithd 5520 171360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_60 unithd 5520 174080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_61 unithd 5520 176800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_62 unithd 5520 179520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_63 unithd 5520 182240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_64 unithd 5520 184960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_65 unithd 5520 187680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_66 unithd 5520 190400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_67 unithd 5520 193120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_68 unithd 5520 195840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_69 unithd 5520 198560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_70 unithd 5520 201280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_71 unithd 5520 204000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_72 unithd 5520 206720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_73 unithd 5520 209440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_74 unithd 5520 212160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_75 unithd 5520 214880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_76 unithd 5520 217600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_77 unithd 5520 220320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_78 unithd 5520 223040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_79 unithd 5520 225760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_80 unithd 5520 228480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_81 unithd 5520 231200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_82 unithd 5520 233920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_83 unithd 5520 236640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_84 unithd 5520 239360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_85 unithd 5520 242080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_86 unithd 5520 244800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_87 unithd 5520 247520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_88 unithd 5520 250240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_89 unithd 5520 252960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_90 unithd 5520 255680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_91 unithd 5520 258400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_92 unithd 5520 261120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_93 unithd 5520 263840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_94 unithd 5520 266560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_95 unithd 5520 269280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_96 unithd 5520 272000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_97 unithd 5520 274720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_98 unithd 5520 277440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_99 unithd 5520 280160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_100 unithd 5520 282880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_101 unithd 5520 285600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_102 unithd 5520 288320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_103 unithd 5520 291040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_104 unithd 5520 293760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_105 unithd 5520 296480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_106 unithd 5520 299200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_107 unithd 5520 301920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_108 unithd 5520 304640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_109 unithd 5520 307360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_110 unithd 5520 310080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_111 unithd 5520 312800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_112 unithd 5520 315520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_113 unithd 5520 318240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_114 unithd 5520 320960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_115 unithd 5520 323680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_116 unithd 5520 326400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_117 unithd 5520 329120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_118 unithd 5520 331840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_119 unithd 5520 334560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_120 unithd 5520 337280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_121 unithd 5520 340000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_122 unithd 5520 342720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_123 unithd 5520 345440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_124 unithd 5520 348160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_125 unithd 5520 350880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_126 unithd 5520 353600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_127 unithd 5520 356320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_128 unithd 5520 359040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_129 unithd 5520 361760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_130 unithd 5520 364480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_131 unithd 5520 367200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_132 unithd 5520 369920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_133 unithd 5520 372640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_134 unithd 5520 375360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_135 unithd 5520 378080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_136 unithd 5520 380800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_137 unithd 5520 383520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_138 unithd 5520 386240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_139 unithd 5520 388960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_140 unithd 5520 391680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_141 unithd 5520 394400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_142 unithd 5520 397120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_143 unithd 5520 399840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_144 unithd 5520 402560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_145 unithd 5520 405280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_146 unithd 5520 408000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_147 unithd 5520 410720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_148 unithd 5520 413440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_149 unithd 5520 416160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_150 unithd 5520 418880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_151 unithd 5520 421600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_152 unithd 5520 424320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_153 unithd 5520 427040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_154 unithd 5520 429760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_155 unithd 5520 432480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_156 unithd 5520 435200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_157 unithd 5520 437920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_158 unithd 5520 440640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_159 unithd 5520 443360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_160 unithd 5520 446080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_161 unithd 5520 448800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_162 unithd 5520 451520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_163 unithd 5520 454240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_164 unithd 5520 456960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_165 unithd 5520 459680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_166 unithd 5520 462400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_167 unithd 5520 465120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_168 unithd 5520 467840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_169 unithd 5520 470560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_170 unithd 5520 473280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_171 unithd 5520 476000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_172 unithd 5520 478720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_173 unithd 5520 481440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_174 unithd 5520 484160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_175 unithd 5520 486880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_176 unithd 5520 489600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_177 unithd 5520 492320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_178 unithd 5520 495040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_179 unithd 5520 497760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_180 unithd 5520 500480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_181 unithd 5520 503200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_182 unithd 5520 505920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_183 unithd 5520 508640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_184 unithd 5520 511360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_185 unithd 5520 514080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_186 unithd 5520 516800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_187 unithd 5520 519520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_188 unithd 5520 522240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_189 unithd 5520 524960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_190 unithd 5520 527680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_191 unithd 5520 530400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_192 unithd 5520 533120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_193 unithd 5520 535840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_194 unithd 5520 538560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_195 unithd 5520 541280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_196 unithd 5520 544000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_197 unithd 5520 546720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_198 unithd 5520 549440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_199 unithd 5520 552160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_200 unithd 5520 554880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_201 unithd 5520 557600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_202 unithd 5520 560320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_203 unithd 5520 563040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_204 unithd 5520 565760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_205 unithd 5520 568480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_206 unithd 5520 571200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_207 unithd 5520 573920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_208 unithd 5520 576640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_209 unithd 5520 579360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_210 unithd 5520 582080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_211 unithd 5520 584800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_212 unithd 5520 587520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_213 unithd 5520 590240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_214 unithd 5520 592960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_215 unithd 5520 595680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_216 unithd 5520 598400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_217 unithd 5520 601120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_218 unithd 5520 603840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_219 unithd 5520 606560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_220 unithd 5520 609280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_221 unithd 5520 612000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_222 unithd 5520 614720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_223 unithd 5520 617440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_224 unithd 5520 620160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_225 unithd 5520 622880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_226 unithd 5520 625600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_227 unithd 5520 628320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_228 unithd 5520 631040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_229 unithd 5520 633760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_230 unithd 5520 636480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_231 unithd 5520 639200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_232 unithd 5520 641920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_233 unithd 5520 644640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_234 unithd 5520 647360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_235 unithd 5520 650080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_236 unithd 5520 652800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_237 unithd 5520 655520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_238 unithd 5520 658240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_239 unithd 5520 660960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_240 unithd 5520 663680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_241 unithd 5520 666400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_242 unithd 5520 669120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_243 unithd 5520 671840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_244 unithd 5520 674560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_245 unithd 5520 677280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_246 unithd 5520 680000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_247 unithd 5520 682720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_248 unithd 5520 685440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_249 unithd 5520 688160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_250 unithd 5520 690880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_251 unithd 5520 693600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_252 unithd 5520 696320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_253 unithd 5520 699040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_254 unithd 5520 701760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_255 unithd 5520 704480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_256 unithd 5520 707200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_257 unithd 5520 709920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_258 unithd 5520 712640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_259 unithd 5520 715360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_260 unithd 5520 718080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_261 unithd 5520 720800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_262 unithd 5520 723520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_263 unithd 5520 726240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_264 unithd 5520 728960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_265 unithd 5520 731680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_266 unithd 5520 734400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_267 unithd 5520 737120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_268 unithd 5520 739840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_269 unithd 5520 742560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_270 unithd 5520 745280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_271 unithd 5520 748000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_272 unithd 5520 750720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_273 unithd 5520 753440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_274 unithd 5520 756160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_275 unithd 5520 758880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_276 unithd 5520 761600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_277 unithd 5520 764320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_278 unithd 5520 767040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_279 unithd 5520 769760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_280 unithd 5520 772480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_281 unithd 5520 775200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_282 unithd 5520 777920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_283 unithd 5520 780640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_284 unithd 5520 783360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_285 unithd 5520 786080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_286 unithd 5520 788800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_287 unithd 5520 791520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_288 unithd 5520 794240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_289 unithd 5520 796960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_290 unithd 5520 799680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_291 unithd 5520 802400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_292 unithd 5520 805120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_293 unithd 5520 807840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_294 unithd 5520 810560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_295 unithd 5520 813280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_296 unithd 5520 816000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_297 unithd 5520 818720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_298 unithd 5520 821440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_299 unithd 5520 824160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_300 unithd 5520 826880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_301 unithd 5520 829600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_302 unithd 5520 832320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_303 unithd 5520 835040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_304 unithd 5520 837760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_305 unithd 5520 840480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_306 unithd 5520 843200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_307 unithd 5520 845920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_308 unithd 5520 848640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_309 unithd 5520 851360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_310 unithd 5520 854080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_311 unithd 5520 856800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_312 unithd 5520 859520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_313 unithd 5520 862240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_314 unithd 5520 864960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_315 unithd 5520 867680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_316 unithd 5520 870400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_317 unithd 5520 873120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_318 unithd 5520 875840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_319 unithd 5520 878560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_320 unithd 5520 881280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_321 unithd 5520 884000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_322 unithd 5520 886720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_323 unithd 5520 889440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_324 unithd 5520 892160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_325 unithd 5520 894880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_326 unithd 5520 897600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_327 unithd 5520 900320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_328 unithd 5520 903040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_329 unithd 5520 905760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_330 unithd 5520 908480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_331 unithd 5520 911200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_332 unithd 5520 913920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_333 unithd 5520 916640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_334 unithd 5520 919360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_335 unithd 5520 922080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_336 unithd 5520 924800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_337 unithd 5520 927520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_338 unithd 5520 930240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_339 unithd 5520 932960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_340 unithd 5520 935680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_341 unithd 5520 938400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_342 unithd 5520 941120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_343 unithd 5520 943840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_344 unithd 5520 946560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_345 unithd 5520 949280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_346 unithd 5520 952000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_347 unithd 5520 954720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_348 unithd 5520 957440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_349 unithd 5520 960160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_350 unithd 5520 962880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_351 unithd 5520 965600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_352 unithd 5520 968320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_353 unithd 5520 971040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_354 unithd 5520 973760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_355 unithd 5520 976480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_356 unithd 5520 979200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_357 unithd 5520 981920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_358 unithd 5520 984640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_359 unithd 5520 987360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_360 unithd 5520 990080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_361 unithd 5520 992800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_362 unithd 5520 995520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_363 unithd 5520 998240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_364 unithd 5520 1000960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_365 unithd 5520 1003680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_366 unithd 5520 1006400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_367 unithd 5520 1009120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_368 unithd 5520 1011840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_369 unithd 5520 1014560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_370 unithd 5520 1017280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_371 unithd 5520 1020000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_372 unithd 5520 1022720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_373 unithd 5520 1025440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_374 unithd 5520 1028160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_375 unithd 5520 1030880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_376 unithd 5520 1033600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_377 unithd 5520 1036320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_378 unithd 5520 1039040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_379 unithd 5520 1041760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_380 unithd 5520 1044480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_381 unithd 5520 1047200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_382 unithd 5520 1049920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_383 unithd 5520 1052640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_384 unithd 5520 1055360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_385 unithd 5520 1058080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_386 unithd 5520 1060800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_387 unithd 5520 1063520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_388 unithd 5520 1066240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_389 unithd 5520 1068960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_390 unithd 5520 1071680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_391 unithd 5520 1074400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_392 unithd 5520 1077120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_393 unithd 5520 1079840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_394 unithd 5520 1082560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_395 unithd 5520 1085280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_396 unithd 5520 1088000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_397 unithd 5520 1090720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_398 unithd 5520 1093440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_399 unithd 5520 1096160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_400 unithd 5520 1098880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_401 unithd 5520 1101600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_402 unithd 5520 1104320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_403 unithd 5520 1107040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_404 unithd 5520 1109760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_405 unithd 5520 1112480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_406 unithd 5520 1115200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_407 unithd 5520 1117920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_408 unithd 5520 1120640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_409 unithd 5520 1123360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_410 unithd 5520 1126080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_411 unithd 5520 1128800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_412 unithd 5520 1131520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_413 unithd 5520 1134240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_414 unithd 5520 1136960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_415 unithd 5520 1139680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_416 unithd 5520 1142400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_417 unithd 5520 1145120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_418 unithd 5520 1147840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_419 unithd 5520 1150560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_420 unithd 5520 1153280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_421 unithd 5520 1156000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_422 unithd 5520 1158720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_423 unithd 5520 1161440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_424 unithd 5520 1164160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_425 unithd 5520 1166880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_426 unithd 5520 1169600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_427 unithd 5520 1172320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_428 unithd 5520 1175040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_429 unithd 5520 1177760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_430 unithd 5520 1180480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_431 unithd 5520 1183200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_432 unithd 5520 1185920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_433 unithd 5520 1188640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_434 unithd 5520 1191360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_435 unithd 5520 1194080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_436 unithd 5520 1196800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_437 unithd 5520 1199520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_438 unithd 5520 1202240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_439 unithd 5520 1204960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_440 unithd 5520 1207680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_441 unithd 5520 1210400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_442 unithd 5520 1213120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_443 unithd 5520 1215840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_444 unithd 5520 1218560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_445 unithd 5520 1221280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_446 unithd 5520 1224000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_447 unithd 5520 1226720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_448 unithd 5520 1229440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_449 unithd 5520 1232160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_450 unithd 5520 1234880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_451 unithd 5520 1237600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_452 unithd 5520 1240320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_453 unithd 5520 1243040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_454 unithd 5520 1245760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_455 unithd 5520 1248480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_456 unithd 5520 1251200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_457 unithd 5520 1253920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_458 unithd 5520 1256640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_459 unithd 5520 1259360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_460 unithd 5520 1262080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_461 unithd 5520 1264800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_462 unithd 5520 1267520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_463 unithd 5520 1270240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_464 unithd 5520 1272960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_465 unithd 5520 1275680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_466 unithd 5520 1278400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_467 unithd 5520 1281120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_468 unithd 5520 1283840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_469 unithd 5520 1286560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_470 unithd 5520 1289280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_471 unithd 5520 1292000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_472 unithd 5520 1294720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_473 unithd 5520 1297440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_474 unithd 5520 1300160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_475 unithd 5520 1302880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_476 unithd 5520 1305600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_477 unithd 5520 1308320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_478 unithd 5520 1311040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_479 unithd 5520 1313760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_480 unithd 5520 1316480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_481 unithd 5520 1319200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_482 unithd 5520 1321920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_483 unithd 5520 1324640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_484 unithd 5520 1327360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_485 unithd 5520 1330080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_486 unithd 5520 1332800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_487 unithd 5520 1335520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_488 unithd 5520 1338240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_489 unithd 5520 1340960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_490 unithd 5520 1343680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_491 unithd 5520 1346400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_492 unithd 5520 1349120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_493 unithd 5520 1351840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_494 unithd 5520 1354560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_495 unithd 5520 1357280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_496 unithd 5520 1360000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_497 unithd 5520 1362720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_498 unithd 5520 1365440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_499 unithd 5520 1368160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_500 unithd 5520 1370880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_501 unithd 5520 1373600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_502 unithd 5520 1376320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_503 unithd 5520 1379040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_504 unithd 5520 1381760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_505 unithd 5520 1384480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_506 unithd 5520 1387200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_507 unithd 5520 1389920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_508 unithd 5520 1392640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_509 unithd 5520 1395360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_510 unithd 5520 1398080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_511 unithd 5520 1400800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_512 unithd 5520 1403520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_513 unithd 5520 1406240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_514 unithd 5520 1408960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_515 unithd 5520 1411680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_516 unithd 5520 1414400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_517 unithd 5520 1417120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_518 unithd 5520 1419840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_519 unithd 5520 1422560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_520 unithd 5520 1425280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_521 unithd 5520 1428000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_522 unithd 5520 1430720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_523 unithd 5520 1433440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_524 unithd 5520 1436160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_525 unithd 5520 1438880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_526 unithd 5520 1441600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_527 unithd 5520 1444320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_528 unithd 5520 1447040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_529 unithd 5520 1449760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_530 unithd 5520 1452480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_531 unithd 5520 1455200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_532 unithd 5520 1457920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_533 unithd 5520 1460640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_534 unithd 5520 1463360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_535 unithd 5520 1466080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_536 unithd 5520 1468800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_537 unithd 5520 1471520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_538 unithd 5520 1474240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_539 unithd 5520 1476960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_540 unithd 5520 1479680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_541 unithd 5520 1482400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_542 unithd 5520 1485120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_543 unithd 5520 1487840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_544 unithd 5520 1490560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_545 unithd 5520 1493280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_546 unithd 5520 1496000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_547 unithd 5520 1498720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_548 unithd 5520 1501440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_549 unithd 5520 1504160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_550 unithd 5520 1506880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_551 unithd 5520 1509600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_552 unithd 5520 1512320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_553 unithd 5520 1515040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_554 unithd 5520 1517760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_555 unithd 5520 1520480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_556 unithd 5520 1523200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_557 unithd 5520 1525920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_558 unithd 5520 1528640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_559 unithd 5520 1531360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_560 unithd 5520 1534080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_561 unithd 5520 1536800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_562 unithd 5520 1539520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_563 unithd 5520 1542240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_564 unithd 5520 1544960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_565 unithd 5520 1547680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_566 unithd 5520 1550400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_567 unithd 5520 1553120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_568 unithd 5520 1555840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_569 unithd 5520 1558560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_570 unithd 5520 1561280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_571 unithd 5520 1564000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_572 unithd 5520 1566720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_573 unithd 5520 1569440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_574 unithd 5520 1572160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_575 unithd 5520 1574880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_576 unithd 5520 1577600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_577 unithd 5520 1580320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_578 unithd 5520 1583040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_579 unithd 5520 1585760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_580 unithd 5520 1588480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_581 unithd 5520 1591200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_582 unithd 5520 1593920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_583 unithd 5520 1596640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_584 unithd 5520 1599360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_585 unithd 5520 1602080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_586 unithd 5520 1604800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_587 unithd 5520 1607520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_588 unithd 5520 1610240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_589 unithd 5520 1612960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_590 unithd 5520 1615680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_591 unithd 5520 1618400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_592 unithd 5520 1621120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_593 unithd 5520 1623840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_594 unithd 5520 1626560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_595 unithd 5520 1629280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_596 unithd 5520 1632000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_597 unithd 5520 1634720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_598 unithd 5520 1637440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_599 unithd 5520 1640160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_600 unithd 5520 1642880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_601 unithd 5520 1645600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_602 unithd 5520 1648320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_603 unithd 5520 1651040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_604 unithd 5520 1653760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_605 unithd 5520 1656480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_606 unithd 5520 1659200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_607 unithd 5520 1661920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_608 unithd 5520 1664640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_609 unithd 5520 1667360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_610 unithd 5520 1670080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_611 unithd 5520 1672800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_612 unithd 5520 1675520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_613 unithd 5520 1678240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_614 unithd 5520 1680960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_615 unithd 5520 1683680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_616 unithd 5520 1686400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_617 unithd 5520 1689120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_618 unithd 5520 1691840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_619 unithd 5520 1694560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_620 unithd 5520 1697280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_621 unithd 5520 1700000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_622 unithd 5520 1702720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_623 unithd 5520 1705440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_624 unithd 5520 1708160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_625 unithd 5520 1710880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_626 unithd 5520 1713600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_627 unithd 5520 1716320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_628 unithd 5520 1719040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_629 unithd 5520 1721760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_630 unithd 5520 1724480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_631 unithd 5520 1727200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_632 unithd 5520 1729920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_633 unithd 5520 1732640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_634 unithd 5520 1735360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_635 unithd 5520 1738080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_636 unithd 5520 1740800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_637 unithd 5520 1743520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_638 unithd 5520 1746240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_639 unithd 5520 1748960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_640 unithd 5520 1751680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_641 unithd 5520 1754400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_642 unithd 5520 1757120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_643 unithd 5520 1759840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_644 unithd 5520 1762560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_645 unithd 5520 1765280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_646 unithd 5520 1768000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_647 unithd 5520 1770720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_648 unithd 5520 1773440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_649 unithd 5520 1776160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_650 unithd 5520 1778880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_651 unithd 5520 1781600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_652 unithd 5520 1784320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_653 unithd 5520 1787040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_654 unithd 5520 1789760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_655 unithd 5520 1792480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_656 unithd 5520 1795200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_657 unithd 5520 1797920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_658 unithd 5520 1800640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_659 unithd 5520 1803360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_660 unithd 5520 1806080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_661 unithd 5520 1808800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_662 unithd 5520 1811520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_663 unithd 5520 1814240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_664 unithd 5520 1816960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_665 unithd 5520 1819680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_666 unithd 5520 1822400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_667 unithd 5520 1825120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_668 unithd 5520 1827840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_669 unithd 5520 1830560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_670 unithd 5520 1833280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_671 unithd 5520 1836000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_672 unithd 5520 1838720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_673 unithd 5520 1841440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_674 unithd 5520 1844160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_675 unithd 5520 1846880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_676 unithd 5520 1849600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_677 unithd 5520 1852320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_678 unithd 5520 1855040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_679 unithd 5520 1857760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_680 unithd 5520 1860480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_681 unithd 5520 1863200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_682 unithd 5520 1865920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_683 unithd 5520 1868640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_684 unithd 5520 1871360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_685 unithd 5520 1874080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_686 unithd 5520 1876800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_687 unithd 5520 1879520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_688 unithd 5520 1882240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_689 unithd 5520 1884960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_690 unithd 5520 1887680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_691 unithd 5520 1890400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_692 unithd 5520 1893120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_693 unithd 5520 1895840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_694 unithd 5520 1898560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_695 unithd 5520 1901280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_696 unithd 5520 1904000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_697 unithd 5520 1906720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_698 unithd 5520 1909440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_699 unithd 5520 1912160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_700 unithd 5520 1914880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_701 unithd 5520 1917600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_702 unithd 5520 1920320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_703 unithd 5520 1923040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_704 unithd 5520 1925760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_705 unithd 5520 1928480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_706 unithd 5520 1931200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_707 unithd 5520 1933920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_708 unithd 5520 1936640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_709 unithd 5520 1939360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_710 unithd 5520 1942080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_711 unithd 5520 1944800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_712 unithd 5520 1947520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_713 unithd 5520 1950240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_714 unithd 5520 1952960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_715 unithd 5520 1955680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_716 unithd 5520 1958400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_717 unithd 5520 1961120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_718 unithd 5520 1963840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_719 unithd 5520 1966560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_720 unithd 5520 1969280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_721 unithd 5520 1972000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_722 unithd 5520 1974720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_723 unithd 5520 1977440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_724 unithd 5520 1980160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_725 unithd 5520 1982880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_726 unithd 5520 1985600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_727 unithd 5520 1988320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_728 unithd 5520 1991040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_729 unithd 5520 1993760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_730 unithd 5520 1996480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_731 unithd 5520 1999200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_732 unithd 5520 2001920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_733 unithd 5520 2004640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_734 unithd 5520 2007360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_735 unithd 5520 2010080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_736 unithd 5520 2012800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_737 unithd 5520 2015520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_738 unithd 5520 2018240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_739 unithd 5520 2020960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_740 unithd 5520 2023680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_741 unithd 5520 2026400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_742 unithd 5520 2029120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_743 unithd 5520 2031840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_744 unithd 5520 2034560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_745 unithd 5520 2037280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_746 unithd 5520 2040000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_747 unithd 5520 2042720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_748 unithd 5520 2045440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_749 unithd 5520 2048160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_750 unithd 5520 2050880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_751 unithd 5520 2053600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_752 unithd 5520 2056320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_753 unithd 5520 2059040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_754 unithd 5520 2061760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_755 unithd 5520 2064480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_756 unithd 5520 2067200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_757 unithd 5520 2069920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_758 unithd 5520 2072640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_759 unithd 5520 2075360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_760 unithd 5520 2078080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_761 unithd 5520 2080800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_762 unithd 5520 2083520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_763 unithd 5520 2086240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_764 unithd 5520 2088960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_765 unithd 5520 2091680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_766 unithd 5520 2094400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_767 unithd 5520 2097120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_768 unithd 5520 2099840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_769 unithd 5520 2102560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_770 unithd 5520 2105280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_771 unithd 5520 2108000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_772 unithd 5520 2110720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_773 unithd 5520 2113440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_774 unithd 5520 2116160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_775 unithd 5520 2118880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_776 unithd 5520 2121600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_777 unithd 5520 2124320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_778 unithd 5520 2127040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_779 unithd 5520 2129760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_780 unithd 5520 2132480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_781 unithd 5520 2135200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_782 unithd 5520 2137920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_783 unithd 5520 2140640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_784 unithd 5520 2143360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_785 unithd 5520 2146080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_786 unithd 5520 2148800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_787 unithd 5520 2151520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_788 unithd 5520 2154240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_789 unithd 5520 2156960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_790 unithd 5520 2159680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_791 unithd 5520 2162400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_792 unithd 5520 2165120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_793 unithd 5520 2167840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_794 unithd 5520 2170560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_795 unithd 5520 2173280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_796 unithd 5520 2176000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_797 unithd 5520 2178720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_798 unithd 5520 2181440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_799 unithd 5520 2184160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_800 unithd 5520 2186880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_801 unithd 5520 2189600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_802 unithd 5520 2192320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_803 unithd 5520 2195040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_804 unithd 5520 2197760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_805 unithd 5520 2200480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_806 unithd 5520 2203200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_807 unithd 5520 2205920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_808 unithd 5520 2208640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_809 unithd 5520 2211360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_810 unithd 5520 2214080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_811 unithd 5520 2216800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_812 unithd 5520 2219520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_813 unithd 5520 2222240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_814 unithd 5520 2224960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_815 unithd 5520 2227680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_816 unithd 5520 2230400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_817 unithd 5520 2233120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_818 unithd 5520 2235840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_819 unithd 5520 2238560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_820 unithd 5520 2241280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_821 unithd 5520 2244000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_822 unithd 5520 2246720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_823 unithd 5520 2249440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_824 unithd 5520 2252160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_825 unithd 5520 2254880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_826 unithd 5520 2257600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_827 unithd 5520 2260320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_828 unithd 5520 2263040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_829 unithd 5520 2265760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_830 unithd 5520 2268480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_831 unithd 5520 2271200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_832 unithd 5520 2273920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_833 unithd 5520 2276640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_834 unithd 5520 2279360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_835 unithd 5520 2282080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_836 unithd 5520 2284800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_837 unithd 5520 2287520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_838 unithd 5520 2290240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_839 unithd 5520 2292960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_840 unithd 5520 2295680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_841 unithd 5520 2298400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_842 unithd 5520 2301120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_843 unithd 5520 2303840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_844 unithd 5520 2306560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_845 unithd 5520 2309280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_846 unithd 5520 2312000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_847 unithd 5520 2314720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_848 unithd 5520 2317440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_849 unithd 5520 2320160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_850 unithd 5520 2322880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_851 unithd 5520 2325600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_852 unithd 5520 2328320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_853 unithd 5520 2331040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_854 unithd 5520 2333760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_855 unithd 5520 2336480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_856 unithd 5520 2339200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_857 unithd 5520 2341920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_858 unithd 5520 2344640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_859 unithd 5520 2347360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_860 unithd 5520 2350080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_861 unithd 5520 2352800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_862 unithd 5520 2355520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_863 unithd 5520 2358240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_864 unithd 5520 2360960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_865 unithd 5520 2363680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_866 unithd 5520 2366400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_867 unithd 5520 2369120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_868 unithd 5520 2371840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_869 unithd 5520 2374560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_870 unithd 5520 2377280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_871 unithd 5520 2380000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_872 unithd 5520 2382720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_873 unithd 5520 2385440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_874 unithd 5520 2388160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_875 unithd 5520 2390880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_876 unithd 5520 2393600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_877 unithd 5520 2396320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_878 unithd 5520 2399040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_879 unithd 5520 2401760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_880 unithd 5520 2404480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_881 unithd 5520 2407200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_882 unithd 5520 2409920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_883 unithd 5520 2412640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_884 unithd 5520 2415360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_885 unithd 5520 2418080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_886 unithd 5520 2420800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_887 unithd 5520 2423520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_888 unithd 5520 2426240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_889 unithd 5520 2428960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_890 unithd 5520 2431680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_891 unithd 5520 2434400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_892 unithd 5520 2437120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_893 unithd 5520 2439840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_894 unithd 5520 2442560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_895 unithd 5520 2445280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_896 unithd 5520 2448000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_897 unithd 5520 2450720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_898 unithd 5520 2453440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_899 unithd 5520 2456160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_900 unithd 5520 2458880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_901 unithd 5520 2461600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_902 unithd 5520 2464320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_903 unithd 5520 2467040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_904 unithd 5520 2469760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_905 unithd 5520 2472480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_906 unithd 5520 2475200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_907 unithd 5520 2477920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_908 unithd 5520 2480640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_909 unithd 5520 2483360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_910 unithd 5520 2486080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_911 unithd 5520 2488800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_912 unithd 5520 2491520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_913 unithd 5520 2494240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_914 unithd 5520 2496960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_915 unithd 5520 2499680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_916 unithd 5520 2502400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_917 unithd 5520 2505120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_918 unithd 5520 2507840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_919 unithd 5520 2510560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_920 unithd 5520 2513280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_921 unithd 5520 2516000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_922 unithd 5520 2518720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_923 unithd 5520 2521440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_924 unithd 5520 2524160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_925 unithd 5520 2526880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_926 unithd 5520 2529600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_927 unithd 5520 2532320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_928 unithd 5520 2535040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_929 unithd 5520 2537760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_930 unithd 5520 2540480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_931 unithd 5520 2543200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_932 unithd 5520 2545920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_933 unithd 5520 2548640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_934 unithd 5520 2551360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_935 unithd 5520 2554080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_936 unithd 5520 2556800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_937 unithd 5520 2559520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_938 unithd 5520 2562240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_939 unithd 5520 2564960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_940 unithd 5520 2567680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_941 unithd 5520 2570400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_942 unithd 5520 2573120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_943 unithd 5520 2575840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_944 unithd 5520 2578560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_945 unithd 5520 2581280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_946 unithd 5520 2584000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_947 unithd 5520 2586720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_948 unithd 5520 2589440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_949 unithd 5520 2592160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_950 unithd 5520 2594880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_951 unithd 5520 2597600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_952 unithd 5520 2600320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_953 unithd 5520 2603040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_954 unithd 5520 2605760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_955 unithd 5520 2608480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_956 unithd 5520 2611200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_957 unithd 5520 2613920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_958 unithd 5520 2616640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_959 unithd 5520 2619360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_960 unithd 5520 2622080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_961 unithd 5520 2624800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_962 unithd 5520 2627520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_963 unithd 5520 2630240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_964 unithd 5520 2632960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_965 unithd 5520 2635680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_966 unithd 5520 2638400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_967 unithd 5520 2641120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_968 unithd 5520 2643840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_969 unithd 5520 2646560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_970 unithd 5520 2649280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_971 unithd 5520 2652000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_972 unithd 5520 2654720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_973 unithd 5520 2657440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_974 unithd 5520 2660160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_975 unithd 5520 2662880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_976 unithd 5520 2665600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_977 unithd 5520 2668320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_978 unithd 5520 2671040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_979 unithd 5520 2673760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_980 unithd 5520 2676480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_981 unithd 5520 2679200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_982 unithd 5520 2681920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_983 unithd 5520 2684640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_984 unithd 5520 2687360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_985 unithd 5520 2690080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_986 unithd 5520 2692800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_987 unithd 5520 2695520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_988 unithd 5520 2698240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_989 unithd 5520 2700960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_990 unithd 5520 2703680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_991 unithd 5520 2706400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_992 unithd 5520 2709120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_993 unithd 5520 2711840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_994 unithd 5520 2714560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_995 unithd 5520 2717280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_996 unithd 5520 2720000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_997 unithd 5520 2722720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_998 unithd 5520 2725440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_999 unithd 5520 2728160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1000 unithd 5520 2730880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1001 unithd 5520 2733600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1002 unithd 5520 2736320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1003 unithd 5520 2739040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1004 unithd 5520 2741760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1005 unithd 5520 2744480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1006 unithd 5520 2747200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1007 unithd 5520 2749920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1008 unithd 5520 2752640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1009 unithd 5520 2755360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1010 unithd 5520 2758080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1011 unithd 5520 2760800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1012 unithd 5520 2763520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1013 unithd 5520 2766240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1014 unithd 5520 2768960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1015 unithd 5520 2771680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1016 unithd 5520 2774400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1017 unithd 5520 2777120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1018 unithd 5520 2779840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1019 unithd 5520 2782560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1020 unithd 5520 2785280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1021 unithd 5520 2788000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1022 unithd 5520 2790720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1023 unithd 5520 2793440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1024 unithd 5520 2796160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1025 unithd 5520 2798880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1026 unithd 5520 2801600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1027 unithd 5520 2804320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1028 unithd 5520 2807040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1029 unithd 5520 2809760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1030 unithd 5520 2812480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1031 unithd 5520 2815200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1032 unithd 5520 2817920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1033 unithd 5520 2820640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1034 unithd 5520 2823360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1035 unithd 5520 2826080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1036 unithd 5520 2828800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1037 unithd 5520 2831520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1038 unithd 5520 2834240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1039 unithd 5520 2836960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1040 unithd 5520 2839680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1041 unithd 5520 2842400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1042 unithd 5520 2845120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1043 unithd 5520 2847840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1044 unithd 5520 2850560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1045 unithd 5520 2853280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1046 unithd 5520 2856000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1047 unithd 5520 2858720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1048 unithd 5520 2861440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1049 unithd 5520 2864160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1050 unithd 5520 2866880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1051 unithd 5520 2869600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1052 unithd 5520 2872320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1053 unithd 5520 2875040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1054 unithd 5520 2877760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1055 unithd 5520 2880480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1056 unithd 5520 2883200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1057 unithd 5520 2885920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1058 unithd 5520 2888640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1059 unithd 5520 2891360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1060 unithd 5520 2894080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1061 unithd 5520 2896800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1062 unithd 5520 2899520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1063 unithd 5520 2902240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1064 unithd 5520 2904960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1065 unithd 5520 2907680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1066 unithd 5520 2910400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1067 unithd 5520 2913120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1068 unithd 5520 2915840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1069 unithd 5520 2918560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1070 unithd 5520 2921280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1071 unithd 5520 2924000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1072 unithd 5520 2926720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1073 unithd 5520 2929440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1074 unithd 5520 2932160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1075 unithd 5520 2934880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1076 unithd 5520 2937600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1077 unithd 5520 2940320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1078 unithd 5520 2943040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1079 unithd 5520 2945760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1080 unithd 5520 2948480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1081 unithd 5520 2951200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1082 unithd 5520 2953920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1083 unithd 5520 2956640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1084 unithd 5520 2959360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1085 unithd 5520 2962080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1086 unithd 5520 2964800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1087 unithd 5520 2967520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1088 unithd 5520 2970240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1089 unithd 5520 2972960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1090 unithd 5520 2975680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1091 unithd 5520 2978400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1092 unithd 5520 2981120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1093 unithd 5520 2983840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1094 unithd 5520 2986560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1095 unithd 5520 2989280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1096 unithd 5520 2992000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1097 unithd 5520 2994720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1098 unithd 5520 2997440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1099 unithd 5520 3000160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1100 unithd 5520 3002880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1101 unithd 5520 3005600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1102 unithd 5520 3008320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1103 unithd 5520 3011040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1104 unithd 5520 3013760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1105 unithd 5520 3016480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1106 unithd 5520 3019200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1107 unithd 5520 3021920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1108 unithd 5520 3024640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1109 unithd 5520 3027360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1110 unithd 5520 3030080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1111 unithd 5520 3032800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1112 unithd 5520 3035520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1113 unithd 5520 3038240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1114 unithd 5520 3040960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1115 unithd 5520 3043680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1116 unithd 5520 3046400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1117 unithd 5520 3049120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1118 unithd 5520 3051840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1119 unithd 5520 3054560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1120 unithd 5520 3057280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1121 unithd 5520 3060000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1122 unithd 5520 3062720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1123 unithd 5520 3065440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1124 unithd 5520 3068160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1125 unithd 5520 3070880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1126 unithd 5520 3073600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1127 unithd 5520 3076320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1128 unithd 5520 3079040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1129 unithd 5520 3081760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1130 unithd 5520 3084480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1131 unithd 5520 3087200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1132 unithd 5520 3089920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1133 unithd 5520 3092640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1134 unithd 5520 3095360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1135 unithd 5520 3098080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1136 unithd 5520 3100800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1137 unithd 5520 3103520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1138 unithd 5520 3106240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1139 unithd 5520 3108960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1140 unithd 5520 3111680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1141 unithd 5520 3114400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1142 unithd 5520 3117120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1143 unithd 5520 3119840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1144 unithd 5520 3122560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1145 unithd 5520 3125280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1146 unithd 5520 3128000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1147 unithd 5520 3130720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1148 unithd 5520 3133440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1149 unithd 5520 3136160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1150 unithd 5520 3138880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1151 unithd 5520 3141600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1152 unithd 5520 3144320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1153 unithd 5520 3147040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1154 unithd 5520 3149760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1155 unithd 5520 3152480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1156 unithd 5520 3155200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1157 unithd 5520 3157920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1158 unithd 5520 3160640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1159 unithd 5520 3163360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1160 unithd 5520 3166080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1161 unithd 5520 3168800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1162 unithd 5520 3171520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1163 unithd 5520 3174240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1164 unithd 5520 3176960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1165 unithd 5520 3179680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1166 unithd 5520 3182400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1167 unithd 5520 3185120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1168 unithd 5520 3187840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1169 unithd 5520 3190560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1170 unithd 5520 3193280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1171 unithd 5520 3196000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1172 unithd 5520 3198720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1173 unithd 5520 3201440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1174 unithd 5520 3204160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1175 unithd 5520 3206880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1176 unithd 5520 3209600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1177 unithd 5520 3212320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1178 unithd 5520 3215040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1179 unithd 5520 3217760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1180 unithd 5520 3220480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1181 unithd 5520 3223200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1182 unithd 5520 3225920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1183 unithd 5520 3228640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1184 unithd 5520 3231360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1185 unithd 5520 3234080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1186 unithd 5520 3236800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1187 unithd 5520 3239520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1188 unithd 5520 3242240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1189 unithd 5520 3244960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1190 unithd 5520 3247680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1191 unithd 5520 3250400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1192 unithd 5520 3253120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1193 unithd 5520 3255840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1194 unithd 5520 3258560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1195 unithd 5520 3261280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1196 unithd 5520 3264000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1197 unithd 5520 3266720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1198 unithd 5520 3269440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1199 unithd 5520 3272160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1200 unithd 5520 3274880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1201 unithd 5520 3277600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1202 unithd 5520 3280320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1203 unithd 5520 3283040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1204 unithd 5520 3285760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1205 unithd 5520 3288480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1206 unithd 5520 3291200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1207 unithd 5520 3293920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1208 unithd 5520 3296640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1209 unithd 5520 3299360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1210 unithd 5520 3302080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1211 unithd 5520 3304800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1212 unithd 5520 3307520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1213 unithd 5520 3310240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1214 unithd 5520 3312960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1215 unithd 5520 3315680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1216 unithd 5520 3318400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1217 unithd 5520 3321120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1218 unithd 5520 3323840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1219 unithd 5520 3326560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1220 unithd 5520 3329280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1221 unithd 5520 3332000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1222 unithd 5520 3334720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1223 unithd 5520 3337440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1224 unithd 5520 3340160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1225 unithd 5520 3342880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1226 unithd 5520 3345600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1227 unithd 5520 3348320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1228 unithd 5520 3351040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1229 unithd 5520 3353760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1230 unithd 5520 3356480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1231 unithd 5520 3359200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1232 unithd 5520 3361920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1233 unithd 5520 3364640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1234 unithd 5520 3367360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1235 unithd 5520 3370080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1236 unithd 5520 3372800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1237 unithd 5520 3375520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1238 unithd 5520 3378240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1239 unithd 5520 3380960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1240 unithd 5520 3383680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1241 unithd 5520 3386400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1242 unithd 5520 3389120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1243 unithd 5520 3391840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1244 unithd 5520 3394560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1245 unithd 5520 3397280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1246 unithd 5520 3400000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1247 unithd 5520 3402720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1248 unithd 5520 3405440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1249 unithd 5520 3408160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1250 unithd 5520 3410880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1251 unithd 5520 3413600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1252 unithd 5520 3416320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1253 unithd 5520 3419040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1254 unithd 5520 3421760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1255 unithd 5520 3424480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1256 unithd 5520 3427200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1257 unithd 5520 3429920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1258 unithd 5520 3432640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1259 unithd 5520 3435360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1260 unithd 5520 3438080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1261 unithd 5520 3440800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1262 unithd 5520 3443520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1263 unithd 5520 3446240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1264 unithd 5520 3448960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1265 unithd 5520 3451680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1266 unithd 5520 3454400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1267 unithd 5520 3457120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1268 unithd 5520 3459840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1269 unithd 5520 3462560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1270 unithd 5520 3465280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1271 unithd 5520 3468000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1272 unithd 5520 3470720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1273 unithd 5520 3473440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1274 unithd 5520 3476160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1275 unithd 5520 3478880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1276 unithd 5520 3481600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1277 unithd 5520 3484320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1278 unithd 5520 3487040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1279 unithd 5520 3489760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1280 unithd 5520 3492480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1281 unithd 5520 3495200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1282 unithd 5520 3497920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1283 unithd 5520 3500640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1284 unithd 5520 3503360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1285 unithd 5520 3506080 FS DO 6323 BY 1 STEP 460 0 ;
+TRACKS X 230 DO 6348 STEP 460 LAYER li1 ;
+TRACKS Y 170 DO 10353 STEP 340 LAYER li1 ;
+TRACKS X 170 DO 8588 STEP 340 LAYER met1 ;
+TRACKS Y 170 DO 10353 STEP 340 LAYER met1 ;
+TRACKS X 230 DO 6348 STEP 460 LAYER met2 ;
+TRACKS Y 230 DO 7652 STEP 460 LAYER met2 ;
+TRACKS X 340 DO 4294 STEP 680 LAYER met3 ;
+TRACKS Y 340 DO 5176 STEP 680 LAYER met3 ;
+TRACKS X 460 DO 3174 STEP 920 LAYER met4 ;
+TRACKS Y 460 DO 3826 STEP 920 LAYER met4 ;
+TRACKS X 1700 DO 859 STEP 3400 LAYER met5 ;
+TRACKS Y 1700 DO 1035 STEP 3400 LAYER met5 ;
+GCELLGRID X 0 DO 423 STEP 6900 ;
+GCELLGRID Y 0 DO 510 STEP 6900 ;
+VIAS 2 ;
+ - via4_3100x3100 + VIARULE M4M5_PR + CUTSIZE 800 800 + LAYERS met4 via4 met5 + CUTSPACING 800 800 + ENCLOSURE 350 350 350 350 + ROWCOL 2 2 ;
+ - via4_1600x3100 + VIARULE M4M5_PR + CUTSIZE 800 800 + LAYERS met4 via4 met5 + CUTSPACING 800 800 + ENCLOSURE 400 350 400 350 + ROWCOL 2 1 ;
+END VIAS
+PINS 645 ;
+ - analog_io[0] + NET analog_io[0] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1426980 ) N ;
+ - analog_io[10] + NET analog_io[10] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2230770 3521200 ) N ;
+ - analog_io[11] + NET analog_io[11] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1906010 3521200 ) N ;
+ - analog_io[12] + NET analog_io[12] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1581710 3521200 ) N ;
+ - analog_io[13] + NET analog_io[13] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1257410 3521200 ) N ;
+ - analog_io[14] + NET analog_io[14] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 932650 3521200 ) N ;
+ - analog_io[15] + NET analog_io[15] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 608350 3521200 ) N ;
+ - analog_io[16] + NET analog_io[16] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 284050 3521200 ) N ;
+ - analog_io[17] + NET analog_io[17] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3486700 ) N ;
+ - analog_io[18] + NET analog_io[18] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3225580 ) N ;
+ - analog_io[19] + NET analog_io[19] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2965140 ) N ;
+ - analog_io[1] + NET analog_io[1] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1692860 ) N ;
+ - analog_io[20] + NET analog_io[20] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2704020 ) N ;
+ - analog_io[21] + NET analog_io[21] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2443580 ) N ;
+ - analog_io[22] + NET analog_io[22] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2183140 ) N ;
+ - analog_io[23] + NET analog_io[23] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1922020 ) N ;
+ - analog_io[24] + NET analog_io[24] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1661580 ) N ;
+ - analog_io[25] + NET analog_io[25] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1400460 ) N ;
+ - analog_io[26] + NET analog_io[26] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1140020 ) N ;
+ - analog_io[27] + NET analog_io[27] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 879580 ) N ;
+ - analog_io[28] + NET analog_io[28] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 618460 ) N ;
+ - analog_io[2] + NET analog_io[2] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1958740 ) N ;
+ - analog_io[3] + NET analog_io[3] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2223940 ) N ;
+ - analog_io[4] + NET analog_io[4] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2489820 ) N ;
+ - analog_io[5] + NET analog_io[5] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2755700 ) N ;
+ - analog_io[6] + NET analog_io[6] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3020900 ) N ;
+ - analog_io[7] + NET analog_io[7] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3286780 ) N ;
+ - analog_io[8] + NET analog_io[8] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2879370 3521200 ) N ;
+ - analog_io[9] + NET analog_io[9] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2555070 3521200 ) N ;
+ - io_in[0] + NET io_in[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 32980 ) N ;
+ - io_in[10] + NET io_in[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2290580 ) N ;
+ - io_in[11] + NET io_in[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2556460 ) N ;
+ - io_in[12] + NET io_in[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2821660 ) N ;
+ - io_in[13] + NET io_in[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3087540 ) N ;
+ - io_in[14] + NET io_in[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3353420 ) N ;
+ - io_in[15] + NET io_in[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2798410 3521200 ) N ;
+ - io_in[16] + NET io_in[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2474110 3521200 ) N ;
+ - io_in[17] + NET io_in[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2149350 3521200 ) N ;
+ - io_in[18] + NET io_in[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1825050 3521200 ) N ;
+ - io_in[19] + NET io_in[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1500750 3521200 ) N ;
+ - io_in[1] + NET io_in[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 231540 ) N ;
+ - io_in[20] + NET io_in[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1175990 3521200 ) N ;
+ - io_in[21] + NET io_in[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 851690 3521200 ) N ;
+ - io_in[22] + NET io_in[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 527390 3521200 ) N ;
+ - io_in[23] + NET io_in[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 202630 3521200 ) N ;
+ - io_in[24] + NET io_in[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3421420 ) N ;
+ - io_in[25] + NET io_in[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3160300 ) N ;
+ - io_in[26] + NET io_in[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2899860 ) N ;
+ - io_in[27] + NET io_in[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2639420 ) N ;
+ - io_in[28] + NET io_in[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2378300 ) N ;
+ - io_in[29] + NET io_in[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2117860 ) N ;
+ - io_in[2] + NET io_in[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 430780 ) N ;
+ - io_in[30] + NET io_in[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1856740 ) N ;
+ - io_in[31] + NET io_in[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1596300 ) N ;
+ - io_in[32] + NET io_in[32] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1335860 ) N ;
+ - io_in[33] + NET io_in[33] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1074740 ) N ;
+ - io_in[34] + NET io_in[34] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 814300 ) N ;
+ - io_in[35] + NET io_in[35] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 553180 ) N ;
+ - io_in[36] + NET io_in[36] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 358020 ) N ;
+ - io_in[37] + NET io_in[37] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 162180 ) N ;
+ - io_in[3] + NET io_in[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 630020 ) N ;
+ - io_in[4] + NET io_in[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 829260 ) N ;
+ - io_in[5] + NET io_in[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1028500 ) N ;
+ - io_in[6] + NET io_in[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1227740 ) N ;
+ - io_in[7] + NET io_in[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1493620 ) N ;
+ - io_in[8] + NET io_in[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1759500 ) N ;
+ - io_in[9] + NET io_in[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2024700 ) N ;
+ - io_oeb[0] + NET io_oeb[0] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 165580 ) N ;
+ - io_oeb[10] + NET io_oeb[10] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2423180 ) N ;
+ - io_oeb[11] + NET io_oeb[11] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2689060 ) N ;
+ - io_oeb[12] + NET io_oeb[12] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2954940 ) N ;
+ - io_oeb[13] + NET io_oeb[13] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3220140 ) N ;
+ - io_oeb[14] + NET io_oeb[14] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3486020 ) N ;
+ - io_oeb[15] + NET io_oeb[15] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2636030 3521200 ) N ;
+ - io_oeb[16] + NET io_oeb[16] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2311730 3521200 ) N ;
+ - io_oeb[17] + NET io_oeb[17] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1987430 3521200 ) N ;
+ - io_oeb[18] + NET io_oeb[18] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1662670 3521200 ) N ;
+ - io_oeb[19] + NET io_oeb[19] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1338370 3521200 ) N ;
+ - io_oeb[1] + NET io_oeb[1] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 364820 ) N ;
+ - io_oeb[20] + NET io_oeb[20] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1014070 3521200 ) N ;
+ - io_oeb[21] + NET io_oeb[21] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 689310 3521200 ) N ;
+ - io_oeb[22] + NET io_oeb[22] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 365010 3521200 ) N ;
+ - io_oeb[23] + NET io_oeb[23] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 40710 3521200 ) N ;
+ - io_oeb[24] + NET io_oeb[24] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3290860 ) N ;
+ - io_oeb[25] + NET io_oeb[25] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3030420 ) N ;
+ - io_oeb[26] + NET io_oeb[26] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2769300 ) N ;
+ - io_oeb[27] + NET io_oeb[27] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2508860 ) N ;
+ - io_oeb[28] + NET io_oeb[28] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2247740 ) N ;
+ - io_oeb[29] + NET io_oeb[29] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1987300 ) N ;
+ - io_oeb[2] + NET io_oeb[2] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 564060 ) N ;
+ - io_oeb[30] + NET io_oeb[30] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1726860 ) N ;
+ - io_oeb[31] + NET io_oeb[31] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1465740 ) N ;
+ - io_oeb[32] + NET io_oeb[32] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1205300 ) N ;
+ - io_oeb[33] + NET io_oeb[33] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 944180 ) N ;
+ - io_oeb[34] + NET io_oeb[34] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 683740 ) N ;
+ - io_oeb[35] + NET io_oeb[35] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 423300 ) N ;
+ - io_oeb[36] + NET io_oeb[36] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 227460 ) N ;
+ - io_oeb[37] + NET io_oeb[37] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 32300 ) N ;
+ - io_oeb[3] + NET io_oeb[3] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 763300 ) N ;
+ - io_oeb[4] + NET io_oeb[4] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 962540 ) N ;
+ - io_oeb[5] + NET io_oeb[5] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1161780 ) N ;
+ - io_oeb[6] + NET io_oeb[6] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1361020 ) N ;
+ - io_oeb[7] + NET io_oeb[7] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1626220 ) N ;
+ - io_oeb[8] + NET io_oeb[8] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1892100 ) N ;
+ - io_oeb[9] + NET io_oeb[9] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2157980 ) N ;
+ - io_out[0] + NET io_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 98940 ) N ;
+ - io_out[10] + NET io_out[10] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2357220 ) N ;
+ - io_out[11] + NET io_out[11] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2622420 ) N ;
+ - io_out[12] + NET io_out[12] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2888300 ) N ;
+ - io_out[13] + NET io_out[13] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3154180 ) N ;
+ - io_out[14] + NET io_out[14] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3419380 ) N ;
+ - io_out[15] + NET io_out[15] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2717450 3521200 ) N ;
+ - io_out[16] + NET io_out[16] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2392690 3521200 ) N ;
+ - io_out[17] + NET io_out[17] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2068390 3521200 ) N ;
+ - io_out[18] + NET io_out[18] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1744090 3521200 ) N ;
+ - io_out[19] + NET io_out[19] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1419330 3521200 ) N ;
+ - io_out[1] + NET io_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 298180 ) N ;
+ - io_out[20] + NET io_out[20] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1095030 3521200 ) N ;
+ - io_out[21] + NET io_out[21] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 770730 3521200 ) N ;
+ - io_out[22] + NET io_out[22] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 445970 3521200 ) N ;
+ - io_out[23] + NET io_out[23] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 121670 3521200 ) N ;
+ - io_out[24] + NET io_out[24] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3356140 ) N ;
+ - io_out[25] + NET io_out[25] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3095700 ) N ;
+ - io_out[26] + NET io_out[26] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2834580 ) N ;
+ - io_out[27] + NET io_out[27] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2574140 ) N ;
+ - io_out[28] + NET io_out[28] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2313020 ) N ;
+ - io_out[29] + NET io_out[29] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2052580 ) N ;
+ - io_out[2] + NET io_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 497420 ) N ;
+ - io_out[30] + NET io_out[30] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1792140 ) N ;
+ - io_out[31] + NET io_out[31] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1531020 ) N ;
+ - io_out[32] + NET io_out[32] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1270580 ) N ;
+ - io_out[33] + NET io_out[33] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1009460 ) N ;
+ - io_out[34] + NET io_out[34] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 749020 ) N ;
+ - io_out[35] + NET io_out[35] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 487900 ) N ;
+ - io_out[36] + NET io_out[36] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 292740 ) N ;
+ - io_out[37] + NET io_out[37] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 96900 ) N ;
+ - io_out[3] + NET io_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 696660 ) N ;
+ - io_out[4] + NET io_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 895900 ) N ;
+ - io_out[5] + NET io_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1095140 ) N ;
+ - io_out[6] + NET io_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1294380 ) N ;
+ - io_out[7] + NET io_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1560260 ) N ;
+ - io_out[8] + NET io_out[8] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1825460 ) N ;
+ - io_out[9] + NET io_out[9] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2091340 ) N ;
+ - la_data_in[0] + NET la_data_in[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 629510 -1200 ) N ;
+ - la_data_in[100] + NET la_data_in[100] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2402810 -1200 ) N ;
+ - la_data_in[101] + NET la_data_in[101] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2420290 -1200 ) N ;
+ - la_data_in[102] + NET la_data_in[102] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2438230 -1200 ) N ;
+ - la_data_in[103] + NET la_data_in[103] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2455710 -1200 ) N ;
+ - la_data_in[104] + NET la_data_in[104] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2473650 -1200 ) N ;
+ - la_data_in[105] + NET la_data_in[105] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2491130 -1200 ) N ;
+ - la_data_in[106] + NET la_data_in[106] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2509070 -1200 ) N ;
+ - la_data_in[107] + NET la_data_in[107] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2527010 -1200 ) N ;
+ - la_data_in[108] + NET la_data_in[108] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2544490 -1200 ) N ;
+ - la_data_in[109] + NET la_data_in[109] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2562430 -1200 ) N ;
+ - la_data_in[10] + NET la_data_in[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 806610 -1200 ) N ;
+ - la_data_in[110] + NET la_data_in[110] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2579910 -1200 ) N ;
+ - la_data_in[111] + NET la_data_in[111] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2597850 -1200 ) N ;
+ - la_data_in[112] + NET la_data_in[112] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2615330 -1200 ) N ;
+ - la_data_in[113] + NET la_data_in[113] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2633270 -1200 ) N ;
+ - la_data_in[114] + NET la_data_in[114] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2650750 -1200 ) N ;
+ - la_data_in[115] + NET la_data_in[115] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2668690 -1200 ) N ;
+ - la_data_in[116] + NET la_data_in[116] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2686170 -1200 ) N ;
+ - la_data_in[117] + NET la_data_in[117] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2704110 -1200 ) N ;
+ - la_data_in[118] + NET la_data_in[118] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2722050 -1200 ) N ;
+ - la_data_in[119] + NET la_data_in[119] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2739530 -1200 ) N ;
+ - la_data_in[11] + NET la_data_in[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 824550 -1200 ) N ;
+ - la_data_in[120] + NET la_data_in[120] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2757470 -1200 ) N ;
+ - la_data_in[121] + NET la_data_in[121] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2774950 -1200 ) N ;
+ - la_data_in[122] + NET la_data_in[122] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2792890 -1200 ) N ;
+ - la_data_in[123] + NET la_data_in[123] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2810370 -1200 ) N ;
+ - la_data_in[124] + NET la_data_in[124] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2828310 -1200 ) N ;
+ - la_data_in[125] + NET la_data_in[125] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2845790 -1200 ) N ;
+ - la_data_in[126] + NET la_data_in[126] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2863730 -1200 ) N ;
+ - la_data_in[127] + NET la_data_in[127] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2881670 -1200 ) N ;
+ - la_data_in[12] + NET la_data_in[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 842030 -1200 ) N ;
+ - la_data_in[13] + NET la_data_in[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 859970 -1200 ) N ;
+ - la_data_in[14] + NET la_data_in[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 877450 -1200 ) N ;
+ - la_data_in[15] + NET la_data_in[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 895390 -1200 ) N ;
+ - la_data_in[16] + NET la_data_in[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 912870 -1200 ) N ;
+ - la_data_in[17] + NET la_data_in[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 930810 -1200 ) N ;
+ - la_data_in[18] + NET la_data_in[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 948750 -1200 ) N ;
+ - la_data_in[19] + NET la_data_in[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 966230 -1200 ) N ;
+ - la_data_in[1] + NET la_data_in[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 646990 -1200 ) N ;
+ - la_data_in[20] + NET la_data_in[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 984170 -1200 ) N ;
+ - la_data_in[21] + NET la_data_in[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1001650 -1200 ) N ;
+ - la_data_in[22] + NET la_data_in[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1019590 -1200 ) N ;
+ - la_data_in[23] + NET la_data_in[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1037070 -1200 ) N ;
+ - la_data_in[24] + NET la_data_in[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1055010 -1200 ) N ;
+ - la_data_in[25] + NET la_data_in[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1072490 -1200 ) N ;
+ - la_data_in[26] + NET la_data_in[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1090430 -1200 ) N ;
+ - la_data_in[27] + NET la_data_in[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1107910 -1200 ) N ;
+ - la_data_in[28] + NET la_data_in[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1125850 -1200 ) N ;
+ - la_data_in[29] + NET la_data_in[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1143790 -1200 ) N ;
+ - la_data_in[2] + NET la_data_in[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 664930 -1200 ) N ;
+ - la_data_in[30] + NET la_data_in[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1161270 -1200 ) N ;
+ - la_data_in[31] + NET la_data_in[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1179210 -1200 ) N ;
+ - la_data_in[32] + NET la_data_in[32] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1196690 -1200 ) N ;
+ - la_data_in[33] + NET la_data_in[33] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1214630 -1200 ) N ;
+ - la_data_in[34] + NET la_data_in[34] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1232110 -1200 ) N ;
+ - la_data_in[35] + NET la_data_in[35] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1250050 -1200 ) N ;
+ - la_data_in[36] + NET la_data_in[36] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1267530 -1200 ) N ;
+ - la_data_in[37] + NET la_data_in[37] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1285470 -1200 ) N ;
+ - la_data_in[38] + NET la_data_in[38] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1303410 -1200 ) N ;
+ - la_data_in[39] + NET la_data_in[39] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1320890 -1200 ) N ;
+ - la_data_in[3] + NET la_data_in[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 682410 -1200 ) N ;
+ - la_data_in[40] + NET la_data_in[40] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1338830 -1200 ) N ;
+ - la_data_in[41] + NET la_data_in[41] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1356310 -1200 ) N ;
+ - la_data_in[42] + NET la_data_in[42] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1374250 -1200 ) N ;
+ - la_data_in[43] + NET la_data_in[43] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1391730 -1200 ) N ;
+ - la_data_in[44] + NET la_data_in[44] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1409670 -1200 ) N ;
+ - la_data_in[45] + NET la_data_in[45] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1427150 -1200 ) N ;
+ - la_data_in[46] + NET la_data_in[46] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1445090 -1200 ) N ;
+ - la_data_in[47] + NET la_data_in[47] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1463030 -1200 ) N ;
+ - la_data_in[48] + NET la_data_in[48] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1480510 -1200 ) N ;
+ - la_data_in[49] + NET la_data_in[49] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1498450 -1200 ) N ;
+ - la_data_in[4] + NET la_data_in[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 700350 -1200 ) N ;
+ - la_data_in[50] + NET la_data_in[50] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1515930 -1200 ) N ;
+ - la_data_in[51] + NET la_data_in[51] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1533870 -1200 ) N ;
+ - la_data_in[52] + NET la_data_in[52] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1551350 -1200 ) N ;
+ - la_data_in[53] + NET la_data_in[53] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1569290 -1200 ) N ;
+ - la_data_in[54] + NET la_data_in[54] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1586770 -1200 ) N ;
+ - la_data_in[55] + NET la_data_in[55] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1604710 -1200 ) N ;
+ - la_data_in[56] + NET la_data_in[56] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1622190 -1200 ) N ;
+ - la_data_in[57] + NET la_data_in[57] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1640130 -1200 ) N ;
+ - la_data_in[58] + NET la_data_in[58] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1658070 -1200 ) N ;
+ - la_data_in[59] + NET la_data_in[59] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1675550 -1200 ) N ;
+ - la_data_in[5] + NET la_data_in[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 717830 -1200 ) N ;
+ - la_data_in[60] + NET la_data_in[60] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1693490 -1200 ) N ;
+ - la_data_in[61] + NET la_data_in[61] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1710970 -1200 ) N ;
+ - la_data_in[62] + NET la_data_in[62] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1728910 -1200 ) N ;
+ - la_data_in[63] + NET la_data_in[63] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1746390 -1200 ) N ;
+ - la_data_in[64] + NET la_data_in[64] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1764330 -1200 ) N ;
+ - la_data_in[65] + NET la_data_in[65] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1781810 -1200 ) N ;
+ - la_data_in[66] + NET la_data_in[66] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1799750 -1200 ) N ;
+ - la_data_in[67] + NET la_data_in[67] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1817690 -1200 ) N ;
+ - la_data_in[68] + NET la_data_in[68] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1835170 -1200 ) N ;
+ - la_data_in[69] + NET la_data_in[69] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1853110 -1200 ) N ;
+ - la_data_in[6] + NET la_data_in[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 735770 -1200 ) N ;
+ - la_data_in[70] + NET la_data_in[70] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1870590 -1200 ) N ;
+ - la_data_in[71] + NET la_data_in[71] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1888530 -1200 ) N ;
+ - la_data_in[72] + NET la_data_in[72] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1906010 -1200 ) N ;
+ - la_data_in[73] + NET la_data_in[73] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1923950 -1200 ) N ;
+ - la_data_in[74] + NET la_data_in[74] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1941430 -1200 ) N ;
+ - la_data_in[75] + NET la_data_in[75] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1959370 -1200 ) N ;
+ - la_data_in[76] + NET la_data_in[76] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1976850 -1200 ) N ;
+ - la_data_in[77] + NET la_data_in[77] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1994790 -1200 ) N ;
+ - la_data_in[78] + NET la_data_in[78] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2012730 -1200 ) N ;
+ - la_data_in[79] + NET la_data_in[79] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2030210 -1200 ) N ;
+ - la_data_in[7] + NET la_data_in[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 753250 -1200 ) N ;
+ - la_data_in[80] + NET la_data_in[80] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2048150 -1200 ) N ;
+ - la_data_in[81] + NET la_data_in[81] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2065630 -1200 ) N ;
+ - la_data_in[82] + NET la_data_in[82] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2083570 -1200 ) N ;
+ - la_data_in[83] + NET la_data_in[83] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2101050 -1200 ) N ;
+ - la_data_in[84] + NET la_data_in[84] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2118990 -1200 ) N ;
+ - la_data_in[85] + NET la_data_in[85] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2136470 -1200 ) N ;
+ - la_data_in[86] + NET la_data_in[86] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2154410 -1200 ) N ;
+ - la_data_in[87] + NET la_data_in[87] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2172350 -1200 ) N ;
+ - la_data_in[88] + NET la_data_in[88] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2189830 -1200 ) N ;
+ - la_data_in[89] + NET la_data_in[89] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2207770 -1200 ) N ;
+ - la_data_in[8] + NET la_data_in[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 771190 -1200 ) N ;
+ - la_data_in[90] + NET la_data_in[90] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2225250 -1200 ) N ;
+ - la_data_in[91] + NET la_data_in[91] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2243190 -1200 ) N ;
+ - la_data_in[92] + NET la_data_in[92] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2260670 -1200 ) N ;
+ - la_data_in[93] + NET la_data_in[93] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2278610 -1200 ) N ;
+ - la_data_in[94] + NET la_data_in[94] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2296090 -1200 ) N ;
+ - la_data_in[95] + NET la_data_in[95] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2314030 -1200 ) N ;
+ - la_data_in[96] + NET la_data_in[96] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2331510 -1200 ) N ;
+ - la_data_in[97] + NET la_data_in[97] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2349450 -1200 ) N ;
+ - la_data_in[98] + NET la_data_in[98] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2367390 -1200 ) N ;
+ - la_data_in[99] + NET la_data_in[99] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2384870 -1200 ) N ;
+ - la_data_in[9] + NET la_data_in[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 789130 -1200 ) N ;
+ - la_data_out[0] + NET la_data_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 635030 -1200 ) N ;
+ - la_data_out[100] + NET la_data_out[100] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2408790 -1200 ) N ;
+ - la_data_out[101] + NET la_data_out[101] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2426270 -1200 ) N ;
+ - la_data_out[102] + NET la_data_out[102] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2444210 -1200 ) N ;
+ - la_data_out[103] + NET la_data_out[103] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2461690 -1200 ) N ;
+ - la_data_out[104] + NET la_data_out[104] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2479630 -1200 ) N ;
+ - la_data_out[105] + NET la_data_out[105] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2497110 -1200 ) N ;
+ - la_data_out[106] + NET la_data_out[106] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2515050 -1200 ) N ;
+ - la_data_out[107] + NET la_data_out[107] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2532530 -1200 ) N ;
+ - la_data_out[108] + NET la_data_out[108] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2550470 -1200 ) N ;
+ - la_data_out[109] + NET la_data_out[109] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2567950 -1200 ) N ;
+ - la_data_out[10] + NET la_data_out[10] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 812590 -1200 ) N ;
+ - la_data_out[110] + NET la_data_out[110] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2585890 -1200 ) N ;
+ - la_data_out[111] + NET la_data_out[111] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2603830 -1200 ) N ;
+ - la_data_out[112] + NET la_data_out[112] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2621310 -1200 ) N ;
+ - la_data_out[113] + NET la_data_out[113] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2639250 -1200 ) N ;
+ - la_data_out[114] + NET la_data_out[114] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2656730 -1200 ) N ;
+ - la_data_out[115] + NET la_data_out[115] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2674670 -1200 ) N ;
+ - la_data_out[116] + NET la_data_out[116] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2692150 -1200 ) N ;
+ - la_data_out[117] + NET la_data_out[117] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2710090 -1200 ) N ;
+ - la_data_out[118] + NET la_data_out[118] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2727570 -1200 ) N ;
+ - la_data_out[119] + NET la_data_out[119] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2745510 -1200 ) N ;
+ - la_data_out[11] + NET la_data_out[11] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 830530 -1200 ) N ;
+ - la_data_out[120] + NET la_data_out[120] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2763450 -1200 ) N ;
+ - la_data_out[121] + NET la_data_out[121] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2780930 -1200 ) N ;
+ - la_data_out[122] + NET la_data_out[122] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2798870 -1200 ) N ;
+ - la_data_out[123] + NET la_data_out[123] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2816350 -1200 ) N ;
+ - la_data_out[124] + NET la_data_out[124] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2834290 -1200 ) N ;
+ - la_data_out[125] + NET la_data_out[125] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2851770 -1200 ) N ;
+ - la_data_out[126] + NET la_data_out[126] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2869710 -1200 ) N ;
+ - la_data_out[127] + NET la_data_out[127] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2887190 -1200 ) N ;
+ - la_data_out[12] + NET la_data_out[12] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 848010 -1200 ) N ;
+ - la_data_out[13] + NET la_data_out[13] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 865950 -1200 ) N ;
+ - la_data_out[14] + NET la_data_out[14] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 883430 -1200 ) N ;
+ - la_data_out[15] + NET la_data_out[15] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 901370 -1200 ) N ;
+ - la_data_out[16] + NET la_data_out[16] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 918850 -1200 ) N ;
+ - la_data_out[17] + NET la_data_out[17] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 936790 -1200 ) N ;
+ - la_data_out[18] + NET la_data_out[18] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 954270 -1200 ) N ;
+ - la_data_out[19] + NET la_data_out[19] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 972210 -1200 ) N ;
+ - la_data_out[1] + NET la_data_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 652970 -1200 ) N ;
+ - la_data_out[20] + NET la_data_out[20] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 989690 -1200 ) N ;
+ - la_data_out[21] + NET la_data_out[21] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1007630 -1200 ) N ;
+ - la_data_out[22] + NET la_data_out[22] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1025570 -1200 ) N ;
+ - la_data_out[23] + NET la_data_out[23] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1043050 -1200 ) N ;
+ - la_data_out[24] + NET la_data_out[24] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1060990 -1200 ) N ;
+ - la_data_out[25] + NET la_data_out[25] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1078470 -1200 ) N ;
+ - la_data_out[26] + NET la_data_out[26] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1096410 -1200 ) N ;
+ - la_data_out[27] + NET la_data_out[27] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1113890 -1200 ) N ;
+ - la_data_out[28] + NET la_data_out[28] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1131830 -1200 ) N ;
+ - la_data_out[29] + NET la_data_out[29] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1149310 -1200 ) N ;
+ - la_data_out[2] + NET la_data_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 670910 -1200 ) N ;
+ - la_data_out[30] + NET la_data_out[30] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1167250 -1200 ) N ;
+ - la_data_out[31] + NET la_data_out[31] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1185190 -1200 ) N ;
+ - la_data_out[32] + NET la_data_out[32] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1202670 -1200 ) N ;
+ - la_data_out[33] + NET la_data_out[33] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1220610 -1200 ) N ;
+ - la_data_out[34] + NET la_data_out[34] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1238090 -1200 ) N ;
+ - la_data_out[35] + NET la_data_out[35] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1256030 -1200 ) N ;
+ - la_data_out[36] + NET la_data_out[36] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1273510 -1200 ) N ;
+ - la_data_out[37] + NET la_data_out[37] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1291450 -1200 ) N ;
+ - la_data_out[38] + NET la_data_out[38] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1308930 -1200 ) N ;
+ - la_data_out[39] + NET la_data_out[39] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1326870 -1200 ) N ;
+ - la_data_out[3] + NET la_data_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 688390 -1200 ) N ;
+ - la_data_out[40] + NET la_data_out[40] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1344350 -1200 ) N ;
+ - la_data_out[41] + NET la_data_out[41] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1362290 -1200 ) N ;
+ - la_data_out[42] + NET la_data_out[42] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1380230 -1200 ) N ;
+ - la_data_out[43] + NET la_data_out[43] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1397710 -1200 ) N ;
+ - la_data_out[44] + NET la_data_out[44] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1415650 -1200 ) N ;
+ - la_data_out[45] + NET la_data_out[45] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1433130 -1200 ) N ;
+ - la_data_out[46] + NET la_data_out[46] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1451070 -1200 ) N ;
+ - la_data_out[47] + NET la_data_out[47] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1468550 -1200 ) N ;
+ - la_data_out[48] + NET la_data_out[48] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1486490 -1200 ) N ;
+ - la_data_out[49] + NET la_data_out[49] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1503970 -1200 ) N ;
+ - la_data_out[4] + NET la_data_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 706330 -1200 ) N ;
+ - la_data_out[50] + NET la_data_out[50] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1521910 -1200 ) N ;
+ - la_data_out[51] + NET la_data_out[51] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1539850 -1200 ) N ;
+ - la_data_out[52] + NET la_data_out[52] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1557330 -1200 ) N ;
+ - la_data_out[53] + NET la_data_out[53] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1575270 -1200 ) N ;
+ - la_data_out[54] + NET la_data_out[54] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1592750 -1200 ) N ;
+ - la_data_out[55] + NET la_data_out[55] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1610690 -1200 ) N ;
+ - la_data_out[56] + NET la_data_out[56] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1628170 -1200 ) N ;
+ - la_data_out[57] + NET la_data_out[57] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1646110 -1200 ) N ;
+ - la_data_out[58] + NET la_data_out[58] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1663590 -1200 ) N ;
+ - la_data_out[59] + NET la_data_out[59] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1681530 -1200 ) N ;
+ - la_data_out[5] + NET la_data_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 723810 -1200 ) N ;
+ - la_data_out[60] + NET la_data_out[60] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1699470 -1200 ) N ;
+ - la_data_out[61] + NET la_data_out[61] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1716950 -1200 ) N ;
+ - la_data_out[62] + NET la_data_out[62] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1734890 -1200 ) N ;
+ - la_data_out[63] + NET la_data_out[63] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1752370 -1200 ) N ;
+ - la_data_out[64] + NET la_data_out[64] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1770310 -1200 ) N ;
+ - la_data_out[65] + NET la_data_out[65] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1787790 -1200 ) N ;
+ - la_data_out[66] + NET la_data_out[66] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1805730 -1200 ) N ;
+ - la_data_out[67] + NET la_data_out[67] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1823210 -1200 ) N ;
+ - la_data_out[68] + NET la_data_out[68] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1841150 -1200 ) N ;
+ - la_data_out[69] + NET la_data_out[69] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1858630 -1200 ) N ;
+ - la_data_out[6] + NET la_data_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 741750 -1200 ) N ;
+ - la_data_out[70] + NET la_data_out[70] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1876570 -1200 ) N ;
+ - la_data_out[71] + NET la_data_out[71] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1894510 -1200 ) N ;
+ - la_data_out[72] + NET la_data_out[72] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1911990 -1200 ) N ;
+ - la_data_out[73] + NET la_data_out[73] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1929930 -1200 ) N ;
+ - la_data_out[74] + NET la_data_out[74] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1947410 -1200 ) N ;
+ - la_data_out[75] + NET la_data_out[75] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1965350 -1200 ) N ;
+ - la_data_out[76] + NET la_data_out[76] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1982830 -1200 ) N ;
+ - la_data_out[77] + NET la_data_out[77] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2000770 -1200 ) N ;
+ - la_data_out[78] + NET la_data_out[78] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2018250 -1200 ) N ;
+ - la_data_out[79] + NET la_data_out[79] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2036190 -1200 ) N ;
+ - la_data_out[7] + NET la_data_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 759230 -1200 ) N ;
+ - la_data_out[80] + NET la_data_out[80] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2054130 -1200 ) N ;
+ - la_data_out[81] + NET la_data_out[81] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2071610 -1200 ) N ;
+ - la_data_out[82] + NET la_data_out[82] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2089550 -1200 ) N ;
+ - la_data_out[83] + NET la_data_out[83] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2107030 -1200 ) N ;
+ - la_data_out[84] + NET la_data_out[84] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2124970 -1200 ) N ;
+ - la_data_out[85] + NET la_data_out[85] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2142450 -1200 ) N ;
+ - la_data_out[86] + NET la_data_out[86] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2160390 -1200 ) N ;
+ - la_data_out[87] + NET la_data_out[87] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2177870 -1200 ) N ;
+ - la_data_out[88] + NET la_data_out[88] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2195810 -1200 ) N ;
+ - la_data_out[89] + NET la_data_out[89] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2213290 -1200 ) N ;
+ - la_data_out[8] + NET la_data_out[8] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 777170 -1200 ) N ;
+ - la_data_out[90] + NET la_data_out[90] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2231230 -1200 ) N ;
+ - la_data_out[91] + NET la_data_out[91] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2249170 -1200 ) N ;
+ - la_data_out[92] + NET la_data_out[92] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2266650 -1200 ) N ;
+ - la_data_out[93] + NET la_data_out[93] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2284590 -1200 ) N ;
+ - la_data_out[94] + NET la_data_out[94] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2302070 -1200 ) N ;
+ - la_data_out[95] + NET la_data_out[95] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2320010 -1200 ) N ;
+ - la_data_out[96] + NET la_data_out[96] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2337490 -1200 ) N ;
+ - la_data_out[97] + NET la_data_out[97] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2355430 -1200 ) N ;
+ - la_data_out[98] + NET la_data_out[98] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2372910 -1200 ) N ;
+ - la_data_out[99] + NET la_data_out[99] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2390850 -1200 ) N ;
+ - la_data_out[9] + NET la_data_out[9] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 794650 -1200 ) N ;
+ - la_oenb[0] + NET la_oenb[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 641010 -1200 ) N ;
+ - la_oenb[100] + NET la_oenb[100] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2414310 -1200 ) N ;
+ - la_oenb[101] + NET la_oenb[101] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2432250 -1200 ) N ;
+ - la_oenb[102] + NET la_oenb[102] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2449730 -1200 ) N ;
+ - la_oenb[103] + NET la_oenb[103] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2467670 -1200 ) N ;
+ - la_oenb[104] + NET la_oenb[104] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2485610 -1200 ) N ;
+ - la_oenb[105] + NET la_oenb[105] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2503090 -1200 ) N ;
+ - la_oenb[106] + NET la_oenb[106] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2521030 -1200 ) N ;
+ - la_oenb[107] + NET la_oenb[107] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2538510 -1200 ) N ;
+ - la_oenb[108] + NET la_oenb[108] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2556450 -1200 ) N ;
+ - la_oenb[109] + NET la_oenb[109] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2573930 -1200 ) N ;
+ - la_oenb[10] + NET la_oenb[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 818570 -1200 ) N ;
+ - la_oenb[110] + NET la_oenb[110] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2591870 -1200 ) N ;
+ - la_oenb[111] + NET la_oenb[111] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2609350 -1200 ) N ;
+ - la_oenb[112] + NET la_oenb[112] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2627290 -1200 ) N ;
+ - la_oenb[113] + NET la_oenb[113] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2645230 -1200 ) N ;
+ - la_oenb[114] + NET la_oenb[114] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2662710 -1200 ) N ;
+ - la_oenb[115] + NET la_oenb[115] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2680650 -1200 ) N ;
+ - la_oenb[116] + NET la_oenb[116] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2698130 -1200 ) N ;
+ - la_oenb[117] + NET la_oenb[117] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2716070 -1200 ) N ;
+ - la_oenb[118] + NET la_oenb[118] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2733550 -1200 ) N ;
+ - la_oenb[119] + NET la_oenb[119] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2751490 -1200 ) N ;
+ - la_oenb[11] + NET la_oenb[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 836050 -1200 ) N ;
+ - la_oenb[120] + NET la_oenb[120] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2768970 -1200 ) N ;
+ - la_oenb[121] + NET la_oenb[121] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2786910 -1200 ) N ;
+ - la_oenb[122] + NET la_oenb[122] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2804390 -1200 ) N ;
+ - la_oenb[123] + NET la_oenb[123] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2822330 -1200 ) N ;
+ - la_oenb[124] + NET la_oenb[124] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2840270 -1200 ) N ;
+ - la_oenb[125] + NET la_oenb[125] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2857750 -1200 ) N ;
+ - la_oenb[126] + NET la_oenb[126] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2875690 -1200 ) N ;
+ - la_oenb[127] + NET la_oenb[127] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2893170 -1200 ) N ;
+ - la_oenb[12] + NET la_oenb[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 853990 -1200 ) N ;
+ - la_oenb[13] + NET la_oenb[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 871470 -1200 ) N ;
+ - la_oenb[14] + NET la_oenb[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 889410 -1200 ) N ;
+ - la_oenb[15] + NET la_oenb[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 907350 -1200 ) N ;
+ - la_oenb[16] + NET la_oenb[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 924830 -1200 ) N ;
+ - la_oenb[17] + NET la_oenb[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 942770 -1200 ) N ;
+ - la_oenb[18] + NET la_oenb[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 960250 -1200 ) N ;
+ - la_oenb[19] + NET la_oenb[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 978190 -1200 ) N ;
+ - la_oenb[1] + NET la_oenb[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 658950 -1200 ) N ;
+ - la_oenb[20] + NET la_oenb[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 995670 -1200 ) N ;
+ - la_oenb[21] + NET la_oenb[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1013610 -1200 ) N ;
+ - la_oenb[22] + NET la_oenb[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1031090 -1200 ) N ;
+ - la_oenb[23] + NET la_oenb[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1049030 -1200 ) N ;
+ - la_oenb[24] + NET la_oenb[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1066970 -1200 ) N ;
+ - la_oenb[25] + NET la_oenb[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1084450 -1200 ) N ;
+ - la_oenb[26] + NET la_oenb[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1102390 -1200 ) N ;
+ - la_oenb[27] + NET la_oenb[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1119870 -1200 ) N ;
+ - la_oenb[28] + NET la_oenb[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1137810 -1200 ) N ;
+ - la_oenb[29] + NET la_oenb[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1155290 -1200 ) N ;
+ - la_oenb[2] + NET la_oenb[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 676430 -1200 ) N ;
+ - la_oenb[30] + NET la_oenb[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1173230 -1200 ) N ;
+ - la_oenb[31] + NET la_oenb[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1190710 -1200 ) N ;
+ - la_oenb[32] + NET la_oenb[32] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1208650 -1200 ) N ;
+ - la_oenb[33] + NET la_oenb[33] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1226130 -1200 ) N ;
+ - la_oenb[34] + NET la_oenb[34] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1244070 -1200 ) N ;
+ - la_oenb[35] + NET la_oenb[35] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1262010 -1200 ) N ;
+ - la_oenb[36] + NET la_oenb[36] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1279490 -1200 ) N ;
+ - la_oenb[37] + NET la_oenb[37] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1297430 -1200 ) N ;
+ - la_oenb[38] + NET la_oenb[38] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1314910 -1200 ) N ;
+ - la_oenb[39] + NET la_oenb[39] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1332850 -1200 ) N ;
+ - la_oenb[3] + NET la_oenb[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 694370 -1200 ) N ;
+ - la_oenb[40] + NET la_oenb[40] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1350330 -1200 ) N ;
+ - la_oenb[41] + NET la_oenb[41] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1368270 -1200 ) N ;
+ - la_oenb[42] + NET la_oenb[42] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1385750 -1200 ) N ;
+ - la_oenb[43] + NET la_oenb[43] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1403690 -1200 ) N ;
+ - la_oenb[44] + NET la_oenb[44] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1421630 -1200 ) N ;
+ - la_oenb[45] + NET la_oenb[45] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1439110 -1200 ) N ;
+ - la_oenb[46] + NET la_oenb[46] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1457050 -1200 ) N ;
+ - la_oenb[47] + NET la_oenb[47] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1474530 -1200 ) N ;
+ - la_oenb[48] + NET la_oenb[48] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1492470 -1200 ) N ;
+ - la_oenb[49] + NET la_oenb[49] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1509950 -1200 ) N ;
+ - la_oenb[4] + NET la_oenb[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 712310 -1200 ) N ;
+ - la_oenb[50] + NET la_oenb[50] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1527890 -1200 ) N ;
+ - la_oenb[51] + NET la_oenb[51] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1545370 -1200 ) N ;
+ - la_oenb[52] + NET la_oenb[52] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1563310 -1200 ) N ;
+ - la_oenb[53] + NET la_oenb[53] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1581250 -1200 ) N ;
+ - la_oenb[54] + NET la_oenb[54] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1598730 -1200 ) N ;
+ - la_oenb[55] + NET la_oenb[55] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1616670 -1200 ) N ;
+ - la_oenb[56] + NET la_oenb[56] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1634150 -1200 ) N ;
+ - la_oenb[57] + NET la_oenb[57] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1652090 -1200 ) N ;
+ - la_oenb[58] + NET la_oenb[58] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1669570 -1200 ) N ;
+ - la_oenb[59] + NET la_oenb[59] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1687510 -1200 ) N ;
+ - la_oenb[5] + NET la_oenb[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 729790 -1200 ) N ;
+ - la_oenb[60] + NET la_oenb[60] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1704990 -1200 ) N ;
+ - la_oenb[61] + NET la_oenb[61] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1722930 -1200 ) N ;
+ - la_oenb[62] + NET la_oenb[62] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1740410 -1200 ) N ;
+ - la_oenb[63] + NET la_oenb[63] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1758350 -1200 ) N ;
+ - la_oenb[64] + NET la_oenb[64] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1776290 -1200 ) N ;
+ - la_oenb[65] + NET la_oenb[65] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1793770 -1200 ) N ;
+ - la_oenb[66] + NET la_oenb[66] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1811710 -1200 ) N ;
+ - la_oenb[67] + NET la_oenb[67] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1829190 -1200 ) N ;
+ - la_oenb[68] + NET la_oenb[68] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1847130 -1200 ) N ;
+ - la_oenb[69] + NET la_oenb[69] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1864610 -1200 ) N ;
+ - la_oenb[6] + NET la_oenb[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 747730 -1200 ) N ;
+ - la_oenb[70] + NET la_oenb[70] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1882550 -1200 ) N ;
+ - la_oenb[71] + NET la_oenb[71] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1900030 -1200 ) N ;
+ - la_oenb[72] + NET la_oenb[72] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1917970 -1200 ) N ;
+ - la_oenb[73] + NET la_oenb[73] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1935910 -1200 ) N ;
+ - la_oenb[74] + NET la_oenb[74] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1953390 -1200 ) N ;
+ - la_oenb[75] + NET la_oenb[75] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1971330 -1200 ) N ;
+ - la_oenb[76] + NET la_oenb[76] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1988810 -1200 ) N ;
+ - la_oenb[77] + NET la_oenb[77] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2006750 -1200 ) N ;
+ - la_oenb[78] + NET la_oenb[78] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2024230 -1200 ) N ;
+ - la_oenb[79] + NET la_oenb[79] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2042170 -1200 ) N ;
+ - la_oenb[7] + NET la_oenb[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 765210 -1200 ) N ;
+ - la_oenb[80] + NET la_oenb[80] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2059650 -1200 ) N ;
+ - la_oenb[81] + NET la_oenb[81] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2077590 -1200 ) N ;
+ - la_oenb[82] + NET la_oenb[82] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2095070 -1200 ) N ;
+ - la_oenb[83] + NET la_oenb[83] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2113010 -1200 ) N ;
+ - la_oenb[84] + NET la_oenb[84] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2130950 -1200 ) N ;
+ - la_oenb[85] + NET la_oenb[85] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2148430 -1200 ) N ;
+ - la_oenb[86] + NET la_oenb[86] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2166370 -1200 ) N ;
+ - la_oenb[87] + NET la_oenb[87] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2183850 -1200 ) N ;
+ - la_oenb[88] + NET la_oenb[88] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2201790 -1200 ) N ;
+ - la_oenb[89] + NET la_oenb[89] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2219270 -1200 ) N ;
+ - la_oenb[8] + NET la_oenb[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 783150 -1200 ) N ;
+ - la_oenb[90] + NET la_oenb[90] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2237210 -1200 ) N ;
+ - la_oenb[91] + NET la_oenb[91] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2254690 -1200 ) N ;
+ - la_oenb[92] + NET la_oenb[92] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2272630 -1200 ) N ;
+ - la_oenb[93] + NET la_oenb[93] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2290570 -1200 ) N ;
+ - la_oenb[94] + NET la_oenb[94] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2308050 -1200 ) N ;
+ - la_oenb[95] + NET la_oenb[95] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2325990 -1200 ) N ;
+ - la_oenb[96] + NET la_oenb[96] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2343470 -1200 ) N ;
+ - la_oenb[97] + NET la_oenb[97] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2361410 -1200 ) N ;
+ - la_oenb[98] + NET la_oenb[98] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2378890 -1200 ) N ;
+ - la_oenb[99] + NET la_oenb[99] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2396830 -1200 ) N ;
+ - la_oenb[9] + NET la_oenb[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 800630 -1200 ) N ;
+ - user_clock2 + NET user_clock2 + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2899150 -1200 ) N ;
+ - user_irq[0] + NET user_irq[0] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2905130 -1200 ) N ;
+ - user_irq[1] + NET user_irq[1] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2911110 -1200 ) N ;
+ - user_irq[2] + NET user_irq[2] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2917090 -1200 ) N ;
+ - vccd1 + NET vccd1 + SPECIAL + DIRECTION INPUT + USE POWER
+ + PORT
+ + LAYER met4 ( -1550 -1769310 ) ( 1550 1769310 )
+ + LAYER met4 ( -181550 -1769310 ) ( -178450 1769310 )
+ + LAYER met4 ( -361550 -1769310 ) ( -358450 1769310 )
+ + LAYER met4 ( -541550 -1769310 ) ( -538450 1769310 )
+ + LAYER met4 ( -721550 -1769310 ) ( -718450 1769310 )
+ + LAYER met4 ( -901550 540160 ) ( -898450 1769310 )
+ + LAYER met4 ( -1081550 540160 ) ( -1078450 1769310 )
+ + LAYER met4 ( -1261550 540160 ) ( -1258450 1769310 )
+ + LAYER met4 ( -1441550 540160 ) ( -1438450 1769310 )
+ + LAYER met4 ( -1621550 540160 ) ( -1618450 1769310 )
+ + LAYER met4 ( -1801550 -1769310 ) ( -1798450 1769310 )
+ + LAYER met4 ( -1981550 -1769310 ) ( -1978450 1769310 )
+ + LAYER met4 ( -2161550 -1769310 ) ( -2158450 1769310 )
+ + LAYER met4 ( -2341550 -1769310 ) ( -2338450 1769310 )
+ + LAYER met4 ( -2521550 -1769310 ) ( -2518450 1769310 )
+ + LAYER met4 ( -2701550 -1769310 ) ( -2698450 1769310 )
+ + LAYER met4 ( -2881550 -1769310 ) ( -2878450 1769310 )
+ + LAYER met4 ( 36030 -1764510 ) ( 39130 1764510 )
+ + LAYER met4 ( -2900550 -1764510 ) ( -2897450 1764510 )
+ + LAYER met4 ( -901550 -1769310 ) ( -898450 -79840 )
+ + LAYER met4 ( -1081550 -1769310 ) ( -1078450 -79840 )
+ + LAYER met4 ( -1261550 -1769310 ) ( -1258450 -79840 )
+ + LAYER met4 ( -1441550 -1769310 ) ( -1438450 -79840 )
+ + LAYER met4 ( -1621550 -1769310 ) ( -1618450 -79840 )
+ + LAYER met5 ( -2900550 1761410 ) ( 39130 1764510 )
+ + LAYER met5 ( -2905350 1674490 ) ( 43930 1677590 )
+ + LAYER met5 ( -2905350 1494490 ) ( 43930 1497590 )
+ + LAYER met5 ( -2905350 1314490 ) ( 43930 1317590 )
+ + LAYER met5 ( -2905350 1134490 ) ( 43930 1137590 )
+ + LAYER met5 ( -2905350 954490 ) ( 43930 957590 )
+ + LAYER met5 ( -2905350 774490 ) ( 43930 777590 )
+ + LAYER met5 ( -2905350 594490 ) ( 43930 597590 )
+ + LAYER met5 ( -2905350 414490 ) ( 43930 417590 )
+ + LAYER met5 ( -2905350 234490 ) ( 43930 237590 )
+ + LAYER met5 ( -2905350 54490 ) ( 43930 57590 )
+ + LAYER met5 ( -2905350 -125510 ) ( 43930 -122410 )
+ + LAYER met5 ( -2905350 -305510 ) ( 43930 -302410 )
+ + LAYER met5 ( -2905350 -485510 ) ( 43930 -482410 )
+ + LAYER met5 ( -2905350 -665510 ) ( 43930 -662410 )
+ + LAYER met5 ( -2905350 -845510 ) ( 43930 -842410 )
+ + LAYER met5 ( -2905350 -1025510 ) ( 43930 -1022410 )
+ + LAYER met5 ( -2905350 -1205510 ) ( 43930 -1202410 )
+ + LAYER met5 ( -2905350 -1385510 ) ( 43930 -1382410 )
+ + LAYER met5 ( -2905350 -1565510 ) ( 43930 -1562410 )
+ + LAYER met5 ( -2905350 -1745510 ) ( 43930 -1742410 )
+ + LAYER met5 ( -2900550 -1764510 ) ( 39130 -1761410 )
+ + FIXED ( 2890520 1759840 ) N ;
+ - vccd2 + NET vccd2 + SPECIAL + DIRECTION INPUT + USE POWER
+ + PORT
+ + LAYER met4 ( -1550 -1778910 ) ( 1550 1778910 )
+ + LAYER met4 ( -181550 -1778910 ) ( -178450 1778910 )
+ + LAYER met4 ( -361550 -1778910 ) ( -358450 1778910 )
+ + LAYER met4 ( -541550 -1778910 ) ( -538450 1778910 )
+ + LAYER met4 ( -721550 -1778910 ) ( -718450 1778910 )
+ + LAYER met4 ( -901550 540160 ) ( -898450 1778910 )
+ + LAYER met4 ( -1081550 540160 ) ( -1078450 1778910 )
+ + LAYER met4 ( -1261550 540160 ) ( -1258450 1778910 )
+ + LAYER met4 ( -1441550 540160 ) ( -1438450 1778910 )
+ + LAYER met4 ( -1621550 540160 ) ( -1618450 1778910 )
+ + LAYER met4 ( -1801550 -1778910 ) ( -1798450 1778910 )
+ + LAYER met4 ( -1981550 -1778910 ) ( -1978450 1778910 )
+ + LAYER met4 ( -2161550 -1778910 ) ( -2158450 1778910 )
+ + LAYER met4 ( -2341550 -1778910 ) ( -2338450 1778910 )
+ + LAYER met4 ( -2521550 -1778910 ) ( -2518450 1778910 )
+ + LAYER met4 ( -2701550 -1778910 ) ( -2698450 1778910 )
+ + LAYER met4 ( -2881550 -1778910 ) ( -2878450 1778910 )
+ + LAYER met4 ( 27030 -1774110 ) ( 30130 1774110 )
+ + LAYER met4 ( -2928750 -1774110 ) ( -2925650 1774110 )
+ + LAYER met4 ( -901550 -1778910 ) ( -898450 -79840 )
+ + LAYER met4 ( -1081550 -1778910 ) ( -1078450 -79840 )
+ + LAYER met4 ( -1261550 -1778910 ) ( -1258450 -79840 )
+ + LAYER met4 ( -1441550 -1778910 ) ( -1438450 -79840 )
+ + LAYER met4 ( -1621550 -1778910 ) ( -1618450 -79840 )
+ + LAYER met5 ( -2928750 1771010 ) ( 30130 1774110 )
+ + LAYER met5 ( -2933550 1693090 ) ( 34930 1696190 )
+ + LAYER met5 ( -2933550 1513090 ) ( 34930 1516190 )
+ + LAYER met5 ( -2933550 1333090 ) ( 34930 1336190 )
+ + LAYER met5 ( -2933550 1153090 ) ( 34930 1156190 )
+ + LAYER met5 ( -2933550 973090 ) ( 34930 976190 )
+ + LAYER met5 ( -2933550 793090 ) ( 34930 796190 )
+ + LAYER met5 ( -2933550 613090 ) ( 34930 616190 )
+ + LAYER met5 ( -2933550 433090 ) ( 34930 436190 )
+ + LAYER met5 ( -2933550 253090 ) ( 34930 256190 )
+ + LAYER met5 ( -2933550 73090 ) ( 34930 76190 )
+ + LAYER met5 ( -2933550 -106910 ) ( 34930 -103810 )
+ + LAYER met5 ( -2933550 -286910 ) ( 34930 -283810 )
+ + LAYER met5 ( -2933550 -466910 ) ( 34930 -463810 )
+ + LAYER met5 ( -2933550 -646910 ) ( 34930 -643810 )
+ + LAYER met5 ( -2933550 -826910 ) ( 34930 -823810 )
+ + LAYER met5 ( -2933550 -1006910 ) ( 34930 -1003810 )
+ + LAYER met5 ( -2933550 -1186910 ) ( 34930 -1183810 )
+ + LAYER met5 ( -2933550 -1366910 ) ( 34930 -1363810 )
+ + LAYER met5 ( -2933550 -1546910 ) ( 34930 -1543810 )
+ + LAYER met5 ( -2933550 -1726910 ) ( 34930 -1723810 )
+ + LAYER met5 ( -2928750 -1774110 ) ( 30130 -1771010 )
+ + FIXED ( 2909120 1759840 ) N ;
+ - vdda1 + NET vdda1 + SPECIAL + DIRECTION INPUT + USE POWER
+ + PORT
+ + LAYER met4 ( -1550 -1788510 ) ( 1550 1788510 )
+ + LAYER met4 ( -181550 -1788510 ) ( -178450 1788510 )
+ + LAYER met4 ( -361550 -1788510 ) ( -358450 1788510 )
+ + LAYER met4 ( -541550 -1788510 ) ( -538450 1788510 )
+ + LAYER met4 ( -721550 540160 ) ( -718450 1788510 )
+ + LAYER met4 ( -901550 540160 ) ( -898450 1788510 )
+ + LAYER met4 ( -1081550 540160 ) ( -1078450 1788510 )
+ + LAYER met4 ( -1261550 540160 ) ( -1258450 1788510 )
+ + LAYER met4 ( -1441550 540160 ) ( -1438450 1788510 )
+ + LAYER met4 ( -1621550 -1788510 ) ( -1618450 1788510 )
+ + LAYER met4 ( -1801550 -1788510 ) ( -1798450 1788510 )
+ + LAYER met4 ( -1981550 -1788510 ) ( -1978450 1788510 )
+ + LAYER met4 ( -2161550 -1788510 ) ( -2158450 1788510 )
+ + LAYER met4 ( -2341550 -1788510 ) ( -2338450 1788510 )
+ + LAYER met4 ( -2521550 -1788510 ) ( -2518450 1788510 )
+ + LAYER met4 ( -2701550 -1788510 ) ( -2698450 1788510 )
+ + LAYER met4 ( 198030 -1783710 ) ( 201130 1783710 )
+ + LAYER met4 ( -2776950 -1783710 ) ( -2773850 1783710 )
+ + LAYER met4 ( -721550 -1788510 ) ( -718450 -79840 )
+ + LAYER met4 ( -901550 -1788510 ) ( -898450 -79840 )
+ + LAYER met4 ( -1081550 -1788510 ) ( -1078450 -79840 )
+ + LAYER met4 ( -1261550 -1788510 ) ( -1258450 -79840 )
+ + LAYER met4 ( -1441550 -1788510 ) ( -1438450 -79840 )
+ + LAYER met5 ( -2776950 1780610 ) ( 201130 1783710 )
+ + LAYER met5 ( -2781750 1711690 ) ( 205930 1714790 )
+ + LAYER met5 ( -2781750 1531690 ) ( 205930 1534790 )
+ + LAYER met5 ( -2781750 1351690 ) ( 205930 1354790 )
+ + LAYER met5 ( -2781750 1171690 ) ( 205930 1174790 )
+ + LAYER met5 ( -2781750 991690 ) ( 205930 994790 )
+ + LAYER met5 ( -2781750 811690 ) ( 205930 814790 )
+ + LAYER met5 ( -2781750 631690 ) ( 205930 634790 )
+ + LAYER met5 ( -2781750 451690 ) ( 205930 454790 )
+ + LAYER met5 ( -2781750 271690 ) ( 205930 274790 )
+ + LAYER met5 ( -2781750 91690 ) ( 205930 94790 )
+ + LAYER met5 ( -2781750 -88310 ) ( 205930 -85210 )
+ + LAYER met5 ( -2781750 -268310 ) ( 205930 -265210 )
+ + LAYER met5 ( -2781750 -448310 ) ( 205930 -445210 )
+ + LAYER met5 ( -2781750 -628310 ) ( 205930 -625210 )
+ + LAYER met5 ( -2781750 -808310 ) ( 205930 -805210 )
+ + LAYER met5 ( -2781750 -988310 ) ( 205930 -985210 )
+ + LAYER met5 ( -2781750 -1168310 ) ( 205930 -1165210 )
+ + LAYER met5 ( -2781750 -1348310 ) ( 205930 -1345210 )
+ + LAYER met5 ( -2781750 -1528310 ) ( 205930 -1525210 )
+ + LAYER met5 ( -2781750 -1708310 ) ( 205930 -1705210 )
+ + LAYER met5 ( -2776950 -1783710 ) ( 201130 -1780610 )
+ + FIXED ( 2747720 1759840 ) N ;
+ - vdda2 + NET vdda2 + SPECIAL + DIRECTION INPUT + USE POWER
+ + PORT
+ + LAYER met4 ( -1550 -1798110 ) ( 1550 1798110 )
+ + LAYER met4 ( -181550 -1798110 ) ( -178450 1798110 )
+ + LAYER met4 ( -361550 -1798110 ) ( -358450 1798110 )
+ + LAYER met4 ( -541550 -1798110 ) ( -538450 1798110 )
+ + LAYER met4 ( -721550 540160 ) ( -718450 1798110 )
+ + LAYER met4 ( -901550 540160 ) ( -898450 1798110 )
+ + LAYER met4 ( -1081550 540160 ) ( -1078450 1798110 )
+ + LAYER met4 ( -1261550 540160 ) ( -1258450 1798110 )
+ + LAYER met4 ( -1441550 540160 ) ( -1438450 1798110 )
+ + LAYER met4 ( -1621550 -1798110 ) ( -1618450 1798110 )
+ + LAYER met4 ( -1801550 -1798110 ) ( -1798450 1798110 )
+ + LAYER met4 ( -1981550 -1798110 ) ( -1978450 1798110 )
+ + LAYER met4 ( -2161550 -1798110 ) ( -2158450 1798110 )
+ + LAYER met4 ( -2341550 -1798110 ) ( -2338450 1798110 )
+ + LAYER met4 ( -2521550 -1798110 ) ( -2518450 1798110 )
+ + LAYER met4 ( -2701550 -1798110 ) ( -2698450 1798110 )
+ + LAYER met4 ( 189030 -1793310 ) ( 192130 1793310 )
+ + LAYER met4 ( -2805150 -1793310 ) ( -2802050 1793310 )
+ + LAYER met4 ( -721550 -1798110 ) ( -718450 -79840 )
+ + LAYER met4 ( -901550 -1798110 ) ( -898450 -79840 )
+ + LAYER met4 ( -1081550 -1798110 ) ( -1078450 -79840 )
+ + LAYER met4 ( -1261550 -1798110 ) ( -1258450 -79840 )
+ + LAYER met4 ( -1441550 -1798110 ) ( -1438450 -79840 )
+ + LAYER met5 ( -2805150 1790210 ) ( 192130 1793310 )
+ + LAYER met5 ( -2809950 1730290 ) ( 196930 1733390 )
+ + LAYER met5 ( -2809950 1550290 ) ( 196930 1553390 )
+ + LAYER met5 ( -2809950 1370290 ) ( 196930 1373390 )
+ + LAYER met5 ( -2809950 1190290 ) ( 196930 1193390 )
+ + LAYER met5 ( -2809950 1010290 ) ( 196930 1013390 )
+ + LAYER met5 ( -2809950 830290 ) ( 196930 833390 )
+ + LAYER met5 ( -2809950 650290 ) ( 196930 653390 )
+ + LAYER met5 ( -2809950 470290 ) ( 196930 473390 )
+ + LAYER met5 ( -2809950 290290 ) ( 196930 293390 )
+ + LAYER met5 ( -2809950 110290 ) ( 196930 113390 )
+ + LAYER met5 ( -2809950 -69710 ) ( 196930 -66610 )
+ + LAYER met5 ( -2809950 -249710 ) ( 196930 -246610 )
+ + LAYER met5 ( -2809950 -429710 ) ( 196930 -426610 )
+ + LAYER met5 ( -2809950 -609710 ) ( 196930 -606610 )
+ + LAYER met5 ( -2809950 -789710 ) ( 196930 -786610 )
+ + LAYER met5 ( -2809950 -969710 ) ( 196930 -966610 )
+ + LAYER met5 ( -2809950 -1149710 ) ( 196930 -1146610 )
+ + LAYER met5 ( -2809950 -1329710 ) ( 196930 -1326610 )
+ + LAYER met5 ( -2809950 -1509710 ) ( 196930 -1506610 )
+ + LAYER met5 ( -2809950 -1689710 ) ( 196930 -1686610 )
+ + LAYER met5 ( -2805150 -1793310 ) ( 192130 -1790210 )
+ + FIXED ( 2766320 1759840 ) N ;
+ - vssa1 + NET vssa1 + SPECIAL + DIRECTION INPUT + USE GROUND
+ + PORT
+ + LAYER met4 ( -1550 -1788510 ) ( 1550 1788510 )
+ + LAYER met4 ( -115930 -1788510 ) ( -112830 1788510 )
+ + LAYER met4 ( -295930 -1788510 ) ( -292830 1788510 )
+ + LAYER met4 ( -475930 -1788510 ) ( -472830 1788510 )
+ + LAYER met4 ( -655930 -1788510 ) ( -652830 1788510 )
+ + LAYER met4 ( -835930 -1788510 ) ( -832830 1788510 )
+ + LAYER met4 ( -1015930 540160 ) ( -1012830 1788510 )
+ + LAYER met4 ( -1195930 540160 ) ( -1192830 1788510 )
+ + LAYER met4 ( -1375930 540160 ) ( -1372830 1788510 )
+ + LAYER met4 ( -1555930 540160 ) ( -1552830 1788510 )
+ + LAYER met4 ( -1735930 540160 ) ( -1732830 1788510 )
+ + LAYER met4 ( -1915930 -1788510 ) ( -1912830 1788510 )
+ + LAYER met4 ( -2095930 -1788510 ) ( -2092830 1788510 )
+ + LAYER met4 ( -2275930 -1788510 ) ( -2272830 1788510 )
+ + LAYER met4 ( -2455930 -1788510 ) ( -2452830 1788510 )
+ + LAYER met4 ( -2635930 -1788510 ) ( -2632830 1788510 )
+ + LAYER met4 ( -2815930 -1788510 ) ( -2812830 1788510 )
+ + LAYER met4 ( -2986130 -1788510 ) ( -2983030 1788510 )
+ + LAYER met4 ( -1015930 -1788510 ) ( -1012830 -79840 )
+ + LAYER met4 ( -1195930 -1788510 ) ( -1192830 -79840 )
+ + LAYER met4 ( -1375930 -1788510 ) ( -1372830 -79840 )
+ + LAYER met4 ( -1555930 -1788510 ) ( -1552830 -79840 )
+ + LAYER met4 ( -1735930 -1788510 ) ( -1732830 -79840 )
+ + LAYER met5 ( -2986130 1785410 ) ( 1550 1788510 )
+ + LAYER met5 ( -2986130 1621690 ) ( 1550 1624790 )
+ + LAYER met5 ( -2986130 1441690 ) ( 1550 1444790 )
+ + LAYER met5 ( -2986130 1261690 ) ( 1550 1264790 )
+ + LAYER met5 ( -2986130 1081690 ) ( 1550 1084790 )
+ + LAYER met5 ( -2986130 901690 ) ( 1550 904790 )
+ + LAYER met5 ( -2986130 721690 ) ( 1550 724790 )
+ + LAYER met5 ( -2986130 541690 ) ( 1550 544790 )
+ + LAYER met5 ( -2986130 361690 ) ( 1550 364790 )
+ + LAYER met5 ( -2986130 181690 ) ( 1550 184790 )
+ + LAYER met5 ( -2986130 1690 ) ( 1550 4790 )
+ + LAYER met5 ( -2986130 -178310 ) ( 1550 -175210 )
+ + LAYER met5 ( -2986130 -358310 ) ( 1550 -355210 )
+ + LAYER met5 ( -2986130 -538310 ) ( 1550 -535210 )
+ + LAYER met5 ( -2986130 -718310 ) ( 1550 -715210 )
+ + LAYER met5 ( -2986130 -898310 ) ( 1550 -895210 )
+ + LAYER met5 ( -2986130 -1078310 ) ( 1550 -1075210 )
+ + LAYER met5 ( -2986130 -1258310 ) ( 1550 -1255210 )
+ + LAYER met5 ( -2986130 -1438310 ) ( 1550 -1435210 )
+ + LAYER met5 ( -2986130 -1618310 ) ( 1550 -1615210 )
+ + LAYER met5 ( -2986130 -1788510 ) ( 1550 -1785410 )
+ + FIXED ( 2952100 1759840 ) N ;
+ - vssa2 + NET vssa2 + SPECIAL + DIRECTION INPUT + USE GROUND
+ + PORT
+ + LAYER met4 ( -1550 -1798110 ) ( 1550 1798110 )
+ + LAYER met4 ( -106930 -1798110 ) ( -103830 1798110 )
+ + LAYER met4 ( -286930 -1798110 ) ( -283830 1798110 )
+ + LAYER met4 ( -466930 -1798110 ) ( -463830 1798110 )
+ + LAYER met4 ( -646930 -1798110 ) ( -643830 1798110 )
+ + LAYER met4 ( -826930 -1798110 ) ( -823830 1798110 )
+ + LAYER met4 ( -1006930 540160 ) ( -1003830 1798110 )
+ + LAYER met4 ( -1186930 540160 ) ( -1183830 1798110 )
+ + LAYER met4 ( -1366930 540160 ) ( -1363830 1798110 )
+ + LAYER met4 ( -1546930 540160 ) ( -1543830 1798110 )
+ + LAYER met4 ( -1726930 540160 ) ( -1723830 1798110 )
+ + LAYER met4 ( -1906930 -1798110 ) ( -1903830 1798110 )
+ + LAYER met4 ( -2086930 -1798110 ) ( -2083830 1798110 )
+ + LAYER met4 ( -2266930 -1798110 ) ( -2263830 1798110 )
+ + LAYER met4 ( -2446930 -1798110 ) ( -2443830 1798110 )
+ + LAYER met4 ( -2626930 -1798110 ) ( -2623830 1798110 )
+ + LAYER met4 ( -2806930 -1798110 ) ( -2803830 1798110 )
+ + LAYER met4 ( -3005330 -1798110 ) ( -3002230 1798110 )
+ + LAYER met4 ( -1006930 -1798110 ) ( -1003830 -79840 )
+ + LAYER met4 ( -1186930 -1798110 ) ( -1183830 -79840 )
+ + LAYER met4 ( -1366930 -1798110 ) ( -1363830 -79840 )
+ + LAYER met4 ( -1546930 -1798110 ) ( -1543830 -79840 )
+ + LAYER met4 ( -1726930 -1798110 ) ( -1723830 -79840 )
+ + LAYER met5 ( -3005330 1795010 ) ( 1550 1798110 )
+ + LAYER met5 ( -3005330 1640290 ) ( 1550 1643390 )
+ + LAYER met5 ( -3005330 1460290 ) ( 1550 1463390 )
+ + LAYER met5 ( -3005330 1280290 ) ( 1550 1283390 )
+ + LAYER met5 ( -3005330 1100290 ) ( 1550 1103390 )
+ + LAYER met5 ( -3005330 920290 ) ( 1550 923390 )
+ + LAYER met5 ( -3005330 740290 ) ( 1550 743390 )
+ + LAYER met5 ( -3005330 560290 ) ( 1550 563390 )
+ + LAYER met5 ( -3005330 380290 ) ( 1550 383390 )
+ + LAYER met5 ( -3005330 200290 ) ( 1550 203390 )
+ + LAYER met5 ( -3005330 20290 ) ( 1550 23390 )
+ + LAYER met5 ( -3005330 -159710 ) ( 1550 -156610 )
+ + LAYER met5 ( -3005330 -339710 ) ( 1550 -336610 )
+ + LAYER met5 ( -3005330 -519710 ) ( 1550 -516610 )
+ + LAYER met5 ( -3005330 -699710 ) ( 1550 -696610 )
+ + LAYER met5 ( -3005330 -879710 ) ( 1550 -876610 )
+ + LAYER met5 ( -3005330 -1059710 ) ( 1550 -1056610 )
+ + LAYER met5 ( -3005330 -1239710 ) ( 1550 -1236610 )
+ + LAYER met5 ( -3005330 -1419710 ) ( 1550 -1416610 )
+ + LAYER met5 ( -3005330 -1599710 ) ( 1550 -1596610 )
+ + LAYER met5 ( -3005330 -1798110 ) ( 1550 -1795010 )
+ + FIXED ( 2961700 1759840 ) N ;
+ - vssd1 + NET vssd1 + SPECIAL + DIRECTION INPUT + USE GROUND
+ + PORT
+ + LAYER met4 ( -1550 -1769310 ) ( 1550 1769310 )
+ + LAYER met4 ( -133930 -1769310 ) ( -130830 1769310 )
+ + LAYER met4 ( -313930 -1769310 ) ( -310830 1769310 )
+ + LAYER met4 ( -493930 -1769310 ) ( -490830 1769310 )
+ + LAYER met4 ( -673930 -1769310 ) ( -670830 1769310 )
+ + LAYER met4 ( -853930 540160 ) ( -850830 1769310 )
+ + LAYER met4 ( -1033930 540160 ) ( -1030830 1769310 )
+ + LAYER met4 ( -1213930 540160 ) ( -1210830 1769310 )
+ + LAYER met4 ( -1393930 540160 ) ( -1390830 1769310 )
+ + LAYER met4 ( -1573930 540160 ) ( -1570830 1769310 )
+ + LAYER met4 ( -1753930 540160 ) ( -1750830 1769310 )
+ + LAYER met4 ( -1933930 -1769310 ) ( -1930830 1769310 )
+ + LAYER met4 ( -2113930 -1769310 ) ( -2110830 1769310 )
+ + LAYER met4 ( -2293930 -1769310 ) ( -2290830 1769310 )
+ + LAYER met4 ( -2473930 -1769310 ) ( -2470830 1769310 )
+ + LAYER met4 ( -2653930 -1769310 ) ( -2650830 1769310 )
+ + LAYER met4 ( -2833930 -1769310 ) ( -2830830 1769310 )
+ + LAYER met4 ( -2947730 -1769310 ) ( -2944630 1769310 )
+ + LAYER met4 ( -853930 -1769310 ) ( -850830 -79840 )
+ + LAYER met4 ( -1033930 -1769310 ) ( -1030830 -79840 )
+ + LAYER met4 ( -1213930 -1769310 ) ( -1210830 -79840 )
+ + LAYER met4 ( -1393930 -1769310 ) ( -1390830 -79840 )
+ + LAYER met4 ( -1573930 -1769310 ) ( -1570830 -79840 )
+ + LAYER met4 ( -1753930 -1769310 ) ( -1750830 -79840 )
+ + LAYER met5 ( -2947730 1766210 ) ( 1550 1769310 )
+ + LAYER met5 ( -2947730 1584490 ) ( 1550 1587590 )
+ + LAYER met5 ( -2947730 1404490 ) ( 1550 1407590 )
+ + LAYER met5 ( -2947730 1224490 ) ( 1550 1227590 )
+ + LAYER met5 ( -2947730 1044490 ) ( 1550 1047590 )
+ + LAYER met5 ( -2947730 864490 ) ( 1550 867590 )
+ + LAYER met5 ( -2947730 684490 ) ( 1550 687590 )
+ + LAYER met5 ( -2947730 504490 ) ( 1550 507590 )
+ + LAYER met5 ( -2947730 324490 ) ( 1550 327590 )
+ + LAYER met5 ( -2947730 144490 ) ( 1550 147590 )
+ + LAYER met5 ( -2947730 -35510 ) ( 1550 -32410 )
+ + LAYER met5 ( -2947730 -215510 ) ( 1550 -212410 )
+ + LAYER met5 ( -2947730 -395510 ) ( 1550 -392410 )
+ + LAYER met5 ( -2947730 -575510 ) ( 1550 -572410 )
+ + LAYER met5 ( -2947730 -755510 ) ( 1550 -752410 )
+ + LAYER met5 ( -2947730 -935510 ) ( 1550 -932410 )
+ + LAYER met5 ( -2947730 -1115510 ) ( 1550 -1112410 )
+ + LAYER met5 ( -2947730 -1295510 ) ( 1550 -1292410 )
+ + LAYER met5 ( -2947730 -1475510 ) ( 1550 -1472410 )
+ + LAYER met5 ( -2947730 -1655510 ) ( 1550 -1652410 )
+ + LAYER met5 ( -2947730 -1769310 ) ( 1550 -1766210 )
+ + FIXED ( 2932900 1759840 ) N ;
+ - vssd2 + NET vssd2 + SPECIAL + DIRECTION INPUT + USE GROUND
+ + PORT
+ + LAYER met4 ( -1550 -1778910 ) ( 1550 1778910 )
+ + LAYER met4 ( -124930 -1778910 ) ( -121830 1778910 )
+ + LAYER met4 ( -304930 -1778910 ) ( -301830 1778910 )
+ + LAYER met4 ( -484930 -1778910 ) ( -481830 1778910 )
+ + LAYER met4 ( -664930 -1778910 ) ( -661830 1778910 )
+ + LAYER met4 ( -844930 -1778910 ) ( -841830 1778910 )
+ + LAYER met4 ( -1024930 540160 ) ( -1021830 1778910 )
+ + LAYER met4 ( -1204930 540160 ) ( -1201830 1778910 )
+ + LAYER met4 ( -1384930 540160 ) ( -1381830 1778910 )
+ + LAYER met4 ( -1564930 540160 ) ( -1561830 1778910 )
+ + LAYER met4 ( -1744930 540160 ) ( -1741830 1778910 )
+ + LAYER met4 ( -1924930 -1778910 ) ( -1921830 1778910 )
+ + LAYER met4 ( -2104930 -1778910 ) ( -2101830 1778910 )
+ + LAYER met4 ( -2284930 -1778910 ) ( -2281830 1778910 )
+ + LAYER met4 ( -2464930 -1778910 ) ( -2461830 1778910 )
+ + LAYER met4 ( -2644930 -1778910 ) ( -2641830 1778910 )
+ + LAYER met4 ( -2824930 -1778910 ) ( -2821830 1778910 )
+ + LAYER met4 ( -2966930 -1778910 ) ( -2963830 1778910 )
+ + LAYER met4 ( -1024930 -1778910 ) ( -1021830 -79840 )
+ + LAYER met4 ( -1204930 -1778910 ) ( -1201830 -79840 )
+ + LAYER met4 ( -1384930 -1778910 ) ( -1381830 -79840 )
+ + LAYER met4 ( -1564930 -1778910 ) ( -1561830 -79840 )
+ + LAYER met4 ( -1744930 -1778910 ) ( -1741830 -79840 )
+ + LAYER met5 ( -2966930 1775810 ) ( 1550 1778910 )
+ + LAYER met5 ( -2966930 1603090 ) ( 1550 1606190 )
+ + LAYER met5 ( -2966930 1423090 ) ( 1550 1426190 )
+ + LAYER met5 ( -2966930 1243090 ) ( 1550 1246190 )
+ + LAYER met5 ( -2966930 1063090 ) ( 1550 1066190 )
+ + LAYER met5 ( -2966930 883090 ) ( 1550 886190 )
+ + LAYER met5 ( -2966930 703090 ) ( 1550 706190 )
+ + LAYER met5 ( -2966930 523090 ) ( 1550 526190 )
+ + LAYER met5 ( -2966930 343090 ) ( 1550 346190 )
+ + LAYER met5 ( -2966930 163090 ) ( 1550 166190 )
+ + LAYER met5 ( -2966930 -16910 ) ( 1550 -13810 )
+ + LAYER met5 ( -2966930 -196910 ) ( 1550 -193810 )
+ + LAYER met5 ( -2966930 -376910 ) ( 1550 -373810 )
+ + LAYER met5 ( -2966930 -556910 ) ( 1550 -553810 )
+ + LAYER met5 ( -2966930 -736910 ) ( 1550 -733810 )
+ + LAYER met5 ( -2966930 -916910 ) ( 1550 -913810 )
+ + LAYER met5 ( -2966930 -1096910 ) ( 1550 -1093810 )
+ + LAYER met5 ( -2966930 -1276910 ) ( 1550 -1273810 )
+ + LAYER met5 ( -2966930 -1456910 ) ( 1550 -1453810 )
+ + LAYER met5 ( -2966930 -1636910 ) ( 1550 -1633810 )
+ + LAYER met5 ( -2966930 -1778910 ) ( 1550 -1775810 )
+ + FIXED ( 2942500 1759840 ) N ;
+ - wb_clk_i + NET wb_clk_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2990 -1200 ) N ;
+ - wb_rst_i + NET wb_rst_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 8510 -1200 ) N ;
+ - wbs_ack_o + NET wbs_ack_o + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 14490 -1200 ) N ;
+ - wbs_adr_i[0] + NET wbs_adr_i[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 38410 -1200 ) N ;
+ - wbs_adr_i[10] + NET wbs_adr_i[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 239430 -1200 ) N ;
+ - wbs_adr_i[11] + NET wbs_adr_i[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 256910 -1200 ) N ;
+ - wbs_adr_i[12] + NET wbs_adr_i[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 274850 -1200 ) N ;
+ - wbs_adr_i[13] + NET wbs_adr_i[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 292330 -1200 ) N ;
+ - wbs_adr_i[14] + NET wbs_adr_i[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 310270 -1200 ) N ;
+ - wbs_adr_i[15] + NET wbs_adr_i[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 327750 -1200 ) N ;
+ - wbs_adr_i[16] + NET wbs_adr_i[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 345690 -1200 ) N ;
+ - wbs_adr_i[17] + NET wbs_adr_i[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 363170 -1200 ) N ;
+ - wbs_adr_i[18] + NET wbs_adr_i[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 381110 -1200 ) N ;
+ - wbs_adr_i[19] + NET wbs_adr_i[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 398590 -1200 ) N ;
+ - wbs_adr_i[1] + NET wbs_adr_i[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 61870 -1200 ) N ;
+ - wbs_adr_i[20] + NET wbs_adr_i[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 416530 -1200 ) N ;
+ - wbs_adr_i[21] + NET wbs_adr_i[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 434470 -1200 ) N ;
+ - wbs_adr_i[22] + NET wbs_adr_i[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 451950 -1200 ) N ;
+ - wbs_adr_i[23] + NET wbs_adr_i[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 469890 -1200 ) N ;
+ - wbs_adr_i[24] + NET wbs_adr_i[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 487370 -1200 ) N ;
+ - wbs_adr_i[25] + NET wbs_adr_i[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 505310 -1200 ) N ;
+ - wbs_adr_i[26] + NET wbs_adr_i[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 522790 -1200 ) N ;
+ - wbs_adr_i[27] + NET wbs_adr_i[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 540730 -1200 ) N ;
+ - wbs_adr_i[28] + NET wbs_adr_i[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 558210 -1200 ) N ;
+ - wbs_adr_i[29] + NET wbs_adr_i[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 576150 -1200 ) N ;
+ - wbs_adr_i[2] + NET wbs_adr_i[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 85330 -1200 ) N ;
+ - wbs_adr_i[30] + NET wbs_adr_i[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 594090 -1200 ) N ;
+ - wbs_adr_i[31] + NET wbs_adr_i[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 611570 -1200 ) N ;
+ - wbs_adr_i[3] + NET wbs_adr_i[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 109250 -1200 ) N ;
+ - wbs_adr_i[4] + NET wbs_adr_i[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 132710 -1200 ) N ;
+ - wbs_adr_i[5] + NET wbs_adr_i[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 150650 -1200 ) N ;
+ - wbs_adr_i[6] + NET wbs_adr_i[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 168130 -1200 ) N ;
+ - wbs_adr_i[7] + NET wbs_adr_i[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 186070 -1200 ) N ;
+ - wbs_adr_i[8] + NET wbs_adr_i[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 203550 -1200 ) N ;
+ - wbs_adr_i[9] + NET wbs_adr_i[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 221490 -1200 ) N ;
+ - wbs_cyc_i + NET wbs_cyc_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 20470 -1200 ) N ;
+ - wbs_dat_i[0] + NET wbs_dat_i[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 43930 -1200 ) N ;
+ - wbs_dat_i[10] + NET wbs_dat_i[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 244950 -1200 ) N ;
+ - wbs_dat_i[11] + NET wbs_dat_i[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 262890 -1200 ) N ;
+ - wbs_dat_i[12] + NET wbs_dat_i[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 280370 -1200 ) N ;
+ - wbs_dat_i[13] + NET wbs_dat_i[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 298310 -1200 ) N ;
+ - wbs_dat_i[14] + NET wbs_dat_i[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 316250 -1200 ) N ;
+ - wbs_dat_i[15] + NET wbs_dat_i[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 333730 -1200 ) N ;
+ - wbs_dat_i[16] + NET wbs_dat_i[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 351670 -1200 ) N ;
+ - wbs_dat_i[17] + NET wbs_dat_i[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 369150 -1200 ) N ;
+ - wbs_dat_i[18] + NET wbs_dat_i[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 387090 -1200 ) N ;
+ - wbs_dat_i[19] + NET wbs_dat_i[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 404570 -1200 ) N ;
+ - wbs_dat_i[1] + NET wbs_dat_i[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 67850 -1200 ) N ;
+ - wbs_dat_i[20] + NET wbs_dat_i[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 422510 -1200 ) N ;
+ - wbs_dat_i[21] + NET wbs_dat_i[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 439990 -1200 ) N ;
+ - wbs_dat_i[22] + NET wbs_dat_i[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 457930 -1200 ) N ;
+ - wbs_dat_i[23] + NET wbs_dat_i[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 475870 -1200 ) N ;
+ - wbs_dat_i[24] + NET wbs_dat_i[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 493350 -1200 ) N ;
+ - wbs_dat_i[25] + NET wbs_dat_i[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 511290 -1200 ) N ;
+ - wbs_dat_i[26] + NET wbs_dat_i[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 528770 -1200 ) N ;
+ - wbs_dat_i[27] + NET wbs_dat_i[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 546710 -1200 ) N ;
+ - wbs_dat_i[28] + NET wbs_dat_i[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 564190 -1200 ) N ;
+ - wbs_dat_i[29] + NET wbs_dat_i[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 582130 -1200 ) N ;
+ - wbs_dat_i[2] + NET wbs_dat_i[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 91310 -1200 ) N ;
+ - wbs_dat_i[30] + NET wbs_dat_i[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 599610 -1200 ) N ;
+ - wbs_dat_i[31] + NET wbs_dat_i[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 617550 -1200 ) N ;
+ - wbs_dat_i[3] + NET wbs_dat_i[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 115230 -1200 ) N ;
+ - wbs_dat_i[4] + NET wbs_dat_i[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 138690 -1200 ) N ;
+ - wbs_dat_i[5] + NET wbs_dat_i[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 156630 -1200 ) N ;
+ - wbs_dat_i[6] + NET wbs_dat_i[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 174110 -1200 ) N ;
+ - wbs_dat_i[7] + NET wbs_dat_i[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 192050 -1200 ) N ;
+ - wbs_dat_i[8] + NET wbs_dat_i[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 209530 -1200 ) N ;
+ - wbs_dat_i[9] + NET wbs_dat_i[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 227470 -1200 ) N ;
+ - wbs_dat_o[0] + NET wbs_dat_o[0] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 49910 -1200 ) N ;
+ - wbs_dat_o[10] + NET wbs_dat_o[10] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 250930 -1200 ) N ;
+ - wbs_dat_o[11] + NET wbs_dat_o[11] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 268870 -1200 ) N ;
+ - wbs_dat_o[12] + NET wbs_dat_o[12] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 286350 -1200 ) N ;
+ - wbs_dat_o[13] + NET wbs_dat_o[13] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 304290 -1200 ) N ;
+ - wbs_dat_o[14] + NET wbs_dat_o[14] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 321770 -1200 ) N ;
+ - wbs_dat_o[15] + NET wbs_dat_o[15] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 339710 -1200 ) N ;
+ - wbs_dat_o[16] + NET wbs_dat_o[16] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 357650 -1200 ) N ;
+ - wbs_dat_o[17] + NET wbs_dat_o[17] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 375130 -1200 ) N ;
+ - wbs_dat_o[18] + NET wbs_dat_o[18] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 393070 -1200 ) N ;
+ - wbs_dat_o[19] + NET wbs_dat_o[19] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 410550 -1200 ) N ;
+ - wbs_dat_o[1] + NET wbs_dat_o[1] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 73830 -1200 ) N ;
+ - wbs_dat_o[20] + NET wbs_dat_o[20] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 428490 -1200 ) N ;
+ - wbs_dat_o[21] + NET wbs_dat_o[21] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 445970 -1200 ) N ;
+ - wbs_dat_o[22] + NET wbs_dat_o[22] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 463910 -1200 ) N ;
+ - wbs_dat_o[23] + NET wbs_dat_o[23] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 481390 -1200 ) N ;
+ - wbs_dat_o[24] + NET wbs_dat_o[24] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 499330 -1200 ) N ;
+ - wbs_dat_o[25] + NET wbs_dat_o[25] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 516810 -1200 ) N ;
+ - wbs_dat_o[26] + NET wbs_dat_o[26] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 534750 -1200 ) N ;
+ - wbs_dat_o[27] + NET wbs_dat_o[27] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 552690 -1200 ) N ;
+ - wbs_dat_o[28] + NET wbs_dat_o[28] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 570170 -1200 ) N ;
+ - wbs_dat_o[29] + NET wbs_dat_o[29] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 588110 -1200 ) N ;
+ - wbs_dat_o[2] + NET wbs_dat_o[2] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 97290 -1200 ) N ;
+ - wbs_dat_o[30] + NET wbs_dat_o[30] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 605590 -1200 ) N ;
+ - wbs_dat_o[31] + NET wbs_dat_o[31] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 623530 -1200 ) N ;
+ - wbs_dat_o[3] + NET wbs_dat_o[3] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 121210 -1200 ) N ;
+ - wbs_dat_o[4] + NET wbs_dat_o[4] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 144670 -1200 ) N ;
+ - wbs_dat_o[5] + NET wbs_dat_o[5] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 162150 -1200 ) N ;
+ - wbs_dat_o[6] + NET wbs_dat_o[6] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 180090 -1200 ) N ;
+ - wbs_dat_o[7] + NET wbs_dat_o[7] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 198030 -1200 ) N ;
+ - wbs_dat_o[8] + NET wbs_dat_o[8] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 215510 -1200 ) N ;
+ - wbs_dat_o[9] + NET wbs_dat_o[9] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 233450 -1200 ) N ;
+ - wbs_sel_i[0] + NET wbs_sel_i[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 55890 -1200 ) N ;
+ - wbs_sel_i[1] + NET wbs_sel_i[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 79810 -1200 ) N ;
+ - wbs_sel_i[2] + NET wbs_sel_i[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 103270 -1200 ) N ;
+ - wbs_sel_i[3] + NET wbs_sel_i[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 126730 -1200 ) N ;
+ - wbs_stb_i + NET wbs_stb_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 26450 -1200 ) N ;
+ - wbs_we_i + NET wbs_we_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 32430 -1200 ) N ;
+END PINS
+SPECIALNETS 8 ;
+ - vccd1 ( PIN vccd1 ) + USE POWER
+ + ROUTED met4 0 + SHAPE STRIPE ( 1964840 2175880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1811240 2175880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1657640 2175880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1504040 2175880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1350440 2175880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1196840 2175880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1964840 1995880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1811240 1995880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1657640 1995880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1504040 1995880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1350440 1995880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1196840 1995880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1964840 1815880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1811240 1815880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1657640 1815880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1504040 1815880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1350440 1815880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1196840 1815880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 1635880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 1635880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 1635880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 1635880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 1635880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 1635880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 1635880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 1635880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 1635880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 1635880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 1635880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 1635880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 1635880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 1635880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 1635880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 1635880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 1635880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 1635880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 1635880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 1455880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 1455880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 1455880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 1455880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 1455880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 1455880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 1455880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 1455880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 1455880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 1455880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 1455880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 1455880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 1455880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 1455880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 1455880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 1455880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 1455880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 1455880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 1455880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 1275880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 1275880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 1275880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 1275880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 1275880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 1275880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 1275880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 1275880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 1275880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 1275880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 1275880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 1275880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 1275880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 1275880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 1275880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 1275880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 1275880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 1275880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 1275880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 1095880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 1095880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 1095880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 1095880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 1095880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 1095880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 1095880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 1095880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 1095880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 1095880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 1095880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 1095880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 1095880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 1095880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 1095880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 1095880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 1095880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 1095880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 1095880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 915880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 915880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 915880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 915880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 915880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 915880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 915880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 915880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 915880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 915880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 915880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 915880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 915880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 915880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 915880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 915880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 915880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 915880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 915880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 735880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 735880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 735880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 735880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 735880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 735880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 735880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 735880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 735880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 735880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 735880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 735880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 735880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 735880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 735880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 735880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 735880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 735880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 735880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 -3120 ) via4_3100x3100
+ NEW met5 3100 + SHAPE STRIPE ( -10030 3522800 ) ( 2929650 3522800 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 3435880 ) ( 2934450 3435880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 3255880 ) ( 2934450 3255880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 3075880 ) ( 2934450 3075880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2895880 ) ( 2934450 2895880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2715880 ) ( 2934450 2715880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2535880 ) ( 2934450 2535880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2355880 ) ( 2934450 2355880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2175880 ) ( 2934450 2175880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1995880 ) ( 2934450 1995880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1815880 ) ( 2934450 1815880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1635880 ) ( 2934450 1635880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1455880 ) ( 2934450 1455880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1275880 ) ( 2934450 1275880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1095880 ) ( 2934450 1095880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 915880 ) ( 2934450 915880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 735880 ) ( 2934450 735880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 555880 ) ( 2934450 555880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 375880 ) ( 2934450 375880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 195880 ) ( 2934450 195880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 15880 ) ( 2934450 15880 )
+ NEW met5 3100 + SHAPE STRIPE ( -10030 -3120 ) ( 2929650 -3120 )
+ NEW met4 3100 + SHAPE STRIPE ( 2890520 -9470 ) ( 2890520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2710520 -9470 ) ( 2710520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2530520 -9470 ) ( 2530520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2350520 -9470 ) ( 2350520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2170520 -9470 ) ( 2170520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1990520 2300000 ) ( 1990520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1810520 2300000 ) ( 1810520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1630520 2300000 ) ( 1630520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1450520 2300000 ) ( 1450520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1270520 2300000 ) ( 1270520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1090520 -9470 ) ( 1090520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 910520 -9470 ) ( 910520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 730520 -9470 ) ( 730520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 550520 -9470 ) ( 550520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 370520 -9470 ) ( 370520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 190520 -9470 ) ( 190520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 10520 -9470 ) ( 10520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2928100 -4670 ) ( 2928100 3524350 )
+ NEW met4 3100 + SHAPE STRIPE ( -8480 -4670 ) ( -8480 3524350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1990520 -9470 ) ( 1990520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1810520 -9470 ) ( 1810520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1630520 -9470 ) ( 1630520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1450520 -9470 ) ( 1450520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1270520 -9470 ) ( 1270520 1680000 ) ;
+ - vccd2 ( PIN vccd2 ) + USE POWER
+ + ROUTED met4 0 + SHAPE STRIPE ( 2937700 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 -12720 ) via4_3100x3100
+ NEW met5 3100 + SHAPE STRIPE ( -19630 3532400 ) ( 2939250 3532400 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3454480 ) ( 2944050 3454480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3274480 ) ( 2944050 3274480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3094480 ) ( 2944050 3094480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2914480 ) ( 2944050 2914480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2734480 ) ( 2944050 2734480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2554480 ) ( 2944050 2554480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2374480 ) ( 2944050 2374480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2194480 ) ( 2944050 2194480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2014480 ) ( 2944050 2014480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1834480 ) ( 2944050 1834480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1654480 ) ( 2944050 1654480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1474480 ) ( 2944050 1474480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1294480 ) ( 2944050 1294480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1114480 ) ( 2944050 1114480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 934480 ) ( 2944050 934480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 754480 ) ( 2944050 754480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 574480 ) ( 2944050 574480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 394480 ) ( 2944050 394480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 214480 ) ( 2944050 214480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 34480 ) ( 2944050 34480 )
+ NEW met5 3100 + SHAPE STRIPE ( -19630 -12720 ) ( 2939250 -12720 )
+ NEW met4 3100 + SHAPE STRIPE ( 2909120 -19070 ) ( 2909120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2729120 -19070 ) ( 2729120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2549120 -19070 ) ( 2549120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2369120 -19070 ) ( 2369120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2189120 -19070 ) ( 2189120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2009120 2300000 ) ( 2009120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1829120 2300000 ) ( 1829120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1649120 2300000 ) ( 1649120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1469120 2300000 ) ( 1469120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1289120 2300000 ) ( 1289120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1109120 -19070 ) ( 1109120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 929120 -19070 ) ( 929120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 749120 -19070 ) ( 749120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 569120 -19070 ) ( 569120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 389120 -19070 ) ( 389120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 209120 -19070 ) ( 209120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 29120 -19070 ) ( 29120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2937700 -14270 ) ( 2937700 3533950 )
+ NEW met4 3100 + SHAPE STRIPE ( -18080 -14270 ) ( -18080 3533950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2009120 -19070 ) ( 2009120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1829120 -19070 ) ( 1829120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1649120 -19070 ) ( 1649120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1469120 -19070 ) ( 1469120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1289120 -19070 ) ( 1289120 1680000 ) ;
+ - vdda1 ( PIN vdda1 ) + USE POWER
+ + ROUTED met4 0 + SHAPE STRIPE ( 2947300 3542000 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2747720 3542000 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2567720 3542000 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2387720 3542000 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2207720 3542000 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2027720 3542000 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1847720 3542000 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1667720 3542000 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1487720 3542000 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1307720 3542000 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1127720 3542000 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 947720 3542000 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 767720 3542000 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 587720 3542000 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 407720 3542000 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 227720 3542000 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 47720 3542000 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -27680 3542000 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2947300 3473080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2747720 3473080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2567720 3473080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2387720 3473080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2207720 3473080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2027720 3473080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1847720 3473080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1667720 3473080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1487720 3473080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1307720 3473080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1127720 3473080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 947720 3473080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 767720 3473080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 587720 3473080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 407720 3473080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 227720 3473080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 47720 3473080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -27680 3473080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2947300 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2747720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2567720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2387720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2207720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2027720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1847720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1667720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1487720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1307720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1127720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 947720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 767720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 587720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 407720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 227720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 47720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -27680 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2947300 3113080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2747720 3113080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2567720 3113080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2387720 3113080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2207720 3113080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2027720 3113080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1847720 3113080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1667720 3113080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1487720 3113080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1307720 3113080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1127720 3113080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 947720 3113080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 767720 3113080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 587720 3113080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 407720 3113080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 227720 3113080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 47720 3113080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -27680 3113080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2947300 2933080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2747720 2933080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2567720 2933080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2387720 2933080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2207720 2933080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2027720 2933080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1847720 2933080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1667720 2933080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1487720 2933080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1307720 2933080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1127720 2933080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 947720 2933080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 767720 2933080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 587720 2933080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 407720 2933080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 227720 2933080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 47720 2933080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -27680 2933080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2947300 2753080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2747720 2753080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2567720 2753080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2387720 2753080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2207720 2753080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2027720 2753080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1847720 2753080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1667720 2753080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1487720 2753080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1307720 2753080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1127720 2753080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 947720 2753080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 767720 2753080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 587720 2753080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 407720 2753080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 227720 2753080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 47720 2753080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -27680 2753080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2947300 2573080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2747720 2573080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2567720 2573080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2387720 2573080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2207720 2573080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2027720 2573080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1847720 2573080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1667720 2573080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1487720 2573080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1307720 2573080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1127720 2573080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 947720 2573080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 767720 2573080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 587720 2573080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 407720 2573080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 227720 2573080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 47720 2573080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -27680 2573080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2947300 2393080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2747720 2393080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2567720 2393080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2387720 2393080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2207720 2393080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2027720 2393080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1847720 2393080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1667720 2393080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1487720 2393080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1307720 2393080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1127720 2393080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 947720 2393080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 767720 2393080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 587720 2393080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 407720 2393080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 227720 2393080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 47720 2393080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -27680 2393080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2947300 2213080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2747720 2213080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2567720 2213080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2387720 2213080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2207720 2213080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1127720 2213080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 947720 2213080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 767720 2213080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 587720 2213080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 407720 2213080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 227720 2213080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 47720 2213080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -27680 2213080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2947300 2033080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2747720 2033080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2567720 2033080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2387720 2033080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2207720 2033080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1127720 2033080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 947720 2033080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 767720 2033080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 587720 2033080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 407720 2033080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 227720 2033080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 47720 2033080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -27680 2033080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2947300 1853080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2747720 1853080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2567720 1853080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2387720 1853080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2207720 1853080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1127720 1853080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 947720 1853080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 767720 1853080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 587720 1853080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 407720 1853080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 227720 1853080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 47720 1853080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -27680 1853080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2947300 1673080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2747720 1673080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2567720 1673080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2387720 1673080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2207720 1673080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2027720 1673080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1847720 1673080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1667720 1673080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1487720 1673080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1307720 1673080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1127720 1673080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 947720 1673080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 767720 1673080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 587720 1673080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 407720 1673080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 227720 1673080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 47720 1673080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -27680 1673080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2947300 1493080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2747720 1493080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2567720 1493080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2387720 1493080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2207720 1493080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2027720 1493080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1847720 1493080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1667720 1493080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1487720 1493080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1307720 1493080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1127720 1493080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 947720 1493080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 767720 1493080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 587720 1493080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 407720 1493080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 227720 1493080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 47720 1493080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -27680 1493080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2947300 1313080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2747720 1313080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2567720 1313080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2387720 1313080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2207720 1313080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2027720 1313080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1847720 1313080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1667720 1313080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1487720 1313080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1307720 1313080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1127720 1313080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 947720 1313080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 767720 1313080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 587720 1313080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 407720 1313080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 227720 1313080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 47720 1313080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -27680 1313080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2947300 1133080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2747720 1133080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2567720 1133080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2387720 1133080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2207720 1133080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2027720 1133080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1847720 1133080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1667720 1133080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1487720 1133080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1307720 1133080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1127720 1133080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 947720 1133080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 767720 1133080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 587720 1133080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 407720 1133080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 227720 1133080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 47720 1133080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -27680 1133080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2947300 953080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2747720 953080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2567720 953080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2387720 953080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2207720 953080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2027720 953080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1847720 953080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1667720 953080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1487720 953080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1307720 953080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1127720 953080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 947720 953080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 767720 953080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 587720 953080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 407720 953080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 227720 953080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 47720 953080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -27680 953080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2947300 773080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2747720 773080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2567720 773080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2387720 773080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2207720 773080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2027720 773080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1847720 773080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1667720 773080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1487720 773080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1307720 773080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1127720 773080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 947720 773080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 767720 773080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 587720 773080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 407720 773080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 227720 773080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 47720 773080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -27680 773080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2947300 593080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2747720 593080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2567720 593080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2387720 593080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2207720 593080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2027720 593080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1847720 593080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1667720 593080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1487720 593080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1307720 593080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1127720 593080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 947720 593080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 767720 593080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 587720 593080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 407720 593080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 227720 593080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 47720 593080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -27680 593080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2947300 413080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2747720 413080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2567720 413080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2387720 413080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2207720 413080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2027720 413080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1847720 413080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1667720 413080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1487720 413080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1307720 413080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1127720 413080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 947720 413080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 767720 413080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 587720 413080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 407720 413080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 227720 413080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 47720 413080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -27680 413080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2947300 233080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2747720 233080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2567720 233080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2387720 233080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2207720 233080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2027720 233080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1847720 233080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1667720 233080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1487720 233080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1307720 233080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1127720 233080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 947720 233080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 767720 233080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 587720 233080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 407720 233080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 227720 233080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 47720 233080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -27680 233080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2947300 53080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2747720 53080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2567720 53080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2387720 53080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2207720 53080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2027720 53080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1847720 53080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1667720 53080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1487720 53080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1307720 53080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1127720 53080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 947720 53080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 767720 53080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 587720 53080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 407720 53080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 227720 53080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 47720 53080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -27680 53080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2947300 -22320 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2747720 -22320 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2567720 -22320 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2387720 -22320 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2207720 -22320 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2027720 -22320 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1847720 -22320 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1667720 -22320 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1487720 -22320 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1307720 -22320 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1127720 -22320 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 947720 -22320 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 767720 -22320 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 587720 -22320 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 407720 -22320 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 227720 -22320 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 47720 -22320 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -27680 -22320 ) via4_3100x3100
+ NEW met5 3100 + SHAPE STRIPE ( -29230 3542000 ) ( 2948850 3542000 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 3473080 ) ( 2953650 3473080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 3293080 ) ( 2953650 3293080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 3113080 ) ( 2953650 3113080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 2933080 ) ( 2953650 2933080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 2753080 ) ( 2953650 2753080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 2573080 ) ( 2953650 2573080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 2393080 ) ( 2953650 2393080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 2213080 ) ( 2953650 2213080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 2033080 ) ( 2953650 2033080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 1853080 ) ( 2953650 1853080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 1673080 ) ( 2953650 1673080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 1493080 ) ( 2953650 1493080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 1313080 ) ( 2953650 1313080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 1133080 ) ( 2953650 1133080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 953080 ) ( 2953650 953080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 773080 ) ( 2953650 773080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 593080 ) ( 2953650 593080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 413080 ) ( 2953650 413080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 233080 ) ( 2953650 233080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 53080 ) ( 2953650 53080 )
+ NEW met5 3100 + SHAPE STRIPE ( -29230 -22320 ) ( 2948850 -22320 )
+ NEW met4 3100 + SHAPE STRIPE ( 2747720 -28670 ) ( 2747720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2567720 -28670 ) ( 2567720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2387720 -28670 ) ( 2387720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2207720 -28670 ) ( 2207720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2027720 2300000 ) ( 2027720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1847720 2300000 ) ( 1847720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1667720 2300000 ) ( 1667720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1487720 2300000 ) ( 1487720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1307720 2300000 ) ( 1307720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1127720 -28670 ) ( 1127720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 947720 -28670 ) ( 947720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 767720 -28670 ) ( 767720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 587720 -28670 ) ( 587720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 407720 -28670 ) ( 407720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 227720 -28670 ) ( 227720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 47720 -28670 ) ( 47720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2947300 -23870 ) ( 2947300 3543550 )
+ NEW met4 3100 + SHAPE STRIPE ( -27680 -23870 ) ( -27680 3543550 )
+ NEW met4 3100 + SHAPE STRIPE ( 2027720 -28670 ) ( 2027720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1847720 -28670 ) ( 1847720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1667720 -28670 ) ( 1667720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1487720 -28670 ) ( 1487720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1307720 -28670 ) ( 1307720 1680000 ) ;
+ - vdda2 ( PIN vdda2 ) + USE POWER
+ + ROUTED met4 0 + SHAPE STRIPE ( 2956900 3551600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2766320 3551600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2586320 3551600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2406320 3551600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2226320 3551600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2046320 3551600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1866320 3551600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1686320 3551600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1506320 3551600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1326320 3551600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1146320 3551600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 966320 3551600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 786320 3551600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 606320 3551600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 426320 3551600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 246320 3551600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 66320 3551600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -37280 3551600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2956900 3491680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2766320 3491680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2586320 3491680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2406320 3491680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2226320 3491680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2046320 3491680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1866320 3491680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1686320 3491680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1506320 3491680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1326320 3491680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1146320 3491680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 966320 3491680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 786320 3491680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 606320 3491680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 426320 3491680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 246320 3491680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 66320 3491680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -37280 3491680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2956900 3311680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2766320 3311680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2586320 3311680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2406320 3311680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2226320 3311680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2046320 3311680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1866320 3311680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1686320 3311680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1506320 3311680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1326320 3311680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1146320 3311680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 966320 3311680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 786320 3311680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 606320 3311680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 426320 3311680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 246320 3311680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 66320 3311680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -37280 3311680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2956900 3131680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2766320 3131680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2586320 3131680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2406320 3131680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2226320 3131680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2046320 3131680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1866320 3131680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1686320 3131680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1506320 3131680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1326320 3131680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1146320 3131680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 966320 3131680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 786320 3131680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 606320 3131680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 426320 3131680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 246320 3131680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 66320 3131680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -37280 3131680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2956900 2951680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2766320 2951680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2586320 2951680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2406320 2951680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2226320 2951680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2046320 2951680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1866320 2951680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1686320 2951680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1506320 2951680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1326320 2951680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1146320 2951680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 966320 2951680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 786320 2951680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 606320 2951680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 426320 2951680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 246320 2951680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 66320 2951680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -37280 2951680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2956900 2771680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2766320 2771680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2586320 2771680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2406320 2771680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2226320 2771680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2046320 2771680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1866320 2771680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1686320 2771680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1506320 2771680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1326320 2771680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1146320 2771680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 966320 2771680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 786320 2771680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 606320 2771680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 426320 2771680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 246320 2771680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 66320 2771680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -37280 2771680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2956900 2591680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2766320 2591680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2586320 2591680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2406320 2591680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2226320 2591680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2046320 2591680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1866320 2591680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1686320 2591680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1506320 2591680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1326320 2591680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1146320 2591680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 966320 2591680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 786320 2591680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 606320 2591680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 426320 2591680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 246320 2591680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 66320 2591680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -37280 2591680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2956900 2411680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2766320 2411680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2586320 2411680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2406320 2411680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2226320 2411680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2046320 2411680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1866320 2411680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1686320 2411680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1506320 2411680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1326320 2411680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1146320 2411680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 966320 2411680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 786320 2411680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 606320 2411680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 426320 2411680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 246320 2411680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 66320 2411680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -37280 2411680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2956900 2231680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2766320 2231680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2586320 2231680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2406320 2231680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2226320 2231680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1146320 2231680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 966320 2231680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 786320 2231680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 606320 2231680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 426320 2231680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 246320 2231680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 66320 2231680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -37280 2231680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2956900 2051680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2766320 2051680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2586320 2051680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2406320 2051680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2226320 2051680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1146320 2051680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 966320 2051680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 786320 2051680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 606320 2051680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 426320 2051680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 246320 2051680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 66320 2051680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -37280 2051680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2956900 1871680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2766320 1871680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2586320 1871680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2406320 1871680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2226320 1871680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1146320 1871680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 966320 1871680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 786320 1871680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 606320 1871680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 426320 1871680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 246320 1871680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 66320 1871680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -37280 1871680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2956900 1691680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2766320 1691680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2586320 1691680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2406320 1691680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2226320 1691680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1146320 1691680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 966320 1691680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 786320 1691680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 606320 1691680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 426320 1691680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 246320 1691680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 66320 1691680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -37280 1691680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2956900 1511680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2766320 1511680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2586320 1511680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2406320 1511680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2226320 1511680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2046320 1511680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1866320 1511680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1686320 1511680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1506320 1511680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1326320 1511680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1146320 1511680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 966320 1511680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 786320 1511680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 606320 1511680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 426320 1511680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 246320 1511680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 66320 1511680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -37280 1511680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2956900 1331680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2766320 1331680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2586320 1331680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2406320 1331680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2226320 1331680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2046320 1331680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1866320 1331680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1686320 1331680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1506320 1331680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1326320 1331680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1146320 1331680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 966320 1331680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 786320 1331680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 606320 1331680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 426320 1331680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 246320 1331680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 66320 1331680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -37280 1331680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2956900 1151680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2766320 1151680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2586320 1151680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2406320 1151680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2226320 1151680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2046320 1151680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1866320 1151680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1686320 1151680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1506320 1151680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1326320 1151680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1146320 1151680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 966320 1151680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 786320 1151680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 606320 1151680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 426320 1151680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 246320 1151680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 66320 1151680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -37280 1151680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2956900 971680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2766320 971680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2586320 971680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2406320 971680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2226320 971680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2046320 971680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1866320 971680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1686320 971680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1506320 971680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1326320 971680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1146320 971680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 966320 971680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 786320 971680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 606320 971680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 426320 971680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 246320 971680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 66320 971680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -37280 971680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2956900 791680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2766320 791680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2586320 791680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2406320 791680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2226320 791680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2046320 791680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1866320 791680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1686320 791680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1506320 791680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1326320 791680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1146320 791680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 966320 791680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 786320 791680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 606320 791680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 426320 791680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 246320 791680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 66320 791680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -37280 791680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2956900 611680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2766320 611680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2586320 611680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2406320 611680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2226320 611680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2046320 611680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1866320 611680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1686320 611680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1506320 611680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1326320 611680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1146320 611680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 966320 611680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 786320 611680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 606320 611680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 426320 611680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 246320 611680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 66320 611680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -37280 611680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2956900 431680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2766320 431680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2586320 431680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2406320 431680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2226320 431680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2046320 431680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1866320 431680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1686320 431680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1506320 431680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1326320 431680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1146320 431680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 966320 431680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 786320 431680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 606320 431680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 426320 431680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 246320 431680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 66320 431680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -37280 431680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2956900 251680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2766320 251680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2586320 251680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2406320 251680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2226320 251680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2046320 251680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1866320 251680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1686320 251680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1506320 251680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1326320 251680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1146320 251680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 966320 251680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 786320 251680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 606320 251680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 426320 251680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 246320 251680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 66320 251680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -37280 251680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2956900 71680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2766320 71680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2586320 71680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2406320 71680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2226320 71680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2046320 71680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1866320 71680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1686320 71680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1506320 71680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1326320 71680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1146320 71680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 966320 71680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 786320 71680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 606320 71680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 426320 71680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 246320 71680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 66320 71680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -37280 71680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2956900 -31920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2766320 -31920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2586320 -31920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2406320 -31920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2226320 -31920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2046320 -31920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1866320 -31920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1686320 -31920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1506320 -31920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1326320 -31920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1146320 -31920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 966320 -31920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 786320 -31920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 606320 -31920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 426320 -31920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 246320 -31920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 66320 -31920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -37280 -31920 ) via4_3100x3100
+ NEW met5 3100 + SHAPE STRIPE ( -38830 3551600 ) ( 2958450 3551600 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 3491680 ) ( 2963250 3491680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 3311680 ) ( 2963250 3311680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 3131680 ) ( 2963250 3131680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 2951680 ) ( 2963250 2951680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 2771680 ) ( 2963250 2771680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 2591680 ) ( 2963250 2591680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 2411680 ) ( 2963250 2411680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 2231680 ) ( 2963250 2231680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 2051680 ) ( 2963250 2051680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1871680 ) ( 2963250 1871680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1691680 ) ( 2963250 1691680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1511680 ) ( 2963250 1511680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1331680 ) ( 2963250 1331680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1151680 ) ( 2963250 1151680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 971680 ) ( 2963250 971680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 791680 ) ( 2963250 791680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 611680 ) ( 2963250 611680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 431680 ) ( 2963250 431680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 251680 ) ( 2963250 251680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 71680 ) ( 2963250 71680 )
+ NEW met5 3100 + SHAPE STRIPE ( -38830 -31920 ) ( 2958450 -31920 )
+ NEW met4 3100 + SHAPE STRIPE ( 2766320 -38270 ) ( 2766320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2586320 -38270 ) ( 2586320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2406320 -38270 ) ( 2406320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2226320 -38270 ) ( 2226320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2046320 2300000 ) ( 2046320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1866320 2300000 ) ( 1866320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1686320 2300000 ) ( 1686320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1506320 2300000 ) ( 1506320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1326320 2300000 ) ( 1326320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1146320 -38270 ) ( 1146320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 966320 -38270 ) ( 966320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 786320 -38270 ) ( 786320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 606320 -38270 ) ( 606320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 426320 -38270 ) ( 426320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 246320 -38270 ) ( 246320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 66320 -38270 ) ( 66320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2956900 -33470 ) ( 2956900 3553150 )
+ NEW met4 3100 + SHAPE STRIPE ( -37280 -33470 ) ( -37280 3553150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2046320 -38270 ) ( 2046320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1866320 -38270 ) ( 1866320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1686320 -38270 ) ( 1686320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1506320 -38270 ) ( 1506320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1326320 -38270 ) ( 1326320 1680000 ) ;
+ - vssa1 ( PIN vssa1 ) + USE GROUND
+ + ROUTED met4 0 + SHAPE STRIPE ( 2952100 3546800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2837720 3546800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2657720 3546800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2477720 3546800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2297720 3546800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2117720 3546800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1937720 3546800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1757720 3546800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1577720 3546800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1397720 3546800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1217720 3546800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1037720 3546800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 857720 3546800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 677720 3546800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 497720 3546800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 317720 3546800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 137720 3546800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -32480 3546800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2952100 3383080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2837720 3383080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2657720 3383080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2477720 3383080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2297720 3383080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2117720 3383080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1937720 3383080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1757720 3383080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1577720 3383080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1397720 3383080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1217720 3383080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1037720 3383080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 857720 3383080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 677720 3383080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 497720 3383080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 317720 3383080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 137720 3383080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -32480 3383080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2952100 3203080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2837720 3203080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2657720 3203080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2477720 3203080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2297720 3203080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2117720 3203080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1937720 3203080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1757720 3203080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1577720 3203080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1397720 3203080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1217720 3203080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1037720 3203080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 857720 3203080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 677720 3203080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 497720 3203080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 317720 3203080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 137720 3203080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -32480 3203080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2952100 3023080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2837720 3023080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2657720 3023080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2477720 3023080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2297720 3023080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2117720 3023080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1937720 3023080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1757720 3023080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1577720 3023080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1397720 3023080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1217720 3023080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1037720 3023080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 857720 3023080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 677720 3023080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 497720 3023080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 317720 3023080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 137720 3023080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -32480 3023080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2952100 2843080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2837720 2843080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2657720 2843080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2477720 2843080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2297720 2843080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2117720 2843080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1937720 2843080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1757720 2843080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1577720 2843080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1397720 2843080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1217720 2843080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1037720 2843080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 857720 2843080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 677720 2843080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 497720 2843080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 317720 2843080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 137720 2843080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -32480 2843080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2952100 2663080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2837720 2663080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2657720 2663080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2477720 2663080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2297720 2663080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2117720 2663080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1937720 2663080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1757720 2663080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1577720 2663080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1397720 2663080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1217720 2663080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1037720 2663080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 857720 2663080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 677720 2663080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 497720 2663080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 317720 2663080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 137720 2663080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -32480 2663080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2952100 2483080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2837720 2483080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2657720 2483080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2477720 2483080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2297720 2483080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2117720 2483080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1937720 2483080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1757720 2483080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1577720 2483080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1397720 2483080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1217720 2483080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1037720 2483080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 857720 2483080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 677720 2483080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 497720 2483080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 317720 2483080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 137720 2483080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -32480 2483080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2952100 2303080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2837720 2303080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2657720 2303080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2477720 2303080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2297720 2303080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2117720 2303080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1937720 2303080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1757720 2303080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1577720 2303080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1397720 2303080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1217720 2303080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1037720 2303080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 857720 2303080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 677720 2303080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 497720 2303080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 317720 2303080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 137720 2303080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -32480 2303080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2952100 2123080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2837720 2123080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2657720 2123080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2477720 2123080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2297720 2123080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2117720 2123080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1037720 2123080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 857720 2123080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 677720 2123080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 497720 2123080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 317720 2123080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 137720 2123080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -32480 2123080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2952100 1943080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2837720 1943080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2657720 1943080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2477720 1943080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2297720 1943080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2117720 1943080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1037720 1943080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 857720 1943080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 677720 1943080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 497720 1943080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 317720 1943080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 137720 1943080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -32480 1943080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2952100 1763080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2837720 1763080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2657720 1763080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2477720 1763080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2297720 1763080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2117720 1763080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1037720 1763080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 857720 1763080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 677720 1763080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 497720 1763080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 317720 1763080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 137720 1763080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -32480 1763080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2952100 1583080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2837720 1583080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2657720 1583080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2477720 1583080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2297720 1583080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2117720 1583080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1937720 1583080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1757720 1583080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1577720 1583080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1397720 1583080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1217720 1583080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1037720 1583080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 857720 1583080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 677720 1583080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 497720 1583080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 317720 1583080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 137720 1583080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -32480 1583080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2952100 1403080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2837720 1403080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2657720 1403080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2477720 1403080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2297720 1403080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2117720 1403080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1937720 1403080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1757720 1403080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1577720 1403080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1397720 1403080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1217720 1403080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1037720 1403080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 857720 1403080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 677720 1403080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 497720 1403080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 317720 1403080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 137720 1403080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -32480 1403080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2952100 1223080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2837720 1223080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2657720 1223080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2477720 1223080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2297720 1223080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2117720 1223080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1937720 1223080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1757720 1223080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1577720 1223080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1397720 1223080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1217720 1223080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1037720 1223080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 857720 1223080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 677720 1223080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 497720 1223080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 317720 1223080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 137720 1223080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -32480 1223080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2952100 1043080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2837720 1043080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2657720 1043080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2477720 1043080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2297720 1043080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2117720 1043080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1937720 1043080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1757720 1043080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1577720 1043080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1397720 1043080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1217720 1043080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1037720 1043080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 857720 1043080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 677720 1043080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 497720 1043080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 317720 1043080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 137720 1043080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -32480 1043080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2952100 863080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2837720 863080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2657720 863080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2477720 863080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2297720 863080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2117720 863080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1937720 863080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1757720 863080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1577720 863080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1397720 863080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1217720 863080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1037720 863080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 857720 863080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 677720 863080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 497720 863080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 317720 863080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 137720 863080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -32480 863080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2952100 683080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2837720 683080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2657720 683080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2477720 683080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2297720 683080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2117720 683080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1937720 683080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1757720 683080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1577720 683080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1397720 683080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1217720 683080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1037720 683080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 857720 683080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 677720 683080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 497720 683080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 317720 683080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 137720 683080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -32480 683080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2952100 503080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2837720 503080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2657720 503080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2477720 503080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2297720 503080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2117720 503080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1937720 503080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1757720 503080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1577720 503080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1397720 503080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1217720 503080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1037720 503080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 857720 503080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 677720 503080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 497720 503080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 317720 503080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 137720 503080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -32480 503080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2952100 323080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2837720 323080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2657720 323080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2477720 323080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2297720 323080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2117720 323080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1937720 323080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1757720 323080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1577720 323080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1397720 323080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1217720 323080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1037720 323080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 857720 323080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 677720 323080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 497720 323080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 317720 323080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 137720 323080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -32480 323080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2952100 143080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2837720 143080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2657720 143080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2477720 143080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2297720 143080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2117720 143080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1937720 143080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1757720 143080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1577720 143080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1397720 143080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1217720 143080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1037720 143080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 857720 143080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 677720 143080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 497720 143080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 317720 143080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 137720 143080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -32480 143080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2952100 -27120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2837720 -27120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2657720 -27120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2477720 -27120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2297720 -27120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2117720 -27120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1937720 -27120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1757720 -27120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1577720 -27120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1397720 -27120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1217720 -27120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1037720 -27120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 857720 -27120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 677720 -27120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 497720 -27120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 317720 -27120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 137720 -27120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -32480 -27120 ) via4_3100x3100
+ NEW met5 3100 + SHAPE STRIPE ( -34030 3546800 ) ( 2953650 3546800 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 3383080 ) ( 2953650 3383080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 3203080 ) ( 2953650 3203080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 3023080 ) ( 2953650 3023080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 2843080 ) ( 2953650 2843080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 2663080 ) ( 2953650 2663080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 2483080 ) ( 2953650 2483080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 2303080 ) ( 2953650 2303080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 2123080 ) ( 2953650 2123080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 1943080 ) ( 2953650 1943080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 1763080 ) ( 2953650 1763080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 1583080 ) ( 2953650 1583080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 1403080 ) ( 2953650 1403080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 1223080 ) ( 2953650 1223080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 1043080 ) ( 2953650 1043080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 863080 ) ( 2953650 863080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 683080 ) ( 2953650 683080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 503080 ) ( 2953650 503080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 323080 ) ( 2953650 323080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 143080 ) ( 2953650 143080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 -27120 ) ( 2953650 -27120 )
+ NEW met4 3100 + SHAPE STRIPE ( 2952100 -28670 ) ( 2952100 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2837720 -28670 ) ( 2837720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2657720 -28670 ) ( 2657720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2477720 -28670 ) ( 2477720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2297720 -28670 ) ( 2297720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2117720 -28670 ) ( 2117720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1937720 2300000 ) ( 1937720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1757720 2300000 ) ( 1757720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1577720 2300000 ) ( 1577720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1397720 2300000 ) ( 1397720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1217720 2300000 ) ( 1217720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1037720 -28670 ) ( 1037720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 857720 -28670 ) ( 857720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 677720 -28670 ) ( 677720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 497720 -28670 ) ( 497720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 317720 -28670 ) ( 317720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 137720 -28670 ) ( 137720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( -32480 -28670 ) ( -32480 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1937720 -28670 ) ( 1937720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1757720 -28670 ) ( 1757720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1577720 -28670 ) ( 1577720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1397720 -28670 ) ( 1397720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1217720 -28670 ) ( 1217720 1680000 ) ;
+ - vssa2 ( PIN vssa2 ) + USE GROUND
+ + ROUTED met4 0 + SHAPE STRIPE ( 2961700 3556400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2856320 3556400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2676320 3556400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2496320 3556400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2316320 3556400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2136320 3556400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1956320 3556400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1776320 3556400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1596320 3556400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1416320 3556400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1236320 3556400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1056320 3556400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 876320 3556400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 696320 3556400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 516320 3556400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 336320 3556400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 156320 3556400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -42080 3556400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2961700 3401680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2856320 3401680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2676320 3401680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2496320 3401680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2316320 3401680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2136320 3401680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1956320 3401680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1776320 3401680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1596320 3401680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1416320 3401680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1236320 3401680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1056320 3401680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 876320 3401680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 696320 3401680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 516320 3401680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 336320 3401680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 156320 3401680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -42080 3401680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2961700 3221680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2856320 3221680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2676320 3221680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2496320 3221680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2316320 3221680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2136320 3221680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1956320 3221680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1776320 3221680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1596320 3221680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1416320 3221680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1236320 3221680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1056320 3221680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 876320 3221680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 696320 3221680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 516320 3221680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 336320 3221680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 156320 3221680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -42080 3221680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2961700 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2856320 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2676320 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2496320 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2316320 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2136320 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1956320 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1776320 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1596320 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1416320 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1236320 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1056320 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 876320 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 696320 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 516320 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 336320 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 156320 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -42080 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2961700 2861680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2856320 2861680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2676320 2861680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2496320 2861680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2316320 2861680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2136320 2861680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1956320 2861680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1776320 2861680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1596320 2861680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1416320 2861680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1236320 2861680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1056320 2861680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 876320 2861680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 696320 2861680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 516320 2861680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 336320 2861680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 156320 2861680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -42080 2861680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2961700 2681680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2856320 2681680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2676320 2681680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2496320 2681680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2316320 2681680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2136320 2681680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1956320 2681680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1776320 2681680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1596320 2681680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1416320 2681680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1236320 2681680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1056320 2681680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 876320 2681680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 696320 2681680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 516320 2681680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 336320 2681680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 156320 2681680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -42080 2681680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2961700 2501680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2856320 2501680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2676320 2501680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2496320 2501680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2316320 2501680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2136320 2501680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1956320 2501680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1776320 2501680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1596320 2501680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1416320 2501680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1236320 2501680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1056320 2501680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 876320 2501680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 696320 2501680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 516320 2501680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 336320 2501680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 156320 2501680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -42080 2501680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2961700 2321680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2856320 2321680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2676320 2321680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2496320 2321680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2316320 2321680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2136320 2321680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1956320 2321680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1776320 2321680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1596320 2321680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1416320 2321680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1236320 2321680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1056320 2321680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 876320 2321680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 696320 2321680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 516320 2321680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 336320 2321680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 156320 2321680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -42080 2321680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2961700 2141680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2856320 2141680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2676320 2141680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2496320 2141680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2316320 2141680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2136320 2141680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1056320 2141680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 876320 2141680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 696320 2141680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 516320 2141680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 336320 2141680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 156320 2141680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -42080 2141680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2961700 1961680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2856320 1961680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2676320 1961680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2496320 1961680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2316320 1961680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2136320 1961680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1056320 1961680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 876320 1961680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 696320 1961680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 516320 1961680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 336320 1961680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 156320 1961680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -42080 1961680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2961700 1781680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2856320 1781680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2676320 1781680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2496320 1781680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2316320 1781680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2136320 1781680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1056320 1781680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 876320 1781680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 696320 1781680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 516320 1781680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 336320 1781680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 156320 1781680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -42080 1781680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2961700 1601680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2856320 1601680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2676320 1601680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2496320 1601680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2316320 1601680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2136320 1601680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1956320 1601680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1776320 1601680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1596320 1601680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1416320 1601680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1236320 1601680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1056320 1601680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 876320 1601680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 696320 1601680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 516320 1601680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 336320 1601680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 156320 1601680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -42080 1601680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2961700 1421680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2856320 1421680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2676320 1421680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2496320 1421680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2316320 1421680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2136320 1421680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1956320 1421680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1776320 1421680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1596320 1421680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1416320 1421680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1236320 1421680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1056320 1421680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 876320 1421680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 696320 1421680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 516320 1421680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 336320 1421680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 156320 1421680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -42080 1421680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2961700 1241680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2856320 1241680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2676320 1241680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2496320 1241680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2316320 1241680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2136320 1241680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1956320 1241680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1776320 1241680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1596320 1241680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1416320 1241680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1236320 1241680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1056320 1241680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 876320 1241680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 696320 1241680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 516320 1241680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 336320 1241680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 156320 1241680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -42080 1241680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2961700 1061680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2856320 1061680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2676320 1061680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2496320 1061680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2316320 1061680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2136320 1061680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1956320 1061680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1776320 1061680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1596320 1061680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1416320 1061680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1236320 1061680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1056320 1061680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 876320 1061680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 696320 1061680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 516320 1061680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 336320 1061680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 156320 1061680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -42080 1061680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2961700 881680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2856320 881680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2676320 881680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2496320 881680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2316320 881680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2136320 881680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1956320 881680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1776320 881680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1596320 881680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1416320 881680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1236320 881680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1056320 881680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 876320 881680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 696320 881680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 516320 881680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 336320 881680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 156320 881680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -42080 881680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2961700 701680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2856320 701680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2676320 701680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2496320 701680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2316320 701680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2136320 701680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1956320 701680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1776320 701680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1596320 701680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1416320 701680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1236320 701680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1056320 701680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 876320 701680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 696320 701680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 516320 701680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 336320 701680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 156320 701680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -42080 701680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2961700 521680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2856320 521680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2676320 521680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2496320 521680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2316320 521680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2136320 521680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1956320 521680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1776320 521680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1596320 521680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1416320 521680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1236320 521680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1056320 521680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 876320 521680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 696320 521680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 516320 521680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 336320 521680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 156320 521680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -42080 521680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2961700 341680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2856320 341680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2676320 341680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2496320 341680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2316320 341680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2136320 341680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1956320 341680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1776320 341680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1596320 341680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1416320 341680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1236320 341680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1056320 341680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 876320 341680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 696320 341680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 516320 341680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 336320 341680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 156320 341680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -42080 341680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2961700 161680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2856320 161680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2676320 161680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2496320 161680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2316320 161680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2136320 161680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1956320 161680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1776320 161680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1596320 161680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1416320 161680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1236320 161680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1056320 161680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 876320 161680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 696320 161680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 516320 161680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 336320 161680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 156320 161680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -42080 161680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2961700 -36720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2856320 -36720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2676320 -36720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2496320 -36720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2316320 -36720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2136320 -36720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1956320 -36720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1776320 -36720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1596320 -36720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1416320 -36720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1236320 -36720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1056320 -36720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 876320 -36720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 696320 -36720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 516320 -36720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 336320 -36720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 156320 -36720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -42080 -36720 ) via4_3100x3100
+ NEW met5 3100 + SHAPE STRIPE ( -43630 3556400 ) ( 2963250 3556400 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 3401680 ) ( 2963250 3401680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 3221680 ) ( 2963250 3221680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 3041680 ) ( 2963250 3041680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 2861680 ) ( 2963250 2861680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 2681680 ) ( 2963250 2681680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 2501680 ) ( 2963250 2501680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 2321680 ) ( 2963250 2321680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 2141680 ) ( 2963250 2141680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1961680 ) ( 2963250 1961680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1781680 ) ( 2963250 1781680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1601680 ) ( 2963250 1601680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1421680 ) ( 2963250 1421680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1241680 ) ( 2963250 1241680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1061680 ) ( 2963250 1061680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 881680 ) ( 2963250 881680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 701680 ) ( 2963250 701680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 521680 ) ( 2963250 521680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 341680 ) ( 2963250 341680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 161680 ) ( 2963250 161680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 -36720 ) ( 2963250 -36720 )
+ NEW met4 3100 + SHAPE STRIPE ( 2961700 -38270 ) ( 2961700 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2856320 -38270 ) ( 2856320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2676320 -38270 ) ( 2676320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2496320 -38270 ) ( 2496320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2316320 -38270 ) ( 2316320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2136320 -38270 ) ( 2136320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1956320 2300000 ) ( 1956320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1776320 2300000 ) ( 1776320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1596320 2300000 ) ( 1596320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1416320 2300000 ) ( 1416320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1236320 2300000 ) ( 1236320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1056320 -38270 ) ( 1056320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 876320 -38270 ) ( 876320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 696320 -38270 ) ( 696320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 516320 -38270 ) ( 516320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 336320 -38270 ) ( 336320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 156320 -38270 ) ( 156320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( -42080 -38270 ) ( -42080 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1956320 -38270 ) ( 1956320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1776320 -38270 ) ( 1776320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1596320 -38270 ) ( 1596320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1416320 -38270 ) ( 1416320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1236320 -38270 ) ( 1236320 1680000 ) ;
+ - vssd1 ( PIN vssd1 ) + USE GROUND
+ + ROUTED met4 0 + SHAPE STRIPE ( 2041640 2265880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1888040 2265880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1734440 2265880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1580840 2265880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1427240 2265880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1273640 2265880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 2041640 2085880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1888040 2085880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1734440 2085880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1580840 2085880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1427240 2085880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1273640 2085880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 2041640 1905880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1888040 1905880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1734440 1905880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1580840 1905880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1427240 1905880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1273640 1905880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 2041640 1725880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1888040 1725880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1734440 1725880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1580840 1725880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1427240 1725880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1273640 1725880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 3527600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 3527600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 3527600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 3527600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 3527600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 3527600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 3527600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 3527600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 3527600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 3527600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 3527600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 3527600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 3527600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 3527600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 3527600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 3527600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 3527600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 3527600 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 3345880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 3345880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 3345880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 3345880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 3345880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 3345880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 3345880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 3345880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 3345880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 3345880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 3345880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 3345880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 3345880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 3345880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 3345880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 3345880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 3345880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 3345880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 3165880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 3165880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 3165880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 3165880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 3165880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 3165880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 3165880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 3165880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 3165880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 3165880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 3165880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 3165880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 3165880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 3165880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 3165880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 3165880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 3165880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 3165880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 2985880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 2985880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 2985880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 2985880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 2985880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 2985880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 2985880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 2985880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 2985880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 2985880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 2985880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 2985880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 2985880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 2985880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 2985880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 2985880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 2985880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 2985880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 2805880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 2805880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 2805880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 2805880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 2805880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 2805880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 2805880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 2805880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 2805880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 2805880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 2805880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 2805880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 2805880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 2805880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 2805880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 2805880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 2805880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 2805880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 2625880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 2625880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 2625880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 2625880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 2625880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 2625880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 2625880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 2625880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 2625880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 2625880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 2625880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 2625880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 2625880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 2625880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 2625880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 2625880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 2625880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 2625880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 2265880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 2265880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 2265880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 2265880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 2265880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 2265880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 2265880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 2265880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 2265880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 2265880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 2265880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 2265880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 2085880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 2085880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 2085880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 2085880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 2085880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 2085880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 2085880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 2085880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 2085880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 2085880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 2085880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 2085880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 1905880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 1905880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 1905880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 1905880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 1905880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 1905880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 1905880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 1905880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 1905880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 1905880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 1905880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 1905880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 1725880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 1725880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 1725880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 1725880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 1725880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 1725880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 1725880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 1725880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 1725880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 1725880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 1725880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 1725880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 -7920 ) via4_3100x3100
+ NEW met5 3100 + SHAPE STRIPE ( -14830 3527600 ) ( 2934450 3527600 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 3345880 ) ( 2934450 3345880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 3165880 ) ( 2934450 3165880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2985880 ) ( 2934450 2985880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2805880 ) ( 2934450 2805880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2625880 ) ( 2934450 2625880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2445880 ) ( 2934450 2445880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2265880 ) ( 2934450 2265880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2085880 ) ( 2934450 2085880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1905880 ) ( 2934450 1905880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1725880 ) ( 2934450 1725880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1545880 ) ( 2934450 1545880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1365880 ) ( 2934450 1365880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1185880 ) ( 2934450 1185880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1005880 ) ( 2934450 1005880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 825880 ) ( 2934450 825880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 645880 ) ( 2934450 645880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 465880 ) ( 2934450 465880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 285880 ) ( 2934450 285880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 105880 ) ( 2934450 105880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 -7920 ) ( 2934450 -7920 )
+ NEW met4 3100 + SHAPE STRIPE ( 2932900 -9470 ) ( 2932900 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2800520 -9470 ) ( 2800520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2620520 -9470 ) ( 2620520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2440520 -9470 ) ( 2440520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2260520 -9470 ) ( 2260520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2080520 2300000 ) ( 2080520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1900520 2300000 ) ( 1900520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1720520 2300000 ) ( 1720520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1540520 2300000 ) ( 1540520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1360520 2300000 ) ( 1360520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1180520 2300000 ) ( 1180520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1000520 -9470 ) ( 1000520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 820520 -9470 ) ( 820520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 640520 -9470 ) ( 640520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 460520 -9470 ) ( 460520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 280520 -9470 ) ( 280520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 100520 -9470 ) ( 100520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( -13280 -9470 ) ( -13280 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2080520 -9470 ) ( 2080520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1900520 -9470 ) ( 1900520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1720520 -9470 ) ( 1720520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1540520 -9470 ) ( 1540520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1360520 -9470 ) ( 1360520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1180520 -9470 ) ( 1180520 1680000 ) ;
+ - vssd2 ( PIN vssd2 ) + USE GROUND
+ + ROUTED met4 0 + SHAPE STRIPE ( 2942500 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 2284480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 2284480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 2284480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 2284480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 2284480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 2284480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 2284480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 2284480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 2284480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 2284480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 2284480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 2284480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 2284480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 2104480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 2104480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 2104480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 2104480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 2104480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 2104480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 2104480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 2104480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 2104480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 2104480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 2104480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 2104480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 2104480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 1924480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 1924480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 1924480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 1924480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 1924480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 1924480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 1924480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 1924480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 1924480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 1924480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 1924480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 1924480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 1924480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 1744480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 1744480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 1744480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 1744480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 1744480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 1744480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 1744480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 1744480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 1744480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 1744480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 1744480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 1744480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 1744480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 -17520 ) via4_3100x3100
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3537200 ) ( 2944050 3537200 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3364480 ) ( 2944050 3364480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3184480 ) ( 2944050 3184480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3004480 ) ( 2944050 3004480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2824480 ) ( 2944050 2824480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2644480 ) ( 2944050 2644480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2464480 ) ( 2944050 2464480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2284480 ) ( 2944050 2284480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2104480 ) ( 2944050 2104480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1924480 ) ( 2944050 1924480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1744480 ) ( 2944050 1744480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1564480 ) ( 2944050 1564480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1384480 ) ( 2944050 1384480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1204480 ) ( 2944050 1204480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1024480 ) ( 2944050 1024480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 844480 ) ( 2944050 844480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 664480 ) ( 2944050 664480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 484480 ) ( 2944050 484480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 304480 ) ( 2944050 304480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 124480 ) ( 2944050 124480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 -17520 ) ( 2944050 -17520 )
+ NEW met4 3100 + SHAPE STRIPE ( 2942500 -19070 ) ( 2942500 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2819120 -19070 ) ( 2819120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2639120 -19070 ) ( 2639120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2459120 -19070 ) ( 2459120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2279120 -19070 ) ( 2279120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2099120 -19070 ) ( 2099120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1919120 2300000 ) ( 1919120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1739120 2300000 ) ( 1739120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1559120 2300000 ) ( 1559120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1379120 2300000 ) ( 1379120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1199120 2300000 ) ( 1199120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1019120 -19070 ) ( 1019120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 839120 -19070 ) ( 839120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 659120 -19070 ) ( 659120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 479120 -19070 ) ( 479120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 299120 -19070 ) ( 299120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 119120 -19070 ) ( 119120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( -22880 -19070 ) ( -22880 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1919120 -19070 ) ( 1919120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1739120 -19070 ) ( 1739120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1559120 -19070 ) ( 1559120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1379120 -19070 ) ( 1379120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1199120 -19070 ) ( 1199120 1680000 ) ;
+END SPECIALNETS
+END DESIGN
diff --git a/openlane/user_project_wrapper/fixed_dont_change/wb_port.txt b/openlane/user_project_wrapper/fixed_dont_change/wb_port.txt
new file mode 100644
index 0000000..b801c10
--- /dev/null
+++ b/openlane/user_project_wrapper/fixed_dont_change/wb_port.txt
@@ -0,0 +1,106 @@
+2990 wb_clk_i
+8510 wb_rst_i
+14490 wbs_ack_o
+38410 wbs_adr_i[0]
+61870 wbs_adr_i[1]
+85330 wbs_adr_i[2]
+239430 wbs_adr_i[10]
+256910 wbs_adr_i[11]
+274850 wbs_adr_i[12]
+292330 wbs_adr_i[13]
+310270 wbs_adr_i[14]
+327750 wbs_adr_i[15]
+345690 wbs_adr_i[16]
+363170 wbs_adr_i[17]
+381110 wbs_adr_i[18]
+398590 wbs_adr_i[19]
+416530 wbs_adr_i[20]
+434470 wbs_adr_i[21]
+451950 wbs_adr_i[22]
+469890 wbs_adr_i[23]
+487370 wbs_adr_i[24]
+505310 wbs_adr_i[25]
+522790 wbs_adr_i[26]
+540730 wbs_adr_i[27]
+558210 wbs_adr_i[28]
+576150 wbs_adr_i[29]
+594090 wbs_adr_i[30]
+611570 wbs_adr_i[31]
+109250 wbs_adr_i[3]
+132710 wbs_adr_i[4]
+150650 wbs_adr_i[5]
+168130 wbs_adr_i[6]
+186070 wbs_adr_i[7]
+203550 wbs_adr_i[8]
+221490 wbs_adr_i[9]
+20470 wbs_cyc_i
+43930 wbs_dat_i[0]
+244950 wbs_dat_i[10]
+262890 wbs_dat_i[11]
+280370 wbs_dat_i[12]
+298310 wbs_dat_i[13]
+316250 wbs_dat_i[14]
+333730 wbs_dat_i[15]
+351670 wbs_dat_i[16]
+369150 wbs_dat_i[17]
+387090 wbs_dat_i[18]
+404570 wbs_dat_i[19]
+67850 wbs_dat_i[1]
+422510 wbs_dat_i[20]
+439990 wbs_dat_i[21]
+457930 wbs_dat_i[22]
+475870 wbs_dat_i[23]
+493350 wbs_dat_i[24]
+511290 wbs_dat_i[25]
+528770 wbs_dat_i[26]
+546710 wbs_dat_i[27]
+564190 wbs_dat_i[28]
+582130 wbs_dat_i[29]
+91310 wbs_dat_i[2]
+599610 wbs_dat_i[30]
+617550 wbs_dat_i[31]
+115230 wbs_dat_i[3]
+138690 wbs_dat_i[4]
+156630 wbs_dat_i[5]
+174110 wbs_dat_i[6]
+192050 wbs_dat_i[7]
+209530 wbs_dat_i[8]
+227470 wbs_dat_i[9]
+49910 wbs_dat_o[0]
+250930 wbs_dat_o[10]
+268870 wbs_dat_o[11]
+286350 wbs_dat_o[12]
+304290 wbs_dat_o[13]
+321770 wbs_dat_o[14]
+339710 wbs_dat_o[15]
+357650 wbs_dat_o[16]
+375130 wbs_dat_o[17]
+393070 wbs_dat_o[18]
+410550 wbs_dat_o[19]
+73830 wbs_dat_o[1]
+428490 wbs_dat_o[20]
+445970 wbs_dat_o[21]
+463910 wbs_dat_o[22]
+481390 wbs_dat_o[23]
+499330 wbs_dat_o[24]
+516810 wbs_dat_o[25]
+534750 wbs_dat_o[26]
+552690 wbs_dat_o[27]
+570170 wbs_dat_o[28]
+588110 wbs_dat_o[29]
+97290 wbs_dat_o[2]
+605590 wbs_dat_o[30]
+623530 wbs_dat_o[31]
+121210 wbs_dat_o[3]
+144670 wbs_dat_o[4]
+162150 wbs_dat_o[5]
+180090 wbs_dat_o[6]
+198030 wbs_dat_o[7]
+215510 wbs_dat_o[8]
+233450 wbs_dat_o[9]
+55890 wbs_sel_i[0]
+79810 wbs_sel_i[1]
+103270 wbs_sel_i[2]
+126730 wbs_sel_i[3]
+26450 wbs_stb_i
+32430 wbs_we_i
diff --git a/openlane/user_project_wrapper/fixed_dont_change/wb_port_uniq.txt b/openlane/user_project_wrapper/fixed_dont_change/wb_port_uniq.txt
new file mode 100644
index 0000000..9d55edd
--- /dev/null
+++ b/openlane/user_project_wrapper/fixed_dont_change/wb_port_uniq.txt
@@ -0,0 +1,106 @@
+2990 wb_clk_i
+8510 wb_rst_i
+14490 wbs_ack_o
+20470 wbs_cyc_i
+26450 wbs_stb_i
+32430 wbs_we_i
+38410 wbs_adr_i[0]
+43930 wbs_dat_i[0]
+49910 wbs_dat_o[0]
+55890 wbs_sel_i[0]
+61870 wbs_adr_i[1]
+67850 wbs_dat_i[1]
+73830 wbs_dat_o[1]
+79810 wbs_sel_i[1]
+85330 wbs_adr_i[2]
+91310 wbs_dat_i[2]
+97290 wbs_dat_o[2]
+103270 wbs_sel_i[2]
+109250 wbs_adr_i[3]
+115230 wbs_dat_i[3]
+121210 wbs_dat_o[3]
+126730 wbs_sel_i[3]
+132710 wbs_adr_i[4]
+138690 wbs_dat_i[4]
+144670 wbs_dat_o[4]
+150650 wbs_adr_i[5]
+156630 wbs_dat_i[5]
+162150 wbs_dat_o[5]
+168130 wbs_adr_i[6]
+174110 wbs_dat_i[6]
+180090 wbs_dat_o[6]
+186070 wbs_adr_i[7]
+192050 wbs_dat_i[7]
+198030 wbs_dat_o[7]
+203550 wbs_adr_i[8]
+209530 wbs_dat_i[8]
+215510 wbs_dat_o[8]
+221490 wbs_adr_i[9]
+227470 wbs_dat_i[9]
+233450 wbs_dat_o[9]
+239430 wbs_adr_i[10]
+244950 wbs_dat_i[10]
+250930 wbs_dat_o[10]
+256910 wbs_adr_i[11]
+262890 wbs_dat_i[11]
+268870 wbs_dat_o[11]
+274850 wbs_adr_i[12]
+280370 wbs_dat_i[12]
+286350 wbs_dat_o[12]
+292330 wbs_adr_i[13]
+298310 wbs_dat_i[13]
+304290 wbs_dat_o[13]
+310270 wbs_adr_i[14]
+316250 wbs_dat_i[14]
+321770 wbs_dat_o[14]
+327750 wbs_adr_i[15]
+333730 wbs_dat_i[15]
+339710 wbs_dat_o[15]
+345690 wbs_adr_i[16]
+351670 wbs_dat_i[16]
+357650 wbs_dat_o[16]
+363170 wbs_adr_i[17]
+369150 wbs_dat_i[17]
+375130 wbs_dat_o[17]
+381110 wbs_adr_i[18]
+387090 wbs_dat_i[18]
+393070 wbs_dat_o[18]
+398590 wbs_adr_i[19]
+404570 wbs_dat_i[19]
+410550 wbs_dat_o[19]
+416530 wbs_adr_i[20]
+422510 wbs_dat_i[20]
+428490 wbs_dat_o[20]
+434470 wbs_adr_i[21]
+439990 wbs_dat_i[21]
+445970 wbs_dat_o[21]
+451950 wbs_adr_i[22]
+457930 wbs_dat_i[22]
+463910 wbs_dat_o[22]
+469890 wbs_adr_i[23]
+475870 wbs_dat_i[23]
+481390 wbs_dat_o[23]
+487370 wbs_adr_i[24]
+493350 wbs_dat_i[24]
+499330 wbs_dat_o[24]
+505310 wbs_adr_i[25]
+511290 wbs_dat_i[25]
+516810 wbs_dat_o[25]
+522790 wbs_adr_i[26]
+528770 wbs_dat_i[26]
+534750 wbs_dat_o[26]
+540730 wbs_adr_i[27]
+546710 wbs_dat_i[27]
+552690 wbs_dat_o[27]
+558210 wbs_adr_i[28]
+564190 wbs_dat_i[28]
+570170 wbs_dat_o[28]
+576150 wbs_adr_i[29]
+582130 wbs_dat_i[29]
+588110 wbs_dat_o[29]
+594090 wbs_adr_i[30]
+599610 wbs_dat_i[30]
+605590 wbs_dat_o[30]
+611570 wbs_adr_i[31]
+617550 wbs_dat_i[31]
+623530 wbs_dat_o[31]
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl
new file mode 100644
index 0000000..1f6639d
--- /dev/null
+++ b/openlane/user_project_wrapper/interactive.tcl
@@ -0,0 +1,346 @@
+#!/usr/bin/env tclsh
+# Copyright 2020-2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+package require openlane; # provides the utils as well
+
+proc run_placement_step {args} {
+ if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
+ set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
+ }
+
+ run_placement
+}
+
+proc run_cts_step {args} {
+ if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
+ set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
+ }
+
+ run_cts
+ run_resizer_timing
+}
+
+proc run_routing_step {args} {
+ if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
+ set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
+ }
+ if { $::env(ECO_ENABLE) == 0 } {
+ run_routing
+ }
+}
+
+proc run_parasitics_sta_step {args} {
+ if { ! [ info exists ::env(PARSITICS_CURRENT_DEF) ] } {
+ set ::env(PARSITICS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PARSITICS_CURRENT_DEF)
+ }
+
+ if { $::env(RUN_SPEF_EXTRACTION) && ($::env(ECO_ENABLE) == 0)} {
+ run_parasitics_sta
+ }
+}
+
+proc run_diode_insertion_2_5_step {args} {
+ if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
+ set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
+ }
+ if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+ run_antenna_check
+ heal_antenna_violators; # modifies the routed DEF
+ }
+
+}
+
+proc run_irdrop_report_step {args} {
+ if { $::env(RUN_IRDROP_REPORT) } {
+ run_irdrop_report
+ }
+}
+
+proc run_lvs_step {{ lvs_enabled 1 }} {
+ if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
+ set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
+ }
+
+ if { $lvs_enabled && $::env(RUN_LVS) } {
+ run_magic_spice_export;
+ run_lvs; # requires run_magic_spice_export
+ }
+
+}
+
+proc run_drc_step {{ drc_enabled 1 }} {
+ if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
+ set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
+ }
+ if { $drc_enabled } {
+ if { $::env(RUN_MAGIC_DRC) } {
+ run_magic_drc
+ }
+ if {$::env(RUN_KLAYOUT_DRC)} {
+ run_klayout_drc
+ }
+ }
+}
+
+proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
+ if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
+ set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
+ }
+ if { $antenna_check_enabled } {
+ run_antenna_check
+ }
+}
+
+proc run_eco_step {args} {
+ if { $::env(ECO_ENABLE) == 1 } {
+ run_eco_flow
+ }
+}
+
+proc run_magic_step {args} {
+ if {$::env(RUN_MAGIC)} {
+ run_magic
+ }
+}
+
+proc run_klayout_step {args} {
+ if {$::env(RUN_KLAYOUT)} {
+ run_klayout
+ }
+ if {$::env(RUN_KLAYOUT_XOR)} {
+ run_klayout_gds_xor
+ }
+}
+
+proc run_post_run_hooks {} {
+ if { [file exists $::env(DESIGN_DIR)/hooks/post_run.py]} {
+ puts_info "Running post run hook"
+ set result [exec $::env(OPENROAD_BIN) -python $::env(DESIGN_DIR)/hooks/post_run.py]
+ puts_info "$result"
+ } else {
+ puts_info "hooks/post_run.py not found, skipping"
+ }
+}
+
+proc run_magic_drc_batch {args} {
+ set options {
+ {-magicrc optional}
+ {-tech optional}
+ {-report required}
+ {-design required}
+ {-gds required}
+ }
+ set flags {}
+ parse_key_args "run_magic_drc_batch" args arg_values $options flags_mag $flags
+ if { [info exists arg_values(-magicrc)] } {
+ set magicrc [file normalize $arg_values(-magicrc)]
+ }
+ if { [info exists arg_values(-tech)] } {
+ set ::env(TECH) [file normalize $arg_values(-tech)]
+ }
+ set ::env(GDS_INPUT) [file normalize $arg_values(-gds)]
+ set ::env(REPORT_OUTPUT) [file normalize $arg_values(-report)]
+ set ::env(DESIGN_NAME) $arg_values(-design)
+
+ if { [info exists magicrc] } {
+ exec magic \
+ -noconsole \
+ -dnull \
+ -rcfile $magicrc \
+ $::env(OPENLANE_ROOT)/scripts/magic/drc_batch.tcl \
+ </dev/null |& tee /dev/tty
+ } else {
+ exec magic \
+ -noconsole \
+ -dnull \
+ $::env(OPENLANE_ROOT)/scripts/magic/drc_batch.tcl \
+ </dev/null |& tee /dev/tty
+ }
+}
+
+proc run_lvs_batch {args} {
+ # runs device level lvs on -gds/CURRENT_GDS and -net/CURRENT_NETLIST
+ # extracts gds only if EXT_NETLIST does not exist
+ set options {
+ {-design required}
+ {-gds optional}
+ {-net optional}
+ }
+ set flags {}
+ parse_key_args "run_lvs_batch" args arg_values $options flags_lvs $flags -no_consume
+
+ prep {*}$args
+
+ if { [info exists arg_values(-gds)] } {
+ set ::env(CURRENT_GDS) [file normalize $arg_values(-gds)]
+ } else {
+ set ::env(CURRENT_GDS) $::env(signoff_results)/$::env(DESIGN_NAME).gds
+ }
+ if { [info exists arg_values(-net)] } {
+ set ::env(CURRENT_NETLIST) [file normalize $arg_values(-net)]
+ }
+
+ assert_files_exist "$::env(CURRENT_GDS) $::env(CURRENT_NETLIST)"
+
+ set ::env(MAGIC_EXT_USE_GDS) 1
+ set ::env(EXT_NETLIST) $::env(signoff_results)/$::env(DESIGN_NAME).gds.spice
+ if { [file exists $::env(EXT_NETLIST)] } {
+ puts_warn "The file $::env(EXT_NETLIST) will be used. If you would like the file re-exported, please delete it."
+ } else {
+ run_magic_spice_export
+ }
+
+ run_lvs
+}
+
+
+proc run_file {args} {
+ set ::env(TCLLIBPATH) $::auto_path
+ exec tclsh {*}$args >&@stdout
+}
+
+
+
+proc run_flow {args} {
+ set options {
+ {-design optional}
+ {-from optional}
+ {-to optional}
+ {-save_path optional}
+ {-override_env optional}
+ }
+ set flags {-save -run_hooks -no_lvs -no_drc -no_antennacheck -gui}
+ parse_key_args "run_non_interactive_mode" args arg_values $options flags_map $flags -no_consume
+
+ prep {*}$args
+ # signal trap SIGINT save_state;
+
+ if { [info exists flags_map(-gui)] } {
+ or_gui
+ return
+ }
+ if { [info exists arg_values(-override_env)] } {
+ load_overrides $arg_values(-override_env)
+ }
+
+ set LVS_ENABLED 1
+ set DRC_ENABLED 0
+
+ set ANTENNACHECK_ENABLED [expr ![info exists flags_map(-no_antennacheck)] ]
+
+ set steps [dict create \
+ "synthesis" "run_synthesis" \
+ "floorplan" "run_floorplan" \
+ "placement" "run_placement_step" \
+ "cts" "run_cts_step" \
+ "routing" "run_routing_step" \
+ "parasitics_sta" "run_parasitics_sta_step" \
+ "eco" "run_eco_step" \
+ "diode_insertion" "run_diode_insertion_2_5_step" \
+ "irdrop" "run_irdrop_report_step" \
+ "gds_magic" "run_magic_step" \
+ "gds_klayout" "run_klayout_step" \
+ "lvs" "run_lvs_step $LVS_ENABLED " \
+ "drc" "run_drc_step $DRC_ENABLED " \
+ "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED " \
+ "cvc" "run_lef_cvc"
+ ]
+
+ if { [info exists arg_values(-from) ]} {
+ puts_info "Starting flow at $arg_values(-from)..."
+ set ::env(CURRENT_STEP) $arg_values(-from)
+ } elseif { [info exists ::env(CURRENT_STEP) ] } {
+ puts_info "Resuming flow from $::env(CURRENT_STEP)..."
+ } else {
+ set ::env(CURRENT_STEP) "synthesis"
+ }
+
+ set_if_unset arg_values(-from) $::env(CURRENT_STEP)
+ set_if_unset arg_values(-to) "cvc"
+
+ set exe 0;
+ dict for {step_name step_exe} $steps {
+ if { [ string equal $arg_values(-from) $step_name ] } {
+ set exe 1;
+ }
+
+ if { $exe } {
+ # For when it fails
+ set ::env(CURRENT_STEP) $step_name
+ [lindex $step_exe 0] [lindex $step_exe 1] ;
+ }
+
+ if { [ string equal $arg_values(-to) $step_name ] } {
+ set exe 0:
+ break;
+ }
+
+ }
+
+ # for when it resumes
+ set steps_as_list [dict keys $steps]
+ set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
+ set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
+
+ # Saves to <RUN_DIR>/results/final
+ save_final_views
+
+ # Saves to design directory or custom
+ if { [info exists flags_map(-save) ] } {
+ if { ! [info exists arg_values(-save_path)] } {
+ set arg_values(-save_path) $::env(DESIGN_DIR)
+ }
+ save_final_views\
+ -save_path $arg_values(-save_path)\
+ -tag $::env(RUN_TAG)
+ }
+ calc_total_runtime
+ save_state
+ generate_final_summary_report
+
+ check_timing_violations
+
+ if { [info exists arg_values(-save_path)]\
+ && $arg_values(-save_path) != "" } {
+ set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]"
+ } else {
+ set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final
+ }
+
+ if {[info exists flags_map(-run_hooks)]} {
+ run_post_run_hooks
+ }
+
+ puts_success "Flow complete."
+
+ show_warnings "Note that the following warnings have been generated:"
+}
+
+run_flow {*}$argv
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
new file mode 100644
index 0000000..a66f27d
--- /dev/null
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -0,0 +1,21 @@
+u_wb_host 1200 325 N
+u_glbl 800 800 N
+u_mbist5 800 1300 N
+u_mbist6 800 1800 N
+u_mbist7 800 2400 N
+u_mbist8 800 3000 N
+u_sram5_1kb 200 1200 N
+u_sram6_1kb 200 1800 N
+u_sram7_1kb 200 2400 N
+u_sram8_1kb 200 3000 N
+
+u_intercon 1200 800 N
+u_mbist1 1600 800 N
+u_mbist2 1600 1400 N
+u_mbist3 1600 2000 N
+u_mbist4 1600 2600 N
+
+u_sram1_2kb 2000 800 N
+u_sram2_2kb 2000 1400 N
+u_sram3_2kb 2000 2000 N
+u_sram4_2kb 2000 2600 N
diff --git a/openlane/user_project_wrapper/pdn_cfg.tcl b/openlane/user_project_wrapper/pdn_cfg.tcl
new file mode 100644
index 0000000..1bf35f4
--- /dev/null
+++ b/openlane/user_project_wrapper/pdn_cfg.tcl
@@ -0,0 +1,168 @@
+# Power nets
+if { [info exists ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS)] } {
+ if { $::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) == 1 } {
+ foreach power_pin $::env(STD_CELL_POWER_PINS) {
+ add_global_connection \
+ -net $::env(VDD_NET) \
+ -inst_pattern .* \
+ -pin_pattern $power_pin \
+ -power
+ }
+ foreach ground_pin $::env(STD_CELL_GROUND_PINS) {
+ add_global_connection \
+ -net $::env(GND_NET) \
+ -inst_pattern .* \
+ -pin_pattern $ground_pin \
+ -ground
+ }
+ }
+}
+
+if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1 &&
+ [info exists ::env(FP_PDN_MACRO_HOOKS)]} {
+ set pdn_hooks [split $::env(FP_PDN_MACRO_HOOKS) ","]
+ foreach pdn_hook $pdn_hooks {
+ set instance_name [lindex $pdn_hook 0]
+ set power_net [lindex $pdn_hook 1]
+ set ground_net [lindex $pdn_hook 2]
+ set power_pin [lindex $pdn_hook 3]
+ set ground_pin [lindex $pdn_hook 4]
+
+ if { $power_pin == "" || $ground_pin == "" } {
+ puts "FP_PDN_MACRO_HOOKS missing power and ground pin names"
+ exit -1
+ }
+
+ add_global_connection \
+ -net $power_net \
+ -inst_pattern $instance_name \
+ -pin_pattern $power_pin \
+ -power
+
+ add_global_connection \
+ -net $ground_net \
+ -inst_pattern $instance_name \
+ -pin_pattern $ground_pin \
+ -ground
+ }
+}
+
+set secondary []
+
+foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
+ if { $vdd != $::env(VDD_NET)} {
+ lappend secondary $vdd
+
+ set db_net [[ord::get_db_block] findNet $vdd]
+ if {$db_net == "NULL"} {
+ set net [odb::dbNet_create [ord::get_db_block] $vdd]
+ $net setSpecial
+ $net setSigType "POWER"
+ }
+ }
+
+ if { $gnd != $::env(GND_NET)} {
+ lappend secondary $gnd
+
+ set db_net [[ord::get_db_block] findNet $gnd]
+ if {$db_net == "NULL"} {
+ set net [odb::dbNet_create [ord::get_db_block] $gnd]
+ $net setSpecial
+ $net setSigType "GROUND"
+ }
+ }
+}
+
+set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \
+ -secondary_power $secondary
+
+# Assesses whether the design is the core of the chip or not based on the
+# value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section
+if { $::env(DESIGN_IS_CORE) == 1 } {
+ # Used if the design is the core of the chip
+ define_pdn_grid \
+ -name stdcell_grid \
+ -starts_with POWER \
+ -voltage_domain CORE \
+ -pins "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
+
+ add_pdn_stripe \
+ -grid stdcell_grid \
+ -layer $::env(FP_PDN_LOWER_LAYER) \
+ -width $::env(FP_PDN_VWIDTH) \
+ -pitch $::env(FP_PDN_VPITCH) \
+ -offset $::env(FP_PDN_VOFFSET) \
+ -spacing $::env(FP_PDN_VSPACING) \
+ -nets "$::env(PDN_STRIPE)" \
+ -starts_with POWER -extend_to_core_ring
+
+ add_pdn_stripe \
+ -grid stdcell_grid \
+ -layer $::env(FP_PDN_UPPER_LAYER) \
+ -width $::env(FP_PDN_HWIDTH) \
+ -pitch $::env(FP_PDN_HPITCH) \
+ -offset $::env(FP_PDN_HOFFSET) \
+ -spacing $::env(FP_PDN_HSPACING) \
+ -nets "$::env(PDN_STRIPE)" \
+ -starts_with POWER -extend_to_core_ring
+
+ add_pdn_connect \
+ -grid stdcell_grid \
+ -layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
+} else {
+ # Used if the design is a macro in the core
+ define_pdn_grid \
+ -name stdcell_grid \
+ -starts_with POWER \
+ -voltage_domain CORE \
+ -pins $::env(FP_PDN_LOWER_LAYER)
+
+ add_pdn_stripe \
+ -grid stdcell_grid \
+ -layer $::env(FP_PDN_LOWER_LAYER) \
+ -width $::env(FP_PDN_VWIDTH) \
+ -pitch $::env(FP_PDN_VPITCH) \
+ -offset $::env(FP_PDN_VOFFSET) \
+ -starts_with POWER
+}
+
+# Adds the standard cell rails if enabled.
+if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
+ add_pdn_stripe \
+ -grid stdcell_grid \
+ -layer $::env(FP_PDN_RAILS_LAYER) \
+ -width $::env(FP_PDN_RAIL_WIDTH) \
+ -followpins \
+ -starts_with POWER
+
+ add_pdn_connect \
+ -grid stdcell_grid \
+ -layers "$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)"
+}
+
+
+# Adds the core ring if enabled.
+if { $::env(FP_PDN_CORE_RING) == 1 } {
+ add_pdn_ring \
+ -grid stdcell_grid \
+ -layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)" \
+ -widths "$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)" \
+ -spacings "$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)" \
+ -core_offset "$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)"
+}
+##################################
+# Common Macro Power Hook Up
+# Power Connect met-4 to met-5
+##################################
+
+define_pdn_grid \
+ -macro \
+ -default \
+ -name macro \
+ -starts_with POWER \
+ -halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
+
+add_pdn_connect \
+ -grid macro \
+ -layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
+
diff --git a/openlane/user_project_wrapper/sta.tcl b/openlane/user_project_wrapper/sta.tcl
new file mode 100644
index 0000000..e002811
--- /dev/null
+++ b/openlane/user_project_wrapper/sta.tcl
@@ -0,0 +1,107 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+
+set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
+set ::env(LIB_TYPICAL) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"
+set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
+set ::env(DESIGN_NAME) "user_project_wrapper"
+set ::env(BASE_SDC_FILE) "base.sdc"
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
+set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
+set ::env(SYNTH_CAP_LOAD) "17.65"
+set ::env(WIRE_RC_LAYER) "met1"
+
+#To disable empty filler cell black box get created
+#set link_make_black_boxes 0
+
+
+set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
+define_corners wc bc tt
+read_liberty -corner bc $::env(LIB_FASTEST)
+read_liberty -corner wc $::env(LIB_SLOWEST)
+read_liberty -corner tt $::env(LIB_TYPICAL)
+
+
+read_verilog netlist/wb_host.v
+read_verilog netlist/mbist1.v
+read_verilog netlist/mbist2.v
+read_verilog netlist/glbl_cfg.v
+read_verilog netlist/wb_interconnect.v
+read_verilog netlist/user_project_wrapper.v
+read_lib -corner tt ../../lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
+read_lib -corner tt ../../lib/sram_1rw1r_32_256_8_sky130_TT_1p8V_25C.lib
+link_design $::env(DESIGN_NAME)
+
+
+read_spef -path u_mbist1 ../../spef/mbist_top1.spef
+read_spef -path u_mbist2 ../../spef/mbist_top1.spef
+read_spef -path u_mbist3 ../../spef/mbist_top1.spef
+read_spef -path u_mbist4 ../../spef/mbist_top1.spef
+read_spef -path u_mbist5 ../../spef/mbist_top2.spef
+read_spef -path u_mbist6 ../../spef/mbist_top2.spef
+read_spef -path u_mbist7 ../../spef/mbist_top2.spef
+read_spef -path u_mbist8 ../../spef/mbist_top2.spef
+read_spef -path u_wb_host ../../spef/wb_host.spef
+read_spef -path u_intercon ../../spef/wb_interconnect.spef
+read_spef -path u_glbl ../../spef/glbl_cfg.spef
+
+read_spef ../../spef/user_project_wrapper.spef
+
+
+read_sdc -echo $::env(BASE_SDC_FILE)
+
+# check for missing constraints
+check_setup -verbose > unconstraints.rpt
+
+set_operating_conditions -analysis_type single
+# Propgate the clock
+set_propagated_clock [all_clocks]
+
+report_tns
+report_wns
+#report_power
+echo "################ CORNER : WC (SLOW) TIMING Report ###################" > timing_ss_max.rpt
+report_checks -unique -path_delay max -slack_max -0.0 -group_count 100 -corner wc >> timing_ss_max.rpt
+report_checks -group_count 100 -path_delay max -path_group $::env(WBM_CLOCK_NAME) -corner wc >> timing_ss_max.rpt
+report_checks -group_count 100 -path_delay max -path_group $::env(WBS_CLOCK_NAME) -corner wc >> timing_ss_max.rpt
+report_checks -group_count 100 -path_delay max -path_group $::env(BIST_CLOCK_NAME) -corner wc >> timing_ss_max.rpt
+report_checks -path_delay max -corner wc >> timing_ss_max.rpt
+
+echo "################ CORNER : BC (SLOW) TIMING Report ###################" > timing_ff_min.rpt
+report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner bc >> timing_ff_min.rpt
+report_checks -group_count 100 -path_delay min -path_group $::env(WBM_CLOCK_NAME) -corner bc >> timing_ff_min.rpt
+report_checks -group_count 100 -path_delay min -path_group $::env(WBS_CLOCK_NAME) -corner bc >> timing_ff_min.rpt
+report_checks -group_count 100 -path_delay min -path_group $::env(BIST_CLOCK_NAME) -corner bc >> timing_ff_min.rpt
+report_checks -path_delay min -corner bc >> timing_ff_min.rpt
+
+echo "################ CORNER : TT (MAX) TIMING Report ###################" > timing_tt_max.rpt
+report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner tt >> timing_tt_max.rpt
+report_checks -group_count 100 -path_delay max -path_group $::env(WBM_CLOCK_NAME) -corner tt >> timing_tt_max.rpt
+report_checks -group_count 100 -path_delay max -path_group $::env(WBS_CLOCK_NAME) -corner tt >> timing_tt_max.rpt
+report_checks -group_count 100 -path_delay max -path_group $::env(BIST_CLOCK_NAME) -corner tt >> timing_tt_max.rpt
+report_checks -path_delay min -corner tt >> timing_tt_min.rpt
+
+echo "################ CORNER : TT (MIN) TIMING Report ###################" > timing_tt_min.rpt
+report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner tt >> timing_tt_min.rpt
+report_checks -group_count 100 -path_delay min -path_group $::env(WBM_CLOCK_NAME) -corner tt >> timing_tt_min.rpt
+report_checks -group_count 100 -path_delay min -path_group $::env(WBS_CLOCK_NAME) -corner tt >> timing_tt_min.rpt
+report_checks -group_count 100 -path_delay min -path_group $::env(BIST_CLOCK_NAME) -corner tt >> timing_tt_min.rpt
+report_checks -path_delay min -corner tt >> timing_tt_min.rpt
+
+report_checks -path_delay min
+
+#exit
diff --git a/openlane/wb_host/base.sdc b/openlane/wb_host/base.sdc
new file mode 100644
index 0000000..021f2ea
--- /dev/null
+++ b/openlane/wb_host/base.sdc
@@ -0,0 +1,129 @@
+###############################################################################
+# Created by write_sdc
+# Sun Nov 14 09:07:48 2021
+###############################################################################
+current_design wb_host
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name wbm_clk_i -period 10.0000 [get_ports {wbm_clk_i}]
+create_clock -name wbs_clk_i -period 10.0000 [get_ports {wbs_clk_i}]
+create_clock -name lbist_clk -period 10.0000 [get_ports {lbist_clk_int}]
+create_clock -name uart_clk -period 100.0000 [get_pins {u_uart2wb.u_core.u_uart_clk.u_mux/X}]
+
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+set_clock_groups -name async_clock -asynchronous \
+ -group [get_clocks {uart_clk}] \
+ -group [get_clocks {wbs_clk_i}]\
+ -group [get_clocks {wbm_clk_i}]\
+ -group [get_clocks {lbist_clk}]\
+ -comment {Async Clock group}
+
+## Scan Mode & Scan Enable
+set_case_analysis 0 [get_pins {u_wb_host/u_scan_buf.u_buf/X}]
+set_case_analysis 0 [get_pins {u_wb_host/scan_en}]
+
+set_case_analysis 0 [get_ports {cfg_cska_wh[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_wh[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_wh[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_wh[3]}]
+
+set_case_analysis 0 [get_ports {cfg_cska_lbist[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_lbist[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_lbist[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_lbist[3]}]
+
+#disable clock gating check at static clock select pins
+set_false_path -through [get_pins u_wbs_clk_sel.u_mux/S]
+
+#Static Signal Clock Skew adjustment
+
+set_max_delay 3.5 -from [get_ports {wbd_clk_int}]
+set_max_delay 2 -to [get_ports {wbd_clk_wh}]
+set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_mbist
+
+set_max_delay 3.5 -to [get_ports {lbist_clk_out}]
+set_max_delay 3.5 -to [get_ports {scan_in}]
+set_max_delay 3.5 -from [get_ports {scan_out}]
+set_max_delay 3.5 -to [get_ports {scan_rst_n}]
+set_max_delay 3.5 -to [get_ports {scan_en}]
+set_max_delay 3.5 -to [get_ports {scan_mode}]
+set_max_delay 3.5 -to [get_ports {cfg_clk_ctrl1[*]}]
+set_max_delay 3.5 -to [get_ports {cfg_clk_ctrl2[*]}]
+set_max_delay 3.5 -to [get_ports {io_out[*]}]
+set_max_delay 3.5 -to [get_ports {io_oeb[*]}]
+set_max_delay 3.5 -to [get_ports {la_data_out[*]}]
+set_max_delay 3.5 -to [get_ports {wbd_int_rst_n}]
+set_max_delay 3.5 -to [get_ports {bist_rst_n}]
+
+
+#Strobe is registered inside the wb_host before generating chip select
+# So wbm_adr_i wbm_we_i wbm_sel_i wbm_dat_i are having 2 cycle setup
+set_multicycle_path -setup -from [get_ports {wbm_adr_i[*]}] 2
+set_multicycle_path -setup -from [get_ports {wbm_cyc_i}] 2
+set_multicycle_path -setup -from [get_ports {wbm_dat_i[*]}] 2
+set_multicycle_path -setup -from [get_ports {wbm_sel_i[*]}] 2
+set_multicycle_path -setup -from [get_ports {wbm_we_i}] 2
+
+set_multicycle_path -hold -from [get_ports {wbm_adr_i[*]}] 2
+set_multicycle_path -hold -from [get_ports {wbm_cyc_i}] 2
+set_multicycle_path -hold -from [get_ports {wbm_dat_i[*]}] 2
+set_multicycle_path -hold -from [get_ports {wbm_sel_i[*]}] 2
+set_multicycle_path -hold -from [get_ports {wbm_we_i}] 2
+
+#
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_rst_i}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_stb_i}]
+
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_rst_i}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_stb_i}]
+
+set_output_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_ack_o}]
+set_output_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[*]}]
+set_output_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_err_o}]
+
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_ack_o}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[*]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_err_o}]
+# WBS I/F
+set_input_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_ack_i}]
+set_input_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_cyc_o}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_stb_o}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_we_o}]
+
+set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[*]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_cyc_o}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[*]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[*]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_stb_o}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_we_o}]
+
+###############################################################################
+# Environment
+###############################################################################
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
+
+###############################################################################
+# Design Rules
+###############################################################################
+
+
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
new file mode 100755
index 0000000..b7a860e
--- /dev/null
+++ b/openlane/wb_host/config.tcl
@@ -0,0 +1,132 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+
+set ::env(DESIGN_NAME) wb_host
+
+set ::env(DESIGN_IS_CORE) "0"
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "wbm_clk_i wbs_clk_i lbist_clk_int u_uart2wb.u_core.u_uart_clk.u_mux/X"
+
+set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+ $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/wb_host/src/wb_host.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/async_fifo.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/async_wb.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_ctl.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/registers.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/async_reg_bus.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_gate.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/crc_32.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/reset_sync.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lbist/src/lbist_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lbist/src/lbist_core.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lbist/src/lbist_reg.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_txfsm.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_rxfsm.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/double_sync_low.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/wb_arb.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/uart2wb/src/uart2wb.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/uart2wb/src/uart2_core.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/uart2wb/src/uart_msg_handler.v \
+ "
+
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+set ::env(SDC_FILE) "$::env(DESIGN_DIR)/base.sdc"
+set ::env(BASE_SDC_FILE) "$::env(DESIGN_DIR)/base.sdc"
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 700 300"
+
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
+
+#set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_TARGET_DENSITY) "0.35"
+
+# helps in anteena fix
+set ::env(USE_ARC_ANTENNA_CHECK) "1"
+
+set ::env(FP_IO_VEXTEND) 4
+set ::env(FP_IO_HEXTEND) 4
+
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 6.2
+set ::env(FP_PDN_HWIDTH) 6.2
+
+#set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
+
+#Lef
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
+
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
+
+set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {0.25}
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) {0.25}
+
+set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {500}
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {500}
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "1"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg
new file mode 100644
index 0000000..9e1f20f
--- /dev/null
+++ b/openlane/wb_host/pin_order.cfg
@@ -0,0 +1,580 @@
+#BUS_SORT
+
+#MANUAL_PLACE
+
+
+#W
+bist_rst_n 0 0 2
+cfg_clk_ctrl1\[31\]
+cfg_clk_ctrl1\[30\]
+cfg_clk_ctrl1\[29\]
+cfg_clk_ctrl1\[28\]
+cfg_clk_ctrl1\[27\]
+cfg_clk_ctrl1\[26\]
+cfg_clk_ctrl1\[25\]
+cfg_clk_ctrl1\[24\]
+cfg_clk_ctrl1\[23\]
+cfg_clk_ctrl1\[22\]
+cfg_clk_ctrl1\[21\]
+cfg_clk_ctrl1\[20\]
+cfg_clk_ctrl1\[19\]
+cfg_clk_ctrl1\[18\]
+cfg_clk_ctrl1\[17\]
+cfg_clk_ctrl1\[16\]
+cfg_clk_ctrl1\[15\]
+cfg_clk_ctrl1\[14\]
+cfg_clk_ctrl1\[13\]
+cfg_clk_ctrl1\[12\]
+cfg_clk_ctrl1\[11\]
+cfg_clk_ctrl1\[10\]
+cfg_clk_ctrl1\[9\]
+cfg_clk_ctrl1\[8\]
+cfg_clk_ctrl1\[7\]
+cfg_clk_ctrl1\[6\]
+cfg_clk_ctrl1\[5\]
+cfg_clk_ctrl1\[4\]
+cfg_clk_ctrl1\[3\]
+cfg_clk_ctrl1\[2\]
+cfg_clk_ctrl1\[1\]
+cfg_clk_ctrl1\[0\]
+
+cfg_clk_ctrl2\[31\]
+cfg_clk_ctrl2\[30\]
+cfg_clk_ctrl2\[29\]
+cfg_clk_ctrl2\[28\]
+cfg_clk_ctrl2\[27\]
+cfg_clk_ctrl2\[26\]
+cfg_clk_ctrl2\[25\]
+cfg_clk_ctrl2\[24\]
+cfg_clk_ctrl2\[23\]
+cfg_clk_ctrl2\[22\]
+cfg_clk_ctrl2\[21\]
+cfg_clk_ctrl2\[20\]
+cfg_clk_ctrl2\[19\]
+cfg_clk_ctrl2\[18\]
+cfg_clk_ctrl2\[17\]
+cfg_clk_ctrl2\[16\]
+cfg_clk_ctrl2\[15\]
+cfg_clk_ctrl2\[14\]
+cfg_clk_ctrl2\[13\]
+cfg_clk_ctrl2\[12\]
+cfg_clk_ctrl2\[11\]
+cfg_clk_ctrl2\[10\]
+cfg_clk_ctrl2\[9\]
+cfg_clk_ctrl2\[8\]
+cfg_clk_ctrl2\[7\]
+cfg_clk_ctrl2\[6\]
+cfg_clk_ctrl2\[5\]
+cfg_clk_ctrl2\[4\]
+cfg_clk_ctrl2\[3\]
+cfg_clk_ctrl2\[2\]
+cfg_clk_ctrl2\[1\]
+cfg_clk_ctrl2\[0\]
+
+cfg_cska_lbist\[3\] 0150 0 4
+cfg_cska_lbist\[2\]
+cfg_cska_lbist\[1\]
+cfg_cska_lbist\[0\]
+lbist_clk_int
+lbist_clk_out
+
+
+scan_clk 0200 0 2
+scan_rst_n
+scan_mode
+scan_en
+scan_in\[7\]
+scan_in\[6\]
+scan_in\[5\]
+scan_in\[4\]
+scan_in\[3\]
+scan_in\[2\]
+scan_in\[1\]
+scan_in\[0\]
+scan_out\[7\]
+scan_out\[6\]
+scan_out\[5\]
+scan_out\[4\]
+scan_out\[3\]
+scan_out\[2\]
+scan_out\[1\]
+scan_out\[0\]
+
+#E
+io_out\[37\] 0 0 2
+io_out\[36\]
+io_out\[35\]
+io_out\[34\]
+io_out\[33\]
+io_out\[32\]
+io_out\[31\]
+io_out\[30\]
+io_out\[29\]
+io_out\[28\]
+io_out\[27\]
+io_out\[26\]
+io_out\[25\]
+io_out\[24\]
+io_out\[23\]
+io_out\[22\]
+io_out\[21\]
+io_out\[20\]
+io_out\[19\]
+io_out\[18\]
+io_out\[17\]
+io_out\[16\]
+io_out\[15\]
+io_out\[14\]
+io_out\[13\]
+io_out\[12\]
+io_out\[11\]
+io_out\[10\]
+io_out\[9\]
+io_out\[8\]
+io_out\[7\]
+io_out\[6\]
+io_out\[5\]
+io_out\[4\]
+io_out\[3\]
+io_out\[2\]
+io_out\[1\]
+io_out\[0\]
+io_oeb\[37\]
+io_oeb\[36\]
+io_oeb\[35\]
+io_oeb\[34\]
+io_oeb\[33\]
+io_oeb\[32\]
+io_oeb\[31\]
+io_oeb\[30\]
+io_oeb\[29\]
+io_oeb\[28\]
+io_oeb\[27\]
+io_oeb\[26\]
+io_oeb\[25\]
+io_oeb\[24\]
+io_oeb\[23\]
+io_oeb\[22\]
+io_oeb\[21\]
+io_oeb\[20\]
+io_oeb\[19\]
+io_oeb\[18\]
+io_oeb\[17\]
+io_oeb\[16\]
+io_oeb\[15\]
+io_oeb\[14\]
+io_oeb\[13\]
+io_oeb\[12\]
+io_oeb\[11\]
+io_oeb\[10\]
+io_oeb\[9\]
+io_oeb\[8\]
+io_oeb\[7\]
+io_oeb\[6\]
+io_oeb\[5\]
+io_oeb\[4\]
+io_oeb\[3\]
+io_oeb\[2\]
+io_oeb\[1\]
+io_oeb\[0\]
+io_in
+
+
+#S
+user_clock2 0000 0 4
+user_irq\[2\]
+user_irq\[1\]
+user_irq\[0\]
+user_clock1
+cfg_cska_wh\[3\]
+cfg_cska_wh\[2\]
+cfg_cska_wh\[1\]
+cfg_cska_wh\[0\]
+wbm_clk_i
+wbm_rst_i
+wbm_ack_o
+wbm_cyc_i
+wbm_stb_i
+wbm_we_i
+wbm_adr_i\[0\]
+wbm_dat_i\[0\]
+wbm_dat_o\[0\]
+wbm_sel_i\[0\]
+wbm_adr_i\[1\]
+wbm_dat_i\[1\]
+wbm_dat_o\[1\]
+wbm_sel_i\[1\]
+wbm_adr_i\[2\]
+wbm_dat_i\[2\]
+wbm_dat_o\[2\]
+wbm_sel_i\[2\]
+wbm_adr_i\[3\]
+wbm_dat_i\[3\]
+wbm_dat_o\[3\]
+wbm_sel_i\[3\]
+wbm_adr_i\[4\]
+wbm_dat_i\[4\]
+wbm_dat_o\[4\]
+wbm_adr_i\[5\]
+wbm_dat_i\[5\]
+wbm_dat_o\[5\]
+wbm_adr_i\[6\]
+wbm_dat_i\[6\]
+wbm_dat_o\[6\]
+wbm_adr_i\[7\]
+wbm_dat_i\[7\]
+wbm_dat_o\[7\]
+wbm_adr_i\[8\]
+wbm_dat_i\[8\]
+wbm_dat_o\[8\]
+wbm_adr_i\[9\]
+wbm_dat_i\[9\]
+wbm_dat_o\[9\]
+wbm_adr_i\[10\]
+wbm_dat_i\[10\]
+wbm_dat_o\[10\]
+wbm_adr_i\[11\]
+wbm_dat_i\[11\]
+wbm_dat_o\[11\]
+wbm_adr_i\[12\]
+wbm_dat_i\[12\]
+wbm_dat_o\[12\]
+wbm_adr_i\[13\]
+wbm_dat_i\[13\]
+wbm_dat_o\[13\]
+wbm_adr_i\[14\]
+wbm_dat_i\[14\]
+wbm_dat_o\[14\]
+wbm_adr_i\[15\]
+wbm_dat_i\[15\]
+wbm_dat_o\[15\]
+wbm_adr_i\[16\]
+wbm_dat_i\[16\]
+wbm_dat_o\[16\]
+wbm_adr_i\[17\]
+
+wbm_dat_i\[17\]
+wbm_dat_o\[17\]
+wbm_adr_i\[18\]
+wbm_dat_i\[18\]
+wbm_dat_o\[18\]
+wbm_adr_i\[19\]
+wbm_dat_i\[19\]
+wbm_dat_o\[19\]
+wbm_adr_i\[20\]
+wbm_dat_i\[20\]
+wbm_dat_o\[20\]
+wbm_adr_i\[21\]
+wbm_dat_i\[21\]
+wbm_dat_o\[21\]
+wbm_adr_i\[22\]
+wbm_dat_i\[22\]
+wbm_dat_o\[22\]
+wbm_adr_i\[23\]
+wbm_dat_i\[23\]
+wbm_dat_o\[23\]
+wbm_adr_i\[24\]
+wbm_dat_i\[24\]
+wbm_dat_o\[24\]
+wbm_adr_i\[25\]
+wbm_dat_i\[25\]
+wbm_dat_o\[25\]
+wbm_adr_i\[26\]
+wbm_dat_i\[26\]
+wbm_dat_o\[26\]
+wbm_adr_i\[27\]
+wbm_dat_i\[27\]
+wbm_dat_o\[27\]
+wbm_adr_i\[28\]
+wbm_dat_i\[28\]
+wbm_dat_o\[28\]
+wbm_adr_i\[29\]
+wbm_dat_i\[29\]
+wbm_dat_o\[29\]
+wbm_adr_i\[30\]
+wbm_dat_i\[30\]
+wbm_dat_o\[30\]
+wbm_adr_i\[31\]
+wbm_dat_i\[31\]
+wbm_dat_o\[31\]
+wbm_err_o
+
+la_data_in\[0\] 250 0 2
+la_data_out\[0\]
+la_data_in\[1\]
+la_data_out\[1\]
+la_data_in\[2\]
+la_data_out\[2\]
+la_data_in\[3\]
+la_data_out\[3\]
+la_data_in\[4\]
+la_data_out\[4\]
+la_data_in\[5\]
+la_data_out\[5\]
+la_data_in\[6\]
+la_data_out\[6\]
+la_data_in\[7\]
+la_data_out\[7\]
+la_data_in\[8\]
+la_data_out\[8\]
+la_data_in\[9\]
+la_data_out\[9\]
+la_data_in\[10\]
+la_data_out\[10\]
+la_data_in\[11\]
+la_data_out\[11\]
+la_data_in\[12\]
+la_data_out\[12\]
+la_data_in\[13\]
+la_data_out\[13\]
+la_data_in\[14\]
+la_data_out\[14\]
+la_data_in\[15\]
+la_data_out\[15\]
+la_data_in\[16\]
+la_data_out\[16\]
+la_data_in\[17\]
+la_data_out\[17\]
+la_data_in\[18\]
+la_data_out\[18\]
+la_data_in\[19\]
+la_data_out\[19\]
+la_data_in\[20\]
+la_data_out\[20\]
+la_data_in\[21\]
+la_data_out\[21\]
+la_data_in\[22\]
+la_data_out\[22\]
+la_data_in\[23\]
+la_data_out\[23\]
+la_data_in\[24\]
+la_data_out\[24\]
+la_data_in\[25\]
+la_data_out\[25\]
+la_data_in\[26\]
+la_data_out\[26\]
+la_data_in\[27\]
+la_data_out\[27\]
+la_data_in\[28\]
+la_data_out\[28\]
+la_data_in\[29\]
+la_data_out\[29\]
+la_data_in\[30\]
+la_data_out\[30\]
+la_data_in\[31\]
+la_data_out\[31\]
+la_data_in\[32\]
+la_data_out\[32\]
+la_data_in\[33\]
+la_data_out\[33\]
+la_data_in\[34\]
+la_data_out\[34\]
+la_data_in\[35\]
+la_data_out\[35\]
+
+la_data_out\[36\]
+la_data_out\[37\]
+la_data_out\[38\]
+la_data_out\[39\]
+la_data_out\[40\]
+la_data_out\[41\]
+la_data_out\[42\]
+la_data_out\[43\]
+la_data_out\[44\]
+la_data_out\[45\]
+la_data_out\[46\]
+la_data_out\[47\]
+la_data_out\[48\]
+la_data_out\[49\]
+la_data_out\[50\]
+la_data_out\[51\]
+la_data_out\[52\]
+la_data_out\[53\]
+la_data_out\[54\]
+la_data_out\[55\]
+la_data_out\[56\]
+la_data_out\[57\]
+la_data_out\[58\]
+la_data_out\[59\]
+la_data_out\[60\]
+la_data_out\[61\]
+la_data_out\[62\]
+la_data_out\[63\]
+la_data_out\[64\]
+la_data_out\[65\]
+la_data_out\[66\]
+la_data_out\[67\]
+la_data_out\[68\]
+la_data_out\[69\]
+la_data_out\[70\]
+la_data_out\[71\]
+la_data_out\[72\]
+la_data_out\[73\]
+la_data_out\[74\]
+la_data_out\[75\]
+la_data_out\[76\]
+la_data_out\[77\]
+la_data_out\[78\]
+la_data_out\[79\]
+la_data_out\[80\]
+la_data_out\[81\]
+la_data_out\[82\]
+la_data_out\[83\]
+la_data_out\[84\]
+la_data_out\[85\]
+la_data_out\[86\]
+la_data_out\[87\]
+la_data_out\[88\]
+la_data_out\[89\]
+la_data_out\[90\]
+la_data_out\[91\]
+la_data_out\[92\]
+la_data_out\[93\]
+la_data_out\[94\]
+la_data_out\[95\]
+la_data_out\[96\]
+la_data_out\[97\]
+la_data_out\[98\]
+la_data_out\[99\]
+la_data_out\[100\]
+la_data_out\[101\]
+la_data_out\[102\]
+la_data_out\[103\]
+la_data_out\[104\]
+la_data_out\[105\]
+la_data_out\[106\]
+la_data_out\[107\]
+la_data_out\[108\]
+la_data_out\[109\]
+la_data_out\[110\]
+la_data_out\[111\]
+la_data_out\[112\]
+la_data_out\[113\]
+la_data_out\[114\]
+la_data_out\[115\]
+la_data_out\[116\]
+la_data_out\[117\]
+la_data_out\[118\]
+la_data_out\[119\]
+la_data_out\[120\]
+la_data_out\[121\]
+la_data_out\[122\]
+la_data_out\[123\]
+la_data_out\[124\]
+la_data_out\[125\]
+la_data_out\[126\]
+la_data_out\[127\]
+
+#N
+wbs_stb_o 0000 0 2
+wbs_we_o
+wbs_adr_o\[31\]
+wbs_adr_o\[30\]
+wbs_adr_o\[29\]
+wbs_adr_o\[28\]
+wbs_adr_o\[27\]
+wbs_adr_o\[26\]
+wbs_adr_o\[25\]
+wbs_adr_o\[24\]
+wbs_adr_o\[23\]
+wbs_adr_o\[22\]
+wbs_adr_o\[21\]
+wbs_adr_o\[20\]
+wbs_adr_o\[19\]
+wbs_adr_o\[18\]
+wbs_adr_o\[17\]
+wbs_adr_o\[16\]
+wbs_adr_o\[15\]
+wbs_adr_o\[14\]
+wbs_adr_o\[13\]
+wbs_adr_o\[12\]
+wbs_adr_o\[11\]
+wbs_adr_o\[10\]
+wbs_adr_o\[9\]
+wbs_adr_o\[8\]
+wbs_adr_o\[7\]
+wbs_adr_o\[6\]
+wbs_adr_o\[5\]
+wbs_adr_o\[4\]
+wbs_adr_o\[3\]
+wbs_adr_o\[2\]
+wbs_adr_o\[1\]
+wbs_adr_o\[0\]
+wbs_sel_o\[3\]
+wbs_sel_o\[2\]
+wbs_sel_o\[1\]
+wbs_sel_o\[0\]
+wbs_dat_o\[31\]
+wbs_dat_o\[30\]
+wbs_dat_o\[29\]
+wbs_dat_o\[28\]
+wbs_dat_o\[27\]
+wbs_dat_o\[26\]
+wbs_dat_o\[25\]
+wbs_dat_o\[24\]
+wbs_dat_o\[23\]
+wbs_dat_o\[22\]
+wbs_dat_o\[21\]
+wbs_dat_o\[20\]
+wbs_dat_o\[19\]
+wbs_dat_o\[18\]
+wbs_dat_o\[17\]
+wbs_dat_o\[16\]
+wbs_dat_o\[15\]
+wbs_dat_o\[14\]
+wbs_dat_o\[13\]
+wbs_dat_o\[12\]
+wbs_dat_o\[11\]
+wbs_dat_o\[10\]
+wbs_dat_o\[9\]
+wbs_dat_o\[8\]
+wbs_dat_o\[7\]
+wbs_dat_o\[6\]
+wbs_dat_o\[5\]
+wbs_dat_o\[4\]
+wbs_dat_o\[3\]
+wbs_dat_o\[2\]
+wbs_dat_o\[1\]
+wbs_dat_o\[0\]
+wbs_dat_i\[31\]
+wbs_dat_i\[30\]
+wbs_dat_i\[29\]
+wbs_dat_i\[28\]
+wbs_dat_i\[27\]
+wbs_dat_i\[26\]
+wbs_dat_i\[25\]
+wbs_dat_i\[24\]
+wbs_dat_i\[23\]
+wbs_dat_i\[22\]
+wbs_dat_i\[21\]
+wbs_dat_i\[20\]
+wbs_dat_i\[19\]
+wbs_dat_i\[18\]
+wbs_dat_i\[17\]
+wbs_dat_i\[16\]
+wbs_dat_i\[15\]
+wbs_dat_i\[14\]
+wbs_dat_i\[13\]
+wbs_dat_i\[12\]
+wbs_dat_i\[11\]
+wbs_dat_i\[10\]
+wbs_dat_i\[9\]
+wbs_dat_i\[8\]
+wbs_dat_i\[7\]
+wbs_dat_i\[6\]
+wbs_dat_i\[5\]
+wbs_dat_i\[4\]
+wbs_dat_i\[3\]
+wbs_dat_i\[2\]
+wbs_dat_i\[1\]
+wbs_dat_i\[0\]
+wbs_ack_i
+wbs_err_i
+wbs_cyc_o
+
+wbd_int_rst_n 110 0 2
+wbs_clk_out
+wbd_clk_int
+wbd_clk_wh
+wbs_clk_i
+
diff --git a/openlane/wb_host/sta/Makefile b/openlane/wb_host/sta/Makefile
new file mode 100644
index 0000000..6f3136c
--- /dev/null
+++ b/openlane/wb_host/sta/Makefile
@@ -0,0 +1,53 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+BLOCKS = wb_host
+DEF = $(foreach block,$(BLOCKS), ../../../def/$(block).def)
+CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
+
+OPENLANE_TAG = mpw4
+OPENLANE_IMAGE_NAME = dineshannayya/openlane:$(OPENLANE_TAG)
+OPENLANE_NETLIST_COMMAND = "cd /project/sta && openroad -exit scripts/or_write_verilog.tcl | tee logs/$@.log"
+OPENLANE_STA_COMMAND = "cd /project/sta && sta scripts/sta.tcl | tee logs/sta.log"
+
+all: $(BLOCKS) sta
+
+$(DEF) :
+ @echo "Missing $@. Please create a def for that design"
+ @exit 1
+
+$(BLOCKS) : % : ../../../def/%.def create
+ docker run -it -v $(PWD)/..:/project -e DESIGN_NAME=$@ -u $(shell id -u $(USER)):$(shell id -g $(USER)) $(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_NETLIST_COMMAND)
+
+sta:
+ #sta inside the docker is crashing with segmentation fault, so are running sta outside the docker
+ #docker run -it -v $(PWD)/..:/project -e DESIGN_NAME=$@ -u $(shell id -u $(USER)):$(shell id -g $(USER)) $(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_STA_COMMAND)
+ export STA_MODE=func
+ sta scripts/sta.tcl | tee logs/sta_func.log
+
+create: clean
+ @echo "create temp directory :)"
+ mkdir -p netlist
+ mkdir -p logs
+ mkdir -p reports/func
+ mkdir -p reports/scan
+
+clean:
+ @echo "clean everything :)"
+ rm -rf netlist
+ rm -rf logs
+ rm -rf reports
+
diff --git a/openlane/wb_host/sta/func.sdc b/openlane/wb_host/sta/func.sdc
new file mode 100644
index 0000000..49e46b6
--- /dev/null
+++ b/openlane/wb_host/sta/func.sdc
@@ -0,0 +1,113 @@
+###############################################################################
+# Created by write_sdc
+# Sun Nov 14 09:07:48 2021
+###############################################################################
+current_design wb_host
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name wbm_clk_i -period 10.0000 [get_ports {wbm_clk_i}]
+create_clock -name wbs_clk_i -period 10.0000 [get_ports {wbs_clk_i}]
+create_clock -name lbist_clk -period 10.0000 [get_pins {u_lbist_clk_sel.u_mux/X}]
+set_clock_uncertainty -from wbm_clk_i -to wbm_clk_i -setup 0.200
+set_clock_uncertainty -from wbm_clk_i -to wbm_clk_i -hold 0.100
+set_clock_uncertainty -from wbs_clk_i -to wbs_clk_i -setup 0.200
+set_clock_uncertainty -from wbs_clk_i -to wbs_clk_i -hold 0.100
+set_clock_uncertainty -from lbist_clk -to lbist_clk -setup 0.200
+set_clock_uncertainty -from lbist_clk -to lbist_clk -hold 0.100
+
+set_clock_groups -name async_clock -asynchronous \
+ -group [get_clocks {wbs_clk_i}]\
+ -group [get_clocks {wbm_clk_i}]\
+ -group [get_clocks {lbist_clk}]\
+ -comment {Async Clock group}
+
+## Scan Mode & Scan Enable
+set_case_analysis 0 [get_pins {u_wb_host/u_scan_buf.u_buf/X}]
+set_case_analysis 0 [get_pins {u_wb_host/scan_en}]
+
+set_case_analysis 0 [get_ports {cfg_cska_wh[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_wh[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_wh[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_wh[3]}]
+
+set_case_analysis 0 [get_pins {cfg_cska_lbist[0]}]
+set_case_analysis 0 [get_pins {cfg_cska_lbist[1]}]
+set_case_analysis 0 [get_pins {cfg_cska_lbist[2]}]
+set_case_analysis 0 [get_pins {cfg_cska_lbist[3]}]
+
+#disable clock gating check at static clock select pins
+set_false_path -through [get_pins u_wbs_clk_sel.u_mux/S]
+
+#Static Signal Clock Skew adjustment
+set_false_path -from [get_ports {cfg_cska_wh[0]}]
+set_false_path -from [get_ports {cfg_cska_wh[1]}]
+set_false_path -from [get_ports {cfg_cska_wh[2]}]
+set_false_path -from [get_ports {cfg_cska_wh[3]}]
+
+set_max_delay 3.5 -from [get_ports {wbd_clk_int}]
+set_max_delay 2 -to [get_ports {wbd_clk_wh}]
+set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_mbist
+
+#Strobe is registered inside the wb_host before generating chip select
+# So wbm_adr_i wbm_we_i wbm_sel_i wbm_dat_i are having 2 cycle setup
+set_multicycle_path -setup -from [get_ports {wbm_adr_i[*]}] 2
+set_multicycle_path -setup -from [get_ports {wbm_cyc_i}] 2
+set_multicycle_path -setup -from [get_ports {wbm_dat_i[*]}] 2
+set_multicycle_path -setup -from [get_ports {wbm_sel_i[*]}] 2
+set_multicycle_path -setup -from [get_ports {wbm_we_i}] 2
+
+set_multicycle_path -hold -from [get_ports {wbm_adr_i[*]}] 2
+set_multicycle_path -hold -from [get_ports {wbm_cyc_i}] 2
+set_multicycle_path -hold -from [get_ports {wbm_dat_i[*]}] 2
+set_multicycle_path -hold -from [get_ports {wbm_sel_i[*]}] 2
+set_multicycle_path -hold -from [get_ports {wbm_we_i}] 2
+
+#
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_rst_i}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_stb_i}]
+
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_rst_i}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_stb_i}]
+
+set_output_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_ack_o}]
+set_output_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[*]}]
+set_output_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_err_o}]
+
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_ack_o}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[*]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_err_o}]
+# WBS I/F
+set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_cyc_o}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_stb_o}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_we_o}]
+
+set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[*]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_cyc_o}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[*]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[*]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_stb_o}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_we_o}]
+
+###############################################################################
+# Environment
+###############################################################################
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
+
+###############################################################################
+# Design Rules
+###############################################################################
+
+
diff --git a/openlane/wb_host/sta/logs/sta_func.log b/openlane/wb_host/sta/logs/sta_func.log
new file mode 100644
index 0000000..d1dc5dc
--- /dev/null
+++ b/openlane/wb_host/sta/logs/sta_func.log
@@ -0,0 +1,7 @@
+OpenSTA 2.3.1 ddd7f39736 Copyright (c) 2019, Parallax Software, Inc.
+License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>
+
+This is free software, and you are free to change and redistribute it
+under certain conditions; type `show_copying' for details.
+This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
+% Error: sta.tcl, 22 can't read "::env(STA_MODE)": no such variable
diff --git a/openlane/wb_host/sta/logs/wb_host.log b/openlane/wb_host/sta/logs/wb_host.log
new file mode 100644
index 0000000..9542be9
--- /dev/null
+++ b/openlane/wb_host/sta/logs/wb_host.log
@@ -0,0 +1,5 @@
+OpenROAD b79f266fe41540eabc064bcaddfe19ed715ac5c2
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[ERROR ORD-0001] ../../../lef/merged_unpadded.lef does not exist.
+ORD-0001
diff --git a/openlane/wb_host/sta/scripts/or_write_verilog.tcl b/openlane/wb_host/sta/scripts/or_write_verilog.tcl
new file mode 100644
index 0000000..5262726
--- /dev/null
+++ b/openlane/wb_host/sta/scripts/or_write_verilog.tcl
@@ -0,0 +1,30 @@
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+set ::env(MERGED_LEF_UNPADDED) "../../../lef/merged_unpadded.lef"
+set ::env(INPUT_DEF) "../../../def/$::env(DESIGN_NAME).def"
+set ::env(SAVE_NETLIST) "netlist/$::env(DESIGN_NAME).v"
+
+
+if {[catch {read_lef $::env(MERGED_LEF_UNPADDED)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+if {[catch {read_def $::env(INPUT_DEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+#write_verilog -include_pwr_gnd $::env(SAVE_POWER_NETLIST)
+write_verilog $::env(SAVE_NETLIST)
+
diff --git a/openlane/wb_host/sta/scripts/sta.tcl b/openlane/wb_host/sta/scripts/sta.tcl
new file mode 100644
index 0000000..663ada0
--- /dev/null
+++ b/openlane/wb_host/sta/scripts/sta.tcl
@@ -0,0 +1,107 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+#
+
+set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
+set ::env(LIB_TYPICAL) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"
+set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
+set ::env(DESIGN_NAME) "wb_host"
+set ::env(BASE_SDC_FILE) $::env(STA_MODE).sdc
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
+set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
+set ::env(SYNTH_CAP_LOAD) "17.65"
+set ::env(WIRE_RC_LAYER) "met1"
+
+#To disable empty filler cell black box get created
+#set link_make_black_boxes 0
+
+
+set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
+define_corners wc bc tt
+read_liberty -corner bc $::env(LIB_FASTEST)
+read_liberty -corner wc $::env(LIB_SLOWEST)
+read_liberty -corner tt $::env(LIB_TYPICAL)
+
+read_lib -corner tt ../lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
+read_lib -corner tt ../lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib
+
+read_verilog netlist/wb_host.v
+
+link_design $::env(DESIGN_NAME)
+
+read_spef ../../../spef/wb_host.spef
+
+
+read_sdc -echo $::env(BASE_SDC_FILE)
+
+# check for missing constraints
+check_setup -verbose > reports/$::env(STA_MODE)/unconstraints.rpt
+
+set_operating_conditions -analysis_type single
+# Propgate the clock
+set_propagated_clock [all_clocks]
+
+report_tns
+report_wns
+#report_power
+#
+echo "################ CORNER : WC (MAX) TIMING Report ###################" > reports/$::env(STA_MODE)/timing_ss_max.rpt
+report_checks -unique -slack_max -0.0 -path_delay max -group_count 100 -corner wc -format full_clock_expanded >> reports/$::env(STA_MODE)/timing_ss_max.rpt
+report_checks -group_count 100 -path_delay max -path_group wbm_clk_i -corner wc -format full_clock_expanded >> reports/$::env(STA_MODE)/timing_ss_max.rpt
+report_checks -group_count 100 -path_delay max -path_group wbs_clk_i -corner wc -format full_clock_expanded >> reports/$::env(STA_MODE)/timing_ss_max.rpt
+report_checks -group_count 100 -path_delay max -path_group lbist_clk -corner wc -format full_clock_expanded >> reports/$::env(STA_MODE)/timing_ss_max.rpt
+report_checks -path_delay max -corner wc >> reports/$::env(STA_MODE)/timing_ss_max.rpt
+
+echo "################ CORNER : WC (MIN) TIMING Report ###################" > reports/$::env(STA_MODE)/timing_ss_min.rpt
+report_checks -unique -slack_max -0.0 -path_delay min -group_count 100 -corner wc -format full_clock_expanded >> reports/$::env(STA_MODE)/timing_ss_min.rpt
+report_checks -group_count 100 -path_delay min -path_group wbm_clk_i -corner wc -format full_clock_expanded >> reports/$::env(STA_MODE)/timing_ss_min.rpt
+report_checks -group_count 100 -path_delay min -path_group wbs_clk_i -corner wc -format full_clock_expanded >> reports/$::env(STA_MODE)/timing_ss_min.rpt
+report_checks -group_count 100 -path_delay min -path_group lbist_clk -corner wc -format full_clock_expanded >> reports/$::env(STA_MODE)/timing_ss_min.rpt
+report_checks -path_delay min -corner wc >> reports/$::env(STA_MODE)/timing_ss_min.rpt
+
+echo "################ CORNER : BC (MAX) TIMING Report ###################" > reports/$::env(STA_MODE)/timing_ff_max.rpt
+report_checks -unique -slack_max -0.0 -path_delay max -group_count 100 -corner bc -format full_clock_expanded >> reports/$::env(STA_MODE)/timing_ff_max.rpt
+report_checks -group_count 100 -path_delay max -path_group wbm_clk_i -corner bc -format full_clock_expanded >> reports/$::env(STA_MODE)/timing_ff_max.rpt
+report_checks -group_count 100 -path_delay max -path_group wbs_clk_i -corner bc -format full_clock_expanded >> reports/$::env(STA_MODE)/timing_ff_max.rpt
+report_checks -group_count 100 -path_delay max -path_group lbist_clk -corner bc -format full_clock_expanded >> reports/$::env(STA_MODE)/timing_ff_max.rpt
+report_checks -path_delay max -corner bc >> reports/$::env(STA_MODE)/timing_ff_max.rpt
+
+echo "################ CORNER : BC (MIN) TIMING Report ###################" > reports/$::env(STA_MODE)/timing_ff_min.rpt
+report_checks -unique -slack_max -0.0 -path_delay min -group_count 100 -corner bc -format full_clock_expanded >> reports/$::env(STA_MODE)/timing_ff_min.rpt
+report_checks -group_count 100 -path_delay min -path_group wbm_clk_i -corner bc -format full_clock_expanded >> reports/$::env(STA_MODE)/timing_ff_min.rpt
+report_checks -group_count 100 -path_delay min -path_group wbs_clk_i -corner bc -format full_clock_expanded >> reports/$::env(STA_MODE)/timing_ff_min.rpt
+report_checks -group_count 100 -path_delay min -path_group lbist_clk -corner bc -format full_clock_expanded >> reports/$::env(STA_MODE)/timing_ff_min.rpt
+report_checks -path_delay min -corner bc >> reports/$::env(STA_MODE)/timing_ff_min.rpt
+
+
+echo "################ CORNER : TT (MAX) TIMING Report ###################" > reports/$::env(STA_MODE)/timing_tt_max.rpt
+report_checks -unique -slack_max -0.0 -path_delay max -group_count 100 -corner tt -format full_clock_expanded >> reports/$::env(STA_MODE)/timing_tt_max.rpt
+report_checks -group_count 100 -path_delay max -path_group wbm_clk_i -corner tt -format full_clock_expanded >> reports/$::env(STA_MODE)/timing_tt_max.rpt
+report_checks -group_count 100 -path_delay max -path_group wbs_clk_i -corner tt -format full_clock_expanded >> reports/$::env(STA_MODE)/timing_tt_max.rpt
+report_checks -group_count 100 -path_delay max -path_group lbist_clk -corner tt -format full_clock_expanded >> reports/$::env(STA_MODE)/timing_tt_max.rpt
+report_checks -path_delay max -corner tt >> reports/$::env(STA_MODE)/timing_tt_max.rpt
+
+echo "################ CORNER : TT (MIN) TIMING Report ###################" > reports/$::env(STA_MODE)/timing_tt_min.rpt
+report_checks -unique -slack_max -0.0 -path_delay min -group_count 100 -corner tt -format full_clock_expanded >> reports/$::env(STA_MODE)/timing_tt_min.rpt
+report_checks -group_count 100 -path_delay min -path_group wbm_clk_i -corner tt -format full_clock_expanded >> reports/$::env(STA_MODE)/timing_tt_min.rpt
+report_checks -group_count 100 -path_delay min -path_group wbs_clk_i -corner tt -format full_clock_expanded >> reports/$::env(STA_MODE)/timing_tt_min.rpt
+report_checks -group_count 100 -path_delay min -path_group lbist_clk -corner tt -format full_clock_expanded >> reports/$::env(STA_MODE)/timing_tt_min.rpt
+report_checks -path_delay min -corner tt >> reports/$::env(STA_MODE)/timing_tt_min.rpt
+
+
+report_checks -path_delay min_max
+
+exit
diff --git a/openlane/wb_interconnect/base.sdc b/openlane/wb_interconnect/base.sdc
new file mode 100644
index 0000000..a97c50d
--- /dev/null
+++ b/openlane/wb_interconnect/base.sdc
@@ -0,0 +1,192 @@
+###############################################################################
+# Created by write_sdc
+# Fri Nov 12 05:00:05 2021
+###############################################################################
+current_design wb_interconnect
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name clk_i -period 10.0000 [get_ports {clk_i}]
+set_clock_uncertainty -rise_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}] -hold 0.2500
+set_clock_uncertainty -rise_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}] -setup 0.2500
+set_clock_uncertainty -rise_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}] -hold 0.2500
+set_clock_uncertainty -rise_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}] -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}] -hold 0.2500
+set_clock_uncertainty -fall_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}] -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}] -hold 0.2500
+set_clock_uncertainty -fall_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}] -setup 0.2500
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+set_case_analysis 0 [get_ports {cfg_cska_wi[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_wi[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_wi[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_wi[3]}]
+
+#Static Signal Clock Skew adjustment
+set_false_path -from [get_ports {cfg_cska_wi[0]}]
+set_false_path -from [get_ports {cfg_cska_wi[1]}]
+set_false_path -from [get_ports {cfg_cska_wi[2]}]
+set_false_path -from [get_ports {cfg_cska_wi[3]}]
+
+# Set max delay for clock skew
+set_max_delay 3.5 -from [get_ports {wbd_clk_int}]
+set_max_delay 2 -to [get_ports {wbd_clk_wi}]
+set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_wi
+##
+set_input_delay -max 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {rst_n}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_sel_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s4_wbd_dat_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s4_wbd_dat_i[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_sel_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s4_wbd_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s4_wbd_dat_i[*]}]
+
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_ack_o}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_err_o}]
+
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_cyc_o}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_sel_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_we_o}]
+
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_cyc_o}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_sel_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_we_o}]
+
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_cyc_o}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_sel_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_we_o}]
+
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_cyc_o}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_sel_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_we_o}]
+
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s4_wbd_adr_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s4_wbd_cyc_o}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s4_wbd_dat_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s4_wbd_sel_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s4_wbd_we_o}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_ack_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_err_o}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_cyc_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_cyc_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_cyc_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_cyc_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s4_wbd_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s4_wbd_cyc_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s4_wbd_dat_o[*]}]
+
+
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {m0_wbd_ack_o}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_err_o}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_cyc_o}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_stb_o}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_we_o}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_cyc_o}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_stb_o}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_we_o}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_cyc_o}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_stb_o}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_we_o}]
+set_load -pin_load 0.0334 [get_ports {s3_wbd_cyc_o}]
+set_load -pin_load 0.0334 [get_ports {s3_wbd_stb_o}]
+set_load -pin_load 0.0334 [get_ports {s3_wbd_we_o}]
+set_load -pin_load 0.0334 [get_ports {s4_wbd_cyc_o}]
+set_load -pin_load 0.0334 [get_ports {s4_wbd_stb_o}]
+set_load -pin_load 0.0334 [get_ports {s4_wbd_we_o}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_wi}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[*]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[*]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[*]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_sel_o[*]}]
+
+set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[*]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[*]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[*]}]
+
+set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[*]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[*]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_sel_o[*]}]
+
+set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[*]}]
+set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[*]}]
+set_load -pin_load 0.0334 [get_ports {s3_wbd_sel_o[*]}]
+
+set_load -pin_load 0.0334 [get_ports {s4_wbd_adr_o[*]}]
+set_load -pin_load 0.0334 [get_ports {s4_wbd_dat_o[*]}]
+set_load -pin_load 0.0334 [get_ports {s4_wbd_sel_o[*]}]
+
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clk_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_stb_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s4_wbd_dat_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s4_wbd_ack_i}]
+###############################################################################
+# Design Rules
+###############################################################################
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
new file mode 100755
index 0000000..6e1de03
--- /dev/null
+++ b/openlane/wb_interconnect/config.tcl
@@ -0,0 +1,120 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+set ::env(DESIGN_NAME) wb_interconnect
+
+
+set ::env(DESIGN_IS_CORE) "0"
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "clk_i"
+
+set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+ $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/wb_stagging.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/wb_interconnect/src/wb_interconnect.sv \
+ "
+
+set ::env(SYNTH_PARAMETERS) "SCW=8 \
+ CH_CLK_WD=9\
+ CH_DATA_WD=104 \
+ "
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+set ::env(SDC_FILE) "$::env(DESIGN_DIR)/base.sdc"
+set ::env(BASE_SDC_FILE) "$::env(DESIGN_DIR)/base.sdc"
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+set ::env(SCAN_TOTAL_CHAINS) 8
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 200 2300"
+
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
+
+#set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(FP_CORE_UTIL) "50"
+set ::env(PL_TARGET_DENSITY) "0.50"
+
+# helps in anteena fix
+set ::env(USE_ARC_ANTENNA_CHECK) "1"
+
+set ::env(FP_IO_VEXTEND) 4
+set ::env(FP_IO_HEXTEND) 4
+
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 6.2
+set ::env(FP_PDN_HWIDTH) 6.2
+
+#set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
+
+#Lef
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
+
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
+
+set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {0.25}
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) {0.25}
+
+set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {500}
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {500}
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "1"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/wb_interconnect/pdn.tcl b/openlane/wb_interconnect/pdn.tcl
new file mode 100644
index 0000000..1fe689b
--- /dev/null
+++ b/openlane/wb_interconnect/pdn.tcl
@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+ name grid
+ rails {
+ met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+ }
+ straps {
+ met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+ met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+ }
+ connect {{met1 met4} {met4 met5}}
+}
+
+pdngen::specify_grid macro {
+ power_pins "VPWR"
+ ground_pins "VGND"
+ blockages "li1 met1 met2 met3 met4"
+ straps {
+ }
+ connect {{met4_PIN_ver met5}}
+}
+
+set ::halo 5
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
new file mode 100644
index 0000000..18c6b9a
--- /dev/null
+++ b/openlane/wb_interconnect/pin_order.cfg
@@ -0,0 +1,1135 @@
+#BUS_SORT
+
+#MANUAL_PLACE
+
+#S
+m0_wbd_stb_i 0000 0 2
+m0_wbd_we_i
+m0_wbd_adr_i\[31\]
+m0_wbd_adr_i\[30\]
+m0_wbd_adr_i\[29\]
+m0_wbd_adr_i\[28\]
+m0_wbd_adr_i\[27\]
+m0_wbd_adr_i\[26\]
+m0_wbd_adr_i\[25\]
+m0_wbd_adr_i\[24\]
+m0_wbd_adr_i\[23\]
+m0_wbd_adr_i\[22\]
+m0_wbd_adr_i\[21\]
+m0_wbd_adr_i\[20\]
+m0_wbd_adr_i\[19\]
+m0_wbd_adr_i\[18\]
+m0_wbd_adr_i\[17\]
+m0_wbd_adr_i\[16\]
+m0_wbd_adr_i\[15\]
+m0_wbd_adr_i\[14\]
+m0_wbd_adr_i\[13\]
+m0_wbd_adr_i\[12\]
+m0_wbd_adr_i\[11\]
+m0_wbd_adr_i\[10\]
+m0_wbd_adr_i\[9\]
+m0_wbd_adr_i\[8\]
+m0_wbd_adr_i\[7\]
+m0_wbd_adr_i\[6\]
+m0_wbd_adr_i\[5\]
+m0_wbd_adr_i\[4\]
+m0_wbd_adr_i\[3\]
+m0_wbd_adr_i\[2\]
+m0_wbd_adr_i\[1\]
+m0_wbd_adr_i\[0\]
+m0_wbd_sel_i\[3\]
+m0_wbd_sel_i\[2\]
+m0_wbd_sel_i\[1\]
+m0_wbd_sel_i\[0\]
+m0_wbd_dat_i\[31\]
+m0_wbd_dat_i\[30\]
+m0_wbd_dat_i\[29\]
+m0_wbd_dat_i\[28\]
+m0_wbd_dat_i\[27\]
+m0_wbd_dat_i\[26\]
+m0_wbd_dat_i\[25\]
+m0_wbd_dat_i\[24\]
+m0_wbd_dat_i\[23\]
+m0_wbd_dat_i\[22\]
+m0_wbd_dat_i\[21\]
+m0_wbd_dat_i\[20\]
+m0_wbd_dat_i\[19\]
+m0_wbd_dat_i\[18\]
+m0_wbd_dat_i\[17\]
+m0_wbd_dat_i\[16\]
+m0_wbd_dat_i\[15\]
+m0_wbd_dat_i\[14\]
+m0_wbd_dat_i\[13\]
+m0_wbd_dat_i\[12\]
+m0_wbd_dat_i\[11\]
+m0_wbd_dat_i\[10\]
+m0_wbd_dat_i\[9\]
+m0_wbd_dat_i\[8\]
+m0_wbd_dat_i\[7\]
+m0_wbd_dat_i\[6\]
+m0_wbd_dat_i\[5\]
+m0_wbd_dat_i\[4\]
+m0_wbd_dat_i\[3\]
+m0_wbd_dat_i\[2\]
+m0_wbd_dat_i\[1\]
+m0_wbd_dat_i\[0\]
+m0_wbd_dat_o\[31\]
+m0_wbd_dat_o\[30\]
+m0_wbd_dat_o\[29\]
+m0_wbd_dat_o\[28\]
+m0_wbd_dat_o\[27\]
+m0_wbd_dat_o\[26\]
+m0_wbd_dat_o\[25\]
+m0_wbd_dat_o\[24\]
+m0_wbd_dat_o\[23\]
+m0_wbd_dat_o\[22\]
+m0_wbd_dat_o\[21\]
+m0_wbd_dat_o\[20\]
+m0_wbd_dat_o\[19\]
+m0_wbd_dat_o\[18\]
+m0_wbd_dat_o\[17\]
+m0_wbd_dat_o\[16\]
+m0_wbd_dat_o\[15\]
+m0_wbd_dat_o\[14\]
+m0_wbd_dat_o\[13\]
+m0_wbd_dat_o\[12\]
+m0_wbd_dat_o\[11\]
+m0_wbd_dat_o\[10\]
+m0_wbd_dat_o\[9\]
+m0_wbd_dat_o\[8\]
+m0_wbd_dat_o\[7\]
+m0_wbd_dat_o\[6\]
+m0_wbd_dat_o\[5\]
+m0_wbd_dat_o\[4\]
+m0_wbd_dat_o\[3\]
+m0_wbd_dat_o\[2\]
+m0_wbd_dat_o\[1\]
+m0_wbd_dat_o\[0\]
+m0_wbd_ack_o
+m0_wbd_err_o
+m0_wbd_cyc_i
+
+rst_n 110 0 2
+cfg_cska_wi\[3\]
+cfg_cska_wi\[2\]
+cfg_cska_wi\[1\]
+cfg_cska_wi\[0\]
+clk_i
+wbd_clk_wi
+wbd_clk_int
+ch_clk_in\[8\]
+ch_clk_in\[7\]
+ch_clk_in\[6\]
+ch_clk_in\[5\]
+ch_clk_in\[4\]
+ch_clk_in\[3\]
+ch_clk_in\[2\]
+ch_clk_in\[1\]
+ch_clk_in\[0\]
+
+
+#W
+ch_clk_out\[0\] 0025 0 2
+s0_wbd_cyc_o
+s0_wbd_stb_o
+s0_wbd_we_o
+s0_wbd_adr_o\[7\]
+s0_wbd_adr_o\[6\]
+s0_wbd_adr_o\[5\]
+s0_wbd_adr_o\[4\]
+s0_wbd_adr_o\[3\]
+s0_wbd_adr_o\[2\]
+s0_wbd_adr_o\[1\]
+s0_wbd_adr_o\[0\]
+s0_wbd_sel_o\[3\]
+s0_wbd_sel_o\[2\]
+s0_wbd_sel_o\[1\]
+s0_wbd_sel_o\[0\]
+s0_wbd_dat_o\[31\]
+s0_wbd_dat_o\[30\]
+s0_wbd_dat_o\[29\]
+s0_wbd_dat_o\[28\]
+s0_wbd_dat_o\[27\]
+s0_wbd_dat_o\[26\]
+s0_wbd_dat_o\[25\]
+s0_wbd_dat_o\[24\]
+s0_wbd_dat_o\[23\]
+s0_wbd_dat_o\[22\]
+s0_wbd_dat_o\[21\]
+s0_wbd_dat_o\[20\]
+s0_wbd_dat_o\[19\]
+s0_wbd_dat_o\[18\]
+s0_wbd_dat_o\[17\]
+s0_wbd_dat_o\[16\]
+s0_wbd_dat_o\[15\]
+s0_wbd_dat_o\[14\]
+s0_wbd_dat_o\[13\]
+s0_wbd_dat_o\[12\]
+s0_wbd_dat_o\[11\]
+s0_wbd_dat_o\[10\]
+s0_wbd_dat_o\[9\]
+s0_wbd_dat_o\[8\]
+s0_wbd_dat_o\[7\]
+s0_wbd_dat_o\[6\]
+s0_wbd_dat_o\[5\]
+s0_wbd_dat_o\[4\]
+s0_wbd_dat_o\[3\]
+s0_wbd_dat_o\[2\]
+s0_wbd_dat_o\[1\]
+s0_wbd_dat_o\[0\]
+s0_wbd_dat_i\[31\]
+s0_wbd_dat_i\[30\]
+s0_wbd_dat_i\[29\]
+s0_wbd_dat_i\[28\]
+s0_wbd_dat_i\[27\]
+s0_wbd_dat_i\[26\]
+s0_wbd_dat_i\[25\]
+s0_wbd_dat_i\[24\]
+s0_wbd_dat_i\[23\]
+s0_wbd_dat_i\[22\]
+s0_wbd_dat_i\[21\]
+s0_wbd_dat_i\[20\]
+s0_wbd_dat_i\[19\]
+s0_wbd_dat_i\[18\]
+s0_wbd_dat_i\[17\]
+s0_wbd_dat_i\[16\]
+s0_wbd_dat_i\[15\]
+s0_wbd_dat_i\[14\]
+s0_wbd_dat_i\[13\]
+s0_wbd_dat_i\[12\]
+s0_wbd_dat_i\[11\]
+s0_wbd_dat_i\[10\]
+s0_wbd_dat_i\[9\]
+s0_wbd_dat_i\[8\]
+s0_wbd_dat_i\[7\]
+s0_wbd_dat_i\[6\]
+s0_wbd_dat_i\[5\]
+s0_wbd_dat_i\[4\]
+s0_wbd_dat_i\[3\]
+s0_wbd_dat_i\[2\]
+s0_wbd_dat_i\[1\]
+s0_wbd_dat_i\[0\]
+s0_wbd_ack_i
+
+ch_data_in\[0\] 0150 0 2
+ch_data_in\[1\]
+ch_data_in\[2\]
+ch_data_in\[3\]
+ch_data_in\[4\]
+ch_data_out\[5\]
+ch_data_out\[6\]
+ch_data_out\[7\]
+ch_data_out\[8\]
+ch_data_out\[9\]
+ch_data_out\[10\]
+ch_data_out\[11\]
+ch_data_out\[12\]
+
+ch_data_in\[13\]
+ch_data_in\[14\]
+ch_data_in\[15\]
+ch_data_in\[16\]
+ch_data_in\[17\]
+ch_data_out\[18\]
+ch_data_out\[19\]
+ch_data_out\[20\]
+ch_data_out\[21\]
+ch_data_out\[22\]
+ch_data_out\[23\]
+ch_data_out\[24\]
+ch_data_out\[25\]
+
+ch_data_in\[26\]
+ch_data_in\[27\]
+ch_data_in\[28\]
+ch_data_in\[29\]
+ch_data_in\[30\]
+ch_data_out\[31\]
+ch_data_out\[32\]
+ch_data_out\[33\]
+ch_data_out\[34\]
+ch_data_out\[35\]
+ch_data_out\[36\]
+ch_data_out\[37\]
+ch_data_out\[38\]
+
+ch_data_in\[39\]
+ch_data_in\[40\]
+ch_data_in\[41\]
+ch_data_in\[42\]
+ch_data_in\[43\]
+ch_data_out\[44\]
+ch_data_out\[45\]
+ch_data_out\[46\]
+ch_data_out\[47\]
+ch_data_out\[48\]
+ch_data_out\[49\]
+ch_data_out\[50\]
+ch_data_out\[51\]
+
+ch_data_in\[52\]
+ch_data_in\[53\]
+ch_data_in\[54\]
+ch_data_in\[55\]
+ch_data_in\[56\]
+ch_data_out\[57\]
+ch_data_out\[58\]
+ch_data_out\[59\]
+ch_data_out\[60\]
+ch_data_out\[61\]
+ch_data_out\[62\]
+ch_data_out\[63\]
+ch_data_out\[64\]
+
+ch_data_in\[65\]
+ch_data_in\[66\]
+ch_data_in\[67\]
+ch_data_in\[68\]
+ch_data_in\[69\]
+ch_data_out\[70\]
+ch_data_out\[71\]
+ch_data_out\[72\]
+ch_data_out\[73\]
+ch_data_out\[74\]
+ch_data_out\[75\]
+ch_data_out\[76\]
+ch_data_out\[77\]
+
+ch_data_in\[78\]
+ch_data_in\[79\]
+ch_data_in\[80\]
+ch_data_in\[81\]
+ch_data_in\[82\]
+ch_data_out\[83\]
+ch_data_out\[84\]
+ch_data_out\[85\]
+ch_data_out\[86\]
+ch_data_out\[87\]
+ch_data_out\[88\]
+ch_data_out\[89\]
+ch_data_out\[90\]
+
+ch_data_in\[91\]
+ch_data_in\[92\]
+ch_data_in\[93\]
+ch_data_in\[94\]
+ch_data_in\[95\]
+ch_data_out\[96\]
+ch_data_out\[97\]
+ch_data_out\[98\]
+ch_data_out\[99\]
+ch_data_out\[100\]
+ch_data_out\[101\]
+ch_data_out\[102\]
+ch_data_out\[103\]
+
+ch_clk_out\[5\] 0525 0 2
+s5_wbd_cyc_o
+s5_wbd_stb_o
+s5_wbd_we_o
+s5_wbd_adr_o\[9\]
+s5_wbd_adr_o\[8\]
+s5_wbd_adr_o\[7\]
+s5_wbd_adr_o\[6\]
+s5_wbd_adr_o\[5\]
+s5_wbd_adr_o\[4\]
+s5_wbd_adr_o\[3\]
+s5_wbd_adr_o\[2\]
+s5_wbd_adr_o\[1\]
+s5_wbd_adr_o\[0\]
+s5_wbd_dat_o\[31\]
+s5_wbd_dat_o\[30\]
+s5_wbd_dat_o\[29\]
+s5_wbd_dat_o\[28\]
+s5_wbd_dat_o\[27\]
+s5_wbd_dat_o\[26\]
+s5_wbd_dat_o\[25\]
+s5_wbd_dat_o\[24\]
+s5_wbd_dat_o\[23\]
+s5_wbd_dat_o\[22\]
+s5_wbd_dat_o\[21\]
+s5_wbd_dat_o\[20\]
+s5_wbd_dat_o\[19\]
+s5_wbd_dat_o\[18\]
+s5_wbd_dat_o\[17\]
+s5_wbd_dat_o\[16\]
+s5_wbd_dat_o\[15\]
+s5_wbd_dat_o\[14\]
+s5_wbd_dat_o\[13\]
+s5_wbd_dat_o\[12\]
+s5_wbd_dat_o\[11\]
+s5_wbd_dat_o\[10\]
+s5_wbd_dat_o\[9\]
+s5_wbd_dat_o\[8\]
+s5_wbd_dat_o\[7\]
+s5_wbd_dat_o\[6\]
+s5_wbd_dat_o\[5\]
+s5_wbd_dat_o\[4\]
+s5_wbd_dat_o\[3\]
+s5_wbd_dat_o\[2\]
+s5_wbd_dat_o\[1\]
+s5_wbd_dat_o\[0\]
+s5_wbd_sel_o\[3\]
+s5_wbd_sel_o\[2\]
+s5_wbd_sel_o\[1\]
+s5_wbd_sel_o\[0\]
+s5_wbd_dat_i\[31\]
+s5_wbd_dat_i\[30\]
+s5_wbd_dat_i\[29\]
+s5_wbd_dat_i\[28\]
+s5_wbd_dat_i\[27\]
+s5_wbd_dat_i\[26\]
+s5_wbd_dat_i\[25\]
+s5_wbd_dat_i\[24\]
+s5_wbd_dat_i\[23\]
+s5_wbd_dat_i\[22\]
+s5_wbd_dat_i\[21\]
+s5_wbd_dat_i\[20\]
+s5_wbd_dat_i\[19\]
+s5_wbd_dat_i\[18\]
+s5_wbd_dat_i\[17\]
+s5_wbd_dat_i\[16\]
+s5_wbd_dat_i\[15\]
+s5_wbd_dat_i\[14\]
+s5_wbd_dat_i\[13\]
+s5_wbd_dat_i\[12\]
+s5_wbd_dat_i\[11\]
+s5_wbd_dat_i\[10\]
+s5_wbd_dat_i\[9\]
+s5_wbd_dat_i\[8\]
+s5_wbd_dat_i\[7\]
+s5_wbd_dat_i\[6\]
+s5_wbd_dat_i\[5\]
+s5_wbd_dat_i\[4\]
+s5_wbd_dat_i\[3\]
+s5_wbd_dat_i\[2\]
+s5_wbd_dat_i\[1\]
+s5_wbd_dat_i\[0\]
+s5_wbd_ack_i
+
+ch_data_out\[52\] 0650 0 2
+ch_data_out\[53\]
+ch_data_out\[54\]
+ch_data_out\[55\]
+ch_data_out\[56\]
+ch_data_in\[57\]
+ch_data_in\[58\]
+ch_data_in\[59\]
+ch_data_in\[60\]
+ch_data_in\[61\]
+ch_data_in\[62\]
+ch_data_in\[63\]
+ch_data_in\[64\]
+
+ch_clk_out\[6\] 1025 0 2
+s6_wbd_cyc_o
+s6_wbd_stb_o
+s6_wbd_we_o
+s6_wbd_adr_o\[9\]
+s6_wbd_adr_o\[8\]
+s6_wbd_adr_o\[7\]
+s6_wbd_adr_o\[6\]
+s6_wbd_adr_o\[5\]
+s6_wbd_adr_o\[4\]
+s6_wbd_adr_o\[3\]
+s6_wbd_adr_o\[2\]
+s6_wbd_adr_o\[1\]
+s6_wbd_adr_o\[0\]
+s6_wbd_dat_o\[31\]
+s6_wbd_dat_o\[30\]
+s6_wbd_dat_o\[29\]
+s6_wbd_dat_o\[28\]
+s6_wbd_dat_o\[27\]
+s6_wbd_dat_o\[26\]
+s6_wbd_dat_o\[25\]
+s6_wbd_dat_o\[24\]
+s6_wbd_dat_o\[23\]
+s6_wbd_dat_o\[22\]
+s6_wbd_dat_o\[21\]
+s6_wbd_dat_o\[20\]
+s6_wbd_dat_o\[19\]
+s6_wbd_dat_o\[18\]
+s6_wbd_dat_o\[17\]
+s6_wbd_dat_o\[16\]
+s6_wbd_dat_o\[15\]
+s6_wbd_dat_o\[14\]
+s6_wbd_dat_o\[13\]
+s6_wbd_dat_o\[12\]
+s6_wbd_dat_o\[11\]
+s6_wbd_dat_o\[10\]
+s6_wbd_dat_o\[9\]
+s6_wbd_dat_o\[8\]
+s6_wbd_dat_o\[7\]
+s6_wbd_dat_o\[6\]
+s6_wbd_dat_o\[5\]
+s6_wbd_dat_o\[4\]
+s6_wbd_dat_o\[3\]
+s6_wbd_dat_o\[2\]
+s6_wbd_dat_o\[1\]
+s6_wbd_dat_o\[0\]
+s6_wbd_sel_o\[3\]
+s6_wbd_sel_o\[2\]
+s6_wbd_sel_o\[1\]
+s6_wbd_sel_o\[0\]
+s6_wbd_dat_i\[31\]
+s6_wbd_dat_i\[30\]
+s6_wbd_dat_i\[29\]
+s6_wbd_dat_i\[28\]
+s6_wbd_dat_i\[27\]
+s6_wbd_dat_i\[26\]
+s6_wbd_dat_i\[25\]
+s6_wbd_dat_i\[24\]
+s6_wbd_dat_i\[23\]
+s6_wbd_dat_i\[22\]
+s6_wbd_dat_i\[21\]
+s6_wbd_dat_i\[20\]
+s6_wbd_dat_i\[19\]
+s6_wbd_dat_i\[18\]
+s6_wbd_dat_i\[17\]
+s6_wbd_dat_i\[16\]
+s6_wbd_dat_i\[15\]
+s6_wbd_dat_i\[14\]
+s6_wbd_dat_i\[13\]
+s6_wbd_dat_i\[12\]
+s6_wbd_dat_i\[11\]
+s6_wbd_dat_i\[10\]
+s6_wbd_dat_i\[9\]
+s6_wbd_dat_i\[8\]
+s6_wbd_dat_i\[7\]
+s6_wbd_dat_i\[6\]
+s6_wbd_dat_i\[5\]
+s6_wbd_dat_i\[4\]
+s6_wbd_dat_i\[3\]
+s6_wbd_dat_i\[2\]
+s6_wbd_dat_i\[1\]
+s6_wbd_dat_i\[0\]
+s6_wbd_ack_i
+
+ch_data_out\[65\] 1150 0 2
+ch_data_out\[66\]
+ch_data_out\[67\]
+ch_data_out\[68\]
+ch_data_out\[69\]
+ch_data_in\[70\]
+ch_data_in\[71\]
+ch_data_in\[72\]
+ch_data_in\[73\]
+ch_data_in\[74\]
+ch_data_in\[75\]
+ch_data_in\[76\]
+ch_data_in\[77\]
+
+ch_clk_out\[7\] 1525 0 2
+s7_wbd_cyc_o
+s7_wbd_stb_o
+s7_wbd_we_o
+s7_wbd_adr_o\[9\]
+s7_wbd_adr_o\[8\]
+s7_wbd_adr_o\[7\]
+s7_wbd_adr_o\[6\]
+s7_wbd_adr_o\[5\]
+s7_wbd_adr_o\[4\]
+s7_wbd_adr_o\[3\]
+s7_wbd_adr_o\[2\]
+s7_wbd_adr_o\[1\]
+s7_wbd_adr_o\[0\]
+s7_wbd_dat_o\[31\]
+s7_wbd_dat_o\[30\]
+s7_wbd_dat_o\[29\]
+s7_wbd_dat_o\[28\]
+s7_wbd_dat_o\[27\]
+s7_wbd_dat_o\[26\]
+s7_wbd_dat_o\[25\]
+s7_wbd_dat_o\[24\]
+s7_wbd_dat_o\[23\]
+s7_wbd_dat_o\[22\]
+s7_wbd_dat_o\[21\]
+s7_wbd_dat_o\[20\]
+s7_wbd_dat_o\[19\]
+s7_wbd_dat_o\[18\]
+s7_wbd_dat_o\[17\]
+s7_wbd_dat_o\[16\]
+s7_wbd_dat_o\[15\]
+s7_wbd_dat_o\[14\]
+s7_wbd_dat_o\[13\]
+s7_wbd_dat_o\[12\]
+s7_wbd_dat_o\[11\]
+s7_wbd_dat_o\[10\]
+s7_wbd_dat_o\[9\]
+s7_wbd_dat_o\[8\]
+s7_wbd_dat_o\[7\]
+s7_wbd_dat_o\[6\]
+s7_wbd_dat_o\[5\]
+s7_wbd_dat_o\[4\]
+s7_wbd_dat_o\[3\]
+s7_wbd_dat_o\[2\]
+s7_wbd_dat_o\[1\]
+s7_wbd_dat_o\[0\]
+s7_wbd_sel_o\[3\]
+s7_wbd_sel_o\[2\]
+s7_wbd_sel_o\[1\]
+s7_wbd_sel_o\[0\]
+s7_wbd_dat_i\[31\]
+s7_wbd_dat_i\[30\]
+s7_wbd_dat_i\[29\]
+s7_wbd_dat_i\[28\]
+s7_wbd_dat_i\[27\]
+s7_wbd_dat_i\[26\]
+s7_wbd_dat_i\[25\]
+s7_wbd_dat_i\[24\]
+s7_wbd_dat_i\[23\]
+s7_wbd_dat_i\[22\]
+s7_wbd_dat_i\[21\]
+s7_wbd_dat_i\[20\]
+s7_wbd_dat_i\[19\]
+s7_wbd_dat_i\[18\]
+s7_wbd_dat_i\[17\]
+s7_wbd_dat_i\[16\]
+s7_wbd_dat_i\[15\]
+s7_wbd_dat_i\[14\]
+s7_wbd_dat_i\[13\]
+s7_wbd_dat_i\[12\]
+s7_wbd_dat_i\[11\]
+s7_wbd_dat_i\[10\]
+s7_wbd_dat_i\[9\]
+s7_wbd_dat_i\[8\]
+s7_wbd_dat_i\[7\]
+s7_wbd_dat_i\[6\]
+s7_wbd_dat_i\[5\]
+s7_wbd_dat_i\[4\]
+s7_wbd_dat_i\[3\]
+s7_wbd_dat_i\[2\]
+s7_wbd_dat_i\[1\]
+s7_wbd_dat_i\[0\]
+s7_wbd_ack_i
+
+ch_data_out\[78\] 1650 0 2
+ch_data_out\[79\]
+ch_data_out\[80\]
+ch_data_out\[81\]
+ch_data_out\[82\]
+ch_data_in\[83\]
+ch_data_in\[84\]
+ch_data_in\[85\]
+ch_data_in\[86\]
+ch_data_in\[87\]
+ch_data_in\[88\]
+ch_data_in\[89\]
+ch_data_in\[90\]
+
+ch_clk_out\[8\] 2025 0 2
+s8_wbd_stb_o
+s8_wbd_we_o
+s8_wbd_adr_o\[9\]
+s8_wbd_adr_o\[8\]
+s8_wbd_adr_o\[7\]
+s8_wbd_adr_o\[6\]
+s8_wbd_adr_o\[5\]
+s8_wbd_adr_o\[4\]
+s8_wbd_adr_o\[3\]
+s8_wbd_adr_o\[2\]
+s8_wbd_adr_o\[1\]
+s8_wbd_adr_o\[0\]
+s8_wbd_dat_o\[31\]
+s8_wbd_dat_o\[30\]
+s8_wbd_dat_o\[29\]
+s8_wbd_dat_o\[28\]
+s8_wbd_dat_o\[27\]
+s8_wbd_dat_o\[26\]
+s8_wbd_dat_o\[25\]
+s8_wbd_dat_o\[24\]
+s8_wbd_dat_o\[23\]
+s8_wbd_dat_o\[22\]
+s8_wbd_dat_o\[21\]
+s8_wbd_dat_o\[20\]
+s8_wbd_dat_o\[19\]
+s8_wbd_dat_o\[18\]
+s8_wbd_dat_o\[17\]
+s8_wbd_dat_o\[16\]
+s8_wbd_dat_o\[15\]
+s8_wbd_dat_o\[14\]
+s8_wbd_dat_o\[13\]
+s8_wbd_dat_o\[12\]
+s8_wbd_dat_o\[11\]
+s8_wbd_dat_o\[10\]
+s8_wbd_dat_o\[9\]
+s8_wbd_dat_o\[8\]
+s8_wbd_dat_o\[7\]
+s8_wbd_dat_o\[6\]
+s8_wbd_dat_o\[5\]
+s8_wbd_dat_o\[4\]
+s8_wbd_dat_o\[3\]
+s8_wbd_dat_o\[2\]
+s8_wbd_dat_o\[1\]
+s8_wbd_dat_o\[0\]
+s8_wbd_sel_o\[3\]
+s8_wbd_sel_o\[2\]
+s8_wbd_sel_o\[1\]
+s8_wbd_sel_o\[0\]
+s8_wbd_dat_i\[31\]
+s8_wbd_dat_i\[30\]
+s8_wbd_dat_i\[29\]
+s8_wbd_dat_i\[28\]
+s8_wbd_dat_i\[27\]
+s8_wbd_dat_i\[26\]
+s8_wbd_dat_i\[25\]
+s8_wbd_dat_i\[24\]
+s8_wbd_dat_i\[23\]
+s8_wbd_dat_i\[22\]
+s8_wbd_dat_i\[21\]
+s8_wbd_dat_i\[20\]
+s8_wbd_dat_i\[19\]
+s8_wbd_dat_i\[18\]
+s8_wbd_dat_i\[17\]
+s8_wbd_dat_i\[16\]
+s8_wbd_dat_i\[15\]
+s8_wbd_dat_i\[14\]
+s8_wbd_dat_i\[13\]
+s8_wbd_dat_i\[12\]
+s8_wbd_dat_i\[11\]
+s8_wbd_dat_i\[10\]
+s8_wbd_dat_i\[9\]
+s8_wbd_dat_i\[8\]
+s8_wbd_dat_i\[7\]
+s8_wbd_dat_i\[6\]
+s8_wbd_dat_i\[5\]
+s8_wbd_dat_i\[4\]
+s8_wbd_dat_i\[3\]
+s8_wbd_dat_i\[2\]
+s8_wbd_dat_i\[1\]
+s8_wbd_dat_i\[0\]
+s8_wbd_ack_i
+s8_wbd_cyc_o
+
+ch_data_out\[91\] 2150 0 2
+ch_data_out\[92\]
+ch_data_out\[93\]
+ch_data_out\[94\]
+ch_data_out\[95\]
+ch_data_in\[96\]
+ch_data_in\[97\]
+ch_data_in\[98\]
+ch_data_in\[99\]
+ch_data_in\[100\]
+ch_data_in\[101\]
+ch_data_in\[102\]
+ch_data_in\[103\]
+
+scan_mode 2200 0 2
+scan_en
+scan_si\[7\]
+scan_si\[6\]
+scan_si\[5\]
+scan_si\[4\]
+scan_si\[3\]
+scan_si\[2\]
+scan_si\[1\]
+scan_si\[0\]
+
+#E
+ch_clk_out\[1\] 0025 0 2
+s1_wbd_cyc_o
+s1_wbd_stb_o
+s1_wbd_we_o
+s1_wbd_adr_o\[10\]
+s1_wbd_adr_o\[9\]
+s1_wbd_adr_o\[8\]
+s1_wbd_adr_o\[7\]
+s1_wbd_adr_o\[6\]
+s1_wbd_adr_o\[5\]
+s1_wbd_adr_o\[4\]
+s1_wbd_adr_o\[3\]
+s1_wbd_adr_o\[2\]
+s1_wbd_adr_o\[1\]
+s1_wbd_adr_o\[0\]
+s1_wbd_dat_o\[31\]
+s1_wbd_dat_o\[30\]
+s1_wbd_dat_o\[29\]
+s1_wbd_dat_o\[28\]
+s1_wbd_dat_o\[27\]
+s1_wbd_dat_o\[26\]
+s1_wbd_dat_o\[25\]
+s1_wbd_dat_o\[24\]
+s1_wbd_dat_o\[23\]
+s1_wbd_dat_o\[22\]
+s1_wbd_dat_o\[21\]
+s1_wbd_dat_o\[20\]
+s1_wbd_dat_o\[19\]
+s1_wbd_dat_o\[18\]
+s1_wbd_dat_o\[17\]
+s1_wbd_dat_o\[16\]
+s1_wbd_dat_o\[15\]
+s1_wbd_dat_o\[14\]
+s1_wbd_dat_o\[13\]
+s1_wbd_dat_o\[12\]
+s1_wbd_dat_o\[11\]
+s1_wbd_dat_o\[10\]
+s1_wbd_dat_o\[9\]
+s1_wbd_dat_o\[8\]
+s1_wbd_dat_o\[7\]
+s1_wbd_dat_o\[6\]
+s1_wbd_dat_o\[5\]
+s1_wbd_dat_o\[4\]
+s1_wbd_dat_o\[3\]
+s1_wbd_dat_o\[2\]
+s1_wbd_dat_o\[1\]
+s1_wbd_dat_o\[0\]
+s1_wbd_sel_o\[3\]
+s1_wbd_sel_o\[2\]
+s1_wbd_sel_o\[1\]
+s1_wbd_sel_o\[0\]
+s1_wbd_dat_i\[31\]
+s1_wbd_dat_i\[30\]
+s1_wbd_dat_i\[29\]
+s1_wbd_dat_i\[28\]
+s1_wbd_dat_i\[27\]
+s1_wbd_dat_i\[26\]
+s1_wbd_dat_i\[25\]
+s1_wbd_dat_i\[24\]
+s1_wbd_dat_i\[23\]
+s1_wbd_dat_i\[22\]
+s1_wbd_dat_i\[21\]
+s1_wbd_dat_i\[20\]
+s1_wbd_dat_i\[19\]
+s1_wbd_dat_i\[18\]
+s1_wbd_dat_i\[17\]
+s1_wbd_dat_i\[16\]
+s1_wbd_dat_i\[15\]
+s1_wbd_dat_i\[14\]
+s1_wbd_dat_i\[13\]
+s1_wbd_dat_i\[12\]
+s1_wbd_dat_i\[11\]
+s1_wbd_dat_i\[10\]
+s1_wbd_dat_i\[9\]
+s1_wbd_dat_i\[8\]
+s1_wbd_dat_i\[7\]
+s1_wbd_dat_i\[6\]
+s1_wbd_dat_i\[5\]
+s1_wbd_dat_i\[4\]
+s1_wbd_dat_i\[3\]
+s1_wbd_dat_i\[2\]
+s1_wbd_dat_i\[1\]
+s1_wbd_dat_i\[0\]
+s1_wbd_ack_i
+
+ch_data_out\[0\] 0150 0 2
+ch_data_out\[1\]
+ch_data_out\[2\]
+ch_data_out\[3\]
+ch_data_out\[4\]
+ch_data_in\[5\]
+ch_data_in\[6\]
+ch_data_in\[7\]
+ch_data_in\[8\]
+ch_data_in\[9\]
+ch_data_in\[10\]
+ch_data_in\[11\]
+ch_data_in\[12\]
+
+ch_clk_out\[2\] 625 0 2
+s2_wbd_cyc_o
+s2_wbd_stb_o
+s2_wbd_we_o
+s2_wbd_adr_o\[10\]
+s2_wbd_adr_o\[9\]
+s2_wbd_adr_o\[8\]
+s2_wbd_adr_o\[7\]
+s2_wbd_adr_o\[6\]
+s2_wbd_adr_o\[5\]
+s2_wbd_adr_o\[4\]
+s2_wbd_adr_o\[3\]
+s2_wbd_adr_o\[2\]
+s2_wbd_adr_o\[1\]
+s2_wbd_adr_o\[0\]
+s2_wbd_dat_o\[31\]
+s2_wbd_dat_o\[30\]
+s2_wbd_dat_o\[29\]
+s2_wbd_dat_o\[28\]
+s2_wbd_dat_o\[27\]
+s2_wbd_dat_o\[26\]
+s2_wbd_dat_o\[25\]
+s2_wbd_dat_o\[24\]
+s2_wbd_dat_o\[23\]
+s2_wbd_dat_o\[22\]
+s2_wbd_dat_o\[21\]
+s2_wbd_dat_o\[20\]
+s2_wbd_dat_o\[19\]
+s2_wbd_dat_o\[18\]
+s2_wbd_dat_o\[17\]
+s2_wbd_dat_o\[16\]
+s2_wbd_dat_o\[15\]
+s2_wbd_dat_o\[14\]
+s2_wbd_dat_o\[13\]
+s2_wbd_dat_o\[12\]
+s2_wbd_dat_o\[11\]
+s2_wbd_dat_o\[10\]
+s2_wbd_dat_o\[9\]
+s2_wbd_dat_o\[8\]
+s2_wbd_dat_o\[7\]
+s2_wbd_dat_o\[6\]
+s2_wbd_dat_o\[5\]
+s2_wbd_dat_o\[4\]
+s2_wbd_dat_o\[3\]
+s2_wbd_dat_o\[2\]
+s2_wbd_dat_o\[1\]
+s2_wbd_dat_o\[0\]
+s2_wbd_sel_o\[3\]
+s2_wbd_sel_o\[2\]
+s2_wbd_sel_o\[1\]
+s2_wbd_sel_o\[0\]
+s2_wbd_dat_i\[31\]
+s2_wbd_dat_i\[30\]
+s2_wbd_dat_i\[29\]
+s2_wbd_dat_i\[28\]
+s2_wbd_dat_i\[27\]
+s2_wbd_dat_i\[26\]
+s2_wbd_dat_i\[25\]
+s2_wbd_dat_i\[24\]
+s2_wbd_dat_i\[23\]
+s2_wbd_dat_i\[22\]
+s2_wbd_dat_i\[21\]
+s2_wbd_dat_i\[20\]
+s2_wbd_dat_i\[19\]
+s2_wbd_dat_i\[18\]
+s2_wbd_dat_i\[17\]
+s2_wbd_dat_i\[16\]
+s2_wbd_dat_i\[15\]
+s2_wbd_dat_i\[14\]
+s2_wbd_dat_i\[13\]
+s2_wbd_dat_i\[12\]
+s2_wbd_dat_i\[11\]
+s2_wbd_dat_i\[10\]
+s2_wbd_dat_i\[9\]
+s2_wbd_dat_i\[8\]
+s2_wbd_dat_i\[7\]
+s2_wbd_dat_i\[6\]
+s2_wbd_dat_i\[5\]
+s2_wbd_dat_i\[4\]
+s2_wbd_dat_i\[3\]
+s2_wbd_dat_i\[2\]
+s2_wbd_dat_i\[1\]
+s2_wbd_dat_i\[0\]
+s2_wbd_ack_i
+
+ch_data_out\[13\] 0750 0 2
+ch_data_out\[14\]
+ch_data_out\[15\]
+ch_data_out\[16\]
+ch_data_out\[17\]
+ch_data_in\[18\]
+ch_data_in\[19\]
+ch_data_in\[20\]
+ch_data_in\[21\]
+ch_data_in\[22\]
+ch_data_in\[23\]
+ch_data_in\[24\]
+ch_data_in\[25\]
+
+ch_clk_out\[3\] 1225 0 2
+s3_wbd_cyc_o
+s3_wbd_stb_o
+s3_wbd_we_o
+s3_wbd_adr_o\[10\]
+s3_wbd_adr_o\[9\]
+s3_wbd_adr_o\[8\]
+s3_wbd_adr_o\[7\]
+s3_wbd_adr_o\[6\]
+s3_wbd_adr_o\[5\]
+s3_wbd_adr_o\[4\]
+s3_wbd_adr_o\[3\]
+s3_wbd_adr_o\[2\]
+s3_wbd_adr_o\[1\]
+s3_wbd_adr_o\[0\]
+s3_wbd_dat_o\[31\]
+s3_wbd_dat_o\[30\]
+s3_wbd_dat_o\[29\]
+s3_wbd_dat_o\[28\]
+s3_wbd_dat_o\[27\]
+s3_wbd_dat_o\[26\]
+s3_wbd_dat_o\[25\]
+s3_wbd_dat_o\[24\]
+s3_wbd_dat_o\[23\]
+s3_wbd_dat_o\[22\]
+s3_wbd_dat_o\[21\]
+s3_wbd_dat_o\[20\]
+s3_wbd_dat_o\[19\]
+s3_wbd_dat_o\[18\]
+s3_wbd_dat_o\[17\]
+s3_wbd_dat_o\[16\]
+s3_wbd_dat_o\[15\]
+s3_wbd_dat_o\[14\]
+s3_wbd_dat_o\[13\]
+s3_wbd_dat_o\[12\]
+s3_wbd_dat_o\[11\]
+s3_wbd_dat_o\[10\]
+s3_wbd_dat_o\[9\]
+s3_wbd_dat_o\[8\]
+s3_wbd_dat_o\[7\]
+s3_wbd_dat_o\[6\]
+s3_wbd_dat_o\[5\]
+s3_wbd_dat_o\[4\]
+s3_wbd_dat_o\[3\]
+s3_wbd_dat_o\[2\]
+s3_wbd_dat_o\[1\]
+s3_wbd_dat_o\[0\]
+s3_wbd_sel_o\[3\]
+s3_wbd_sel_o\[2\]
+s3_wbd_sel_o\[1\]
+s3_wbd_sel_o\[0\]
+s3_wbd_dat_i\[31\]
+s3_wbd_dat_i\[30\]
+s3_wbd_dat_i\[29\]
+s3_wbd_dat_i\[28\]
+s3_wbd_dat_i\[27\]
+s3_wbd_dat_i\[26\]
+s3_wbd_dat_i\[25\]
+s3_wbd_dat_i\[24\]
+s3_wbd_dat_i\[23\]
+s3_wbd_dat_i\[22\]
+s3_wbd_dat_i\[21\]
+s3_wbd_dat_i\[20\]
+s3_wbd_dat_i\[19\]
+s3_wbd_dat_i\[18\]
+s3_wbd_dat_i\[17\]
+s3_wbd_dat_i\[16\]
+s3_wbd_dat_i\[15\]
+s3_wbd_dat_i\[14\]
+s3_wbd_dat_i\[13\]
+s3_wbd_dat_i\[12\]
+s3_wbd_dat_i\[11\]
+s3_wbd_dat_i\[10\]
+s3_wbd_dat_i\[9\]
+s3_wbd_dat_i\[8\]
+s3_wbd_dat_i\[7\]
+s3_wbd_dat_i\[6\]
+s3_wbd_dat_i\[5\]
+s3_wbd_dat_i\[4\]
+s3_wbd_dat_i\[3\]
+s3_wbd_dat_i\[2\]
+s3_wbd_dat_i\[1\]
+s3_wbd_dat_i\[0\]
+s3_wbd_ack_i
+
+ch_data_out\[26\] 1350 0 2
+ch_data_out\[27\]
+ch_data_out\[28\]
+ch_data_out\[29\]
+ch_data_out\[30\]
+ch_data_in\[31\]
+ch_data_in\[32\]
+ch_data_in\[33\]
+ch_data_in\[34\]
+ch_data_in\[35\]
+ch_data_in\[36\]
+ch_data_in\[37\]
+ch_data_in\[38\]
+
+ch_clk_out\[4\] 1825 0 2
+s4_wbd_cyc_o
+s4_wbd_stb_o
+s4_wbd_we_o
+s4_wbd_adr_o\[10\]
+s4_wbd_adr_o\[9\]
+s4_wbd_adr_o\[8\]
+s4_wbd_adr_o\[7\]
+s4_wbd_adr_o\[6\]
+s4_wbd_adr_o\[5\]
+s4_wbd_adr_o\[4\]
+s4_wbd_adr_o\[3\]
+s4_wbd_adr_o\[2\]
+s4_wbd_adr_o\[1\]
+s4_wbd_adr_o\[0\]
+s4_wbd_dat_o\[31\]
+s4_wbd_dat_o\[30\]
+s4_wbd_dat_o\[29\]
+s4_wbd_dat_o\[28\]
+s4_wbd_dat_o\[27\]
+s4_wbd_dat_o\[26\]
+s4_wbd_dat_o\[25\]
+s4_wbd_dat_o\[24\]
+s4_wbd_dat_o\[23\]
+s4_wbd_dat_o\[22\]
+s4_wbd_dat_o\[21\]
+s4_wbd_dat_o\[20\]
+s4_wbd_dat_o\[19\]
+s4_wbd_dat_o\[18\]
+s4_wbd_dat_o\[17\]
+s4_wbd_dat_o\[16\]
+s4_wbd_dat_o\[15\]
+s4_wbd_dat_o\[14\]
+s4_wbd_dat_o\[13\]
+s4_wbd_dat_o\[12\]
+s4_wbd_dat_o\[11\]
+s4_wbd_dat_o\[10\]
+s4_wbd_dat_o\[9\]
+s4_wbd_dat_o\[8\]
+s4_wbd_dat_o\[7\]
+s4_wbd_dat_o\[6\]
+s4_wbd_dat_o\[5\]
+s4_wbd_dat_o\[4\]
+s4_wbd_dat_o\[3\]
+s4_wbd_dat_o\[2\]
+s4_wbd_dat_o\[1\]
+s4_wbd_dat_o\[0\]
+s4_wbd_sel_o\[3\]
+s4_wbd_sel_o\[2\]
+s4_wbd_sel_o\[1\]
+s4_wbd_sel_o\[0\]
+s4_wbd_dat_i\[31\]
+s4_wbd_dat_i\[30\]
+s4_wbd_dat_i\[29\]
+s4_wbd_dat_i\[28\]
+s4_wbd_dat_i\[27\]
+s4_wbd_dat_i\[26\]
+s4_wbd_dat_i\[25\]
+s4_wbd_dat_i\[24\]
+s4_wbd_dat_i\[23\]
+s4_wbd_dat_i\[22\]
+s4_wbd_dat_i\[21\]
+s4_wbd_dat_i\[20\]
+s4_wbd_dat_i\[19\]
+s4_wbd_dat_i\[18\]
+s4_wbd_dat_i\[17\]
+s4_wbd_dat_i\[16\]
+s4_wbd_dat_i\[15\]
+s4_wbd_dat_i\[14\]
+s4_wbd_dat_i\[13\]
+s4_wbd_dat_i\[12\]
+s4_wbd_dat_i\[11\]
+s4_wbd_dat_i\[10\]
+s4_wbd_dat_i\[9\]
+s4_wbd_dat_i\[8\]
+s4_wbd_dat_i\[7\]
+s4_wbd_dat_i\[6\]
+s4_wbd_dat_i\[5\]
+s4_wbd_dat_i\[4\]
+s4_wbd_dat_i\[3\]
+s4_wbd_dat_i\[2\]
+s4_wbd_dat_i\[1\]
+s4_wbd_dat_i\[0\]
+s4_wbd_ack_i
+
+ch_data_out\[39\] 1950 0 2
+ch_data_out\[40\]
+ch_data_out\[41\]
+ch_data_out\[42\]
+ch_data_out\[43\]
+ch_data_in\[44\]
+ch_data_in\[45\]
+ch_data_in\[46\]
+ch_data_in\[47\]
+ch_data_in\[48\]
+ch_data_in\[49\]
+ch_data_in\[50\]
+ch_data_in\[51\]
+
+scan_mode_o 2200 0 2
+scan_en_o
+scan_so\[7\]
+scan_so\[6\]
+scan_so\[5\]
+scan_so\[4\]
+scan_so\[3\]
+scan_so\[2\]
+scan_so\[1\]
+scan_so\[0\]
diff --git a/openlane/wb_interconnect/sta.tcl b/openlane/wb_interconnect/sta.tcl
new file mode 100644
index 0000000..cb809a5
--- /dev/null
+++ b/openlane/wb_interconnect/sta.tcl
@@ -0,0 +1,57 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+
+set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
+set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
+set ::env(CURRENT_NETLIST) runs/wb_interconnect/results/synthesis/wb_interconnect.synthesis_preroute.v
+set ::env(DESIGN_NAME) "wb_interconnect"
+set ::env(CURRENT_SPEF) ../../spef/wb_interconnect.spef
+set ::env(BASE_SDC_FILE) "base.sdc"
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
+set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
+set ::env(SYNTH_CAP_LOAD) "17.65"
+set ::env(WIRE_RC_LAYER) "met1"
+
+
+set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
+read_liberty -min $::env(LIB_FASTEST)
+read_liberty -max $::env(LIB_SLOWEST)
+read_verilog $::env(CURRENT_NETLIST)
+link_design $::env(DESIGN_NAME)
+
+read_spef $::env(CURRENT_SPEF)
+
+read_sdc -echo $::env(BASE_SDC_FILE)
+
+# check for missing constraints
+check_setup -verbose > unconstraints.rpt
+
+set_operating_conditions -analysis_type single
+# Propgate the clock
+set_propagated_clock [all_clocks]
+
+report_tns
+report_wns
+report_power
+report_checks -unique -slack_max -0.0 -group_count 100
+report_checks -unique -slack_min -0.0 -group_count 100
+report_checks -path_delay min_max
+report_checks -group_count 100 -slack_max -0.01 > timing.rpt
+
+report_checks -group_count 100 -slack_min -0.01 >> timing.rpt
+
+
diff --git a/verilog/gl/user_project_wrapper.v.gz b/verilog/gl/user_project_wrapper.v.gz
new file mode 100644
index 0000000..55d332d
--- /dev/null
+++ b/verilog/gl/user_project_wrapper.v.gz
Binary files differ
diff --git a/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv b/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv
new file mode 100644
index 0000000..7fd1a62
--- /dev/null
+++ b/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv
@@ -0,0 +1,205 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// clock skew adjust ////
+//// ////
+//// This file is part of the YIFive cores project ////
+//// https://github.com/dineshannayya/yifive_r0.git ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description ////
+//// This block is useful for global clock skew adjustment ////
+//// logic implementation: ////
+//// clk_out = (sel=0) ? clk_in : ////
+//// (sel=1) ? clk_d1 : ////
+//// (sel=1) ? clk_d2 : ////
+//// ..... ////
+//// (sel=15)? clk_d15 :clk_in ////
+//// ////
+//// Note: each d* indicate clk buf delay ////
+//// ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 29th Feb 2021, Dinesh A ////
+//// Initial version ////
+///
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+// Clock-in is east pad direction
+// clock out give in other three direction for better placement
+/////////////////////////////////////////////////////////////////////
+module clk_skew_adjust(
+`ifdef USE_POWER_PINS
+ vccd1,// User area 1 1.8V supply
+ vssd1,// User area 1 digital ground
+`endif
+clk_in, sel, clk_out);
+
+
+`ifdef USE_POWER_PINS
+ input vccd1;// User area 1 1.8V supply
+ input vssd1;// User area 1 digital ground
+`endif
+ input clk_in;
+ output clk_out;
+ input [3:0] sel;
+ wire in0;
+ wire in1;
+ wire in2;
+ wire in3;
+ wire in4;
+ wire in5;
+ wire in6;
+ wire in7;
+ wire in8;
+ wire in9;
+ wire in10;
+ wire in11;
+ wire in12;
+ wire in13;
+ wire in14;
+ wire in15;
+
+ wire clk_d1;
+ wire clk_d2;
+ wire clk_d3;
+ wire clk_d4;
+ wire clk_d5;
+ wire clk_d6;
+ wire clk_d7;
+ wire clk_d8;
+ wire clk_d9;
+ wire clk_d10;
+ wire clk_d11;
+ wire clk_d12;
+ wire clk_d13;
+ wire clk_d14;
+ wire clk_d15;
+
+ wire d00;
+ wire d01;
+ wire d02;
+ wire d03;
+ wire d04;
+ wire d05;
+ wire d06;
+ wire d07;
+ wire d10;
+ wire d11;
+ wire d12;
+ wire d13;
+ wire d20;
+ wire d21;
+ wire d30;
+
+
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_1 (.A(clk_in), .X(clk_d1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_2 (.A(clk_d1), .X(clk_d2));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_3 (.A(clk_d2), .X(clk_d3));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_4 (.A(clk_d3), .X(clk_d4));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_5 (.A(clk_d4), .X(clk_d5));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_6 (.A(clk_d5), .X(clk_d6));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_7 (.A(clk_d6), .X(clk_d7));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_8 (.A(clk_d7), .X(clk_d8));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_9 (.A(clk_d8), .X(clk_d9));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_10 (.A(clk_d9), .X(clk_d10));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_11 (.A(clk_d10), .X(clk_d11));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_12 (.A(clk_d11), .X(clk_d12));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_13 (.A(clk_d12), .X(clk_d13));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_14 (.A(clk_d13), .X(clk_d14));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_15 (.A(clk_d14), .X(clk_d15));
+
+
+ // Tap point selection
+ assign in0 = clk_in;
+ assign in1 = clk_d1;
+ assign in2 = clk_d2;
+ assign in3 = clk_d3;
+ assign in4 = clk_d4;
+ assign in5 = clk_d5;
+ assign in6 = clk_d6;
+ assign in7 = clk_d7;
+ assign in8 = clk_d8;
+ assign in9 = clk_d9;
+ assign in10 = clk_d10;
+ assign in11 = clk_d11;
+ assign in12 = clk_d12;
+ assign in13 = clk_d13;
+ assign in14 = clk_d14;
+ assign in15 = clk_d15;
+
+
+ // first level mux - 8
+ sky130_fd_sc_hd__mux2_1 u_mux_level_00 ( .X (d00) , .A0 (in0), .A1(in1), .S(sel[0]));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_01 ( .X (d01) , .A0 (in2), .A1(in3), .S(sel[0]));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_02 ( .X (d02) , .A0 (in4), .A1(in5), .S(sel[0]));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_03 ( .X (d03) , .A0 (in6), .A1(in7), .S(sel[0]));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_04 ( .X (d04) , .A0 (in8), .A1(in9), .S(sel[0]));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_05 ( .X (d05) , .A0 (in10), .A1(in11), .S(sel[0]));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_06 ( .X (d06) , .A0 (in12), .A1(in13), .S(sel[0]));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_07 ( .X (d07) , .A0 (in14), .A1(in15), .S(sel[0]));
+
+ // second level mux - 4
+ sky130_fd_sc_hd__mux2_1 u_mux_level_10 ( .X (d10) , .A0 (d00), .A1(d01), .S(sel[1]));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_11 ( .X (d11) , .A0 (d02), .A1(d03), .S(sel[1]));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_12 ( .X (d12) , .A0 (d04), .A1(d05), .S(sel[1]));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_13 ( .X (d13) , .A0 (d06), .A1(d07), .S(sel[1]));
+
+ // third level mux - 2
+ sky130_fd_sc_hd__mux2_1 u_mux_level_20 ( .X (d20) , .A0 (d10), .A1(d11), .S(sel[2]));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_21 ( .X (d21) , .A0 (d12), .A1(d13), .S(sel[2]));
+
+ // fourth level mux - 1
+ sky130_fd_sc_hd__mux2_4 u_mux_level_30 ( .X (d30) , .A0 (d20), .A1(d21), .S(sel[3]));
+
+
+ assign clk_out = d30;
+
+endmodule
diff --git a/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.v b/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.v
new file mode 100644
index 0000000..a961a50
--- /dev/null
+++ b/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.v
@@ -0,0 +1,2898 @@
+module clk_skew_adjust (clk_in,
+ clk_out,
+ vccd1,
+ vssd1,
+ sel);
+ input clk_in;
+ output clk_out;
+ input vccd1;
+ input vssd1;
+ input [3:0] sel;
+
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_1 (.A(clk_in),
+ .X(clk_d1),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_10 (.A(clk_d9),
+ .X(clk_d10),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_11 (.A(clk_d10),
+ .X(clk_d11),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_12 (.A(clk_d11),
+ .X(clk_d12),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_13 (.A(clk_d12),
+ .X(clk_d13),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_14 (.A(clk_d13),
+ .X(clk_d14),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_15 (.A(clk_d14),
+ .X(clk_d15),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_2 (.A(clk_d1),
+ .X(clk_d2),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_3 (.A(clk_d2),
+ .X(clk_d3),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_4 (.A(clk_d3),
+ .X(clk_d4),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_5 (.A(clk_d4),
+ .X(clk_d5),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_6 (.A(clk_d5),
+ .X(clk_d6),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_7 (.A(clk_d6),
+ .X(clk_d7),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_8 (.A(clk_d7),
+ .X(clk_d8),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_9 (.A(clk_d8),
+ .X(clk_d9),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_00 (.A0(clk_in),
+ .A1(clk_d1),
+ .S(sel[0]),
+ .X(d00),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_01 (.A0(clk_d2),
+ .A1(clk_d3),
+ .S(sel[0]),
+ .X(d01),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_02 (.A0(clk_d4),
+ .A1(clk_d5),
+ .S(sel[0]),
+ .X(d02),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_03 (.A0(clk_d6),
+ .A1(clk_d7),
+ .S(sel[0]),
+ .X(d03),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_04 (.A0(clk_d8),
+ .A1(clk_d9),
+ .S(sel[0]),
+ .X(d04),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_05 (.A0(clk_d10),
+ .A1(clk_d11),
+ .S(sel[0]),
+ .X(d05),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_06 (.A0(clk_d12),
+ .A1(clk_d13),
+ .S(sel[0]),
+ .X(d06),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_07 (.A0(clk_d14),
+ .A1(clk_d15),
+ .S(sel[0]),
+ .X(d07),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_10 (.A0(d00),
+ .A1(d01),
+ .S(sel[1]),
+ .X(d10),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_11 (.A0(d02),
+ .A1(d03),
+ .S(sel[1]),
+ .X(d11),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_12 (.A0(d04),
+ .A1(d05),
+ .S(sel[1]),
+ .X(d12),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_13 (.A0(d06),
+ .A1(d07),
+ .S(sel[1]),
+ .X(d13),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_20 (.A0(d10),
+ .A1(d11),
+ .S(sel[2]),
+ .X(d20),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_21 (.A0(d12),
+ .A1(d13),
+ .S(sel[2]),
+ .X(d21),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_4 u_mux_level_30 (.A0(d20),
+ .A1(d21),
+ .S(sel[3]),
+ .X(clk_out),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_6 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_7 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_8 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_9 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_10 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_11 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_12 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_13 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_14 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_16 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_17 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_18 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_19 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_20 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_21 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_22 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_23 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_24 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_25 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_26 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_28 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_29 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_30 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_31 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_32 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_33 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_34 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_35 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_36 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_37 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_38 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_39 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_40 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_41 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_42 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_43 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_44 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_45 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_46 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_47 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_48 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_49 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_50 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_51 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_52 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_53 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_54 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_55 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_56 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_57 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_58 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_59 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_60 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_61 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_62 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_63 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_64 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_65 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_66 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_67 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_68 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_69 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_70 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_71 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_72 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_73 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_74 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_75 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_76 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_77 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_78 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_79 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_80 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_81 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_82 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_83 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_84 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_85 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_86 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_87 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_88 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_89 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_90 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_91 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_92 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_93 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_94 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_95 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_96 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_97 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_98 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_99 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_100 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_101 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_102 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_103 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_104 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_105 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_106 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_107 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_108 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_109 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_110 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_111 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_112 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_113 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_114 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_115 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_116 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_117 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_118 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_119 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_120 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_121 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_122 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_123 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_124 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_125 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_126 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_127 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_128 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_129 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_130 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_131 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_132 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_133 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_134 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_135 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_136 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_137 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_138 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_139 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_140 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_141 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_142 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_143 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_144 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_145 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_146 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_147 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_148 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_149 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_150 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_151 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_152 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_153 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_154 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_155 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_156 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_157 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_158 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_159 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_160 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_161 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_162 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_163 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_164 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_165 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_0_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_32 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_44 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_0_56 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_63 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_75 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_0_87 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_94 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_106 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_0_118 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_125 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_137 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_0_149 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_156 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_168 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_0_180 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_0_187 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_1_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_32 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_44 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_56 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_68 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_80 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_93 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_105 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_117 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_129 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_141 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_154 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_166 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_178 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_39 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_2_51 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_2_59 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_62 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_74 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_86 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_98 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_110 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_123 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_135 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_147 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_159 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_171 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_2_184 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_3_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_32 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_44 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_56 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_68 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_80 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_93 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_105 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_117 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_129 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_141 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_154 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_166 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_178 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_4_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_4_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_4_23 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_4_35 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_4_47 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_4_59 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_4_62 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_4_74 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_4_86 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_4_98 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_4_110 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_4_123 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_4_135 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_4_147 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_4_159 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_4_171 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_4_184 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_5_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_5_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_5_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_5_32 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_5_44 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_5_56 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_5_68 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_5_80 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_5_93 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_5_114 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_5_126 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_5_134 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_5_146 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_5_152 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_5_154 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_5_166 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_5_178 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_39 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_6_51 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_6_59 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_62 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_74 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_86 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_98 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_110 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_123 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_135 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_147 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_159 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_171 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_6_184 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_7_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_32 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_44 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_56 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_68 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_80 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_102 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_114 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_126 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_138 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_7_150 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_154 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_166 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_178 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_39 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_8_51 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_8_59 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_62 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_74 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_86 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_98 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_110 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_123 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_135 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_147 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_159 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_171 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_8_184 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_9_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_9_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_9_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_9_32 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_9_44 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_9_56 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_9_64 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_9_76 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_9_88 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_9_93 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_9_105 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_9_117 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_9_129 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_9_141 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_9_154 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_9_166 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_9_183 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_9_189 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_39 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_10_51 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_10_59 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_62 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_74 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_86 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_98 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_110 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_123 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_135 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_147 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_159 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_171 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_10_184 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_11_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_11_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_11_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_11_32 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_11_44 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_11_56 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_11_68 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_11_80 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_11_93 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_11_105 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_11_117 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_11_129 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_11_141 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_11_154 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_11_166 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_11_174 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_11_186 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_12_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_12_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_12_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_12_39 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_12_51 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_12_59 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_12_62 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_12_74 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_12_86 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_12_98 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_12_106 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_12_118 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_12_123 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_12_135 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_12_147 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_12_159 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_12_171 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_12_184 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_13_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_32 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_44 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_56 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_68 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_80 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_93 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_105 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_117 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_129 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_141 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_154 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_166 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_178 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_14_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_14_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_14_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_14_39 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_14_51 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_14_59 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_14_62 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_14_74 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_14_86 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_14_98 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_14_110 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_14_123 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_14_135 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_14_146 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_14_158 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_14_164 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_14_174 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_14_182 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_14_184 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_15_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_32 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_44 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_56 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_68 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_80 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_93 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_105 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_117 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_129 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_141 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_154 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_166 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_178 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_39 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_16_51 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_16_59 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_62 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_74 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_86 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_98 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_110 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_123 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_135 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_147 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_159 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_171 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_16_184 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_17_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_17_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_17_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_17_32 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_17_44 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_17_56 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_17_60 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_17_73 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_17_85 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_17_91 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_17_93 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_17_105 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_17_117 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_17_129 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_17_141 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_17_154 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_17_166 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_17_174 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_17_186 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_18_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_18_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_18_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_18_40 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_18_52 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_18_60 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_18_62 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_18_74 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_18_86 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_18_98 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_18_110 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_18_123 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_18_135 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_18_147 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_18_159 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_18_171 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_18_184 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_19_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_32 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_44 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_56 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_68 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_80 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_93 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_105 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_117 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_129 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_141 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_154 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_166 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_178 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_39 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_20_51 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_20_59 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_62 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_74 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_86 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_98 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_110 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_123 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_135 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_147 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_159 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_171 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_20_184 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_21_12 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_21_24 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_21_30 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_21_32 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_21_44 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_21_56 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_21_68 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_21_80 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_21_93 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_21_105 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_21_117 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_21_129 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_21_141 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_21_154 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_21_166 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_21_179 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_21_187 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_22_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_22_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_22_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_22_39 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_22_51 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_22_59 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_22_71 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_22_83 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_22_95 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_22_107 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_22_119 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_22_132 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_22_144 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_22_156 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_22_168 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_22_180 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_22_184 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_23_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_23_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_23_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_23_32 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_23_44 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_23_56 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_23_68 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_23_80 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_23_93 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_23_105 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_23_117 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_23_123 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_23_133 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_23_145 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_23_154 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_23_167 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_23_179 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_23_187 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_39 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_24_51 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_24_59 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_62 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_74 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_86 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_98 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_110 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_123 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_135 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_147 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_159 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_171 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_24_184 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_25_12 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_25_24 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_25_30 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_25_32 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_25_44 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_25_56 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_25_68 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_25_80 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_25_93 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_25_105 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_25_117 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_25_129 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_25_141 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_25_154 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_25_166 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_25_174 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_25_186 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_26_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_26_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_26_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_26_39 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_26_51 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_26_59 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_26_62 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_26_74 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_26_86 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_26_98 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_26_110 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_26_123 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_26_135 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_26_147 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_26_159 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_26_167 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_26_179 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_26_184 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_27_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_32 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_44 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_56 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_68 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_80 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_93 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_105 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_117 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_129 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_141 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_154 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_166 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_178 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_39 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_28_51 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_28_59 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_62 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_74 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_86 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_98 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_110 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_123 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_135 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_147 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_159 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_171 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_28_184 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_29_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_29_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_29_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_29_32 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_29_44 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_29_56 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_29_68 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_29_76 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_29_88 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_29_93 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_29_105 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_29_117 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_29_129 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_29_141 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_29_154 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_29_166 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_29_181 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_29_189 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_30_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_30_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_30_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_30_39 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_30_51 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_30_59 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_30_62 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_30_74 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_30_86 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_30_98 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_30_106 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_30_117 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_30_121 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_30_123 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_30_135 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_30_139 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_30_149 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_30_161 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_30_169 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_30_179 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_30_184 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_31_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_31_15 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_31_27 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_31_32 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_31_44 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_31_56 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_31_63 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_31_75 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_31_87 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_31_94 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_31_106 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_31_118 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_31_125 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_31_137 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_31_147 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_31_156 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_31_168 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_31_180 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_31_187 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+endmodule
diff --git a/verilog/rtl/clk_skew_adjust/synth/Makefile b/verilog/rtl/clk_skew_adjust/synth/Makefile
new file mode 100644
index 0000000..f6ae1df
--- /dev/null
+++ b/verilog/rtl/clk_skew_adjust/synth/Makefile
@@ -0,0 +1,49 @@
+# //////////////////////////////////////////////////////////////////////////////
+# // SPDX-FileCopyrightText: 2021, Dinesh Annayya
+# //
+# // Licensed under the Apache License, Version 2.0 (the "License");
+# // you may not use this file except in compliance with the License.
+# // You may obtain a copy of the License at
+# //
+# // http://www.apache.org/licenses/LICENSE-2.0
+# //
+# // Unless required by applicable law or agreed to in writing, software
+# // distributed under the License is distributed on an "AS IS" BASIS,
+# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# // See the License for the specific language governing permissions and
+# // limitations under the License.
+# // SPDX-License-Identifier: Apache-2.0
+# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+# // //////////////////////////////////////////////////////////////////////////
+#------------------------------------------------------------------------------
+# Makefile for Synthesis
+#------------------------------------------------------------------------------
+
+# Paths
+export ROOT_DIR := $(shell pwd)
+export REPORT_DIR := $(ROOT_DIR)/reports
+export NETLIST_DIR := $(ROOT_DIR)/netlist
+export TMP_DIR := $(ROOT_DIR)/tmp
+
+
+# Targets
+.PHONY: clean create synth
+
+default: clean create synth
+
+synth: clean create
+ yosys -g -c synth.tcl -l synth.log
+
+create:
+ mkdir -p ./tmp/synthesis;
+ mkdir -p ./reports;
+ mkdir -p ./netlist;
+ $(OPENLANE_ROOT)/scripts/libtrim.pl $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib $(PDK_ROOT)/sky130A/libs.tech/openlane/sky130_fd_sc_hd/no_synth.cells > ./tmp/trimmed.lib
+
+
+
+clean:
+ $(RM) -R synth.log
+ $(RM) -R $(REPORT_DIR)
+ $(RM) -R $(NETLIST_DIR)
+ $(RM) -R $(TMP_DIR)
diff --git a/verilog/rtl/clk_skew_adjust/synth/synth.tcl b/verilog/rtl/clk_skew_adjust/synth/synth.tcl
new file mode 100755
index 0000000..b7adea6
--- /dev/null
+++ b/verilog/rtl/clk_skew_adjust/synth/synth.tcl
@@ -0,0 +1,385 @@
+# //////////////////////////////////////////////////////////////////////////////
+# // SPDX-FileCopyrightText: 2021, Dinesh Annayya
+# //
+# // Licensed under the Apache License, Version 2.0 (the "License");
+# // you may not use this file except in compliance with the License.
+# // You may obtain a copy of the License at
+# //
+# // http://www.apache.org/licenses/LICENSE-2.0
+# //
+# // Unless required by applicable law or agreed to in writing, software
+# // distributed under the License is distributed on an "AS IS" BASIS,
+# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# // See the License for the specific language governing permissions and
+# // limitations under the License.
+# // SPDX-License-Identifier: Apache-2.0
+# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+# // //////////////////////////////////////////////////////////////////////////
+# inputs expected as env vars
+#set opt $::env(SYNTH_OPT)
+########### config.tcl ##################
+# User config
+
+# User config
+set ::env(DESIGN_DIR) ../
+
+set ::env(PROJ_DIR) ../../../../
+
+# User config
+set ::env(DESIGN_NAME) clk_mux
+
+# Change if needed
+set ::env(VERILOG_FILES) [glob \
+ ../src/clk_mux.v ]
+
+
+set ::env(SYNTH_DEFINES) [list YOSYS ]
+
+
+set ::env(LIB_SYNTH) ./tmp/trimmed.lib
+
+
+# Fill this
+set ::env(CLOCK_PERIOD) "10"
+#set ::env(CLOCK_PORT) "mclk"
+set ::env(CLOCK_TREE_SYNTH) 0
+
+set ::env(RUN_SIMPLE_CTS) 0
+set ::env(SYNTH_BUFFERING) 0
+set ::env(SYNTH_SIZING) 0
+
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
+set ::env(SYNTH_CAP_LOAD) "17.65"
+set ::env(SYNTH_MAX_TRAN) "[expr {0.1*10.0}]"
+
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(FP_CORE_UTIL) 50
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+set ::env(CELL_PAD) 4
+
+set ::env(SYNTH_NO_FLAT) "0"
+
+
+set ::env(SYNTH_STRATEGY) "AREA 0"
+set ::env(SYNTH_TIELO_PORT) "sky130_fd_sc_hd__conb_1 LO"
+set ::env(SYNTH_TIEHI_PORT) "sky130_fd_sc_hd__conb_1 HI"
+set ::env(SYNTH_MIN_BUF_PORT) "sky130_fd_sc_hd__buf_2 A X"
+
+
+#set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+
+
+
+set ::env(yosys_tmp_file_tag) "./tmp/"
+set ::env(TMP_DIR) "./tmp/"
+set ::env(yosys_netlist_dir) "./netlist"
+set ::env(yosys_report_file_tag) "./reports/yosys"
+set ::env(yosys_result_file_tag) "./reports/yosys.synthesis"
+
+set ::env(SAVE_NETLIST) $::env(yosys_netlist_dir)/$::env(DESIGN_NAME).gv
+
+
+
+########### End of config.tcl
+set buffering $::env(SYNTH_BUFFERING)
+set sizing $::env(SYNTH_SIZING)
+
+yosys -import
+
+set vtop $::env(DESIGN_NAME)
+#set sdc_file $::env(SDC_FILE)
+set sclib $::env(LIB_SYNTH)
+
+if { [info exists ::env(SYNTH_DEFINES) ] } {
+ foreach define $::env(SYNTH_DEFINES) {
+ log "Defining $define"
+ verilog_defines -D$define
+ }
+}
+
+set vIdirsArgs ""
+if {[info exist ::env(VERILOG_INCLUDE_DIRS)]} {
+ foreach dir $::env(VERILOG_INCLUDE_DIRS) {
+ log "Adding include file -I$dir "
+ lappend vIdirsArgs "-I$dir"
+ }
+ set vIdirsArgs [join $vIdirsArgs]
+}
+
+
+
+if { [info exists ::env(EXTRA_LIBS) ] } {
+ foreach lib $::env(EXTRA_LIBS) {
+ read_liberty {*}$vIdirsArgs -lib -ignore_miss_dir -setattr blackbox $lib
+ }
+}
+
+
+
+# ns expected (in sdc as well)
+set clock_period [expr {$::env(CLOCK_PERIOD)*1000}]
+
+set driver $::env(SYNTH_DRIVING_CELL)
+set cload $::env(SYNTH_CAP_LOAD)
+# input pin cap of IN_3VX8
+set max_FO $::env(SYNTH_MAX_FANOUT)
+if {![info exist ::env(SYNTH_MAX_TRAN)]} {
+ set ::env(SYNTH_MAX_TRAN) [expr {0.1*$clock_period}]
+} else {
+ set ::env(SYNTH_MAX_TRAN) [expr {$::env(SYNTH_MAX_TRAN) * 1000}]
+}
+set max_Tran $::env(SYNTH_MAX_TRAN)
+
+
+# Mapping parameters
+set A_factor 0.00
+set B_factor 0.88
+set F_factor 0.00
+
+# Don't change these unless you know what you are doing
+set stat_ext ".stat.rpt"
+set chk_ext ".chk.rpt"
+set gl_ext ".gl.v"
+set constr_ext ".$clock_period.constr"
+set timing_ext ".timing.txt"
+set abc_ext ".abc"
+
+
+# get old sdc, add library specific stuff for abc scripts
+set sdc_file $::env(yosys_tmp_file_tag).sdc
+set outfile [open ${sdc_file} w]
+#puts $outfile $sdc_data
+puts $outfile "set_driving_cell ${driver}"
+puts $outfile "set_load ${cload}"
+close $outfile
+
+
+# ABC Scrips
+set abc_rs_K "resub,-K,"
+set abc_rs "resub"
+set abc_rsz "resub,-z"
+set abc_rw_K "rewrite,-K,"
+set abc_rw "rewrite"
+set abc_rwz "rewrite,-z"
+set abc_rf "refactor"
+set abc_rfz "refactor,-z"
+set abc_b "balance"
+
+set abc_resyn2 "${abc_b}; ${abc_rw}; ${abc_rf}; ${abc_b}; ${abc_rw}; ${abc_rwz}; ${abc_b}; ${abc_rfz}; ${abc_rwz}; ${abc_b}"
+set abc_share "strash; multi,-m; ${abc_resyn2}"
+set abc_resyn2a "${abc_b};${abc_rw};${abc_b};${abc_rw};${abc_rwz};${abc_b};${abc_rwz};${abc_b}"
+set abc_resyn3 "balance;resub;resub,-K,6;balance;resub,-z;resub,-z,-K,6;balance;resub,-z,-K,5;balance"
+set abc_resyn2rs "${abc_b};${abc_rs_K},6;${abc_rw};${abc_rs_K},6,-N,2;${abc_rf};${abc_rs_K},8;${abc_rw};${abc_rs_K},10;${abc_rwz};${abc_rs_K},10,-N,2;${abc_b},${abc_rs_K},12;${abc_rfz};${abc_rs_K},12,-N,2;${abc_rwz};${abc_b}"
+
+set abc_choice "fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; fraig_restore"
+set abc_choice2 "fraig_store; balance; fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; fraig_restore"
+
+set abc_map_old_cnt "map,-p,-a,-B,0.2,-A,0.9,-M,0"
+set abc_map_old_dly "map,-p,-B,0.2,-A,0.9,-M,0"
+set abc_retime_area "retime,-D,{D},-M,5"
+set abc_retime_dly "retime,-D,{D},-M,6"
+set abc_map_new_area "amap,-m,-Q,0.1,-F,20,-A,20,-C,5000"
+
+set abc_area_recovery_1 "${abc_choice}; map;"
+set abc_area_recovery_2 "${abc_choice2}; map;"
+
+set map_old_cnt "map,-p,-a,-B,0.2,-A,0.9,-M,0"
+set map_old_dly "map,-p,-B,0.2,-A,0.9,-M,0"
+set abc_retime_area "retime,-D,{D},-M,5"
+set abc_retime_dly "retime,-D,{D},-M,6"
+set abc_map_new_area "amap,-m,-Q,0.1,-F,20,-A,20,-C,5000"
+
+if {$buffering==1} {
+ set abc_fine_tune "buffer,-N,${max_FO},-S,${max_Tran};upsize,{D};dnsize,{D}"
+} elseif {$sizing} {
+ set abc_fine_tune "upsize,{D};dnsize,{D}"
+} else {
+ set abc_fine_tune ""
+}
+
+
+set delay_scripts [list \
+ "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_map_old_dly};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
+ \
+ "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_choice2};${abc_map_old_dly};${abc_area_recovery_2}; retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
+ \
+ "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_choice};${abc_map_old_dly};${abc_area_recovery_1}; retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
+ \
+ "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_old_dly};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
+ ]
+
+set area_scripts [list \
+ "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
+ \
+ "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_new_area};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
+ \
+ "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_choice2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_new_area};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
+ ]
+
+set all_scripts [list {*}$delay_scripts {*}$area_scripts]
+
+set strategy_parts [split $::env(SYNTH_STRATEGY)]
+
+proc synth_strategy_format_err { } {
+ upvar area_scripts area_scripts
+ upvar delay_scripts delay_scripts
+ log -stderr "\[ERROR] Misformatted SYNTH_STRATEGY (\"$::env(SYNTH_STRATEGY)\")."
+ log -stderr "\[ERROR] Correct format is \"DELAY|AREA 0-[expr [llength $delay_scripts]-1]|0-[expr [llength $area_scripts]-1]\"."
+ exit 1
+}
+
+if { [llength $strategy_parts] != 2 } {
+ synth_strategy_format_err
+}
+
+set strategy_type [lindex $strategy_parts 0]
+set strategy_type_idx [lindex $strategy_parts 1]
+
+if { $strategy_type != "AREA" && $strategy_type != "DELAY" } {
+ log -stderr "\[ERROR] AREA|DELAY tokens not found. ($strategy_type)"
+ synth_strategy_format_err
+}
+
+if { $strategy_type == "DELAY" && $strategy_type_idx >= [llength $delay_scripts] } {
+ log -stderr "\[ERROR] strategy index ($strategy_type_idx) is too high."
+ synth_strategy_format_err
+}
+
+if { $strategy_type == "AREA" && $strategy_type_idx >= [llength $area_scripts] } {
+ log -stderr "\[ERROR] strategy index ($strategy_type_idx) is too high."
+ synth_strategy_format_err
+}
+
+if { $strategy_type == "DELAY" } {
+ set strategy $strategy_type_idx
+} else {
+ set strategy [expr {[llength $delay_scripts]+$strategy_type_idx}]
+}
+
+
+for { set i 0 } { $i < [llength $::env(VERILOG_FILES)] } { incr i } {
+ read_verilog -sv {*}$vIdirsArgs [lindex $::env(VERILOG_FILES) $i]
+}
+
+if { [info exists ::env(VERILOG_FILES_BLACKBOX)] } {
+ foreach verilog_file $::env(VERILOG_FILES_BLACKBOX) {
+ read_verilog -sv {*}$vIdirsArgs -lib $verilog_file
+ }
+}
+select -module $vtop
+show -format dot -prefix $::env(TMP_DIR)/synthesis/hierarchy
+select -clear
+
+hierarchy -check -top $vtop
+
+# Infer tri-state buffers.
+set tbuf_map false
+if { [info exists ::env(TRISTATE_BUFFER_MAP)] } {
+ if { [file exists $::env(TRISTATE_BUFFER_MAP)] } {
+ set tbuf_map true
+ tribuf
+ } else {
+ log "WARNING: TRISTATE_BUFFER_MAP is defined but could not be found: $::env(TRISTATE_BUFFER_MAP)"
+ }
+}
+
+if { $::env(SYNTH_NO_FLAT) } {
+ synth -top $vtop
+} else {
+ synth -top $vtop -flatten
+}
+
+share -aggressive
+opt
+opt_clean -purge
+
+tee -o "$::env(yosys_report_file_tag)_pre.stat" stat
+
+# Map tri-state buffers.
+if { $tbuf_map } {
+ log {mapping tbuf}
+ techmap -map $::env(TRISTATE_BUFFER_MAP)
+ simplemap
+}
+
+# handle technology mapping of 4-MUX, and tell Yosys to infer 4-muxes
+if { [info exists ::env(SYNTH_MUX4_MAP)] && [file exists $::env(SYNTH_MUX4_MAP)] } {
+ muxcover -mux4
+ techmap -map $::env(SYNTH_MUX4_MAP)
+ simplemap
+}
+
+# handle technology mapping of 2-MUX
+if { [info exists ::env(SYNTH_MUX_MAP)] && [file exists $::env(SYNTH_MUX_MAP)] } {
+ techmap -map $::env(SYNTH_MUX_MAP)
+ simplemap
+}
+
+# handle technology mapping of latches
+if { [info exists ::env(SYNTH_LATCH_MAP)] && [file exists $::env(SYNTH_LATCH_MAP)] } {
+ techmap -map $::env(SYNTH_LATCH_MAP)
+ simplemap
+}
+
+dfflibmap -liberty $sclib
+tee -o "$::env(yosys_report_file_tag)_dff.stat" stat
+
+if { [info exists ::env(SYNTH_EXPLORE)] && $::env(SYNTH_EXPLORE) } {
+ design -save myDesign
+
+ for { set index 0 } { $index < [llength $all_scripts] } { incr index } {
+ log "\[INFO\]: ABC: WireLoad : S_$index"
+ design -load myDesign
+
+ abc -D $clock_period \
+ -constr "$sdc_file" \
+ -liberty $sclib \
+ -script [lindex $all_scripts $index]
+
+ setundef -zero
+
+ hilomap -hicell {*}$::env(SYNTH_TIEHI_PORT) -locell {*}$::env(SYNTH_TIELO_PORT)
+
+ # get rid of the assignments that make verilog2def fail
+ splitnets
+ opt_clean -purge
+ insbuf -buf {*}$::env(SYNTH_MIN_BUF_PORT)
+
+ tee -o "$::env(yosys_report_file_tag)_$index$chk_ext" check
+ write_verilog -noattr -noexpr -nohex -nodec -defparam "$::env(yosys_result_file_tag)_$index.v"
+ design -reset
+ }
+} else {
+
+ log "\[INFO\]: ABC: WireLoad : S_$strategy"
+
+ abc -D $clock_period \
+ -constr "$sdc_file" \
+ -liberty $sclib \
+ -script [lindex $all_scripts $strategy] \
+ -showtmp;
+
+ setundef -zero
+
+ hilomap -hicell {*}$::env(SYNTH_TIEHI_PORT) -locell {*}$::env(SYNTH_TIELO_PORT)
+
+ # get rid of the assignments that make verilog2def fail
+ splitnets
+ opt_clean -purge
+ insbuf -buf {*}$::env(SYNTH_MIN_BUF_PORT)
+
+ tee -o "$::env(yosys_report_file_tag)_$strategy$chk_ext" check
+ write_verilog -noattr -noexpr -nohex -nodec -defparam "$::env(SAVE_NETLIST)"
+}
+
+if { $::env(SYNTH_NO_FLAT) } {
+ design -reset
+ file copy -force $::env(SAVE_NETLIST) $::env(yosys_tmp_file_tag)_unflat.v
+ read_verilog -sv $::env(SAVE_NETLIST)
+ synth -top $vtop -flatten
+ splitnets
+ opt_clean -purge
+ insbuf -buf {*}$::env(SYNTH_MIN_BUF_PORT)
+ write_verilog -noattr -noexpr -nohex -nodec -defparam "$::env(SAVE_NETLIST)"
+ tee -o "$::env(yosys_report_file_tag)_$strategy$chk_ext" check
+}
diff --git a/verilog/rtl/digital_core.v b/verilog/rtl/digital_core.v
new file mode 100644
index 0000000..c57d82c
--- /dev/null
+++ b/verilog/rtl/digital_core.v
@@ -0,0 +1,738 @@
+
+`include "top_defines.v"
+module digital_core (
+
+ reset_n ,
+ scan_mode ,
+ scan_enable ,
+ fastsim_mode ,
+ mastermode ,
+ xtal_clk ,
+ clkout ,
+ reset_out_n ,
+
+ // Reg Bus Interface Signal
+ ext_reg_cs ,
+ ext_reg_tid ,
+ ext_reg_wr ,
+ ext_reg_addr ,
+ ext_reg_wdata ,
+ ext_reg_be ,
+
+ // Outputs
+ ext_reg_rdata ,
+ ext_reg_ack ,
+
+
+ // Line Side Interface TX Path
+ phy_tx_en ,
+ phy_txd ,
+ phy_tx_clk ,
+
+ // Line Side Interface RX Path
+ phy_rx_clk ,
+ phy_rx_dv ,
+ phy_rxd ,
+
+ //MDIO interface
+ mdio_clk ,
+ mdio_in ,
+ mdio_out ,
+ mdio_out_en ,
+
+
+ // UART Line Interface
+ si ,
+ so ,
+
+
+ spi_sck ,
+ spi_so ,
+ spi_si ,
+ spi_cs_n ,
+
+
+ // External ROM interface
+ wb_xrom_adr ,
+ wb_xrom_ack ,
+ wb_xrom_err ,
+ wb_xrom_wr ,
+ wb_xrom_rdata ,
+ wb_xrom_wdata ,
+
+ wb_xrom_stb ,
+ wb_xrom_cyc ,
+
+ // External RAM interface
+ wb_xram_adr ,
+ wb_xram_ack ,
+ wb_xram_err ,
+ wb_xram_wr ,
+ wb_xram_be ,
+ wb_xram_rdata ,
+ wb_xram_wdata ,
+
+ wb_xram_stb ,
+ wb_xram_cyc,
+
+ ea_in
+
+
+
+ );
+
+
+//----------------------------------------
+// Global Clock Defination
+//----------------------------------------
+input reset_n ; // Active Low Reset
+input scan_mode ; // scan mode
+input scan_enable ; // scan enable
+input fastsim_mode ; // Fast Sim Mode
+input mastermode ; // 1 : Risc master mode
+
+input xtal_clk ; // xtal clock 25Mhz
+output clkout ; // clock output
+output reset_out_n ; // clock output
+
+//---------------------------------
+// Reg Bus Interface Signal
+//---------------------------------
+input ext_reg_cs ;
+input ext_reg_wr ;
+input [3:0] ext_reg_tid ;
+input [14:0] ext_reg_addr ;
+input [31:0] ext_reg_wdata ;
+input [3:0] ext_reg_be ;
+
+// Outputs
+output [31:0] ext_reg_rdata ;
+output ext_reg_ack ;
+
+//----------------------------------------
+// MAC Line Side Interface TX Path
+//----------------------------------------
+output phy_tx_en ; // MAC Tx Enable
+output [7:0] phy_txd ; // MAC Tx Data
+input phy_tx_clk ; // MAC Tx Clock
+
+//----------------------------------------
+// MAC Line Side Interface RX Path
+//----------------------------------------
+input phy_rx_clk ; // MAC Rx Clock
+input phy_rx_dv ; // MAC Rx Dv
+input [7:0] phy_rxd ; // MAC Rxd
+
+//----------------------------------------
+// MDIO interface
+//----------------------------------------
+output mdio_clk ; // MDIO Clock
+input mdio_in ; // MDIO Data
+output mdio_out ; // MDIO Data
+output mdio_out_en ; // MDIO Data
+
+
+//----------------------------------------
+// UART Line Interface
+//----------------------------------------
+input si ; // serial in
+output so ; // serial out
+
+//----------------------------------------
+// SPI Line Interface
+//----------------------------------------
+
+output spi_sck ; // clock
+output spi_so ; // data out
+input spi_si ; // data in
+output [3:0] spi_cs_n ; // chip select
+
+//----------------------------------------
+// 8051 core ROM related signals
+//---------------------------------------
+output [15:0] wb_xrom_adr ; // instruction address
+input wb_xrom_ack ; // instruction acknowlage
+output wb_xrom_err ; // instruction error
+output wb_xrom_wr ; // instruction error
+input [31:0] wb_xrom_rdata ; // rom data input
+output [31:0] wb_xrom_wdata ; // rom data input
+
+output wb_xrom_stb ; // instruction strobe
+output wb_xrom_cyc ; // instruction cycle
+
+
+//----------------------------------------
+// 8051 core RAM related signals
+//---------------------------------------
+output [15:0] wb_xram_adr ; // data-ram address
+input wb_xram_ack ; // data-ram acknowlage
+output wb_xram_err ; // data-ram error
+output wb_xram_wr ; // data-ram error
+output [3:0] wb_xram_be ; // Byte enable
+input [31:0] wb_xram_rdata ; // ram data input
+output [31:0] wb_xram_wdata ; // ram data input
+
+output wb_xram_stb ; // data-ram strobe
+output wb_xram_cyc ; // data-ram cycle
+
+
+input ea_in ; // input for external access (ea signal)
+ // ea=0 program is in external rom
+ // ea=1 program is in internal rom
+//---------------------------------------------
+// 8051 Instruction ROM interface
+//---------------------------------------------
+wire [15:0] wbi_risc_adr;
+wire [31:0] wbi_risc_rdata;
+
+
+//-----------------------------
+// MAC Related wire Decleration
+//-----------------------------
+wire [8:0] app_rxfifo_rddata_o ;
+wire [31:0] app_rx_desc_data ;
+wire mdio_out_en ;
+wire mdio_out ;
+wire gen_resetn ;
+
+
+//---------------------------------------------
+// 8051 Instruction RAM interface
+//---------------------------------------------
+wire [15:0] wbd_risc_adr ;
+wire [7:0] wbd_risc_rdata ;
+wire [7:0] wbd_risc_wdata ;
+
+wire [14:0] reg_mac_addr ;
+wire [31:0] reg_mac_wdata ;
+wire [3:0] reg_mac_be ;
+wire [31:0] reg_mac_rdata ;
+wire reg_mac_ack ;
+
+wire [14:0] reg_uart_addr ;
+wire [31:0] reg_uart_wdata ;
+wire [3:0] reg_uart_be ;
+wire [31:0] reg_uart_rdata ;
+wire reg_uart_ack ;
+
+wire [14:0] reg_spi_addr ;
+wire [31:0] reg_spi_wdata ;
+wire [3:0] reg_spi_be ;
+wire [31:0] reg_spi_rdata ;
+wire reg_spi_ack ;
+
+wire [3:0] wb_xrom_be ;
+wire [3:0] wb_xram_be ;
+
+wire [7:0] p0 ;
+wire [7:0] p1 ;
+wire [7:0] p2 ;
+wire [7:0] p3 ;
+
+wire [3:0] wbgt_taddr ;
+wire [31:0] wbgt_din ;
+wire [31:0] wbgt_dout ;
+wire [12:0] wbgt_addr ;
+wire [3:0] wbgt_be ;
+wire wbgt_we ;
+wire wbgt_ack ;
+wire wbgt_stb ;
+wire wbgt_cyc ;
+
+wire [3:0] wbgr_taddr ;
+wire [31:0] wbgr_din ;
+wire [31:0] wbgr_dout ;
+wire [12:0] wbgr_addr ;
+wire [3:0] wbgr_be ;
+wire wbgr_we ;
+wire wbgr_ack ;
+wire wbgr_stb ;
+wire wbgr_cyc ;
+
+wire [8:0] app_txfifo_wrdata_i;
+wire [15:0] app_txfifo_addr;
+wire [15:0] app_rxfifo_addr;
+wire [3:0] tx_qcnt ;
+wire [3:0] rx_qcnt ;
+
+wire tx_q_empty = (tx_qcnt == 0);
+wire rx_q_empty = (rx_qcnt == 0);
+
+wire [31:0] reg_rdata = (reg_mac_ack) ? reg_mac_rdata :
+ (reg_uart_ack) ? reg_uart_rdata :
+ (reg_spi_ack) ? reg_spi_rdata : 'h0;
+
+wire reg_ack = reg_mac_ack | reg_uart_ack | reg_spi_ack;
+
+
+assign reset_out_n = gen_resetn;
+
+
+assign wb_xram_adr[15] = 0;
+assign wb_xram_adr[1:0] = 2'b00;
+assign wb_xrom_adr[15:13] = 0;
+
+wire [9:0] cfg_tx_buf_qbase_addr;
+wire [9:0] cfg_rx_buf_qbase_addr;
+
+// QCounter Inc/dec generation
+
+wire tx_qcnt_inc = (cfg_tx_buf_qbase_addr == wb_xram_adr[15:6]) & wb_xram_stb & wb_xram_wr & wb_xram_ack && (wb_xram_be[3] == 1'b1);
+wire tx_qcnt_dec = (cfg_tx_buf_qbase_addr == wb_xram_adr[15:6]) & wb_xram_stb & !wb_xram_wr & wb_xram_ack && (wb_xram_be[3] == 1'b1);
+wire rx_qcnt_inc = (cfg_rx_buf_qbase_addr == wb_xram_adr[15:6]) & wb_xram_stb & wb_xram_wr & wb_xram_ack && (wb_xram_be[3] == 1'b1);
+wire rx_qcnt_dec = (cfg_rx_buf_qbase_addr == wb_xram_adr[15:6]) & wb_xram_stb & !wb_xram_wr & wb_xram_ack && (wb_xram_be[3] == 1'b1);
+
+assign reg_mac_addr[1:0] = 2'b0;
+assign reg_uart_addr[1:0] = 2'b0;
+assign reg_spi_addr[1:0] = 2'b0;
+//-------------------------------------------
+// clock-gen instantiation
+//-------------------------------------------
+clkgen u_clkgen (
+ . reset_n (reset_n ),
+ . fastsim_mode (fastsim_mode ),
+ . mastermode (mastermode ),
+ . xtal_clk (xtal_clk ),
+ . clkout (clkout ),
+ . gen_resetn (gen_resetn ),
+ . risc_reset (risc_reset ),
+ . app_clk (app_clk ),
+ . uart_ref_clk (uart_clk_16x )
+
+ );
+
+//--------------------------------------------------------------
+// Target ID Mapping
+// 4'b0100 -- MAC core
+// 4'b0011 -- UART
+// 4'b0010 -- SPI core
+// 4'b0001 -- External RAM
+// 4'b0000 -- External ROM
+//--------------------------------------------------------------
+
+
+wire [31:0] wb_master2_rdata;
+
+wire [3:0] wb_master2_be = (wbd_risc_adr[1:0] == 2'b00) ? 4'b0001:
+ (wbd_risc_adr[1:0] == 2'b01) ? 4'b0010:
+ (wbd_risc_adr[1:0] == 2'b10) ? 4'b0100: 4'b1000;
+
+assign wbd_risc_rdata = (wbd_risc_adr[1:0] == 2'b00) ? wb_master2_rdata[7:0]:
+ (wbd_risc_adr[1:0] == 2'b01) ? wb_master2_rdata[15:8]:
+ (wbd_risc_adr[1:0] == 2'b10) ? wb_master2_rdata[23:16]:
+ wb_master2_rdata[31:24];
+
+//------------------------------
+// RISC Data Memory Map
+// 0x0000 to 0x7FFFF - Data Memory
+// 0x8000 to 0x8FFF - SPI
+// 0x9000 to 0x9FFF - UART
+// 0xA000 to 0xAFFF - MAC Core
+//-----------------------------
+//
+wire [3:0] wbd_tar_id = (wbd_risc_adr[15] == 1'b0 ) ? 4'b0001 :
+ (wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0010 :
+ (wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0011 : 4'b0100;
+
+wb_crossbar #(5,5,32,4,13,4) u_wb_crossbar (
+
+ .rst_n (gen_resetn ),
+ .clk (app_clk ),
+
+
+ // Master Interface Signal
+ .wbd_taddr_master ({4'b0000,
+ wbd_tar_id,
+ ext_reg_tid,
+ wbgt_taddr,
+ wbgr_taddr}),
+ .wbd_din_master ({32'h0 ,
+ {wbd_risc_wdata[7:0],
+ wbd_risc_wdata[7:0],
+ wbd_risc_wdata[7:0],
+ wbd_risc_wdata[7:0]},
+ ext_reg_wdata,
+ wbgt_din,
+ wbgr_din}
+ ),
+ .wbd_dout_master ({wbi_risc_rdata,
+ wb_master2_rdata,
+ ext_reg_rdata,
+ wbgt_dout,
+ wbgr_dout}
+ ),
+ .wbd_adr_master ({wbi_risc_adr[12:0],
+ wbd_risc_adr[14:2],
+ ext_reg_addr[14:2],
+ wbgt_addr,
+ wbgr_addr}
+ ),
+ .wbd_be_master ({4'b1111,
+ wb_master2_be,
+ ext_reg_be,
+ wbgt_be,
+ wbgr_be}
+ ),
+ .wbd_we_master ({1'b0,wbd_risc_we,ext_reg_wr,
+ wbgt_we,wbgr_we} ),
+ .wbd_ack_master ({wbi_risc_ack,
+ wbd_risc_ack,
+ ext_reg_ack,
+ wbgt_ack,
+ wbgr_ack} ),
+ .wbd_stb_master ({wbi_risc_stb,
+ wbd_risc_stb,
+ ext_reg_cs,
+ wbgt_stb,
+ wbgr_stb} ),
+ .wbd_cyc_master ({wbi_risc_stb|wbi_risc_ack,
+ wbd_risc_stb|wbd_risc_ack,
+ ext_reg_cs|ext_reg_ack,
+ wbgt_cyc,wbgr_cyc}),
+ .wbd_err_master (),
+ .wbd_rty_master (),
+
+ // Slave Interface Signal
+ .wbd_din_slave ({
+ reg_mac_wdata,
+ reg_uart_wdata,
+ reg_spi_wdata,
+ wb_xram_wdata,
+ wb_xrom_wdata
+ }),
+ .wbd_dout_slave ({
+ reg_mac_rdata,
+ reg_uart_rdata,
+ reg_spi_rdata,
+ {wb_xram_rdata},
+ wb_xrom_rdata
+ }),
+ .wbd_adr_slave ({reg_mac_addr[14:2],
+ reg_uart_addr[14:2],
+ reg_spi_addr[14:2],
+ wb_xram_adr[14:2],
+ wb_xrom_adr[12:0]}
+ ),
+ .wbd_be_slave ({reg_mac_be,
+ reg_uart_be,
+ reg_spi_be,
+ wb_xram_be,
+ wb_xrom_be}
+ ),
+ .wbd_we_slave ({reg_mac_wr,
+ reg_uart_wr,
+ reg_spi_wr,
+ wb_xram_wr,
+ wb_xrom_wr
+ }),
+ .wbd_ack_slave ({reg_mac_ack,
+ reg_uart_ack,
+ reg_spi_ack,
+ wb_xram_ack,
+ wb_xrom_ack
+ }),
+ .wbd_stb_slave ({reg_mac_cs,
+ reg_uart_cs,
+ reg_spi_cs,
+ wb_xram_stb,
+ wb_xrom_stb
+ }),
+ .wbd_cyc_slave (),
+ .wbd_err_slave (),
+ .wbd_rty_slave ()
+ );
+
+
+//-------------------------------------------
+// GMAC core instantiation
+//-------------------------------------------
+
+g_mac_top u_eth_dut (
+
+ .scan_mode (1'b0 ),
+ .s_reset_n (gen_resetn ),
+ .tx_reset_n (gen_resetn ),
+ .rx_reset_n (gen_resetn ),
+ .reset_mdio_clk_n (gen_resetn ),
+ .app_reset_n (gen_resetn ),
+
+ // Reg Bus Interface Signal
+ . reg_cs (reg_mac_cs ),
+ . reg_wr (reg_mac_wr ),
+ . reg_addr (reg_mac_addr[5:2] ),
+ . reg_wdata (reg_mac_wdata ),
+ . reg_be (reg_mac_be ),
+
+ // Outputs
+ . reg_rdata (reg_mac_rdata ),
+ . reg_ack (reg_mac_ack ),
+
+
+ .app_clk (app_clk ),
+
+ // Application RX FIFO Interface
+ .app_txfifo_wren_i (app_txfifo_wren_i ),
+ .app_txfifo_wrdata_i (app_txfifo_wrdata_i ),
+ .app_txfifo_addr (app_txfifo_addr ),
+ .app_txfifo_full_o (app_txfifo_full_o ),
+ .app_txfifo_afull_o (app_txfifo_afull_o ),
+ .app_txfifo_space_o ( ),
+
+ // Application TX FIFO Interface
+ .app_rxfifo_rden_i (app_rxfifo_rden_i ),
+ .app_rxfifo_empty_o (app_rxfifo_empty_o ),
+ .app_rxfifo_aempty_o (app_rxfifo_aempty_o ),
+ .app_rxfifo_cnt_o ( ),
+ .app_rxfifo_rdata_o (app_rxfifo_rddata_o ),
+ .app_rxfifo_addr (app_rxfifo_addr ),
+
+ .app_rx_desc_req (app_rx_desc_req ),
+ .app_rx_desc_ack (app_rx_desc_ack ),
+ .app_rx_desc_discard (app_rx_desc_discard ),
+ .app_rx_desc_data (app_rx_desc_data ),
+
+ // Line Side Interface TX Path
+ .phy_tx_en (phy_tx_en ),
+ .phy_tx_er ( ),
+ .phy_txd (phy_txd ),
+ .phy_tx_clk (phy_tx_clk ),
+
+ // Line Side Interface RX Path
+ .phy_rx_clk (phy_rx_clk ),
+ .phy_rx_er (1'b0 ),
+ .phy_rx_dv (phy_rx_dv ),
+ .phy_rxd (phy_rxd ),
+ .phy_crs (1'b0 ),
+
+ //MDIO interface
+ .mdio_clk (mdio_clk ),
+ .mdio_in (mdio_in ),
+ .mdio_out_en (mdio_out_en ),
+ .mdio_out (mdio_out ),
+
+ // QCounter
+ .rx_buf_qbase_addr (cfg_rx_buf_qbase_addr),
+ .tx_buf_qbase_addr (cfg_tx_buf_qbase_addr),
+
+ .tx_qcnt_inc (tx_qcnt_inc),
+ .tx_qcnt_dec (tx_qcnt_dec),
+ .rx_qcnt_inc (rx_qcnt_inc),
+ .rx_qcnt_dec (rx_qcnt_dec),
+ .tx_qcnt (tx_qcnt),
+ .rx_qcnt (rx_qcnt)
+
+
+ );
+
+
+
+
+
+wb_rd_mem2mem #(.D_WD(32),.BE_WD(4),.ADR_WD(13),.TAR_WD(4)) u_wb_gmac_tx (
+
+ .rst_n ( gen_resetn ),
+ .clk ( app_clk ),
+
+ // descriptor handshake
+ .cfg_desc_baddr (cfg_tx_buf_qbase_addr),
+ .desc_q_empty (tx_q_empty ),
+
+ // Master Interface Signal
+ .mem_taddr ( 4'h1 ),
+ .mem_full (app_txfifo_full_o ),
+ .mem_afull (app_txfifo_afull_o ),
+ .mem_wr (app_txfifo_wren_i ),
+ .mem_din (app_txfifo_wrdata_i ),
+
+ // Slave Interface Signal
+ .wbo_dout ( wbgt_dout ),
+ .wbo_taddr ( wbgt_taddr ),
+ .wbo_addr ( wbgt_addr ),
+ .wbo_be ( wbgt_be ),
+ .wbo_we ( wbgt_we ),
+ .wbo_ack ( wbgt_ack ),
+ .wbo_stb ( wbgt_stb ),
+ .wbo_cyc ( wbgt_cyc ),
+ .wbo_err ( wbgt_err ),
+ .wbo_rty ( wbgt_rty )
+ );
+
+
+wb_wr_mem2mem #(.D_WD(32),.BE_WD(4),.ADR_WD(13),.TAR_WD(4)) u_wb_gmac_rx(
+
+ .rst_n ( gen_resetn ),
+ .clk ( app_clk ),
+
+
+ // Master Interface Signal
+ .mem_taddr ( 4'h1 ),
+ .mem_addr (app_rxfifo_addr ),
+ .mem_empty (app_rxfifo_empty_o ),
+ .mem_aempty (app_rxfifo_aempty_o ),
+ .mem_rd (app_rxfifo_rden_i ),
+ .mem_dout (app_rxfifo_rddata_o[7:0]),
+ .mem_eop (app_rxfifo_rddata_o[8]),
+
+ .cfg_desc_baddr (cfg_rx_buf_qbase_addr ),
+ .desc_req (app_rx_desc_req ),
+ .desc_ack (app_rx_desc_ack ),
+ .desc_disccard (app_rx_desc_discard ),
+ .desc_data (app_rx_desc_data ),
+ // Slave Interface Signal
+ .wbo_din ( wbgr_din ),
+ .wbo_taddr ( wbgr_taddr ),
+ .wbo_addr ( wbgr_addr ),
+ .wbo_be ( wbgr_be ),
+ .wbo_we ( wbgr_we ),
+ .wbo_ack ( wbgr_ack ),
+ .wbo_stb ( wbgr_stb ),
+ .wbo_cyc ( wbgr_cyc ),
+ .wbo_err ( wbgr_err ),
+ .wbo_rty ( wbgr_rty )
+ );
+
+//-------------------------------------
+// UART core instantiation
+//-------------------------------------
+
+uart_core u_uart_core
+
+ (
+ . line_reset_n (gen_resetn ),
+ . line_clk_16x (uart_clk_16x ),
+
+ . app_reset_n (gen_resetn ),
+ . app_clk (app_clk ),
+
+
+ // Reg Bus Interface Signal
+ . reg_cs (reg_uart_cs ),
+ . reg_wr (reg_uart_wr ),
+ . reg_addr (reg_uart_addr[5:2] ),
+ . reg_wdata (reg_uart_wdata ),
+ . reg_be (reg_uart_be ),
+
+ // Outputs
+ . reg_rdata (reg_uart_rdata ),
+ . reg_ack (reg_uart_ack ),
+
+
+
+ // Line Interface
+ . si (si ),
+ . so (so )
+
+ );
+
+
+//--------------------------------
+// SPI core instantiation
+//--------------------------------
+
+
+spi_core u_spi_core (
+
+ . clk (app_clk ),
+ . reset_n (gen_resetn ),
+
+ // Reg Bus Interface Signal
+ . reg_cs (reg_spi_cs ),
+ . reg_wr (reg_spi_wr ),
+ . reg_addr (reg_spi_addr[5:2] ),
+ . reg_wdata (reg_spi_wdata ),
+ . reg_be (reg_spi_be ),
+
+ // Outputs
+ . reg_rdata (reg_spi_rdata ),
+ . reg_ack (reg_spi_ack ),
+
+
+ . sck (spi_sck ),
+ . so (spi_so ),
+ . si (spi_si ),
+ . cs_n (spi_cs_n )
+
+ );
+
+
+
+oc8051_top u_8051_core (
+ . wb_rst_i (risc_reset ),
+ . wb_clk_i (app_clk ),
+
+//interface to instruction rom
+ . wbi_adr_o (wbi_risc_adr ),
+ . wbi_dat_i (wbi_risc_rdata ),
+ . wbi_stb_o (wbi_risc_stb ),
+ . wbi_ack_i (wbi_risc_ack ),
+ . wbi_cyc_o (wbi_risc_cyc ),
+ . wbi_err_i (wbi_risc_err ),
+
+//interface to data ram
+ . wbd_dat_i (wbd_risc_rdata ),
+ . wbd_dat_o (wbd_risc_wdata ),
+ . wbd_adr_o (wbd_risc_adr ),
+ . wbd_we_o (wbd_risc_we ),
+ . wbd_ack_i (wbd_risc_ack ),
+ . wbd_stb_o (wbd_risc_stb ),
+ . wbd_cyc_o (wbd_risc_cyc ),
+ . wbd_err_i (wbd_risc_err ),
+
+// interrupt interface
+ . int0_i ( ),
+ . int1_i ( ),
+
+
+// port interface
+ `ifdef OC8051_PORTS
+ `ifdef OC8051_PORT0
+ .p0_i ( p0 ),
+ .p0_o ( p0 ),
+ `endif
+
+ `ifdef OC8051_PORT1
+ .p1_i ( p1 ),
+ .p1_o ( p1 ),
+ `endif
+
+ `ifdef OC8051_PORT2
+ .p2_i ( p2 ),
+ .p2_o ( p2 ),
+ `endif
+
+ `ifdef OC8051_PORT3
+ .p3_i ( p3 ),
+ .p3_o ( p3 ),
+ `endif
+ `endif
+
+// serial interface
+ `ifdef OC8051_UART
+ .rxd_i ( ),
+ .txd_o ( ),
+ `endif
+
+// counter interface
+ `ifdef OC8051_TC01
+ .t0_i ( ),
+ .t1_i ( ),
+ `endif
+
+ `ifdef OC8051_TC2
+ .t2_i ( ),
+ .t2ex_i ( ),
+ `endif
+
+// BIST
+`ifdef OC8051_BIST
+ .scanb_rst ( ),
+ .scanb_clk ( ),
+ .scanb_si ( ),
+ .scanb_so ( ),
+ .scanb_en ( ),
+`endif
+// external access (active low)
+ .ea_in (ea_in )
+ );
+
+endmodule
diff --git a/verilog/rtl/glbl/src/glbl_cfg.sv b/verilog/rtl/glbl/src/glbl_cfg.sv
new file mode 100644
index 0000000..6ce06a1
--- /dev/null
+++ b/verilog/rtl/glbl/src/glbl_cfg.sv
@@ -0,0 +1,576 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Global confg register ////
+//// ////
+//// This file is part of the mbist_ctrl project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block generate all the global config and status ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 18 Nov 2021 Dinesh A ////
+//// Initial version ////
+//// 0.2 - 27 Nov 2021, Dinesh A ////
+//// Scan Ports added & Chip ID change to LBST ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module glbl_cfg #(parameter SCW = 8 // SCAN CHAIN WIDTH
+ ) (
+
+`ifdef USE_POWER_PINS
+ inout vccd1, // User area 1 1.8V supply
+ inout vssd1, // User area 1 digital ground
+`endif
+
+ input logic mclk,
+ input logic reset_n,
+
+ // Scan I/F
+ input logic scan_en,
+ input logic scan_mode,
+ input logic [SCW-1:0] scan_si,
+ output logic [SCW-1:0] scan_so,
+ output logic scan_en_o,
+ output logic scan_mode_o,
+
+ // Clock Skew Adjust
+ input logic wbd_clk_int ,
+ input logic [3:0] cfg_cska_glbl ,
+ output logic wbd_clk_glbl , // clock skew adjust for web host
+
+
+ // Reg Bus Interface Signal
+ input logic reg_cs,
+ input logic reg_wr,
+ input logic [7:0] reg_addr,
+ input logic [31:0] reg_wdata,
+ input logic [3:0] reg_be,
+
+ // Outputs
+ output logic [31:0] reg_rdata,
+ output logic reg_ack,
+
+ // BIST I/F
+ output logic [7:0] bist_en,
+ output logic [7:0] bist_run,
+ output logic [7:0] bist_load,
+
+ output logic [7:0] bist_sdi,
+ output logic [7:0] bist_shift,
+ input logic [7:0] bist_sdo,
+
+ input logic [7:0] bist_done,
+ input logic [7:0] bist_error,
+ input logic [7:0] bist_correct,
+ input logic [3:0] bist_error_cnt0,
+ input logic [3:0] bist_error_cnt1,
+ input logic [3:0] bist_error_cnt2,
+ input logic [3:0] bist_error_cnt3,
+ input logic [3:0] bist_error_cnt4,
+ input logic [3:0] bist_error_cnt5,
+ input logic [3:0] bist_error_cnt6,
+ input logic [3:0] bist_error_cnt7
+
+ );
+
+
+
+//-----------------------------------------------------------------------
+// Internal Wire Declarations
+//-----------------------------------------------------------------------
+
+logic sw_rd_en ;
+logic sw_wr_en ;
+logic [3:0] sw_addr ; // addressing 16 registers
+logic [3:0] wr_be ;
+logic [31:0] sw_reg_wdata;
+
+
+
+logic [31:0] reg_0; // Software_Reg 0
+logic [31:0] reg_1; // Software Reg 1
+logic [7:0] cfg_bist_ctrl_1; // BIST control
+logic [31:0] cfg_bist_ctrl_2; // BIST control
+logic [31:0] cfg_bist_status_1; // BIST Status
+logic [31:0] cfg_bist_status_2; // BIST Status
+logic [31:0] serail_dout; // BIST Serial Signature
+logic [31:0] reg_9; // Software_Reg 9
+logic [31:0] reg_10; // Software Reg 10
+logic [31:0] reg_11; // Software Reg 11
+
+logic [31:0] reg_out;
+
+//-----------------------------------------------------------------------
+// Main code starts here
+//-----------------------------------------------------------------------
+
+
+assign scan_en_o = scan_en;
+assign scan_mode_o = scan_mode;
+
+// wb_host clock skew control
+clk_skew_adjust u_skew_glbl
+ (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ .clk_in (wbd_clk_int ),
+ .sel (cfg_cska_glbl ),
+ .clk_out (wbd_clk_glbl )
+ );
+
+//-----------------------------------------------------------------------
+// register read enable and write enable decoding logic
+//-----------------------------------------------------------------------
+
+assign sw_addr = reg_addr [5:2];
+assign sw_rd_en = reg_cs & !reg_wr;
+assign sw_wr_en = reg_cs & reg_wr;
+assign wr_be = reg_be;
+assign sw_reg_wdata = reg_wdata;
+
+
+wire sw_wr_en_0 = sw_wr_en & (sw_addr == 4'h0);
+wire sw_rd_en_0 = sw_rd_en & (sw_addr == 4'h0);
+wire sw_wr_en_1 = sw_wr_en & (sw_addr == 4'h1);
+wire sw_rd_en_1 = sw_rd_en & (sw_addr == 4'h1);
+wire sw_wr_en_2 = sw_wr_en & (sw_addr == 4'h2);
+wire sw_rd_en_2 = sw_rd_en & (sw_addr == 4'h2);
+wire sw_wr_en_3 = sw_wr_en & (sw_addr == 4'h3);
+wire sw_rd_en_3 = sw_rd_en & (sw_addr == 4'h3);
+wire sw_wr_en_4 = sw_wr_en & (sw_addr == 4'h4);
+wire sw_rd_en_4 = sw_rd_en & (sw_addr == 4'h4);
+wire sw_wr_en_5 = sw_wr_en & (sw_addr == 4'h5);
+wire sw_rd_en_5 = sw_rd_en & (sw_addr == 4'h5);
+wire sw_wr_en_6 = sw_wr_en & (sw_addr == 4'h6);
+wire sw_rd_en_6 = sw_rd_en & (sw_addr == 4'h6);
+wire sw_wr_en_7 = sw_wr_en & (sw_addr == 4'h7);
+wire sw_rd_en_7 = sw_rd_en & (sw_addr == 4'h7);
+wire sw_wr_en_8 = sw_wr_en & (sw_addr == 4'h8);
+wire sw_wr_en_9 = sw_wr_en & (sw_addr == 4'h9);
+wire sw_wr_en_10 = sw_wr_en & (sw_addr == 4'hA);
+wire sw_wr_en_11 = sw_wr_en & (sw_addr == 4'hB);
+
+logic wb_req;
+logic wb_req_d;
+logic wb_req_pedge;
+
+always_ff @(negedge reset_n or posedge mclk) begin
+ if ( reset_n == 1'b0 ) begin
+ wb_req <= '0;
+ wb_req_d <= '0;
+ end else begin
+ wb_req <= reg_cs && (reg_ack == 0) ;
+ wb_req_d <= wb_req;
+ end
+end
+
+// Detect pos edge of request
+assign wb_req_pedge = (wb_req_d ==0) && (wb_req==1'b1);
+//-----------------------------------------------------------------
+// Reg 4/5 are BIST Serial I/F register and it takes minimum 32
+// cycle to respond ACK back
+// ----------------------------------------------------------------
+wire ser_acc = sw_wr_en_6 | sw_rd_en_7;
+wire non_ser_acc = reg_cs ? !ser_acc : 1'b0;
+wire serial_ack;
+
+always @ (posedge mclk or negedge reset_n)
+begin : preg_out_Seq
+ if (reset_n == 1'b0) begin
+ reg_rdata <= 'h0;
+ reg_ack <= 1'b0;
+ end else if (ser_acc && serial_ack) begin
+ reg_rdata <= serail_dout ;
+ reg_ack <= 1'b1;
+ end else if (non_ser_acc && !reg_ack) begin
+ reg_rdata <= reg_out ;
+ reg_ack <= 1'b1;
+ end else begin
+ reg_ack <= 1'b0;
+ end
+end
+
+always @( *)
+begin
+ reg_out [31:0] = 32'h0;
+
+ case (sw_addr [3:0])
+ 4'b0000 : reg_out [31:0] = reg_0;
+ 4'b0001 : reg_out [31:0] = reg_1;
+ 4'b0010 : reg_out [31:0] = {24'h0,cfg_bist_ctrl_1};
+ 4'b0011 : reg_out [31:0] = cfg_bist_ctrl_2 [31:0];
+ 4'b0100 : reg_out [31:0] = cfg_bist_status_1 [31:0];
+ 4'b0101 : reg_out [31:0] = cfg_bist_status_2 [31:0];
+ 4'b0110 : reg_out [31:0] = 'h0; // Serial Write Data
+ 4'b0111 : reg_out [31:0] = serail_dout; // This is with Shift
+ 4'b1000 : reg_out [31:0] = serail_dout; // This is previous Shift
+ 4'b1001 : reg_out [31:0] = reg_9; // Software Reg1
+ 4'b1010 : reg_out [31:0] = reg_10; // Software Reg2
+ 4'b1011 : reg_out [31:0] = reg_11; // Software Reg3
+ default : reg_out [31:0] = 'h0;
+ endcase
+end
+
+
+//-----------------------------------------------------------------------
+// Individual register assignments
+//-----------------------------------------------------------------------
+//-----------------------------------------------------------------------
+// reg-0
+// -----------------------------------------------------------------
+generic_register #(8,8'h11 ) u_reg0_be0 (
+ .we ({8{sw_wr_en_0 &
+ wr_be[0] }} ),
+ .data_in (sw_reg_wdata[7:0] ),
+ .reset_n (reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (reg_0[7:0] )
+ );
+
+generic_register #(8,8'h22 ) u_reg0_be1 (
+ .we ({8{sw_wr_en_0 &
+ wr_be[1] }} ),
+ .data_in (sw_reg_wdata[15:8] ),
+ .reset_n (reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (reg_0[15:8] )
+ );
+generic_register #(8,8'h33 ) u_reg0_be2 (
+ .we ({8{sw_wr_en_0 &
+ wr_be[2] }} ),
+ .data_in (sw_reg_wdata[23:16] ),
+ .reset_n (reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (reg_0[23:16] )
+ );
+
+generic_register #(8,8'h44 ) u_reg0_be3 (
+ .we ({8{sw_wr_en_0 &
+ wr_be[3] }} ),
+ .data_in (sw_reg_wdata[31:24] ),
+ .reset_n (reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (reg_0[31:24] )
+ );
+
+//-----------------------------------------------------------------------
+// reg-1
+// -----------------------------------------------------------------
+generic_register #(8,8'hAA ) u_reg1_be0 (
+ .we ({8{sw_wr_en_1 &
+ wr_be[0] }} ),
+ .data_in (sw_reg_wdata[7:0] ),
+ .reset_n (reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (reg_1[7:0] )
+ );
+
+generic_register #(8,8'hBB ) u_reg1_be1 (
+ .we ({8{sw_wr_en_1 &
+ wr_be[1] }} ),
+ .data_in (sw_reg_wdata[15:8] ),
+ .reset_n (reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (reg_1[15:8] )
+ );
+generic_register #(8,8'hCC ) u_reg1_be2 (
+ .we ({8{sw_wr_en_1 &
+ wr_be[2] }} ),
+ .data_in (sw_reg_wdata[23:16] ),
+ .reset_n (reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (reg_1[23:16] )
+ );
+
+generic_register #(8,8'hDD ) u_reg1_be3 (
+ .we ({8{sw_wr_en_1 &
+ wr_be[3] }} ),
+ .data_in (sw_reg_wdata[31:24] ),
+ .reset_n (reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (reg_1[31:24] )
+ );
+
+//-----------------------------------------------------------------------
+// reg-2
+// -----------------------------------------------------------------
+generic_register #(8,8'h0 ) u_reg2_be0 (
+ .we ({8{sw_wr_en_2 &
+ wr_be[0] }} ),
+ .data_in (sw_reg_wdata[7:0] ),
+ .reset_n (reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (cfg_bist_ctrl_1[7:0] )
+ );
+
+
+wire [3:0] bist_serial_sel = cfg_bist_ctrl_1[3:0];
+//-----------------------------------------------------------------------
+// reg-3
+// -----------------------------------------------------------------
+// Bist control
+assign bist_en[0] = cfg_bist_ctrl_2[0];
+assign bist_run[0] = cfg_bist_ctrl_2[1];
+assign bist_load[0] = cfg_bist_ctrl_2[2];
+
+assign bist_en[1] = cfg_bist_ctrl_2[4];
+assign bist_run[1] = cfg_bist_ctrl_2[5];
+assign bist_load[1] = cfg_bist_ctrl_2[6];
+
+assign bist_en[2] = cfg_bist_ctrl_2[8];
+assign bist_run[2] = cfg_bist_ctrl_2[9];
+assign bist_load[2] = cfg_bist_ctrl_2[10];
+
+assign bist_en[3] = cfg_bist_ctrl_2[12];
+assign bist_run[3] = cfg_bist_ctrl_2[13];
+assign bist_load[3] = cfg_bist_ctrl_2[14];
+
+assign bist_en[4] = cfg_bist_ctrl_2[16];
+assign bist_run[4] = cfg_bist_ctrl_2[17];
+assign bist_load[4] = cfg_bist_ctrl_2[18];
+
+assign bist_en[5] = cfg_bist_ctrl_2[20];
+assign bist_run[5] = cfg_bist_ctrl_2[21];
+assign bist_load[5] = cfg_bist_ctrl_2[22];
+
+assign bist_en[6] = cfg_bist_ctrl_2[24];
+assign bist_run[6] = cfg_bist_ctrl_2[25];
+assign bist_load[6] = cfg_bist_ctrl_2[26];
+
+assign bist_en[7] = cfg_bist_ctrl_2[28];
+assign bist_run[7] = cfg_bist_ctrl_2[29];
+assign bist_load[7] = cfg_bist_ctrl_2[30];
+
+
+
+generic_register #(8,8'h0 ) u_bist_ctrl_be0 (
+ .we ({8{sw_wr_en_3 &
+ wr_be[0] }} ),
+ .data_in (sw_reg_wdata[7:0] ),
+ .reset_n (reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (cfg_bist_ctrl_2[7:0] )
+ );
+
+generic_register #(8,8'h0 ) u_bist_ctrl_be1 (
+ .we ({8{sw_wr_en_3 &
+ wr_be[1] }} ),
+ .data_in (sw_reg_wdata[15:8] ),
+ .reset_n (reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (cfg_bist_ctrl_2[15:8] )
+ );
+generic_register #(8,8'h0 ) u_bist_ctrl_be2 (
+ .we ({8{sw_wr_en_3 &
+ wr_be[2] }} ),
+ .data_in (sw_reg_wdata[23:16] ),
+ .reset_n (reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (cfg_bist_ctrl_2[23:16] )
+ );
+
+generic_register #(8,8'h0 ) u_bist_ctrl_be3 (
+ .we ({8{sw_wr_en_3 &
+ wr_be[3] }} ),
+ .data_in (sw_reg_wdata[31:24] ),
+ .reset_n (reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (cfg_bist_ctrl_2[31:24] )
+ );
+
+
+//-----------------------------------------------------------------------
+// reg-3
+//-----------------------------------------------------------------
+
+assign cfg_bist_status_2 = { bist_error_cnt7, 1'b0, bist_correct[7], bist_error[7], bist_done[7],
+ bist_error_cnt6, 1'b0, bist_correct[6], bist_error[6], bist_done[6],
+ bist_error_cnt5, 1'b0, bist_correct[5], bist_error[5], bist_done[5],
+ bist_error_cnt4, 1'b0, bist_correct[4], bist_error[4], bist_done[4]
+ };
+assign cfg_bist_status_1 = { bist_error_cnt3, 1'b0, bist_correct[3], bist_error[3], bist_done[3],
+ bist_error_cnt2, 1'b0, bist_correct[2], bist_error[2], bist_done[2],
+ bist_error_cnt1, 1'b0, bist_correct[1], bist_error[1], bist_done[1],
+ bist_error_cnt0, 1'b0, bist_correct[0], bist_error[0], bist_done[0]
+ };
+
+//-----------------------------------------------------------------------
+// reg-4 => Write to Serail I/F
+// reg-5 => READ from Serail I/F
+//-----------------------------------------------------------------
+wire bist_sdi_int;
+wire bist_shift_int;
+wire bist_sdo_int;
+
+assign bist_sdo_int = (bist_serial_sel == 4'b0000) ? bist_sdo[0] :
+ (bist_serial_sel == 4'b0001) ? bist_sdo[1] :
+ (bist_serial_sel == 4'b0010) ? bist_sdo[2] :
+ (bist_serial_sel == 4'b0011) ? bist_sdo[3] :
+ (bist_serial_sel == 4'b0100) ? bist_sdo[4] :
+ (bist_serial_sel == 4'b0101) ? bist_sdo[5] :
+ (bist_serial_sel == 4'b0110) ? bist_sdo[6] :
+ (bist_serial_sel == 4'b0111) ? bist_sdo[7] :
+ 1'b0;
+
+assign bist_shift[0] = (bist_serial_sel == 4'b0000) ? bist_shift_int : 1'b0;
+assign bist_shift[1] = (bist_serial_sel == 4'b0001) ? bist_shift_int : 1'b0;
+assign bist_shift[2] = (bist_serial_sel == 4'b0010) ? bist_shift_int : 1'b0;
+assign bist_shift[3] = (bist_serial_sel == 4'b0011) ? bist_shift_int : 1'b0;
+assign bist_shift[4] = (bist_serial_sel == 4'b0100) ? bist_shift_int : 1'b0;
+assign bist_shift[5] = (bist_serial_sel == 4'b0101) ? bist_shift_int : 1'b0;
+assign bist_shift[6] = (bist_serial_sel == 4'b0110) ? bist_shift_int : 1'b0;
+assign bist_shift[7] = (bist_serial_sel == 4'b0111) ? bist_shift_int : 1'b0;
+
+assign bist_sdi[0] = (bist_serial_sel == 4'b0000) ? bist_sdi_int : 1'b0;
+assign bist_sdi[1] = (bist_serial_sel == 4'b0001) ? bist_sdi_int : 1'b0;
+assign bist_sdi[2] = (bist_serial_sel == 4'b0010) ? bist_sdi_int : 1'b0;
+assign bist_sdi[3] = (bist_serial_sel == 4'b0011) ? bist_sdi_int : 1'b0;
+assign bist_sdi[4] = (bist_serial_sel == 4'b0100) ? bist_sdi_int : 1'b0;
+assign bist_sdi[5] = (bist_serial_sel == 4'b0101) ? bist_sdi_int : 1'b0;
+assign bist_sdi[6] = (bist_serial_sel == 4'b0110) ? bist_sdi_int : 1'b0;
+assign bist_sdi[7] = (bist_serial_sel == 4'b0111) ? bist_sdi_int : 1'b0;
+
+ser_inf_32b u_ser_intf
+ (
+
+ // Master Port
+ .rst_n (reset_n), // Regular Reset signal
+ .clk (mclk), // System clock
+ .reg_wr (sw_wr_en_6 & wb_req_pedge), // Write Request
+ .reg_rd (sw_rd_en_7 & wb_req_pedge), // Read Request
+ .reg_wdata (reg_wdata) , // data output
+ .reg_rdata (serail_dout), // data input
+ .reg_ack (serial_ack), // acknowlegement
+
+ // Slave Port
+ .sdi (bist_sdi_int), // Serial SDI
+ .shift (bist_shift_int), // Shift Signal
+ .sdo (bist_sdo_int) // Serial SDO
+
+ );
+
+
+//-----------------------------------------
+// Software Reg-1 : ASCI Representation of LBST = 32'h4C66_8354
+// ----------------------------------------
+gen_32b_reg #(32'h4C66_8354) u_reg_9 (
+ //List of Inputs
+ .reset_n (reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_9 ),
+ .we (wr_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_9 )
+ );
+
+//-----------------------------------------
+// Software Reg-2, Release date: <DAY><MONTH><YEAR>
+// ----------------------------------------
+gen_32b_reg #(32'h1603_2022) u_reg_101 (
+ //List of Inputs
+ .reset_n (reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_10 ),
+ .we (wr_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_10 )
+ );
+
+//-----------------------------------------
+// Software Reg-3: Poject Revison 1.6 = 0001600
+// ----------------------------------------
+gen_32b_reg #(32'h0001_6000) u_reg_11 (
+ //List of Inputs
+ .reset_n (reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_11 ),
+ .we (wr_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_11 )
+ );
+
+endmodule
diff --git a/verilog/rtl/glbl/src/run_iverilog b/verilog/rtl/glbl/src/run_iverilog
new file mode 100755
index 0000000..d9b0e86
--- /dev/null
+++ b/verilog/rtl/glbl/src/run_iverilog
@@ -0,0 +1 @@
+iverilog -g2005-sv glbl_cfg.sv ../../lib/ser_inf_32b.sv ../../lib/registers.v
diff --git a/verilog/rtl/glbl/src/run_verilator b/verilog/rtl/glbl/src/run_verilator
new file mode 100755
index 0000000..aaa2366
--- /dev/null
+++ b/verilog/rtl/glbl/src/run_verilator
@@ -0,0 +1 @@
+verilator -cc glbl_cfg.sv ../../lib/ser_inf_32b.sv ../../lib/registers.v --top-module glbl_cfg
diff --git a/verilog/rtl/gmac/crc32/g_rx_crc32.v b/verilog/rtl/gmac/crc32/g_rx_crc32.v
new file mode 100755
index 0000000..c14ce14
--- /dev/null
+++ b/verilog/rtl/gmac/crc32/g_rx_crc32.v
@@ -0,0 +1,302 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+/***************************************************************
+ Description:
+ rx_crc32.v: This block contains the crc32 checker.
+ * CRC is generated in the receive data when mi2rc_rcv_valid is asserted.
+ * For the recieve data. crc_ok indicates whenther the packet was
+ * good or bad.
+ * The 32-bit crc shift register is reset to all 1's when
+ * mi2rc_strt_rcv is asserted.
+
+ *********************************************************************/
+module g_rx_crc32 (
+ // CRC Valid signal to rx_fsm
+ rc2rf_crc_ok,
+
+ // Global Signals
+ phy_rx_clk,
+ reset_n,
+ // CRC Data signals
+ mi2rc_strt_rcv,
+ mi2rc_rcv_valid,
+ mi2rc_rx_byte
+ );
+
+ // defx[ine inputs and outputs.
+
+ output rc2rf_crc_ok; // asserted when crc check is ok. to rx.
+
+ input phy_rx_clk; // serial clock from phy.
+ input reset_n; // global asynchronous reset.
+
+ input mi2rc_rcv_valid; // when asserted, crc is computed on
+ // rx_crc_data. from rx.
+ input mi2rc_strt_rcv; // when asserted, crc shift register is
+ // reset to all 1's. from rx.
+ input [7:0] mi2rc_rx_byte; // receive data. from rx.
+
+
+
+
+ // reg/wire declarations for primary outputs.
+ wire rc2rf_crc_ok;
+
+ // define constants and parameters here.
+ // define local signals here.
+
+ wire [7:0] crc_in;
+ wire gen_crc;
+ reg [31:0] current_crc, next_crc;
+ reg crc_ok_ul;
+
+ wire [31:0] rx_fcs;
+
+ // code starts here.
+
+ // select either rx_crc_data or tx_data as the input to crc generator.
+ assign crc_in = mi2rc_rx_byte;
+
+ // enable crc generator
+
+ assign gen_crc = mi2rc_rcv_valid ; //
+
+ // 32-bit crc shift register for crc calculation.
+
+ always @(posedge phy_rx_clk or negedge reset_n)
+ begin
+ if (!reset_n)
+ begin
+ current_crc <= 32'hffffffff;
+ end
+ else
+ begin
+ if (mi2rc_strt_rcv)
+ begin
+ current_crc <= 32'hffffffff;
+ end
+ else if (gen_crc) // generate crc
+ begin
+ current_crc <= next_crc;
+ end // else: !if(tx_reset_crc || mi2rc_strt_rcv)
+ end // else: !if(!reset_n)
+ end // always @ (posedge phy_rx_clk or negedge reset_n)
+
+ // combinational logic to generate next_crc
+
+ always @(current_crc or crc_in)
+ begin
+
+ next_crc[0] = current_crc[8] ^ current_crc[2] ^ crc_in[2];
+ next_crc[1] = current_crc[9] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[3] ^ crc_in[3];
+ next_crc[2] = current_crc[10] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[1] ^ crc_in[1] ^ current_crc[4] ^
+ crc_in[4];
+ next_crc[3] = current_crc[11] ^ current_crc[1] ^ crc_in[1] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[5] ^
+ crc_in[5];
+ next_crc[4] = current_crc[12] ^ current_crc[2] ^ crc_in[2] ^
+ current_crc[3] ^ crc_in[3] ^ current_crc[6] ^
+ current_crc[0] ^ crc_in[0] ^ crc_in[6];
+ next_crc[5] = current_crc[13] ^ current_crc[3] ^ crc_in[3] ^
+ current_crc[4] ^ crc_in[4] ^ current_crc[7] ^
+ current_crc[1] ^ crc_in[1] ^ crc_in[7];
+ next_crc[6] = current_crc[14] ^ current_crc[4] ^ crc_in[4] ^
+ current_crc[5] ^ crc_in[5];
+ next_crc[7] = current_crc[15] ^ current_crc[5] ^ crc_in[5] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6];
+ next_crc[8] = current_crc[16] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[9] = current_crc[17] ^ current_crc[1] ^ crc_in[1] ^
+ current_crc[7] ^ current_crc[1] ^ crc_in[1] ^
+ crc_in[7];
+ next_crc[10] = current_crc[18] ^ current_crc[2] ^ crc_in[2];
+ next_crc[11] = current_crc[19] ^ current_crc[3] ^ crc_in[3];
+ next_crc[12] = current_crc[20] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[4] ^ crc_in[4];
+ next_crc[13] = current_crc[21] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[1] ^ crc_in[1] ^ current_crc[5] ^
+ crc_in[5];
+ next_crc[14] = current_crc[22] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[1] ^ crc_in[1] ^ current_crc[2] ^
+ crc_in[2] ^ current_crc[6] ^ current_crc[0] ^
+ crc_in[0] ^ crc_in[6];
+ next_crc[15] = current_crc[23] ^ current_crc[1] ^ crc_in[1] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[16] = current_crc[24] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[4] ^ crc_in[4];
+ next_crc[17] = current_crc[25] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[1] ^ crc_in[1] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[4] ^ crc_in[4] ^
+ current_crc[5] ^ crc_in[5];
+ next_crc[18] = current_crc[26] ^ current_crc[1] ^ crc_in[1] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[4] ^
+ crc_in[4] ^ current_crc[5] ^ crc_in[5] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6];
+ next_crc[19] = current_crc[27] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[5] ^ crc_in[5] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[20] = current_crc[28] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[1] ^ crc_in[1] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[4] ^ crc_in[4] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[21] = current_crc[29] ^ current_crc[1] ^ crc_in[1] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[4] ^
+ crc_in[4] ^ current_crc[5] ^ crc_in[5] ^
+ current_crc[7] ^ current_crc[1] ^ crc_in[1] ^
+ crc_in[7];
+ next_crc[22] = current_crc[30] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[5] ^ crc_in[5] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6];
+ next_crc[23] = current_crc[31] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[1] ^ crc_in[1] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[4] ^ crc_in[4] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[24] = current_crc[0] ^ crc_in[0] ^ current_crc[1] ^
+ crc_in[1] ^ current_crc[2] ^ crc_in[2] ^
+ current_crc[4] ^ crc_in[4] ^ current_crc[5] ^
+ crc_in[5] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[25] = current_crc[1] ^ crc_in[1] ^ current_crc[2] ^
+ crc_in[2] ^ current_crc[3] ^ crc_in[3] ^
+ current_crc[5] ^ crc_in[5] ^ current_crc[6] ^
+ current_crc[0] ^ crc_in[0] ^ crc_in[6];
+ next_crc[26] = current_crc[2] ^ crc_in[2] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[4] ^ crc_in[4] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[27] = current_crc[3] ^ crc_in[3] ^ current_crc[4] ^
+ crc_in[4] ^ current_crc[5] ^ crc_in[5] ^
+ current_crc[7] ^ current_crc[1] ^ crc_in[1] ^
+ crc_in[7];
+ next_crc[28] = current_crc[4] ^crc_in[4] ^ current_crc[5] ^
+ crc_in[5] ^ current_crc[6] ^ current_crc[0] ^
+ crc_in[0] ^ crc_in[6];
+ next_crc[29] = current_crc[5] ^ crc_in[5] ^ current_crc[6] ^
+ current_crc[0] ^ crc_in[0] ^ crc_in[6] ^
+ current_crc[7] ^ current_crc[1] ^ crc_in[1] ^
+ crc_in[7];
+ next_crc[30] = current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[31] = current_crc[7] ^ current_crc[1] ^ crc_in[1] ^
+ crc_in[7];
+ end // always
+
+assign rx_fcs[0] = current_crc[31];
+assign rx_fcs[1] = current_crc[30];
+assign rx_fcs[2] = current_crc[29];
+assign rx_fcs[3] = current_crc[28];
+assign rx_fcs[4] = current_crc[27];
+assign rx_fcs[5] = current_crc[26];
+assign rx_fcs[6] = current_crc[25];
+assign rx_fcs[7] = current_crc[24];
+assign rx_fcs[8] = current_crc[23];
+assign rx_fcs[9] = current_crc[22];
+assign rx_fcs[10] = current_crc[21];
+assign rx_fcs[11] = current_crc[20];
+assign rx_fcs[12] = current_crc[19];
+assign rx_fcs[13] = current_crc[18];
+assign rx_fcs[14] = current_crc[17];
+assign rx_fcs[15] = current_crc[16];
+assign rx_fcs[16] = current_crc[15];
+assign rx_fcs[17] = current_crc[14];
+assign rx_fcs[18] = current_crc[13];
+assign rx_fcs[19] = current_crc[12];
+assign rx_fcs[20] = current_crc[11];
+assign rx_fcs[21] = current_crc[10];
+assign rx_fcs[22] = current_crc[9];
+assign rx_fcs[23] = current_crc[8];
+assign rx_fcs[24] = current_crc[7];
+assign rx_fcs[25] = current_crc[6];
+assign rx_fcs[26] = current_crc[5];
+assign rx_fcs[27] = current_crc[4];
+assign rx_fcs[28] = current_crc[3];
+assign rx_fcs[29] = current_crc[2];
+assign rx_fcs[30] = current_crc[1];
+assign rx_fcs[31] = current_crc[0];
+
+ always @(rx_fcs)
+ begin
+ if (rx_fcs == 32'hc704dd7b)
+ crc_ok_ul = 1;
+ else
+ crc_ok_ul = 0;
+ end // always
+
+
+ assign rc2rf_crc_ok = crc_ok_ul;
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/verilog/rtl/gmac/crc32/g_tx_crc32.v b/verilog/rtl/gmac/crc32/g_tx_crc32.v
new file mode 100755
index 0000000..c72d65a
--- /dev/null
+++ b/verilog/rtl/gmac/crc32/g_tx_crc32.v
@@ -0,0 +1,271 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+/***************************************************************
+ Description:
+ crc_32.v: This block contains the tx_crc32 generator.
+ CRC is generated on the tx data when gen_tx_crc asserted.
+ The 32-bit crc shift register is reset to all 1's when either
+ tx_reset_crc asserted
+
+ *********************************************************************/
+module g_tx_crc32 (
+ // List of outputs.
+ tx_fcs,
+
+ // List of inputs
+ gen_tx_crc,
+ tx_reset_crc,
+ tx_data,
+ sclk,
+ reset_n);
+
+ // defx[ine inputs and outputs.
+
+ input gen_tx_crc; // when asserted, crc is generated on the
+ // tx_data[3:0].
+ input tx_reset_crc; // when asserted, crc shift register is
+ // reset to all 1's. from link_phy_intfc.
+ input [7:0] tx_data; // trasnmit data.
+ input sclk; // serial clock from phy.
+ input reset_n; // global asynchronous reset.
+
+
+ output [31:0] tx_fcs; // 32-bit crc for tx_data. to link_phy_intfc.
+
+
+ // reg/wire declarations for primary outputs.
+ wire [31:0] tx_fcs;
+
+ // define constants and parameters here.
+
+ // define local signals here.
+
+ wire [7:0] crc_in;
+ wire gen_crc;
+ wire[7:0] tx_data_in;
+ wire carry0,carry1,carry2,carry3;
+ wire carry4,carry5,carry6,carry7;
+ reg [31:0] current_crc, next_crc;
+
+ // code starts here.
+ assign tx_data_in = tx_data;
+ assign crc_in = tx_data_in;
+
+ assign gen_crc = gen_tx_crc;
+
+ // 32-bit crc shift register for crc calculation.
+
+ always @(posedge sclk or negedge reset_n)
+ begin
+ if (!reset_n)
+ begin
+ current_crc <= 32'hffffffff;
+ end
+ else
+ begin
+ if (tx_reset_crc )
+ begin
+ current_crc <= 32'hffffffff;
+ end
+ else if (gen_crc) // generate crc
+ begin
+ current_crc <= next_crc;
+ end // else: !if(tx_reset_crc )
+ end // else: !if(reset_n)
+ end // always @ (posedge sclk or negedge reset_n)
+
+ // combinational logic to generate next_crc
+
+ always @(current_crc or crc_in)
+ begin
+
+ next_crc[0] = current_crc[8] ^ current_crc[2] ^ crc_in[2];
+ next_crc[1] = current_crc[9] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[3] ^ crc_in[3];
+ next_crc[2] = current_crc[10] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[1] ^ crc_in[1] ^ current_crc[4] ^
+ crc_in[4];
+ next_crc[3] = current_crc[11] ^ current_crc[1] ^ crc_in[1] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[5] ^
+ crc_in[5];
+ next_crc[4] = current_crc[12] ^ current_crc[2] ^ crc_in[2] ^
+ current_crc[3] ^ crc_in[3] ^ current_crc[6] ^
+ current_crc[0] ^ crc_in[0] ^ crc_in[6];
+ next_crc[5] = current_crc[13] ^ current_crc[3] ^ crc_in[3] ^
+ current_crc[4] ^ crc_in[4] ^ current_crc[7] ^
+ current_crc[1] ^ crc_in[1] ^ crc_in[7];
+ next_crc[6] = current_crc[14] ^ current_crc[4] ^ crc_in[4] ^
+ current_crc[5] ^ crc_in[5];
+ next_crc[7] = current_crc[15] ^ current_crc[5] ^ crc_in[5] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6];
+ next_crc[8] = current_crc[16] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[9] = current_crc[17] ^ current_crc[1] ^ crc_in[1] ^
+ current_crc[7] ^ current_crc[1] ^ crc_in[1] ^
+ crc_in[7];
+ next_crc[10] = current_crc[18] ^ current_crc[2] ^ crc_in[2];
+ next_crc[11] = current_crc[19] ^ current_crc[3] ^ crc_in[3];
+ next_crc[12] = current_crc[20] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[4] ^ crc_in[4];
+ next_crc[13] = current_crc[21] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[1] ^ crc_in[1] ^ current_crc[5] ^
+ crc_in[5];
+ next_crc[14] = current_crc[22] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[1] ^ crc_in[1] ^ current_crc[2] ^
+ crc_in[2] ^ current_crc[6] ^ current_crc[0] ^
+ crc_in[0] ^ crc_in[6];
+ next_crc[15] = current_crc[23] ^ current_crc[1] ^ crc_in[1] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[16] = current_crc[24] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[4] ^ crc_in[4];
+ next_crc[17] = current_crc[25] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[1] ^ crc_in[1] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[4] ^ crc_in[4] ^
+ current_crc[5] ^ crc_in[5];
+ next_crc[18] = current_crc[26] ^ current_crc[1] ^ crc_in[1] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[4] ^
+ crc_in[4] ^ current_crc[5] ^ crc_in[5] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6];
+ next_crc[19] = current_crc[27] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[5] ^ crc_in[5] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[20] = current_crc[28] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[1] ^ crc_in[1] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[4] ^ crc_in[4] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[21] = current_crc[29] ^ current_crc[1] ^ crc_in[1] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[4] ^
+ crc_in[4] ^ current_crc[5] ^ crc_in[5] ^
+ current_crc[7] ^ current_crc[1] ^ crc_in[1] ^
+ crc_in[7];
+ next_crc[22] = current_crc[30] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[5] ^ crc_in[5] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6];
+ next_crc[23] = current_crc[31] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[1] ^ crc_in[1] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[4] ^ crc_in[4] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[24] = current_crc[0] ^ crc_in[0] ^ current_crc[1] ^
+ crc_in[1] ^ current_crc[2] ^ crc_in[2] ^
+ current_crc[4] ^ crc_in[4] ^ current_crc[5] ^
+ crc_in[5] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[25] = current_crc[1] ^ crc_in[1] ^ current_crc[2] ^
+ crc_in[2] ^ current_crc[3] ^ crc_in[3] ^
+ current_crc[5] ^ crc_in[5] ^ current_crc[6] ^
+ current_crc[0] ^ crc_in[0] ^ crc_in[6];
+ next_crc[26] = current_crc[2] ^ crc_in[2] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[4] ^ crc_in[4] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[27] = current_crc[3] ^ crc_in[3] ^ current_crc[4] ^
+ crc_in[4] ^ current_crc[5] ^ crc_in[5] ^
+ current_crc[7] ^ current_crc[1] ^ crc_in[1] ^
+ crc_in[7];
+ next_crc[28] = current_crc[4] ^crc_in[4] ^ current_crc[5] ^
+ crc_in[5] ^ current_crc[6] ^ current_crc[0] ^
+ crc_in[0] ^ crc_in[6];
+ next_crc[29] = current_crc[5] ^ crc_in[5] ^ current_crc[6] ^
+ current_crc[0] ^ crc_in[0] ^ crc_in[6] ^
+ current_crc[7] ^ current_crc[1] ^ crc_in[1] ^
+ crc_in[7];
+ next_crc[30] = current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[31] = current_crc[7] ^ current_crc[1] ^ crc_in[1] ^
+ crc_in[7];
+ end // always
+
+// assign tx_fcs = ~current_crc;
+ assign tx_fcs[0] = !current_crc[0];
+ assign tx_fcs[1] = !current_crc[1];
+ assign tx_fcs[2] = !current_crc[2];
+ assign tx_fcs[3] = !current_crc[3];
+ assign tx_fcs[4] = !current_crc[4];
+ assign tx_fcs[5] = !current_crc[5];
+ assign tx_fcs[6] = !current_crc[6];
+ assign tx_fcs[7] = !current_crc[7];
+ assign tx_fcs[8] = !current_crc[8];
+ assign tx_fcs[9] = !current_crc[9];
+ assign tx_fcs[10] = !current_crc[10];
+ assign tx_fcs[11] = !current_crc[11];
+ assign tx_fcs[12] = !current_crc[12];
+ assign tx_fcs[13] = !current_crc[13];
+ assign tx_fcs[14] = !current_crc[14];
+ assign tx_fcs[15] = !current_crc[15];
+ assign tx_fcs[16] = !current_crc[16];
+ assign tx_fcs[17] = !current_crc[17];
+ assign tx_fcs[18] = !current_crc[18];
+ assign tx_fcs[19] = !current_crc[19];
+ assign tx_fcs[20] = !current_crc[20];
+ assign tx_fcs[21] = !current_crc[21];
+ assign tx_fcs[22] = !current_crc[22];
+ assign tx_fcs[23] = !current_crc[23];
+ assign tx_fcs[24] = !current_crc[24];
+ assign tx_fcs[25] = !current_crc[25];
+ assign tx_fcs[26] = !current_crc[26];
+ assign tx_fcs[27] = !current_crc[27];
+ assign tx_fcs[28] = !current_crc[28];
+ assign tx_fcs[29] = !current_crc[29];
+ assign tx_fcs[30] = !current_crc[30];
+ assign tx_fcs[31] = !current_crc[31];
+
+endmodule
diff --git a/verilog/rtl/gmac/ctrl/eth_parser.v b/verilog/rtl/gmac/ctrl/eth_parser.v
new file mode 100644
index 0000000..0361a61
--- /dev/null
+++ b/verilog/rtl/gmac/ctrl/eth_parser.v
@@ -0,0 +1,302 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Mar 2, 2011 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+// ------------------------------------------------------------------------
+// Description :
+// This module instantiates the Eth/Arp/IP/TCP/UDP Packet Parser
+//
+// ------------------------------------------------------------------------
+module g_eth_parser (
+ s_reset_n,
+ app_clk,
+
+ // Configuration
+ cfg_filters,
+ cfg_mac_sa,
+ cfg_ip_sa,
+
+ // Input Control Information
+ eop,
+ dval,
+ data,
+
+ // output status
+ pkt_done,
+ pkt_len,
+ pkt_status,
+ pkt_drop_ind,
+ pkt_drop_reason
+ );
+
+//------------------------------
+// Global Input signal
+//------------------------------
+input s_reset_n; // Active low reset signal
+input app_clk ; // Application clock
+
+//------------------------------
+// Configuration
+//------------------------------
+input [31:0] cfg_filters; // Filter rules
+ // [0] - filtering enabled
+ // [1] - allow local mac-da only
+ // [2] - allow local mac-da only + IP4 local ip-da
+ // [3] - allow local mac-da only + IP4 local ip-da + TCP
+ // [4] - allow local mac-da only + IP4 local ip-da + UDP
+ // [5] - allow local mac-da only + IP4 local ip-da + ICMP
+ // [6] - allow local mac-da only + ARP
+
+input [47:0] cfg_mac_sa; // 48 bit mac DA
+input [31:0] cfg_ip_sa; // 32 bit IP DA
+
+//---------------------------
+// Input Control Information
+//---------------------------
+input eop;
+input dval;
+input [7:0] data;
+
+//-----------------------------
+// output status
+//-----------------------------
+output [11:0] pkt_len; // Packet Length
+output pkt_done; // Packet Processing done indication
+output [15:0] pkt_status; // packet processing status
+ // [1:0] - MAC-DA
+ // 2'b00 - Broadcast frame
+ // 2'b01 - Multicast frame
+ // 2'b10 - unicast frame, other than local DA
+ // 2'b11 - unicast local DA frame
+ // [3:2] - MAC-SA
+ // 2'b00 - Broadcast frame
+ // 2'b01 - Multicast frame
+ // 2'b10 - unicast frame, other than local DA
+ // 2'b11 - unicast local DA frame
+ // [6:4] - 3'b000 - Unknown Ethernet frame
+ // 3'b001 - IP4 Frame
+ // 3'b010 - IP4 Frame + TCP
+ // 3'b011 - IP4 Frame + UDP
+ // 3'b100 - IP4 Frame + ICMP
+ // 3'b101 - ARP frame
+output pkt_drop_ind; // Packet Drop Inidcation
+
+output [7:0] pkt_drop_reason; // Reason for Frame Drop
+ // [0] - Non Local DA
+ // [1] - Local DA == Remote SA
+ // [2] - Non Local IP-DA
+ // [3] - Local IP-DA == Remote IP-SA
+ // [4] - Not Valid IP4/TCP/UDP/ARP/ICMP Frame
+ // [5] - L2 Check sum error
+ // [6] - L3 Check Sum Error
+ // [7] - L4 Check Sum Error
+
+reg [11:0] bcnt ; // Byte counter
+reg [11:0] pkt_len ; // packet length
+reg pkt_done ; // packet complete indication + Packet Status Valid
+reg pkt_drop_ind ;
+
+
+always @(negedge s_reset_n or posedge app_clk) begin
+ if(s_reset_n == 1'b0) begin
+ bcnt <= 0;
+ pkt_len <= 0;
+ pkt_done <= 0;
+ pkt_drop_ind <= 0;
+ end
+ else begin
+ if(dval) begin
+ if(eop) begin
+ bcnt <= 0;
+ pkt_len <= bcnt +1;
+ pkt_done <= 1;
+ end else begin
+ bcnt <= bcnt +1;
+ pkt_done <= 0;
+ end
+ end else begin
+ pkt_done <= 0;
+ end
+ end
+end
+
+reg mac_da_bc ; // frame da is broad cast
+reg mac_da_mc ; // frame da is multicast
+reg mac_da_match ; // frame da match to local address
+reg mac_sa_bc ; // frame sa is broadcast
+reg mac_sa_mc ; // frame sa is multicast
+reg mac_sa_match ; // frame sa match to local address
+reg ipv4f ; // frame is ipv4
+reg arpf ; // frame is arp
+reg tcpf ; // frame is tcp
+reg udpf ; // frame is udp
+reg ip_sa_match ; // ip4 sa matches to local IP Address
+reg ip_da_match ; // ip4 da matches to local IP Address
+reg[15:0] pkt_status ; // Packet Status
+
+always @(negedge s_reset_n or posedge app_clk) begin
+ if(s_reset_n == 1'b0) begin
+ mac_da_bc <= 0;
+ mac_da_mc <= 0;
+ mac_da_match <= 0;
+ mac_sa_bc <= 0;
+ mac_sa_mc <= 0;
+ mac_sa_match <= 0;
+ ipv4f <= 0;
+ arpf <= 0;
+ tcpf <= 0;
+ udpf <= 0;
+ ip_sa_match <= 0;
+ ip_da_match <= 0;
+ pkt_status <= 0;
+ end
+ else begin
+ if(dval) begin
+ if(!eop) begin
+ // DA Analysis
+ // Broadcast Frame
+ mac_da_bc <= (bcnt == 0) ? (data == 8'hff) :
+ (bcnt == 1) ? (data == 8'hff) & mac_da_bc :
+ (bcnt == 2) ? (data == 8'hff) & mac_da_bc :
+ (bcnt == 3) ? (data == 8'hff) & mac_da_bc :
+ (bcnt == 4) ? (data == 8'hff) & mac_da_bc :
+ (bcnt == 5) ? (data == 8'hff) & mac_da_bc : mac_da_bc;
+ // multicast frame
+ mac_da_mc <= (bcnt == 0) ? (data[7] == 1'b1) : mac_da_mc & !mac_da_bc;
+
+ // local unicast frame
+ mac_da_match <= (bcnt == 0) ? (cfg_mac_sa[7:0] == data) :
+ (bcnt == 1) ? (cfg_mac_sa[15:8] == data) & mac_da_match :
+ (bcnt == 2) ? (cfg_mac_sa[23:16] == data) & mac_da_match :
+ (bcnt == 3) ? (cfg_mac_sa[31:24] == data) & mac_da_match :
+ (bcnt == 4) ? (cfg_mac_sa[39:32] == data) & mac_da_match :
+ (bcnt == 5) ? (cfg_mac_sa[47:40] == data) & mac_da_match :
+ mac_da_match;
+
+
+ // SA Analysis
+ mac_sa_bc <= (bcnt == 6) ? (data == 8'hff) :
+ (bcnt == 7) ? (data == 8'hff) & mac_sa_bc :
+ (bcnt == 8) ? (data == 8'hff) & mac_sa_bc :
+ (bcnt == 9) ? (data == 8'hff) & mac_sa_bc :
+ (bcnt == 10) ? (data == 8'hff) & mac_sa_bc :
+ (bcnt == 11) ? (data == 8'hff) & mac_sa_bc : mac_sa_bc;
+
+ mac_sa_mc <= (bcnt == 6) ? (data[7] == 1'b1) : mac_sa_mc & !mac_sa_bc;
+
+ mac_sa_match <= (bcnt == 6) ? (cfg_mac_sa[7:0] == data) :
+ (bcnt == 7) ? (cfg_mac_sa[15:8] == data) & mac_sa_match :
+ (bcnt == 8) ? (cfg_mac_sa[23:16] == data) & mac_sa_match :
+ (bcnt == 9) ? (cfg_mac_sa[31:24] == data) & mac_sa_match :
+ (bcnt == 10) ? (cfg_mac_sa[39:32] == data) & mac_sa_match :
+ (bcnt == 11) ? (cfg_mac_sa[47:40] == data) & mac_sa_match :
+ mac_sa_match;
+
+ // L3 Protocol Analysis
+ ipv4f <= (bcnt == 12) ? (data == 8'h08) :
+ (bcnt == 13) ? (data == 8'h00) & ipv4f : ipv4f;
+
+ arpf <= (bcnt == 12) ? (data == 8'h08) :
+ (bcnt == 13) ? (data == 8'h06) & arpf : arpf;
+ // L4 Protocol Analysis
+ tcpf <= (bcnt == 23) ? (data == 8'h06) & ipv4f: tcpf;
+ udpf <= (bcnt == 23) ? (data == 8'h11) & ipv4f: udpf;
+ // IP DA and SA Match
+ ip_sa_match <= (bcnt == 26) ? (data == cfg_ip_sa[7:0]) & ipv4f:
+ (bcnt == 27) ? (data == cfg_ip_sa[15:8]) & ipv4f & ip_sa_match:
+ (bcnt == 28) ? (data == cfg_ip_sa[23:16]) & ipv4f & ip_sa_match:
+ (bcnt == 29) ? (data == cfg_ip_sa[31:24]) & ipv4f & ip_sa_match:
+ ip_sa_match;
+ ip_da_match <= (bcnt == 26) ? (data == cfg_ip_sa[7:0]) & ipv4f:
+ (bcnt == 27) ? (data == cfg_ip_sa[15:8]) & ipv4f & ip_da_match:
+ (bcnt == 28) ? (data == cfg_ip_sa[23:16]) & ipv4f & ip_da_match:
+ (bcnt == 29) ? (data == cfg_ip_sa[31:24]) & ipv4f & ip_da_match:
+ ip_da_match;
+
+ end else begin // on EOP
+
+ if(&mac_da_match) begin
+ pkt_status[1:0] <= 2'b11; // Local DA
+ end else if(mac_da_bc) begin
+ pkt_status[1:0] <= 2'b00; // Broadcast frame
+ end else if(mac_da_mc) begin
+ pkt_status[1:0] <= 2'b01; // Multicase frame
+ end else
+ pkt_status[1:0] <= 2'b10; // Unknown Unicast frame
+
+ if(&mac_sa_match) begin
+ pkt_status[3:2] <= 2'b11; // Local DA
+ end else if(mac_sa_bc) begin
+ pkt_status[3:2] <= 2'b00; // Broadcast frame
+ end else if(mac_sa_mc) begin
+ pkt_status[3:2] <= 2'b01; // Multicast frame
+ end else
+ pkt_status[3:2] <= 2'b10; // Unknown Unicast frame
+
+ if(tcpf) begin
+ pkt_status[6:4] <= 3'b010; // IP4 Frame + TCP
+ end else if(udpf) begin
+ pkt_status[6:4] <= 3'b011; // IP4 Frame + UDP
+ end else if(arpf) begin
+ pkt_status[6:4] <= 3'b101; // ARP frame
+ end else
+ pkt_status[6:4] <= 2'b00; // UnKnown Ethernet frame
+
+ mac_da_match <= 0;
+ mac_sa_match <= 0;
+ mac_sa_bc <= 0;
+ mac_sa_mc <= 0;
+ mac_da_bc <= 0;
+ mac_da_mc <= 0;
+ tcpf <= 0;
+ udpf <= 0;
+ arpf <= 0;
+ ipv4f <= 0;
+ end
+ end
+ end
+end
+
+
+endmodule
diff --git a/verilog/rtl/gmac/mac/byte_reg.v b/verilog/rtl/gmac/mac/byte_reg.v
new file mode 100755
index 0000000..693fe0e
--- /dev/null
+++ b/verilog/rtl/gmac/mac/byte_reg.v
@@ -0,0 +1,81 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Mar 2, 2011 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+/***************************************************************
+ Description:
+ byte_reg.v: instantiates 32 registers to make a quad
+ This enables maintaining timing on blocks
+ in check
+***********************************************************************/
+module half_dup_byte_reg(
+ //List of Inputs
+ we,
+ data_in,
+ reset_n,
+ clk,
+
+ //List of Outputs
+ data_out
+);
+
+ input [7:0] we;
+ input [7:0] data_in;
+ input reset_n;
+ input clk;
+ output [7:0] data_out;
+
+
+ generic_register #(8,0) u_reg (
+
+ .we (we),
+ .clk (clk),
+ .reset_n (reset_n),
+ .data_in (data_in),
+ .data_out (data_out)
+ );
+
+
+endmodule
+
diff --git a/verilog/rtl/gmac/mac/dble_reg.v b/verilog/rtl/gmac/mac/dble_reg.v
new file mode 100755
index 0000000..dcc6e36
--- /dev/null
+++ b/verilog/rtl/gmac/mac/dble_reg.v
@@ -0,0 +1,91 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Mar 2, 2011 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+/***************************************************************
+ Description:
+ Synchronizes the pulse from one clock to another
+ * clock domain
+***********************************************************************/
+module half_dup_dble_reg (
+ //outputs
+ sync_out_pulse,
+ //inputs
+ in_pulse,
+ dest_clk,
+ reset_n);
+
+ output sync_out_pulse; //output synchronised to slow clock
+ input in_pulse; //input based on fast clock, pulse
+ input dest_clk; //slow clock
+ input reset_n;
+
+ reg s1_sync_out,d_sync_out,s2_sync_out;
+
+ //double register the data in the slow clock domain
+ always @(posedge dest_clk or negedge reset_n)
+ begin
+ if (!reset_n)
+ begin
+ s1_sync_out <= 0;
+ s2_sync_out <= 0;
+ d_sync_out <= 0;
+ end // if (reset_n)
+ else
+ begin
+ s1_sync_out <= in_pulse;
+ s2_sync_out <= s1_sync_out;
+ d_sync_out <= s2_sync_out;
+ end // else: !if(reset_n)
+ end // always @ (posedge dest_clk or negedge reset_n)
+
+ assign sync_out_pulse = d_sync_out;
+
+endmodule // dble_reg
+
+
+
+
+
+
diff --git a/verilog/rtl/gmac/mac/filelist_mac.f b/verilog/rtl/gmac/mac/filelist_mac.f
new file mode 100644
index 0000000..a7362ea
--- /dev/null
+++ b/verilog/rtl/gmac/mac/filelist_mac.f
@@ -0,0 +1,19 @@
+dble_reg.v
+g_tx_fsm.v
+g_deferral.v
+g_tx_top.v
+g_rx_fsm.v
+g_cfg_mgmt.v
+s2f_sync.v
+g_md_intf.v
+g_deferral_rx.v
+g_rx_top.v
+g_mii_intf.v
+g_mac_core.v
+../crc32/g_rx_crc32.v
+../crc32/g_tx_crc32.v
+-v ../../lib/registers.v
+-v ../../lib/toggle_sync.v
+-v ../../lib/stat_counter.v
++lint=all
++v2k
diff --git a/verilog/rtl/gmac/mac/g_cfg_mgmt.v b/verilog/rtl/gmac/mac/g_cfg_mgmt.v
new file mode 100755
index 0000000..3943cfc
--- /dev/null
+++ b/verilog/rtl/gmac/mac/g_cfg_mgmt.v
@@ -0,0 +1,981 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Mar 2, 2011 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+/***************************************************************
+ Description:
+ cfg_mgmt.v: contains the configuration, register information, Application
+ read from any location. But can write to a limited set of locations,
+ Please refer to the design data sheets for register locations
+***********************************************************************/
+module g_cfg_mgmt (
+ //List of Inputs
+
+ // Reg Bus Interface Signal
+ reg_cs,
+ reg_wr,
+ reg_addr,
+ reg_wdata,
+ reg_be,
+
+ // Outputs
+ reg_rdata,
+ reg_ack,
+
+ // Rx Status
+ rx_sts_vld,
+ rx_sts,
+
+ // Rx Status
+ tx_sts_vld,
+ tx_sts,
+
+ // MDIO READ DATA FROM PHY
+ md2cf_cmd_done,
+ md2cf_status,
+ md2cf_data,
+
+ app_clk,
+ app_reset_n,
+
+ //List of Outputs
+ // MII Control
+ cf2mi_loopback_en,
+ cf_mac_mode,
+ cf_chk_rx_dfl,
+ cf2mi_rmii_en,
+
+ cfg_uni_mac_mode_change_i,
+
+ //CHANNEL enable
+ cf2tx_ch_en,
+ //CHANNEL CONTROL TX
+ cf_silent_mode,
+ cf2df_dfl_single,
+ cf2df_dfl_single_rx,
+ cf2tx_pad_enable,
+ cf2tx_append_fcs,
+ //CHANNEL CONTROL RX
+ cf2rx_ch_en,
+ cf2rx_strp_pad_en,
+ cf2rx_snd_crc,
+ cf2rx_runt_pkt_en,
+ cf_mac_sa,
+ cfg_ip_sa,
+ cfg_mac_filter,
+
+ cf2rx_max_pkt_sz,
+ cf2tx_force_bad_fcs,
+ //MDIO CONTROL & DATA
+ cf2md_datain,
+ cf2md_regad,
+ cf2md_phyad,
+ cf2md_op,
+ cf2md_go,
+
+ rx_buf_base_addr,
+ tx_buf_base_addr,
+ rx_buf_qbase_addr,
+ tx_buf_qbase_addr,
+
+ tx_qcnt_inc,
+ tx_qcnt_dec,
+ tx_qcnt,
+
+ rx_qcnt_inc,
+ rx_qcnt_dec,
+ rx_qcnt
+
+ );
+
+ parameter mac_mdio_en = 1'b1;
+
+
+ //pin out definations
+ //---------------------------------
+ // Reg Bus Interface Signal
+ //---------------------------------
+ input reg_cs ;
+ input reg_wr ;
+ input [3:0] reg_addr ;
+ input [31:0] reg_wdata ;
+ input [3:0] reg_be ;
+
+ // Outputs
+ output [31:0] reg_rdata ;
+ output reg_ack ;
+
+ input rx_sts_vld ; // rx status valid indication, sync w.r.t app clk
+ input [7:0] rx_sts ; // rx status bits
+
+ input tx_sts_vld ; // tx status valid indication, sync w.r.t app clk
+ input tx_sts ; // tx status bits
+
+ //List of Inputs
+
+ input app_clk ;
+ input app_reset_n ;
+ input md2cf_cmd_done ; // Read/Write MDIO completed
+ input md2cf_status ; // MDIO transfer error
+ input [15:0] md2cf_data ; // Data from PHY for a
+ // mdio read access
+
+
+ //List of Outputs
+ output cf2mi_rmii_en ; // Working in RMII when set to 1
+ output cf_mac_mode ; // mac mode set this to 1 for 100Mbs/10Mbs
+ output cf_chk_rx_dfl ; // Check for RX Deferal
+ output [47:0] cf_mac_sa ;
+ output [31:0] cfg_ip_sa ;
+ output [31:0] cfg_mac_filter ;
+ output cf2tx_ch_en ; //enable the TX channel
+ output cf_silent_mode ; //PHY Inactive
+ output [7:0] cf2df_dfl_single ; //number of clk ticks for dfl
+ output [7:0] cf2df_dfl_single_rx ; //number of clk ticks for dfl
+
+ output cf2tx_pad_enable ; //enable padding, < 64 bytes
+ output cf2tx_append_fcs ; //append CRC for TX frames
+ output cf2rx_ch_en ; //Enable RX channel
+ output cf2rx_strp_pad_en ; //strip the padded bytes on RX frame
+ output cf2rx_snd_crc ; //send FCS to application, else strip
+ //the FCS before sending to application
+ output cf2mi_loopback_en ; // TX to RX loop back enable
+ output cf2rx_runt_pkt_en ; //don't throw packets less than 64 bytes
+ output [15:0] cf2md_datain ;
+ output [4:0] cf2md_regad ;
+ output [4:0] cf2md_phyad ;
+ output cf2md_op ;
+ output cf2md_go ;
+
+ output [15:0] cf2rx_max_pkt_sz ; //max rx packet size
+ output cf2tx_force_bad_fcs ; //force bad fcs on tx
+
+ output cfg_uni_mac_mode_change_i;
+
+ output [3:0] rx_buf_base_addr; // Rx Data Buffer Base Address
+ output [3:0] tx_buf_base_addr; // Tx Data Buffer Base Address
+ output [9:0] rx_buf_qbase_addr; // Rx Q Base Address
+ output [9:0] tx_buf_qbase_addr; // Tx Q Base Address
+
+ input tx_qcnt_inc;
+ input tx_qcnt_dec;
+ output [3:0] tx_qcnt;
+
+ input rx_qcnt_inc;
+ input rx_qcnt_dec;
+ output [3:0] rx_qcnt;
+
+
+// Wire assignments for output signals
+ wire [15:0] cf2md_datain;
+ wire [4:0] cf2md_regad;
+ wire [4:0] cf2md_phyad;
+ wire cf2md_op;
+ wire cf2md_go;
+ wire mdio_cmd_done_sync;
+
+ wire int_mdio_cmd_done_sync;
+ assign mdio_cmd_done_sync = (mac_mdio_en) ? int_mdio_cmd_done_sync : 1'b0;
+
+ s2f_sync U1_s2f_sync ( .sync_out_pulse(int_mdio_cmd_done_sync),
+ .in_pulse(md2cf_cmd_done),
+ .dest_clk(app_clk),
+ .reset_n(app_reset_n));
+
+
+
+// Wire and Reg assignments for local signals
+ reg int_md2cf_status;
+ wire [7:0] mac_mode_out;
+ wire [7:0] mac_cntrl_out_1, mac_cntrl_out_2;
+ wire [7:0] dfl_params_rx_out;
+ wire [7:0] dfl_params1_out;
+ wire [7:0] slottime_out_1;
+ wire [7:0] slottime_out_2;
+ wire [31:0] mdio_cmd_out;
+ wire [7:0] mdio_stat_out_1;
+ wire [7:0] mdio_stat_out_2;
+ wire [7:0] mdio_stat_out_3;
+ wire [7:0] mdio_stat_out_4;
+ wire [7:0] mdio_cmd_out_1;
+ wire [7:0] mdio_cmd_out_2;
+ wire [7:0] mdio_cmd_out_3;
+ wire [7:0] mdio_cmd_out_4;
+ wire [7:0] mac_sa_out_1;
+ wire [7:0] mac_sa_out_2;
+ wire [7:0] mac_sa_out_3;
+ wire [7:0] mac_sa_out_4;
+ wire [7:0] mac_sa_out_5;
+ wire [7:0] mac_sa_out_6;
+ wire [47:0] cf_mac_sa;
+ wire [15:0] cf2rx_max_pkt_sz;
+ wire cf2tx_force_bad_fcs;
+ reg force_bad_fcs;
+ reg cont_force_bad_fcs;
+ wire [31:0] mdio_stat_out;
+ reg cf2tx_force_bad_fcs_en;
+ reg cf2tx_cont_force_bad_fcs_en;
+ reg [15:0] int_mdio_stat_out;
+
+//-----------------------------------------------------------------------
+// Internal Wire Declarations
+//-----------------------------------------------------------------------
+
+wire sw_rd_en;
+wire sw_wr_en;
+wire [3:0] sw_addr ; // addressing 16 registers
+wire [3:0] wr_be ;
+
+reg [31:0] reg_rdata ;
+reg reg_ack ;
+
+wire [31:0] reg_0; // Software_Reg_0
+wire [31:0] reg_1; // Software-Reg_1
+wire [31:0] reg_2; // Software-Reg_2
+wire [31:0] reg_3; // Software-Reg_3
+wire [31:0] reg_4; // Software-Reg_4
+wire [31:0] reg_5; // Software-Reg_5
+wire [31:0] reg_6; // Software-Reg_6
+wire [31:0] reg_7; // Software-Reg_7
+wire [31:0] reg_8; // Software-Reg_8
+wire [31:0] reg_9; // Software-Reg_9
+wire [31:0] reg_10; // Software-Reg_10
+wire [31:0] reg_11; // Software-Reg_11
+wire [31:0] reg_12; // Software-Reg_12
+wire [31:0] reg_13; // Software-Reg_13
+wire [31:0] reg_14; // Software-Reg_14
+wire [31:0] reg_15; // Software-Reg_15
+reg [31:0] reg_out;
+
+//-----------------------------------------------------------------------
+// Internal Logic Starts here
+//-----------------------------------------------------------------------
+ assign sw_addr = reg_addr [3:0];
+ assign sw_rd_en = reg_cs & !reg_wr;
+ assign sw_wr_en = reg_cs & reg_wr;
+ assign wr_be = reg_be;
+
+
+//-----------------------------------------------------------------------
+// Read path mux
+//-----------------------------------------------------------------------
+
+always @ (posedge app_clk or negedge app_reset_n)
+begin : preg_out_Seq
+ if (app_reset_n == 1'b0)
+ begin
+ reg_rdata [31:0] <= 32'h0000_0000;
+ reg_ack <= 1'b0;
+ end
+ else if (sw_rd_en && !reg_ack)
+ begin
+ reg_rdata [31:0] <= reg_out [31:0];
+ reg_ack <= 1'b1;
+ end
+ else if (sw_wr_en && !reg_ack)
+ reg_ack <= 1'b1;
+ else
+ begin
+ reg_ack <= 1'b0;
+ end
+end
+
+
+//-----------------------------------------------------------------------
+// register read enable and write enable decoding logic
+//-----------------------------------------------------------------------
+wire sw_wr_en_0 = sw_wr_en & (sw_addr == 4'h0);
+wire sw_rd_en_0 = sw_rd_en & (sw_addr == 4'h0);
+wire sw_wr_en_1 = sw_wr_en & (sw_addr == 4'h1);
+wire sw_rd_en_1 = sw_rd_en & (sw_addr == 4'h1);
+wire sw_wr_en_2 = sw_wr_en & (sw_addr == 4'h2);
+wire sw_rd_en_2 = sw_rd_en & (sw_addr == 4'h2);
+wire sw_wr_en_3 = sw_wr_en & (sw_addr == 4'h3);
+wire sw_rd_en_3 = sw_rd_en & (sw_addr == 4'h3);
+wire sw_wr_en_4 = sw_wr_en & (sw_addr == 4'h4);
+wire sw_rd_en_4 = sw_rd_en & (sw_addr == 4'h4);
+wire sw_wr_en_5 = sw_wr_en & (sw_addr == 4'h5);
+wire sw_rd_en_5 = sw_rd_en & (sw_addr == 4'h5);
+wire sw_wr_en_6 = sw_wr_en & (sw_addr == 4'h6);
+wire sw_rd_en_6 = sw_rd_en & (sw_addr == 4'h6);
+wire sw_wr_en_7 = sw_wr_en & (sw_addr == 4'h7);
+wire sw_rd_en_7 = sw_rd_en & (sw_addr == 4'h7);
+wire sw_wr_en_8 = sw_wr_en & (sw_addr == 4'h8);
+wire sw_rd_en_8 = sw_rd_en & (sw_addr == 4'h8);
+wire sw_wr_en_9 = sw_wr_en & (sw_addr == 4'h9);
+wire sw_rd_en_9 = sw_rd_en & (sw_addr == 4'h9);
+wire sw_wr_en_10 = sw_wr_en & (sw_addr == 4'hA);
+wire sw_rd_en_10 = sw_rd_en & (sw_addr == 4'hA);
+wire sw_wr_en_11 = sw_wr_en & (sw_addr == 4'hB);
+wire sw_rd_en_11 = sw_rd_en & (sw_addr == 4'hB);
+wire sw_wr_en_12 = sw_wr_en & (sw_addr == 4'hC);
+wire sw_rd_en_12 = sw_rd_en & (sw_addr == 4'hC);
+wire sw_wr_en_13 = sw_wr_en & (sw_addr == 4'hD);
+wire sw_rd_en_13 = sw_rd_en & (sw_addr == 4'hD);
+wire sw_wr_en_14 = sw_wr_en & (sw_addr == 4'hE);
+wire sw_rd_en_14 = sw_rd_en & (sw_addr == 4'hE);
+wire sw_wr_en_15 = sw_wr_en & (sw_addr == 4'hF);
+wire sw_rd_en_15 = sw_rd_en & (sw_addr == 4'hF);
+
+
+always @( *)
+begin : preg_sel_Com
+
+ reg_out [31:0] = 32'd0;
+
+ case (sw_addr [3:0])
+ 4'b0000 : reg_out [31:0] = reg_0 [31:0];
+ 4'b0001 : reg_out [31:0] = reg_1 [31:0];
+ 4'b0010 : reg_out [31:0] = reg_2 [31:0];
+ 4'b0011 : reg_out [31:0] = reg_3 [31:0];
+ 4'b0100 : reg_out [31:0] = reg_4 [31:0];
+ 4'b0101 : reg_out [31:0] = reg_5 [31:0];
+ 4'b0110 : reg_out [31:0] = reg_6 [31:0];
+ 4'b0111 : reg_out [31:0] = reg_7 [31:0];
+ 4'b1000 : reg_out [31:0] = reg_8 [31:0];
+ 4'b1001 : reg_out [31:0] = reg_9 [31:0];
+ 4'b1010 : reg_out [31:0] = reg_10 [31:0];
+ 4'b1011 : reg_out [31:0] = reg_11 [31:0];
+ 4'b1100 : reg_out [31:0] = reg_12 [31:0];
+ 4'b1101 : reg_out [31:0] = reg_13 [31:0];
+ 4'b1110 : reg_out [31:0] = reg_14 [31:0];
+ 4'b1111 : reg_out [31:0] = reg_15 [31:0];
+ endcase
+end
+
+
+ //instantiate all the registers
+
+ //========================================================================//
+ // TX_CNTRL_REGISTER : Address value 00H
+ // BIT[0] = Transmit Channel Enable
+ // BIT[1] = DONT CARE
+ // BIT[2] = Retry Packet in case of Collisions
+ // BIT[3] = Enable padding
+ // BIT[4] = Append CRC
+ // BIT[5] = Perform a Two Part Deferral
+ // BIT[6] = RMII Enable bit
+ // BIT[7] = Force TX FCS Error
+
+
+generic_register #(8,0 ) u_mac_cntrl_reg_1 (
+ .we ({8{sw_wr_en_0 &
+ wr_be[0] }}),
+ .data_in (reg_wdata[7:0] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (mac_cntrl_out_1[7:0] )
+ );
+
+generic_register #(8,0 ) u_mac_cntrl_reg_2 (
+ .we ({8{sw_wr_en_0 &
+ wr_be[1]}} ),
+ .data_in (reg_wdata[15:8] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (mac_cntrl_out_2[7:0] )
+ );
+
+ generic_register #(8,0 ) u_mac_cntrl_reg_3 (
+ .we ({8{sw_wr_en_0 & wr_be[2] }}),
+ .data_in (reg_wdata[23:16] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out ({tx_buf_base_addr[3:0],
+ rx_buf_base_addr[3:0]} )
+ );
+
+
+ // TX Control Register
+ assign cf2tx_ch_en = mac_cntrl_out_1[0];
+ assign cf2tx_pad_enable = mac_cntrl_out_1[3];
+ assign cf2tx_append_fcs = mac_cntrl_out_1[4];
+ assign cf2tx_force_bad_fcs = mac_cntrl_out_1[7];
+
+ // RX_CNTRL_REGISTER
+ // BIT[0] = Receive Channel Enable
+ // BIT[1] = Strip Padding from the Receive data
+ // BIT[2] = Send CRC along with data to the host
+ // BIT[4] = Check RX Deferral
+ // BIT[6] = Receive Runt Packet
+ assign cf2rx_ch_en = mac_cntrl_out_2[0];
+ assign cf2rx_strp_pad_en = mac_cntrl_out_2[1];
+ assign cf2rx_snd_crc = mac_cntrl_out_2[2];
+ assign cf_chk_rx_dfl = mac_cntrl_out_2[4];
+ assign cf2rx_runt_pkt_en = mac_cntrl_out_2[6];
+
+assign reg_0[31:0] = {8'h0,tx_buf_base_addr[3:0],
+ rx_buf_base_addr[3:0],
+ mac_cntrl_out_2[7:0],
+ mac_cntrl_out_1[7:0]};
+
+
+// reg1 free
+assign reg_1[31:0] = 32'h0;
+
+//========================================================================//
+ //TRANSMIT DEFFERAL CONTROL REGISTER: Address value 08H
+ //BIT[7:0] = Defferal TX
+ //BIT[15:8] = Defferal RX
+
+ generic_register #(8,0 ) dfl_params1_en_reg (
+ .we ({8{sw_wr_en_2 &
+ wr_be[0] }} ),
+ .data_in (reg_wdata[7:0] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (dfl_params1_out[7:0] )
+ );
+
+ assign cf2df_dfl_single = dfl_params1_out[7:0];
+
+ generic_register #(8,0 ) dfl_params_rx_en_reg (
+ .we ({8{sw_wr_en_2 &
+ wr_be[1] }} ),
+ .data_in (reg_wdata[15:8] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (dfl_params_rx_out[7:0] )
+ );
+ assign cf2df_dfl_single_rx = dfl_params_rx_out[7:0];
+
+assign reg_2[15:0] = {16'h0,dfl_params_rx_out,dfl_params1_out};
+
+ //========================================================================//
+ // MAC_MODE REGISTER: Address value 0CH
+ // BIT[0] = 10/100 or 1000 1 1000, 0 is 10/100 Channel Enable
+ // BIT[1] = Mii/Rmii Default is Mii
+ // BIT[2] = MAC used in Loop back Mode
+ // BIT[3] = Burst Enable
+ // BIT[4] = Half Duplex
+ // BIT[5] = Silent Mode (During Loopback the Tx --> RX and NOT to PHY)
+ // BIT[6] = crs based flow control enable
+ // BIT[7] = Mac Mode Change
+
+ generic_register #(8,0 ) mac_mode_reg (
+ .we ({8{sw_wr_en_3 & wr_be[0]}}),
+ .data_in (reg_wdata[7:0] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (mac_mode_out[7:0] )
+ );
+
+ assign cf_mac_mode = mac_mode_out[0];
+ assign cf2mi_rmii_en = mac_mode_out[1];
+ assign cf2mi_loopback_en = mac_mode_out[2];
+ assign cf_silent_mode = mac_mode_out[5];
+ assign cfg_uni_mac_mode_change_i = mac_mode_out[7];
+
+
+assign reg_3[31:0] = {24'h0,mac_mode_out};
+ //========================================================================//
+ //MDIO COMMAND REGISTER: ADDRESS 10H
+ //BIT[15:0] = MDIO DATA TO PHY
+ //BIT[20:16] = MDIO REGISTER ADDR
+ //BIT[25:21] = MDIO PHY ADDR
+ //BIT[26] = MDIO COMMAND OPCODE READ/WRITE(0:read,1:write)
+ //BIT[31] = GO MDIO
+
+ generic_register #(8,0 ) mdio_cmd_reg_1 (
+ .we ({8{sw_wr_en_4 &
+ wr_be[0]}} ),
+ .data_in (reg_wdata[7:0] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (mdio_cmd_out_1[7:0] )
+ );
+
+ generic_register #(8,0 ) mdio_cmd_reg_2 (
+ .we ({8{sw_wr_en_4 &
+ wr_be[1]}} ),
+ .data_in (reg_wdata[15:8] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (mdio_cmd_out_2[7:0] )
+ );
+
+ generic_register #(8,0 ) mdio_cmd_reg_3 (
+ .we ({8{sw_wr_en_4 &
+ wr_be[2]}} ),
+ .data_in (reg_wdata[23:16] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (mdio_cmd_out_3[7:0] )
+ );
+
+
+
+ //byte_reg mdio_cmd_reg_4 (.we({8{mdio_cmd_en_4 && cfg_rw}}), .data_in(reg_wdata),
+ // .reset_n(app_reset_n), .clk(app_clk), .data_out(mdio_cmd_out_4));
+
+
+ generic_register #(7,0 ) mdio_cmd_reg_4 (
+ .we ({7{sw_wr_en_4 &
+ wr_be[3]}} ),
+ .data_in (reg_wdata[30:24] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (mdio_cmd_out_4[6:0] )
+ );
+
+req_register #(0 ) u_mdio_req (
+ .cpu_we ({sw_wr_en_4 &
+ wr_be[3] } ),
+ .cpu_req (reg_wdata[31] ),
+ .hware_ack (mdio_cmd_done_sync ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (mdio_cmd_out_4[7] )
+ );
+
+
+ assign mdio_cmd_out = {mdio_cmd_out_4, mdio_cmd_out_3,mdio_cmd_out_2,mdio_cmd_out_1};
+
+ assign reg_4 = {mdio_cmd_out};
+
+ assign cf2md_datain = mdio_cmd_out[15:0];
+ assign cf2md_regad = mdio_cmd_out[20:16];
+ assign cf2md_phyad = mdio_cmd_out[25:21];
+ assign cf2md_op = mdio_cmd_out[26];
+ assign cf2md_go = mdio_cmd_out[31];
+
+
+ //========================================================================//
+ //MDIO STATUS REGISTER: ADDRESS 14H
+ //BIT[15:0] = MDIO DATA FROM PHY
+ //BIT[31] = STATUS OF MDIO TRANSFER
+
+ always @(posedge app_clk
+ or negedge app_reset_n)
+ begin
+ if(!app_reset_n) begin
+ int_mdio_stat_out <= 16'b0;
+ int_md2cf_status <= 1'b0;
+ end
+ else
+ if(mdio_cmd_done_sync)
+ begin
+ int_mdio_stat_out[15:0] <= md2cf_data;
+ // int_mdio_stat_out[30:16] <= int_mdio_stat_out[30:16];
+ int_md2cf_status <= md2cf_status;
+ end // else: !if(reset)
+ end // always @ (posedge app_clk...
+
+ assign mdio_stat_out = (mac_mdio_en == 1'b1) ? {int_md2cf_status, 15'b0, int_mdio_stat_out} : 32'b0;
+
+
+ assign reg_5 = {mdio_stat_out};
+
+ //========================================================================//
+ //MAC Source Address Register 18-1C
+
+ generic_register #(8,0 ) mac_sa_reg_1 (
+ .we ({8{sw_wr_en_6 & wr_be[0] }}),
+ .data_in (reg_wdata[7:0] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (mac_sa_out_1[7:0] )
+ );
+ generic_register #(8,0 ) mac_sa_reg_2 (
+ .we ({8{sw_wr_en_6 & wr_be[1] }}),
+ .data_in (reg_wdata[15:8] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (mac_sa_out_2[7:0] )
+ );
+
+ generic_register #(8,0 ) mac_sa_reg_3 (
+ .we ({8{sw_wr_en_6 & wr_be[2] }}),
+ .data_in (reg_wdata[23:16] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (mac_sa_out_3[7:0] )
+ );
+
+ generic_register #(8,0 ) mac_sa_reg_4 (
+ .we ({8{sw_wr_en_6 & wr_be[3] }}),
+ .data_in (reg_wdata[31:24] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (mac_sa_out_4[7:0] )
+ );
+
+ generic_register #(8,0 ) mac_sa_reg_5 (
+ .we ({8{sw_wr_en_7 & wr_be[0] }}),
+ .data_in (reg_wdata[7:0] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (mac_sa_out_5[7:0] )
+ );
+
+ generic_register #(8,0 ) mac_sa_reg_6 (
+ .we ({8{sw_wr_en_7 & wr_be[1] }}),
+ .data_in (reg_wdata[15:8] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (mac_sa_out_6[7:0] )
+ );
+
+// assign cf_mac_sa = { mac_sa_out_1, mac_sa_out_2, mac_sa_out_3,
+// mac_sa_out_4, mac_sa_out_5, mac_sa_out_6};
+ assign cf_mac_sa = { mac_sa_out_6, mac_sa_out_5, mac_sa_out_4,
+ mac_sa_out_3, mac_sa_out_2, mac_sa_out_1};
+
+ assign reg_6[31:0] = cf_mac_sa[31:0];
+ assign reg_7[31:0] = {16'h0,cf_mac_sa[47:32]};
+//========================================================================//
+//MAC max packet size Register 20
+
+ generic_register #(8,0 ) max_pkt_sz_reg0 (
+ .we ({8{sw_wr_en_8 & wr_be[0] }}),
+ .data_in (reg_wdata[7:0] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (cf2rx_max_pkt_sz[7:0] )
+ );
+
+ generic_register #(8,0 ) max_pkt_sz_reg1 (
+ .we ({8{sw_wr_en_8 & wr_be[1] }}),
+ .data_in (reg_wdata[15:8] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (cf2rx_max_pkt_sz[15:8] )
+ );
+
+ assign reg_8[31:0] = {16'h0,cf2rx_max_pkt_sz[15:0]};
+
+
+//========================================================================//
+//MAC max packet size Register 20
+
+ generic_register #(2,0 ) m_rx_qbase_addr_1 (
+ .we ({2{sw_wr_en_9 & wr_be[0] }}),
+ .data_in (reg_wdata[7:6] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (rx_buf_qbase_addr[1:0] )
+ );
+
+ generic_register #(8,0 ) m_rx_qbase_addr_2 (
+ .we ({8{sw_wr_en_9 & wr_be[1] }}),
+ .data_in (reg_wdata[15:8] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (rx_buf_qbase_addr[9:2] )
+ );
+
+
+ generic_register #(2,0 ) m_tx_qbase_addr_1 (
+ .we ({2{sw_wr_en_9 & wr_be[2] }}),
+ .data_in (reg_wdata[23:22] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (tx_buf_qbase_addr[1:0] )
+ );
+
+ generic_register #(8,0 ) m_tx_qbase_addr_2 (
+ .we ({8{sw_wr_en_9 & wr_be[3] }}),
+ .data_in (reg_wdata[31:24] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (tx_buf_qbase_addr[9:2] )
+ );
+
+
+ assign reg_9[15:0] = {rx_buf_qbase_addr[9:0],6'h0};
+ assign reg_9[31:16] = {tx_buf_qbase_addr[9:0],6'h0};
+
+
+
+//-----------------------------------------------------------------------
+// RX-Clock Static Counter Status Signal
+//-----------------------------------------------------------------------
+// Note: rx_sts_vld signal is only synchronised w.r.t application clock, and
+// assumption is rx_sts is stable untill next packet received
+ assign rx_good_frm_trig = rx_sts_vld && (rx_sts[7:0] == 'h0);
+ assign rx_bad_frm_trig = rx_sts_vld && (rx_sts[7:0] != 'h0);
+
+
+stat_counter #(16) u_stat_rx_good_frm (
+ // Clock and Reset Signals
+ . sys_clk (app_clk ),
+ . s_reset_n (app_reset_n ),
+
+ . count_inc (rx_good_frm_trig),
+ . count_dec (1'b0 ),
+
+ . reg_sel (sw_wr_en_10 ),
+ . reg_wr_data (reg_wdata[15:0] ),
+ . reg_wr (wr_be[0] ), // Byte write not supported for cntr
+
+ . cntr_intr ( ),
+ . cntrout (reg_10[15:0] )
+ );
+
+stat_counter #(16) u_stat_rx_bad_frm (
+ // Clock and Reset Signals
+ . sys_clk (app_clk ),
+ . s_reset_n (app_reset_n ),
+
+ . count_inc (rx_bad_frm_trig ),
+ . count_dec (1'b0 ),
+
+ . reg_sel (sw_wr_en_10 ),
+ . reg_wr_data (reg_wdata[31:16] ),
+ . reg_wr (wr_be[0] ), // Byte write not supported for cntr
+
+ . cntr_intr ( ),
+ . cntrout (reg_10[31:16] )
+ );
+
+
+ wire tx_good_frm_trig = tx_sts_vld ;
+
+stat_counter #(16) u_stat_tx_good_frm (
+ // Clock and Reset Signals
+ . sys_clk (app_clk ),
+ . s_reset_n (app_reset_n ),
+
+ . count_inc (tx_good_frm_trig ),
+ . count_dec (1'b0 ),
+
+ . reg_sel (sw_wr_en_11 ),
+ . reg_wr_data (reg_wdata[15:0] ),
+ . reg_wr (wr_be[0] ), // Byte write not supported for cntr
+
+ . cntr_intr ( ),
+ . cntrout (reg_11[15:0] )
+ );
+
+assign reg_11[31:16] = 16'h0;
+
+// reg_12 & reg_13
+
+stat_counter #(4) u_rx_qcnt (
+ // Clock and Reset Signals
+ . sys_clk (app_clk ),
+ . s_reset_n (app_reset_n ),
+
+ . count_inc (rx_qcnt_inc ),
+ . count_dec (rx_qcnt_dec ),
+
+ . reg_sel (sw_wr_en_12 ),
+ . reg_wr_data (reg_wdata[3:0] ),
+ . reg_wr (wr_be[0] ), // Byte write not supported for cntr
+
+ . cntr_intr ( ),
+ . cntrout (rx_qcnt )
+ );
+
+stat_counter #(4) u_tx_qcnt (
+ // Clock and Reset Signals
+ . sys_clk (app_clk ),
+ . s_reset_n (app_reset_n ),
+
+ . count_inc (tx_qcnt_inc ),
+ . count_dec (tx_qcnt_dec ),
+
+ . reg_sel (sw_wr_en_12 ),
+ . reg_wr_data (reg_wdata[11:8] ),
+ . reg_wr (wr_be[2] ), // Byte write not supported for cntr
+
+ . cntr_intr ( ),
+ . cntrout (tx_qcnt )
+ );
+
+assign reg_12[7:0] = {4'h0,rx_qcnt[3:0]};
+assign reg_12[15:8] = {4'h0,tx_qcnt[3:0]};
+assign reg_12[31:16] = {16'h0};
+
+generic_intr_stat_reg #(9) u_intr_stat (
+ //inputs
+ . clk (app_clk ),
+ . reset_n (app_reset_n ),
+ . reg_we ({{1{sw_wr_en_13 & wr_be[1]}},
+ {8{sw_wr_en_13 & wr_be[0]}}} ),
+ . reg_din (reg_wdata[8:0] ),
+ . hware_req ({tx_sts,rx_sts[7:0]} ),
+
+ //outputs
+ . data_out (reg_13[8:0] )
+ );
+
+assign reg_13[31:9] = 23'h0;
+
+// IP SA [31:0]
+
+ generic_register #(8,0 ) u_ip_sa_0 (
+ .we ({8{sw_wr_en_14 & wr_be[0] }}),
+ .data_in (reg_wdata[7:0] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (cfg_ip_sa[7:0] )
+ );
+
+ generic_register #(8,0 ) u_ip_sa_1 (
+ .we ({8{sw_wr_en_14 & wr_be[1] }}),
+ .data_in (reg_wdata[15:8] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (cfg_ip_sa[15:8] )
+ );
+
+
+ generic_register #(8,0 ) u_ip_sa_2 (
+ .we ({8{sw_wr_en_14 & wr_be[2] }}),
+ .data_in (reg_wdata[23:16] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (cfg_ip_sa[23:16] )
+ );
+
+ generic_register #(8,0 ) u_ip_sa_3 (
+ .we ({8{sw_wr_en_14 & wr_be[3] }}),
+ .data_in (reg_wdata[31:24] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (cfg_ip_sa[31:24] )
+ );
+
+assign reg_14 = cfg_ip_sa[31:0];
+
+// Mac filter
+
+ generic_register #(8,0 ) u_mac_filter_0 (
+ .we ({8{sw_wr_en_15 & wr_be[0] }}),
+ .data_in (reg_wdata[7:0] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (cfg_mac_filter[7:0] )
+ );
+
+ generic_register #(8,0 ) u_mac_filter_1 (
+ .we ({8{sw_wr_en_14 & wr_be[1] }}),
+ .data_in (reg_wdata[15:8] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (cfg_mac_filter[15:8] )
+ );
+
+
+ generic_register #(8,0 ) u_mac_filter_2 (
+ .we ({8{sw_wr_en_14 & wr_be[2] }}),
+ .data_in (reg_wdata[23:16] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (cfg_mac_filter[23:16] )
+ );
+
+ generic_register #(8,0 ) u_mac_filter_3 (
+ .we ({8{sw_wr_en_14 & wr_be[3] }}),
+ .data_in (reg_wdata[31:24] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (cfg_mac_filter[31:24] )
+ );
+
+assign reg_15 = cfg_mac_filter[31:0];
+endmodule
+
diff --git a/verilog/rtl/gmac/mac/g_deferral.v b/verilog/rtl/gmac/mac/g_deferral.v
new file mode 100755
index 0000000..6f0ec0b
--- /dev/null
+++ b/verilog/rtl/gmac/mac/g_deferral.v
@@ -0,0 +1,197 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Mar 2, 2011 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+/***************************************************************
+ Description:
+ deferral.v : This block performs the deferral algorithm for
+ half duplex mode, as per the IEEE 802.3 section 4.2.3.2.2
+ This block also implements the optional two part deferral
+ mechanism.
+***********************************************************************/
+
+module g_deferral (
+ df2tx_dfl_dn,
+ cf2df_dfl_single,
+ phy_tx_en,
+ phy_tx_er,
+ tx_clk,
+ app_reset_n);
+
+
+ input [7:0] cf2df_dfl_single; //program with 9.6 ms
+ input phy_tx_en; //TX frame is done, wait for IPG
+ //used in FULL duplex
+ input phy_tx_er; //TX Error
+ input tx_clk; //MII provided tx_clk
+ input app_reset_n;
+
+ output df2tx_dfl_dn; //when active hold the TX, else
+ //TX can send preamble
+
+ wire df2tx_dfl_dn;
+
+ parameter dfl_idle_st = 6'b000000;
+ parameter dfl_dfl_st = 6'b000010;
+ parameter dfl_full_tx_dn_st = 6'b010000;
+ parameter dfl_wipg_st = 6'b100000;
+
+ reg [5:0] curr_dfl_st, nxt_dfl_st;
+ reg dfl_dn;
+ reg strt_dfl;
+ reg [7:0] dfl_cntr;
+
+ reg phy_tx_en_d;
+
+ wire was_xmitted;
+
+ assign df2tx_dfl_dn = dfl_dn;
+ /*****************************************************************
+ * Synchronous process for the FSM to enable and disable TX on
+ * receive activity
+ *****************************************************************/
+ always @(posedge tx_clk or negedge app_reset_n)
+ begin
+ if (!app_reset_n)
+ curr_dfl_st <= dfl_idle_st;
+ else
+ curr_dfl_st <= nxt_dfl_st;
+ end // always @ (posedge tx_clk or negedge app_reset_n)
+
+ /*****************************************************************
+ * comb process for the FSM to enable and disable TX on
+ * receive activity
+ *****************************************************************/
+ always @(curr_dfl_st or dfl_cntr
+ or phy_tx_en or phy_tx_er or was_xmitted)
+ begin
+ strt_dfl = 0;
+ dfl_dn = 0;
+ nxt_dfl_st = curr_dfl_st;
+
+ case (curr_dfl_st)
+ dfl_idle_st :
+ begin
+ dfl_dn = 1;
+ if (phy_tx_en)
+ begin
+ dfl_dn = 0;
+ nxt_dfl_st = dfl_full_tx_dn_st;
+ end // if (phy_tx_en)
+ else
+ nxt_dfl_st = dfl_idle_st;
+ end // case: dfl_idle_st
+
+ dfl_full_tx_dn_st :
+ begin
+ // full duplex mode, wait till the current tx
+ // frame is transmitted and wait for IPG time,
+ // no need to wait for two part defferal
+ if (!phy_tx_en && !phy_tx_er)
+ begin
+ strt_dfl = 1;
+ nxt_dfl_st = dfl_wipg_st;
+ end // if (!phy_tx_en)
+ else
+ nxt_dfl_st = dfl_full_tx_dn_st;
+ end // case: dfl_full_tx_dn_st
+
+ dfl_wipg_st :
+ begin
+ // This state is reached when there is no transmit
+ // in progress. In this state IPG counter should checked
+ // and upon its expiry indicate deferral done
+ // to tx_fsm block
+ if (dfl_cntr == 8'd0)
+ begin
+ dfl_dn = 1;
+ nxt_dfl_st = dfl_idle_st;
+ end
+ else
+ nxt_dfl_st = dfl_wipg_st;
+ end // case: dfl_wipg_st
+
+ default :
+ begin
+ nxt_dfl_st = dfl_idle_st;
+ end
+ endcase // case (curr_dfl_st)
+ end // always @ (curr_dfl_st )
+
+ //counter for the single phase deferral scheme
+ always @(posedge tx_clk or negedge app_reset_n)
+ begin
+ if (!app_reset_n)
+ dfl_cntr <= 8'd0;
+ else
+ begin
+ if (strt_dfl)
+ begin
+ dfl_cntr <= cf2df_dfl_single;
+ end
+ else
+ dfl_cntr <= dfl_cntr - 1;
+ end // else: !if(app_reset_n)
+ end // always @ (posedge tx_clk or negedge app_reset_n)
+
+
+ // Detect Packet end
+ assign was_xmitted = (phy_tx_en_d == 1'b1 && phy_tx_en == 1'b0) ? 1'b1 : 1'b0;
+
+
+ always @(posedge tx_clk or negedge app_reset_n)
+ begin
+ if (!app_reset_n)
+ phy_tx_en_d <= 1'b0;
+ else
+ phy_tx_en_d <= phy_tx_en;
+ end // always @ (posedge tx_clk or negedge app_reset_n)
+
+
+
+endmodule // deferral
+
+
+
+
diff --git a/verilog/rtl/gmac/mac/g_deferral_rx.v b/verilog/rtl/gmac/mac/g_deferral_rx.v
new file mode 100755
index 0000000..2368581
--- /dev/null
+++ b/verilog/rtl/gmac/mac/g_deferral_rx.v
@@ -0,0 +1,191 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Mar 2, 2011 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+/***************************************************************
+ Description:
+ deferral.v : This block performs the deferral algorithm for
+ half duplex mode, as per the IEEE 802.3 section 4.2.3.2.2
+ This block also implements the optional two part deferral
+ mechanism.
+***********************************************************************/
+
+module g_deferral_rx (
+ rx_dfl_dn,
+ dfl_single,
+ rx_dv,
+ rx_clk,
+ reset_n);
+
+
+ input [7:0] dfl_single; //program with 9.6 ms
+ input rx_dv; //TX frame is done, wait for IPG
+ //used in FULL duplex
+ input rx_clk; //MII provided rx_clk
+ input reset_n;
+
+ output rx_dfl_dn; //when active hold the TX, else
+ //TX can send preamble
+
+ parameter dfl_idle_st = 6'b000000;
+ parameter dfl_dfl_st = 6'b000010;
+ parameter dfl_full_tx_dn_st = 6'b010000;
+ parameter dfl_wipg_st = 6'b100000;
+
+ reg [5:0] curr_dfl_st, nxt_dfl_st;
+ reg rx_dfl_dn;
+ reg strt_dfl;
+ reg [8:0] fst_dfl_cntr;
+ reg [8:0] dfl_cntr;
+ reg [8:0] scnd_dfl_cntr;
+
+ /*****************************************************************
+ * Synchronous process for the FSM to enable and disable TX on
+ * receive activity
+ *****************************************************************/
+ always @(posedge rx_clk or negedge reset_n)
+ begin
+ if (!reset_n)
+ curr_dfl_st <= dfl_idle_st;
+ else
+ curr_dfl_st <= nxt_dfl_st;
+ end // always @ (posedge rx_clk or negedge reset_n)
+
+ /*****************************************************************
+ * comb process for the FSM to enable and disable TX on
+ * receive activity
+ *****************************************************************/
+ always @(curr_dfl_st or dfl_cntr or rx_dv)
+ begin
+ strt_dfl = 0;
+ rx_dfl_dn = 0;
+ nxt_dfl_st = curr_dfl_st;
+
+ case (curr_dfl_st)
+ dfl_idle_st :
+ begin
+ rx_dfl_dn = 1;
+ if (rx_dv)
+ begin
+ rx_dfl_dn = 0;
+ nxt_dfl_st = dfl_full_tx_dn_st;
+ end // if (rx_dv)
+ else
+ nxt_dfl_st = dfl_idle_st;
+ end // case: dfl_idle_st
+
+ dfl_full_tx_dn_st :
+ begin
+ // full duplex mode, wait till the current tx
+ // frame is transmitted and wait for IPG time,
+ // no need to wait for two part defferal
+ if (!rx_dv)
+ begin
+ strt_dfl = 1;
+ nxt_dfl_st = dfl_wipg_st;
+ end // if (!rx_dv)
+ else
+ nxt_dfl_st = dfl_full_tx_dn_st;
+ end // case: dfl_full_tx_dn_st
+
+ dfl_wipg_st :
+ begin
+ // This state is reached when there is no transmit
+ // in progress. In this state IPG counter should checked
+ // and upon its expiry indicate deferral done
+ // to tx_fsm block
+ if (dfl_cntr == 9'd0)
+ begin
+ rx_dfl_dn = 1;
+ nxt_dfl_st = dfl_idle_st;
+ end
+ else
+ nxt_dfl_st = dfl_wipg_st;
+ end // case: dfl_wipg_st
+
+ dfl_dfl_st :
+ //wait in this state till deferral time is done
+ //if CRS is active before the deferral time
+ //restart the deferral process again
+ begin
+ begin
+ if (dfl_cntr == 9'd0)
+ begin
+ rx_dfl_dn = 1;
+ nxt_dfl_st = dfl_idle_st;
+ end
+ else
+ nxt_dfl_st = dfl_dfl_st;
+ end //
+ end // case: dfl_dfl_st
+
+ default :
+ begin
+ nxt_dfl_st = dfl_idle_st;
+ end
+ endcase // case (curr_dfl_st)
+ end // always @ (curr_dfl_st )
+
+ //counter for the single phase deferral scheme
+ always @(posedge rx_clk or negedge reset_n)
+ begin
+ if (!reset_n)
+ dfl_cntr <= 9'd0;
+ else
+ begin
+ if (strt_dfl)
+ begin
+ dfl_cntr[7:0] <= dfl_single;
+ dfl_cntr[8] <= 0;
+ end
+ else
+ dfl_cntr <= dfl_cntr - 1;
+ end // else: !if(reset_n)
+ end // always @ (posedge rx_clk or negedge reset_n)
+
+endmodule // deferral
+
+
+
+
diff --git a/verilog/rtl/gmac/mac/g_mac_core.v b/verilog/rtl/gmac/mac/g_mac_core.v
new file mode 100755
index 0000000..ac82d16
--- /dev/null
+++ b/verilog/rtl/gmac/mac/g_mac_core.v
@@ -0,0 +1,609 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Mar 2, 2011 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+ module g_mac_core (
+ scan_mode,
+ s_reset_n,
+ tx_reset_n,
+ rx_reset_n,
+ reset_mdio_clk_n,
+ app_reset_n,
+
+ app_clk,
+
+ // Reg Bus Interface Signal
+ reg_cs,
+ reg_wr,
+ reg_addr,
+ reg_wdata,
+ reg_be,
+
+ // Outputs
+ reg_rdata,
+ reg_ack,
+
+
+ // RX FIFO Interface Signal
+ rx_fifo_full_i,
+ rx_fifo_wr_o,
+ rx_fifo_data_o,
+ rx_commit_wr_o,
+ rx_rewind_wr_o,
+ rx_commit_write_done_o,
+ clr_rx_error_from_rx_fsm_o,
+ rx_fifo_error_i,
+
+ // TX FIFO Interface Signal
+ tx_fifo_data_i,
+ tx_fifo_empty_i,
+ tx_fifo_rdy_i,
+ tx_fifo_rd_o,
+ tx_commit_read_o,
+
+ // Phy Signals
+
+ // Line Side Interface TX Path
+ phy_tx_en,
+ phy_tx_er,
+ phy_txd,
+ phy_tx_clk,
+
+ // Line Side Interface RX Path
+ phy_rx_clk,
+ phy_rx_er,
+ phy_rx_dv,
+ phy_rxd,
+ phy_crs,
+
+ //MDIO interface
+ mdio_clk,
+ mdio_in,
+ mdio_out_en,
+ mdio_out,
+
+ // configuration output
+ cf_mac_sa,
+ cfg_ip_sa,
+ cfg_mac_filter,
+ rx_buf_base_addr,
+ tx_buf_base_addr,
+
+ rx_buf_qbase_addr,
+ tx_buf_qbase_addr,
+
+ tx_qcnt_inc,
+ tx_qcnt_dec,
+ tx_qcnt,
+
+ rx_qcnt_inc,
+ rx_qcnt_dec,
+ rx_qcnt
+
+ );
+
+parameter mac_mdio_en = 1'b1;
+
+//-----------------------------------------------------------------------
+// INPUT/OUTPUT DECLARATIONS
+//-----------------------------------------------------------------------
+input scan_mode;
+input s_reset_n;
+input tx_reset_n;
+input rx_reset_n;
+input reset_mdio_clk_n;
+input app_reset_n;
+
+//-----------------------------------------------------------------------
+// Application Clock Related Declaration
+//-----------------------------------------------------------------------
+input app_clk;
+
+// Conntrol Bus Sync with Application Clock
+//---------------------------------
+// Reg Bus Interface Signal
+//---------------------------------
+ input reg_cs ;
+ input reg_wr ;
+ input [3:0] reg_addr ;
+ input [31:0] reg_wdata ;
+ input [3:0] reg_be ;
+
+ // Outputs
+ output [31:0] reg_rdata ;
+ output reg_ack ;
+
+
+
+// RX FIFO Interface Signal
+output clr_rx_error_from_rx_fsm_o;
+input rx_fifo_full_i;
+output rx_fifo_wr_o;
+output [8:0] rx_fifo_data_o;
+output rx_commit_wr_o;
+output rx_commit_write_done_o;
+output rx_rewind_wr_o;
+input rx_fifo_error_i;
+
+//-----------------------------------------------------------------------
+// TX-Clock Domain Status Signal
+//-----------------------------------------------------------------------
+output tx_commit_read_o;
+output tx_fifo_rd_o;
+
+input [8:0] tx_fifo_data_i;
+input tx_fifo_empty_i;
+input tx_fifo_rdy_i;
+
+
+//-----------------------------------------------------------------------
+// Line-Tx Signal
+//-----------------------------------------------------------------------
+output phy_tx_en;
+output phy_tx_er;
+output [7:0] phy_txd;
+input phy_tx_clk;
+
+//-----------------------------------------------------------------------
+// Line-Rx Signal
+//-----------------------------------------------------------------------
+input phy_rx_clk;
+input phy_rx_er;
+input phy_rx_dv;
+input [7:0] phy_rxd;
+input phy_crs;
+
+
+//-----------------------------------------------------------------------
+// MDIO Signal
+//-----------------------------------------------------------------------
+input mdio_clk;
+input mdio_in;
+output mdio_out_en;
+output mdio_out;
+
+output [47:0] cf_mac_sa;
+output [31:0] cfg_ip_sa;
+output [31:0] cfg_mac_filter;
+output [3:0] rx_buf_base_addr;
+output [3:0] tx_buf_base_addr;
+
+output [9:0] rx_buf_qbase_addr; // Rx Q Base Address
+output [9:0] tx_buf_qbase_addr; // Tx Q Base Address
+
+input tx_qcnt_inc;
+input tx_qcnt_dec;
+output [3:0] tx_qcnt;
+
+input rx_qcnt_inc;
+input rx_qcnt_dec;
+output [3:0] rx_qcnt;
+
+//-----------------------------------------------------------------------
+// RX-Clock Domain Status Signal
+//-----------------------------------------------------------------------
+wire rx_sts_vld_o;
+wire [15:0] rx_sts_bytes_rcvd_o;
+wire rx_sts_large_pkt_o;
+wire rx_sts_lengthfield_err_o;
+wire rx_sts_len_mismatch_o;
+wire rx_sts_crc_err_o;
+wire rx_sts_runt_pkt_rcvd_o;
+wire rx_sts_rx_overrun_o;
+wire rx_sts_frm_length_err_o;
+wire rx_sts_rx_er_o;
+
+
+//-----------------------------------------------------------------------
+// TX-Clock Domain Status Signal
+//-----------------------------------------------------------------------
+wire tx_sts_vld_o ;
+wire [15:0]tx_sts_byte_cntr_o ;
+wire tx_sts_fifo_underrun_o;
+// TX Interface Status Signal
+wire tx_set_fifo_undrn_o ;
+
+wire[7:0] mi2rx_rx_byte,tx2mi_tx_byte;
+wire [7:0] cf2df_dfl_single_rx;
+wire [15:0] cf2rx_max_pkt_sz;
+
+ g_rx_top u_rx_top(
+ //application
+ .app_clk (app_clk),
+ .app_reset_n (s_reset_n),
+ .rx_reset_n (rx_reset_n),
+ .scan_mode (scan_mode),
+
+ .rx_sts_vld (rx_sts_vld_o),
+ .rx_sts_bytes_rcvd (rx_sts_bytes_rcvd_o),
+ .rx_sts_large_pkt (rx_sts_large_pkt_o),
+ .rx_sts_lengthfield_err (rx_sts_lengthfield_err_o),
+ .rx_sts_len_mismatch (rx_sts_len_mismatch_o),
+ .rx_sts_crc_err (rx_sts_crc_err_o),
+ .rx_sts_runt_pkt_rcvd (rx_sts_runt_pkt_rcvd_o),
+ .rx_sts_rx_overrun (rx_sts_rx_overrun_o),
+ .rx_sts_frm_length_err (rx_sts_frm_length_err_o),
+ .clr_rx_error_from_rx_fsm (clr_rx_error_from_rx_fsm_o),
+ .rx_fifo_full (rx_fifo_full_i),
+ .rx_dt_wrt (rx_fifo_wr_o),
+ .rx_dt_out (rx_fifo_data_o),
+ .rx_commit_wr (rx_commit_wr_o),
+ .commit_write_done (rx_commit_write_done_o),
+ .rx_rewind_wr (rx_rewind_wr_o),
+ //mii interface
+ .phy_rx_clk (phy_rx_clk),
+ .mi2rx_strt_rcv (mi2rx_strt_rcv),
+ .mi2rx_rcv_vld (mi2rx_rcv_vld),
+ .mi2rx_rx_byte (mi2rx_rx_byte),
+ .mi2rx_end_rcv (mi2rx_end_rcv),
+ .mi2rx_extend (mi2rx_extend),
+ .mi2rx_frame_err (mi2rx_frame_err),
+ .mi2rx_end_frame (mi2rx_end_frame),
+ .mi2rx_crs (mi2rx_crs),
+ .df2rx_dfl_dn (df2rx_dfl_dn),
+ //PHY Signals
+ .phy_rx_dv (phy_rx_dv),
+ //Config interface
+ .cf2rx_max_pkt_sz (cf2rx_max_pkt_sz),
+ .cf2rx_rx_ch_en (cf2rx_ch_en),
+ .cf2rx_strp_pad_en (cf2rx_strp_pad_en),
+ .cf2rx_snd_crc (cf2rx_snd_crc),
+ .cf2rx_rcv_runt_pkt_en (cf2rx_runt_pkt_en),
+ .cf_macmode (cf_mac_mode_o),
+ .cf2df_dfl_single_rx (cf2df_dfl_single_rx),
+ .ap2rx_rx_fifo_err (rx_fifo_error_i),
+ //for crs based flow control
+ .phy_crs (phy_crs)
+ );
+
+ wire [4:0] cf2md_regad,cf2md_phyad;
+ wire [15:0] cf2md_datain,md2cf_data;
+
+
+
+ wire md2cf_status;
+ wire md2cf_cmd_done;
+ wire cf2md_op;
+ wire cf2md_go;
+ wire mdc;
+
+ wire int_s_reset_n;
+ wire [4:0] int_cf2md_regad;
+ wire [4:0] int_cf2md_phyad;
+ wire int_cf2md_op;
+ wire int_cf2md_go;
+ wire [15:0] int_cf2md_datain;
+
+ wire int_md2cf_status;
+ wire [15:0] int_md2cf_data;
+ wire int_md2cf_cmd_done;
+
+ wire int_mdio_clk;
+ wire int_mdio_out_en;
+ wire int_mdio_out;
+ wire int_mdc;
+ wire int_mdio_in;
+
+// ------------------------------------------------------------------------
+// MDIO Enable/disable Mux
+// MDIO is used only in the WAN MAC block. The MDIO block has to be disabled
+// in all other places. When MDIO is enabled the MDIO block signals will be
+// connected to core module appriprotately. If MDIO is disabled, all inputs
+// to the MDIO module is made zero and all outputs from this module to other
+// modules is made zero. The enable/disable is controlled by the parameter
+// mac_mdio_en.
+// ------------------------------------------------------------------------
+
+// ------------------------------------------------------------------------
+// Inputs to the MDIO module
+// ------------------------------------------------------------------------
+
+assign int_s_reset_n = (mac_mdio_en == 1'b1) ? reset_mdio_clk_n : 1'b1;
+assign int_cf2md_regad = (mac_mdio_en == 1'b1) ? cf2md_regad : 5'b0;
+assign int_cf2md_phyad = (mac_mdio_en == 1'b1) ? cf2md_phyad : 5'b0;
+assign int_cf2md_op = (mac_mdio_en == 1'b1) ? cf2md_op : 1'b0;
+assign int_cf2md_go = (mac_mdio_en == 1'b1) ? cf2md_go : 1'b0;
+assign int_cf2md_datain = (mac_mdio_en == 1'b1) ? cf2md_datain : 16'b0;
+
+// ------------------------------------------------------------------------
+// Outputs from the MDIO module used locally
+// ------------------------------------------------------------------------
+
+assign md2cf_status = (mac_mdio_en == 1'b1) ? int_md2cf_status : 1'b0;
+assign md2cf_data = (mac_mdio_en == 1'b1) ? int_md2cf_data : 16'b0;
+//assign md2cf_cmd_done = (mac_mdio_en == 1'b1) ? int_md2cf_cmd_done : 1'b0;
+
+// ------------------------------------------------------------------------
+// Outputs from the MDIO module driven out of this module
+// ------------------------------------------------------------------------
+
+assign mdio_out_en = (mac_mdio_en == 1'b1) ? int_mdio_out_en : 1'b0;
+assign mdio_out = (mac_mdio_en == 1'b1) ? int_mdio_out : 1'b0;
+assign mdc = (mac_mdio_en == 1'b1) ? int_mdc : 1'b0;
+
+assign int_mdio_clk = (mac_mdio_en == 1'b1) ? mdio_clk : 1'b0;
+assign int_mdio_in = (mac_mdio_en == 1'b1) ? mdio_in : 1'b0;
+
+// ------------------------------------------------------------------------
+// MDIO module connected with 'int_' signals
+// ------------------------------------------------------------------------
+
+
+ g_md_intf u_md_intf(
+ //apllication interface
+ .scan_mode (scan_mode),
+ .reset_n (int_s_reset_n),
+
+ .mdio_clk (int_mdio_clk),
+ .mdio_in (int_mdio_in),
+ .mdio_outen_reg (int_mdio_out_en),
+ .mdio_out_reg (int_mdio_out),
+ //Config interface
+ .mdio_regad (int_cf2md_regad),
+ .mdio_phyad (int_cf2md_phyad),
+ .mdio_op (int_cf2md_op),
+ .go_mdio (int_cf2md_go),
+ .mdio_datain (int_cf2md_datain),
+ .mdio_dataout (int_md2cf_data),
+ .mdio_cmd_done (md2cf_cmd_done),
+ .mdio_stat (int_md2cf_status),
+ .mdc (int_mdc)
+ );
+
+
+ wire [7:0] cf2df_dfl_single;
+ wire [47:0] cf_mac_sa;
+ wire cf2tx_force_bad_fcs;
+ wire set_fifo_undrn;
+
+ g_tx_top U_tx_top (
+ .app_clk (app_clk) ,
+ .set_fifo_undrn (tx_set_fifo_undrn_o),
+
+ //Outputs
+ //TX FIFO management
+ .tx_commit_read (tx_commit_read_o),
+ .tx_dt_rd (tx_fifo_rd_o),
+
+ //MII interface
+ .tx2mi_strt_preamble (tx2mi_strt_preamble),
+ .tx2mi_byte_valid (tx2mi_byte_valid),
+ .tx2mi_byte (tx2mi_tx_byte),
+ .tx2mi_end_transmit (tx2mi_end_transmit),
+ .tx_ch_en (tx_ch_en),
+
+ //Status to application
+ .tx_sts_vld (tx_sts_vld_o),
+ .tx_sts_byte_cntr (tx_sts_byte_cntr_o),
+ .tx_sts_fifo_underrun (tx_sts_fifo_underrun_o),
+
+ //Inputs
+ //MII interface
+ .phy_tx_en (phy_tx_en),
+ .phy_tx_er (phy_tx_er),
+
+
+ //configuration
+ .cf2tx_ch_en (cf2tx_ch_en),
+ .cf2df_dfl_single (cf2df_dfl_single),
+ .cf2tx_pad_enable (cf2tx_pad_enable),
+ .cf2tx_append_fcs (cf2tx_append_fcs),
+ .cf_mac_mode (cf_mac_mode_o),
+ .cf_mac_sa (cf_mac_sa),
+ .cf2tx_force_bad_fcs (cf2tx_force_bad_fcs),
+
+ //FIFO data
+ .app_tx_dt_in (tx_fifo_data_i),
+ .app_tx_fifo_empty (tx_fifo_empty_i),
+ .app_tx_rdy (tx_fifo_rdy_i),
+
+ //MII
+ .mi2tx_byte_ack (mi2tx_byte_ack),
+
+ .app_reset_n (s_reset_n),
+ .tx_reset_n (tx_reset_n),
+ .tx_clk (phy_tx_clk)
+ );
+
+ toggle_sync u_rx_sts_sync (
+ . in_clk (phy_rx_clk ),
+ . in_rst_n (rx_reset_n ),
+ . in (rx_sts_vld_o ),
+ . out_clk (app_clk ),
+ . out_rst_n (app_reset_n ),
+ . out_req (rx_sts_vld_ss ),
+ . out_ack (rx_sts_vld_ss )
+ );
+
+
+ toggle_sync u_tx_sts_sync (
+ . in_clk (phy_tx_clk ),
+ . in_rst_n (tx_reset_n ),
+ . in (tx_sts_vld_o ),
+ . out_clk (app_clk ),
+ . out_rst_n (app_reset_n ),
+ . out_req (tx_sts_vld_ss ),
+ . out_ack (tx_sts_vld_ss )
+ );
+
+
+
+ g_cfg_mgmt #(mac_mdio_en) u_cfg_mgmt (
+
+ // Reg Bus Interface Signal
+ . reg_cs (reg_cs),
+ . reg_wr (reg_wr),
+ . reg_addr (reg_addr),
+ . reg_wdata (reg_wdata),
+ . reg_be (reg_be),
+
+ // Outputs
+ . reg_rdata (reg_rdata),
+ . reg_ack (reg_ack),
+
+ // Rx Status
+ . rx_sts_vld(rx_sts_vld_ss),
+ . rx_sts ({rx_sts_large_pkt_o,
+ rx_sts_lengthfield_err_o,
+ rx_sts_len_mismatch_o,
+ rx_sts_crc_err_o,
+ rx_sts_runt_pkt_rcvd_o,
+ rx_sts_rx_overrun_o,
+ rx_sts_frm_length_err_o,
+ rx_sts_rx_er_o
+ }),
+
+ // Tx Status
+ . tx_sts_vld(tx_sts_vld_ss),
+ . tx_sts (tx_sts_fifo_underrun_o),
+
+ // MDIO READ DATA FROM PHY
+ // Since MDIO is not required for the half duplex
+ // MACs the done is always tied to 1'b1
+ .md2cf_cmd_done (md2cf_cmd_done),
+ .md2cf_status (md2cf_status),
+ .md2cf_data (md2cf_data),
+
+ .app_clk (app_clk),
+ .app_reset_n (app_reset_n),
+
+ //List of Outputs
+ // MII Control
+ .cf2mi_loopback_en (cf2mi_loopback_en),
+ .cf_mac_mode (cf_mac_mode_o),
+ .cf_chk_rx_dfl (cf_chk_rx_dfl),
+ .cf_silent_mode (cf_silent_mode),
+ .cf2mi_rmii_en (cf2mi_rmii_en_o),
+
+ // Config In
+ .cfg_uni_mac_mode_change_i (cfg_uni_mac_mode_change_i),
+
+ //CHANNEL enable
+ .cf2tx_ch_en (cf2tx_ch_en),
+ .cf2df_dfl_single (cf2df_dfl_single),
+ .cf2df_dfl_single_rx (cf2df_dfl_single_rx),
+ .cf2tx_pad_enable (cf2tx_pad_enable),
+ .cf2tx_append_fcs (cf2tx_append_fcs),
+ //CHANNEL CONTROL RX
+ .cf2rx_max_pkt_sz (cf2rx_max_pkt_sz),
+ .cf2rx_ch_en (cf2rx_ch_en),
+ .cf2rx_strp_pad_en (cf2rx_strp_pad_en),
+ .cf2rx_snd_crc (cf2rx_snd_crc),
+ .cf2rx_runt_pkt_en (cf2rx_runt_pkt_en),
+ .cf_mac_sa (cf_mac_sa),
+ .cfg_ip_sa (cfg_ip_sa),
+ .cfg_mac_filter (cfg_mac_filter),
+ .cf2tx_force_bad_fcs (cf2tx_force_bad_fcs),
+ //MDIO CONTROL & DATA
+ .cf2md_datain (cf2md_datain),
+ .cf2md_regad (cf2md_regad),
+ .cf2md_phyad (cf2md_phyad),
+ .cf2md_op (cf2md_op),
+ .cf2md_go (cf2md_go),
+
+ .rx_buf_base_addr (rx_buf_base_addr),
+ .tx_buf_base_addr (tx_buf_base_addr),
+
+ .rx_buf_qbase_addr (rx_buf_qbase_addr),
+ .tx_buf_qbase_addr (tx_buf_qbase_addr),
+
+ .tx_qcnt_inc (tx_qcnt_inc),
+ .tx_qcnt_dec (tx_qcnt_dec),
+ .tx_qcnt (tx_qcnt),
+
+ .rx_qcnt_inc (rx_qcnt_inc),
+ .rx_qcnt_dec (rx_qcnt_dec),
+ .rx_qcnt (rx_qcnt)
+
+
+ );
+
+ g_mii_intf u_mii_intf(
+ // Data and Control Signals to tx_fsm and rx_fsm
+ .mi2rx_strt_rcv (mi2rx_strt_rcv),
+ .mi2rx_rcv_vld (mi2rx_rcv_vld),
+ .mi2rx_rx_byte (mi2rx_rx_byte),
+ .mi2rx_end_rcv (mi2rx_end_rcv),
+ .mi2rx_extend (mi2rx_extend),
+ .mi2rx_frame_err (mi2rx_frame_err),
+ .mi2rx_end_frame (mi2rx_end_frame),
+ .mi2rx_crs (mi2rx_crs),
+ .mi2tx_byte_ack (mi2tx_byte_ack),
+ .cfg_uni_mac_mode_change (cfg_uni_mac_mode_change_i),
+
+ // Phy Signals
+ .phy_tx_en (phy_tx_en),
+ .phy_tx_er (phy_tx_er),
+ .phy_txd (phy_txd),
+ .phy_tx_clk (phy_tx_clk),
+ .phy_rx_clk (phy_rx_clk),
+ .tx_reset_n (tx_reset_n),
+ .rx_reset_n (rx_reset_n),
+ .phy_rx_er (phy_rx_er),
+ .phy_rx_dv (phy_rx_dv),
+ .phy_rxd (phy_rxd),
+ .phy_crs (phy_crs),
+
+ // Reset signal
+ // .app_reset (app_reset),
+ .rx_sts_rx_er_reg (rx_sts_rx_er),
+ .app_reset_n (s_reset_n),
+
+ // Signals from Config Management
+ .cf2mi_loopback_en (cf2mi_loopback_en),
+ .cf2mi_rmii_en (cf2mi_rmii_en_o),
+ .cf_mac_mode (cf_mac_mode_o),
+ .cf_chk_rx_dfl (cf_chk_rx_dfl),
+ .cf_silent_mode (cf_silent_mode),
+
+ // Signal from Application to transmit JAM
+ .df2rx_dfl_dn (df2rx_dfl_dn),
+
+ // Inputs from Transmit FSM
+ .tx2mi_strt_preamble (tx2mi_strt_preamble),
+ .tx2mi_end_transmit (tx2mi_end_transmit),
+ .tx2mi_tx_byte (tx2mi_tx_byte),
+ .tx_ch_en (tx_ch_en),
+ .mi2tx_slot_vld ()
+ );
+endmodule
diff --git a/verilog/rtl/gmac/mac/g_md_intf.v b/verilog/rtl/gmac/mac/g_md_intf.v
new file mode 100755
index 0000000..03e56b6
--- /dev/null
+++ b/verilog/rtl/gmac/mac/g_md_intf.v
@@ -0,0 +1,547 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Mar 2, 2011 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+/***************************************************************
+ Description:
+
+ md_intf.v: This verilog file is for the mdio interface of the mac
+ This block enables the station to communicate with the
+ PHYs. This interface is kicked of by a go command from
+ the application. This intiates the read and write operation
+ to the PHY. Upon completion of the operation it returns
+ a indication called command done with the status of such
+ operation.
+
+***************************************************************/
+/************** MODULE DECLARATION ****************************/
+
+module g_md_intf(
+ scan_mode,
+ reset_n,
+ mdio_clk,
+ mdio_in,
+ mdio_outen_reg,
+ mdio_out_reg,
+ mdio_regad,
+ mdio_phyad,
+ mdio_op,
+ go_mdio,
+ mdio_datain,
+ mdio_dataout,
+ mdio_cmd_done,
+ mdio_stat,
+ mdc
+ );
+
+
+parameter FIVE = 5'h5;
+parameter SIXTEEN = 5'd16;
+parameter THIRTY_TWO = 5'd31;
+parameter WRITE = 1;
+
+/******* INPUT & OUTPUT DECLARATIONS *************************/
+
+ input scan_mode ; // scan_mode = 1
+ input reset_n; // reset from mac application interface
+ input mdio_in; // Input signal used to read data from PHY
+ input mdio_clk; // Input signal used to read data from PHY
+ input[4:0] mdio_regad; // register address for the current PHY operation
+ input[4:0] mdio_phyad; // Phy address to which the current operation is intended
+ input mdio_op; // 1 = READ 0 = WRITE
+ input go_mdio; // This is go command from the application for a MDIO
+ // transfer
+ input[15:0] mdio_datain; // 16 bit Write value from application to MDIO block
+ output[15:0] mdio_dataout; // 16 bit Read value for a MDIO transfer
+ output mdio_cmd_done; // This is from MDIO to indicate mdio command completion
+ output mdio_stat; // Status of completion. 0 = No error 1= Error
+ output mdio_out_reg; // Output signal used to write data to PHY
+ output mdio_outen_reg; // Enable signal 1= Output mode on 0 = Input mode
+ output mdc; // This is the MDIO clock
+
+/******* WIRE & REG DECLARATION FOR INPUT AND OUTPUTS ********/
+ wire mdc;
+ wire [15:0] mdio_dataout;
+ wire go_mdio_sync;
+ reg mdio_stat;
+ reg mdio_cmd_done;
+ reg mdio_out_en;
+ reg mdio_out;
+
+ half_dup_dble_reg U_dble_reg1 (
+ //outputs
+ .sync_out_pulse(go_mdio_sync),
+ //inputs
+ .in_pulse(go_mdio),
+ .dest_clk(mdio_clk),
+ .reset_n(reset_n)
+ );
+
+
+
+
+/*** REG & WIRE DECLARATIONS FOR LOCAL SIGNALS ***************/
+ reg[3:0] mdio_cur_st;
+ reg[3:0] mdio_nxt_st;
+ parameter mdio_idle_st= 4'd0,
+ mdio_idle1_st = 4'd1,
+ mdio_sfd1_st= 4'd2,
+ mdio_sfd2_st= 4'd3,
+ mdio_op1_st= 4'd4,
+ mdio_op2_st= 4'd5,
+ mdio_phyaddr_st= 4'd6,
+ mdio_regaddr_st= 4'd7,
+ mdio_turnar_st= 4'd8,
+ mdio_wrturn_st= 4'd9,
+ mdio_rdturn_st= 4'd10,
+ mdio_read_st= 4'd11,
+ mdio_write_st= 4'd12,
+ mdio_complete_st= 4'd13,
+ mdio_preamble_st= 4'd14;
+
+ reg operation;
+ reg phyaddr_mux_sel;
+ reg regaddr_mux_sel;
+ reg write_data_mux_sel;
+ reg read_data_mux_sel;
+ wire[4:0] inc_temp_count;
+ reg[4:0] temp_count;
+ reg reset_temp_count;
+ reg inc_count;
+ reg[4:0] phy_addr;
+ reg[4:0] reg_addr;
+ reg[15:0] transmit_data;
+ reg[15:0] receive_data;
+ reg set_mdio_stat,clr_mdio_stat;
+
+/***************** WIRE ASSIGNMENTS *************************/
+ assign mdc = mdio_clk;
+ assign mdio_dataout = receive_data;
+
+/******** SEQUENTIAL LOGIC **********************************/
+
+ always @(mdio_cur_st or go_mdio_sync or inc_temp_count or
+ transmit_data or operation or phy_addr or reg_addr or temp_count or mdio_in)
+ begin
+ mdio_nxt_st = mdio_cur_st;
+ inc_count = 1'b0;
+ //mdio_cmd_done = 1'b0;
+ mdio_out = 1'b0;
+ mdio_out_en = 1'b0;
+ set_mdio_stat = 1'b0;
+ clr_mdio_stat = 1'b0;
+ phyaddr_mux_sel = 1'b0;
+ read_data_mux_sel = 1'b0;
+ regaddr_mux_sel = 1'b0;
+ reset_temp_count = 1'b0;
+ write_data_mux_sel = 1'b0;
+
+ casex(mdio_cur_st ) // synopsys parallel_case full_case
+
+ mdio_idle_st:
+ // This state waits for signal go_mdio
+ // upon this command from config block
+ // mdio state machine starts to send
+ // SOF delimter
+ begin
+ if(~go_mdio_sync)
+ mdio_nxt_st = mdio_idle1_st; //mdio_sfd1_st;
+ else
+ mdio_nxt_st = mdio_idle_st;
+ end
+
+ mdio_idle1_st:
+ begin
+ if (go_mdio_sync)
+ mdio_nxt_st = mdio_preamble_st;
+ else
+ mdio_nxt_st = mdio_idle1_st;
+ end
+
+ mdio_preamble_st:
+ begin
+ clr_mdio_stat = 1'b1;
+ mdio_out_en = 1'b1;
+ mdio_out = 1'b1;
+ if (temp_count == THIRTY_TWO)
+ begin
+ mdio_nxt_st = mdio_sfd1_st;
+ reset_temp_count = 1'b1;
+ end
+ else
+ begin
+ inc_count = 1'b1;
+ mdio_nxt_st = mdio_preamble_st;
+ end
+ end
+
+ mdio_sfd1_st:
+ // This state shifts the first bit
+ // of Start of Frame De-limiter
+ begin
+ mdio_out_en = 1'b1;
+ mdio_out = 1'b0;
+ mdio_nxt_st = mdio_sfd2_st;
+ end
+
+ mdio_sfd2_st:
+ // This state shifts the second bit
+ // of Start of Frame De-limiter
+ begin
+ mdio_out_en = 1'b1;
+ mdio_out = 1'b1;
+ mdio_nxt_st = mdio_op1_st;
+ end
+
+ mdio_op1_st:
+ // This state shifts the first bit
+ // of type of operation read/write
+ begin
+ mdio_out_en = 1'b1;
+ if(operation)
+ mdio_out = 1'b0;
+ else
+ mdio_out = 1'b1;
+ mdio_nxt_st = mdio_op2_st;
+ end
+
+ mdio_op2_st:
+ // This state shifts the second bit
+ // of type of operation read/write and
+ // determines the appropriate next state
+ // needed for such operation
+ begin
+ mdio_out_en = 1'b1;
+ mdio_nxt_st = mdio_phyaddr_st;
+ if(operation)
+ mdio_out = 1'b1;
+ else
+ mdio_out = 1'b0;
+ end
+
+ mdio_phyaddr_st:
+ // This state shifts the phy-address on the mdio
+ begin
+ mdio_out_en = 1'b1;
+ phyaddr_mux_sel = 1'b1;
+ if(inc_temp_count == FIVE)
+ begin
+ reset_temp_count = 1'b1;
+ mdio_out = phy_addr[4];
+ mdio_nxt_st = mdio_regaddr_st;
+ end
+ else
+ begin
+ inc_count = 1'b1;
+ mdio_out = phy_addr[4];
+ mdio_nxt_st = mdio_phyaddr_st;
+ end
+ end
+
+ mdio_regaddr_st:
+ // This state shifts the register in the phy to which
+ // this operation is intended
+ begin
+ mdio_out_en = 1'b1;
+ regaddr_mux_sel = 1'b1;
+ if(inc_temp_count == FIVE)
+ begin
+ reset_temp_count = 1'b1;
+ mdio_out = reg_addr[4];
+ mdio_nxt_st = mdio_turnar_st;
+ end
+ else
+ begin
+ inc_count = 1'b1;
+ mdio_out = reg_addr[4];
+ mdio_nxt_st = mdio_regaddr_st;
+ end
+ end
+
+ mdio_turnar_st:
+ // This state determines whether the output enable
+ // needs to on or of based on the type of command
+ begin
+ mdio_out = 1'b1;
+ if(operation)
+ begin
+ mdio_out_en = 1'b1;
+ mdio_nxt_st = mdio_wrturn_st;
+ end
+ else
+ begin
+ mdio_out_en = 1'b0;
+ mdio_nxt_st = mdio_rdturn_st;
+ end
+ end
+
+ mdio_wrturn_st:
+ // This state is used for write turn around
+ begin
+ mdio_out_en = 1'b1;
+ mdio_out = 1'b0;
+ mdio_nxt_st = mdio_write_st;
+ end
+
+ mdio_rdturn_st:
+ // This state is used to read turn around state
+ // the output enable is switched off
+ begin
+ if (mdio_in)
+ set_mdio_stat = 1'b1;
+ mdio_out_en = 1'b0;
+ mdio_nxt_st = mdio_read_st;
+ end
+
+ mdio_write_st:
+ // This state transfers the 16 bits of data to the
+ // PHY
+ begin
+ mdio_out_en = 1'b1;
+ write_data_mux_sel = 1'b1;
+ if(inc_temp_count == SIXTEEN)
+ begin
+ reset_temp_count = 1'b1;
+ mdio_out = transmit_data[15];
+ mdio_nxt_st = mdio_complete_st;
+ end
+ else
+ begin
+ inc_count = 1'b1;
+ mdio_out = transmit_data[15];
+ mdio_nxt_st = mdio_write_st;
+ end
+ end
+
+ mdio_read_st:
+ // This state receives the 16 bits of data from the
+ // PHY
+ begin
+ mdio_out_en = 1'b0;
+ read_data_mux_sel = 1'b1;
+ if(inc_temp_count == SIXTEEN)
+ begin
+ reset_temp_count = 1'b1;
+ mdio_nxt_st = mdio_complete_st;
+ end
+ else
+ begin
+ inc_count = 1'b1;
+ mdio_nxt_st = mdio_read_st;
+ end
+ end
+
+ mdio_complete_st:
+ // This completes the mdio transfers indicates to the
+ // application of such complete
+ begin
+ mdio_nxt_st = mdio_idle_st;
+ mdio_out_en = 1'b0;
+ read_data_mux_sel = 1'b0;
+ //mdio_cmd_done = 1'b1;
+// mdio_stat = 1'b0;
+ end
+ endcase
+ end
+always @(mdio_cur_st)
+ mdio_cmd_done = (mdio_cur_st == 4'd13);
+
+
+always @(posedge mdio_clk or negedge reset_n)
+begin
+ if (!reset_n)
+ mdio_stat <= 1'b0;
+ else if (set_mdio_stat)
+ mdio_stat <= 1'b1;
+ else if (clr_mdio_stat)
+ mdio_stat <= 1'b0;
+end
+
+
+// This latches the PHY address, Register address and the
+// Transmit data and the type of operation
+//
+ always @(posedge mdio_clk or negedge reset_n)
+ begin
+ if(!reset_n)
+ begin
+ phy_addr <= 5'd0;
+ reg_addr <= 5'd0;
+ transmit_data <= 16'd0;
+ operation <= 1'b0;
+ receive_data <= 16'd0;
+ end
+ else
+ begin
+ if(go_mdio_sync)
+ begin
+ phy_addr <= mdio_phyad;
+ reg_addr <= mdio_regad;
+ if(mdio_op == WRITE)
+ begin
+ operation <= 1'b1;
+ transmit_data <= mdio_datain;
+ end
+ end
+ else
+ begin
+ operation <= 1'b0;
+ phy_addr <= phy_addr;
+ transmit_data <= transmit_data;
+ reg_addr <= reg_addr;
+ end // else: !if(go_mdio)
+
+ if(phyaddr_mux_sel)
+ begin
+ /*
+ phy_addr[0] <= phy_addr[1];
+ phy_addr[1] <= phy_addr[2];
+ phy_addr[2] <= phy_addr[3];
+ phy_addr[3] <= phy_addr[4];
+ */
+ phy_addr[4] <= phy_addr[3];
+ phy_addr[3] <= phy_addr[2];
+ phy_addr[2] <= phy_addr[1];
+ phy_addr[1] <= phy_addr[0];
+ end
+ if(regaddr_mux_sel)
+ begin
+ reg_addr[4] <= reg_addr[3];
+ reg_addr[3] <= reg_addr[2];
+ reg_addr[2] <= reg_addr[1];
+ reg_addr[1] <= reg_addr[0];
+ end
+ if(write_data_mux_sel)
+ begin
+ transmit_data[15] <= transmit_data[14];
+ transmit_data[14] <= transmit_data[13];
+ transmit_data[13] <= transmit_data[12];
+ transmit_data[12] <= transmit_data[11];
+ transmit_data[11] <= transmit_data[10];
+ transmit_data[10] <= transmit_data[9];
+ transmit_data[9] <= transmit_data[8];
+ transmit_data[8] <= transmit_data[7];
+ transmit_data[7] <= transmit_data[6];
+ transmit_data[6] <= transmit_data[5];
+ transmit_data[5] <= transmit_data[4];
+ transmit_data[4] <= transmit_data[3];
+ transmit_data[3] <= transmit_data[2];
+ transmit_data[2] <= transmit_data[1];
+ transmit_data[1] <= transmit_data[0];
+ end
+ if(read_data_mux_sel)
+ begin
+ receive_data[0] <= mdio_in;
+ receive_data[1] <= receive_data[0];
+ receive_data[2] <= receive_data[1];
+ receive_data[3] <= receive_data[2];
+ receive_data[4] <= receive_data[3];
+ receive_data[5] <= receive_data[4];
+ receive_data[6] <= receive_data[5];
+ receive_data[7] <= receive_data[6];
+ receive_data[8] <= receive_data[7];
+ receive_data[9] <= receive_data[8];
+ receive_data[10] <= receive_data[9];
+ receive_data[11] <= receive_data[10];
+ receive_data[12] <= receive_data[11];
+ receive_data[13] <= receive_data[12];
+ receive_data[14] <= receive_data[13];
+ receive_data[15] <= receive_data[14];
+ end
+ end // else: !if(!reset_n)
+ end // always @ (posedge mdio_clk or negedge reset_n)
+
+ // Temporary counter used to shift the data on the mdio line
+ // This is also used to receive data on the line
+ assign inc_temp_count = temp_count + 5'h1;
+
+ always @(posedge mdio_clk or negedge reset_n)
+ begin
+ if(!reset_n)
+ mdio_cur_st <= mdio_idle_st;
+ else
+ mdio_cur_st <= mdio_nxt_st;
+ end // always @ (posedge mdio_clk or negedge reset_n)
+
+ reg mdio_outen_reg, mdio_out_reg;
+
+ //----------------------------------------------
+ // Note: Druring Scan Mode inverted mdio_clk used for
+ // mdio_outen_reg & mdio_out_reg
+ //-----------------------------------------------
+ wire mdio_clk_scan = (scan_mode) ? !mdio_clk : mdio_clk;
+
+ always @(negedge mdio_clk_scan or negedge reset_n)
+ begin
+ if(!reset_n)
+ begin
+ mdio_outen_reg <= 1'b0;
+ mdio_out_reg <= 1'b0;
+ end
+ else
+ begin
+ mdio_outen_reg <= mdio_out_en;
+ mdio_out_reg <= mdio_out;
+ end
+
+ end // always @ (posedge mdio_clk or negedge reset_n)
+
+ always @(posedge mdio_clk or negedge reset_n)
+ begin
+ if(!reset_n)
+ temp_count <= 5'b0;
+ else
+ begin
+ if(reset_temp_count)
+ temp_count <= 5'b0;
+ else if(inc_count)
+ temp_count <= inc_temp_count;
+ end // else: !if(reset_n)
+ end // always @ (posedge mdio_clk or negedge reset_n)
+
+
+
+endmodule
+
+
diff --git a/verilog/rtl/gmac/mac/g_mii_intf.v b/verilog/rtl/gmac/mac/g_mii_intf.v
new file mode 100755
index 0000000..afbdf8f
--- /dev/null
+++ b/verilog/rtl/gmac/mac/g_mii_intf.v
@@ -0,0 +1,1077 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Mar 2, 2011 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+/***************************************************************
+ Description:
+
+ mii_intf.v: This verilog file is reduced mii interface for ethenet
+ The transmit state machine generates a condition to indicate
+ start transmit. This is done using strt_preamble. The transmit
+ state machine upon detecting strt_preamble generates pre-amble
+ and start of frame de-limiter and then starts accepting the data
+ from the transmit block by asserting the transmit nibble ack.
+
+ ***************************************************************/
+/************** MODULE DECLARATION ****************************/
+module g_mii_intf(
+ // Data and Control Signals to tx_fsm and rx_fsm
+ mi2rx_strt_rcv,
+ mi2rx_rcv_vld,
+ mi2rx_rx_byte,
+ mi2rx_end_rcv,
+ mi2rx_extend,
+ mi2rx_frame_err,
+ mi2rx_end_frame,
+ mi2rx_crs,
+ mi2tx_byte_ack,
+ mi2tx_slot_vld,
+ cfg_uni_mac_mode_change,
+
+ // Phy Signals
+ phy_tx_en,
+ phy_tx_er,
+ phy_txd,
+ phy_tx_clk,
+ phy_rx_clk,
+ tx_reset_n,
+ rx_reset_n,
+ phy_rx_er,
+ phy_rx_dv,
+ phy_rxd,
+ phy_crs,
+ rx_sts_rx_er_reg,
+
+ // Reset signal
+ app_reset_n,
+
+ // Signals from Config Management
+ cf2mi_loopback_en,
+ cf2mi_rmii_en,
+ cf_mac_mode,
+ cf_chk_rx_dfl,
+ cf_silent_mode,
+
+ // Signal from Application to transmit JAM
+ df2rx_dfl_dn,
+
+ // Inputs from Transmit FSM
+ tx2mi_strt_preamble,
+ tx2mi_end_transmit,
+ tx2mi_tx_byte,
+ tx_ch_en
+ );
+
+
+parameter NO_GMII_PREAMBLE = 5'b00111;
+parameter NO_MII_PREAMBLE = 5'b01111;
+parameter NO_RMII_PREAMBLE = 5'b11111;
+parameter GMII_JAM_COUNT = 5'b0011;
+parameter MII_JAM_COUNT = 5'b0111;
+parameter RMII_JAM_COUNT = 5'b1111;
+
+ /******* INPUT & OUTPUT DECLARATIONS *************************/
+
+ output mi2rx_strt_rcv; // This is generated by the MII block to indicate start
+ // of receive data.
+ output mi2rx_rcv_vld; // This signal is asserted by MII on reception of valid
+ // bytes to indicate to the RX block to accept data from PHY
+ output[7:0] mi2rx_rx_byte; // This the receive data from the PHY gathered as bytes
+ output mi2rx_end_rcv; // This signal is asserted with the last data assembled
+ output mi2rx_extend; // This signal is asserted during carrier extension (Receive)
+ output mi2rx_frame_err; // This signal is asserted during Dibit Error (In RMII Mode)
+ // or Nibble Error in (MII Mode)
+ output mi2rx_end_frame; // End of Frame
+ output mi2rx_crs; // CRS signal in rx_clk domain
+ output mi2tx_byte_ack; // MII block acknowledges a byte during transmit
+ output mi2tx_slot_vld; // MII block acknowledges valid slot during transmit // mfilardo
+
+ output phy_tx_en; // Enable data on TX
+ output phy_tx_er; // Transmit Error (Used in Carrier Extension in 1000 Mode)
+ output[7:0] phy_txd; // Transmit data on the line
+
+ input phy_tx_clk; // Transmit Clock in 10/100 Mb/s
+
+ output rx_sts_rx_er_reg;
+ input app_reset_n; // reset from the application interface
+
+ input phy_rx_clk; // Receive Clock in 10/100/1000 Mb/s
+ input phy_rx_er; // Receive Error. Used in Carrier Extension in 1000 Mode
+ input phy_rx_dv; // Receive Data Valid from the PHY
+ input[7:0] phy_rxd; // Receive Data
+ input phy_crs; // Carrier Sense from the line
+
+ input tx_reset_n;
+ input rx_reset_n;
+
+
+ input cf2mi_loopback_en; // loop back enable
+ input cf2mi_rmii_en; // RMII Mode
+ input cf_mac_mode; // Mac Mode 0--> 10/100 Mode, 1--> 1000 Mode
+ input cf_chk_rx_dfl; // Check for Deferal
+ input cf_silent_mode; // PHY Inactive
+ input df2rx_dfl_dn; // Deferal Done in Rx Clock Domain
+ input tx2mi_strt_preamble; // Tx FSM indicates to MII to generate
+ // preamble on the line
+ input tx2mi_end_transmit; // This is provided by the TX block to
+ // indicate end of transmit
+ input[7:0] tx2mi_tx_byte; // 8 bits of data from Tx block
+ input tx_ch_en; // Transmitt Enable
+ input cfg_uni_mac_mode_change;
+
+ /******* WIRE & REG DECLARATION FOR INPUT AND OUTPUTS ********/
+ reg phy_tx_en;
+ reg mi2tx_byte_ack;
+ reg mi2tx_slot_vld;
+ reg [7:0] phy_txd;
+ wire [7:0] mi2rx_rx_byte;
+ reg [7:0] mi2rx_rx_byte_in;
+ reg mi2rx_extend;
+ reg mi2rx_extend_err;
+ reg mi2rx_strt_rcv;
+ reg mi2rx_end_rcv;
+ reg mi2rx_rcv_vld;
+ reg mi2rx_frame_err;
+
+ /*** REG & WIRE DECLARATIONS FOR LOCAL SIGNALS ***************/
+
+ reg [4:0] tx_preamble_cnt_val;
+
+
+ reg strt_rcv_in;
+ reg end_rcv_in;
+ reg rx_dv_in;
+ reg rx_er_in;
+ reg rcv_valid_in;
+
+
+
+ reg [7:0] rxd_in;
+
+ parameter mii_rx_idle_st = 3'd0, mii_rx_pre_st = 3'd1,
+ mii_rx_byte_st = 3'd2, mii_rx_end_st = 3'd3,
+ mii_rx_dibit_st = 3'd4, mii_rx_nibble_st = 3'd5;
+
+ reg [2:0] mii_rx_nxt_st;
+ reg [2:0] mii_rx_cur_st;
+
+ parameter mii_tx_idle_st = 4'd0, mii_tx_pre_st = 4'd1,
+ mii_tx_byte_st = 4'd2, mii_tx_end_st = 4'd3,
+ mii_tx_nibble_st = 4'd5,
+ mii_tx_nibble_end_st = 4'd6, mii_tx_dibit_st = 4'd7,
+ mii_tx_dibit_end_st = 4'd8;
+
+ reg [3:0] mii_tx_cur_st;
+ reg [3:0] mii_tx_nxt_st;
+
+ wire receive_detect;
+ wire pre_condition;
+ wire sfd_condition;
+ wire tx_en;
+ wire tx_er;
+ wire [7:0] txd;
+ wire byte_boundary_rx, byte_boundary_tx;
+
+ reg tx_en_in;
+ reg tx_err_in;
+ reg tx_ext_in;
+ reg tx_pre_in;
+ reg tx_sfd_in;
+ reg tx_xfr_ack_in;
+ reg inc_preamble_cntr;
+ reg rst_preamble_cntr;
+ reg [1:0] tx_xfr_cnt, rx_xfr_cnt, tx_slot_xfr_cnt;
+ reg rx_dv;
+ reg rx_er;
+ reg rcv_err_in;
+ reg mi2rx_end_frame_in;
+
+ reg [1:0] tx_dibit_in;
+ reg mi2rx_extend_in, mi2rx_extend_err_in, mi2rx_end_frame;
+ reg crs_in;
+ reg phy_tx_er;
+
+ wire dibit_check_rx, dibit_check_tx;
+ wire nibble_check_rx, nibble_check_tx;
+ wire pre_condition_gmii, pre_condition_mii, pre_condition_rmii;
+ wire sfd_condition_gmii, sfd_condition_mii, sfd_condition_rmii;
+ wire [3:0] tx_nibble_in;
+ reg [7:0] rxd;
+ wire receive_detect_pulse;
+ reg d_receive_detect;
+
+
+ reg lb_tx_en, lb_tx_er;
+ reg rx_dv_del;
+ reg [1:0] rxd_del;
+ reg rx_dfl_dn;
+ reg rx_dfl_dn_reg;
+
+
+ /******** SEQUENTIAL LOGIC **********************************/
+
+ // This logic generates appropriate receive data valid
+ // in case of loop back
+ always @(tx_en or phy_rxd or txd or phy_rx_dv or tx_er or phy_crs
+ or cf2mi_loopback_en or phy_tx_en or phy_rx_er or
+ cf2mi_rmii_en or cf_mac_mode)
+ begin
+ if(cf2mi_loopback_en)
+ begin
+ rx_dv_in = tx_en;
+ rx_er_in = tx_er;
+ rxd_in = txd;
+ crs_in = (tx_en | tx_er) && cf_mac_mode;
+ end // if (mii_loopback_en)
+ else
+ begin
+ rx_dv_in = phy_rx_dv ;
+ rx_er_in = phy_rx_er;
+ rxd_in = phy_rxd;
+ // *** NOTE ****
+ // phy_crs should be a combination of crs and tx_en
+ // In Full Duplex tx_en determines deferral in half duplex
+ // crs determines deferral
+ crs_in = (tx_en | tx_er);
+ end // else: !if(mii_loopback_en)
+ end
+
+
+ // Following state machine is to detect start preamble and
+ // transmit preamble and sfd and then the data.
+ // This state machine also generates acknowledge to TX block
+ // to allow the TX block to update its byte pointers
+ always @(posedge phy_tx_clk or negedge tx_reset_n)
+ begin
+ if(!tx_reset_n)
+ begin
+ mii_tx_cur_st <= mii_tx_idle_st;
+ end
+ else if (tx_ch_en)
+ begin
+ mii_tx_cur_st <= mii_tx_nxt_st;
+ end
+ else
+ begin
+ mii_tx_cur_st <= mii_tx_idle_st;
+ end
+ end
+
+ always @(mii_tx_cur_st or tx2mi_strt_preamble or tx2mi_end_transmit or cf_mac_mode
+ or cf2mi_rmii_en or tx_preamble_cnt_val or byte_boundary_tx
+ or tx_xfr_cnt or receive_detect
+ or receive_detect_pulse or cfg_uni_mac_mode_change)
+ begin
+
+ mii_tx_nxt_st = mii_tx_cur_st;
+ tx_en_in = 1'b0;
+ tx_pre_in = 1'b0;
+ tx_sfd_in = 1'b0;
+ tx_err_in = 1'b0;
+ tx_ext_in = 1'b0;
+ inc_preamble_cntr = 1'b0;
+ rst_preamble_cntr = 1'b0;
+ tx_xfr_ack_in = 1'b0;
+
+ casex(mii_tx_cur_st) // synopsys parallel_case full_case
+
+ mii_tx_idle_st:
+ // wait from start from transmit state machine
+ begin
+ if(tx2mi_strt_preamble)
+ begin
+ inc_preamble_cntr = 1'b1;
+ tx_en_in = 1'b1;
+ tx_pre_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_pre_st;
+ end
+ else
+ mii_tx_nxt_st = mii_tx_idle_st;
+ end
+
+ mii_tx_pre_st:
+ // This state generates the preamble to be transmitted and
+ // generates SFD before transitioning the data state
+ begin
+ if((tx_preamble_cnt_val == NO_GMII_PREAMBLE) && cf_mac_mode)
+ begin
+ tx_en_in = 1'b1;
+ tx_sfd_in = 1'b1;
+ tx_xfr_ack_in = 1'b1;
+ rst_preamble_cntr = 1'b1;
+ mii_tx_nxt_st = mii_tx_byte_st;
+ end
+ else if((tx_preamble_cnt_val == NO_MII_PREAMBLE) && !cf_mac_mode &&
+ !cf2mi_rmii_en)
+ begin
+ tx_en_in = 1'b1;
+ tx_sfd_in = 1'b1;
+ tx_xfr_ack_in = 1'b1;
+ rst_preamble_cntr = 1'b1;
+ mii_tx_nxt_st = mii_tx_nibble_st;
+ end
+ else if((tx_preamble_cnt_val == NO_RMII_PREAMBLE) && !cf_mac_mode &&
+ cf2mi_rmii_en)
+ begin
+ tx_en_in = 1'b1;
+ tx_sfd_in = 1'b1;
+ tx_xfr_ack_in = 1'b1;
+ rst_preamble_cntr = 1'b1;
+ mii_tx_nxt_st = mii_tx_dibit_st;
+ end
+ else
+ begin
+ inc_preamble_cntr = 1'b1;
+ tx_en_in = 1'b1;
+ tx_pre_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_pre_st;
+ end
+ end
+
+ mii_tx_byte_st:
+ // This state picks up a byte from the transmit block
+ // before transmitting on the line
+ begin
+ if(tx2mi_end_transmit && byte_boundary_tx )
+ begin
+ tx_en_in = 1'b1;
+ tx_xfr_ack_in = 1'b0;
+ mii_tx_nxt_st = mii_tx_end_st;
+ end
+ else if (!cf_mac_mode & cfg_uni_mac_mode_change)
+ begin
+ tx_en_in = 1'b1;
+ tx_xfr_ack_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_nibble_st;
+ end
+ else
+ begin
+ tx_en_in = 1'b1;
+ tx_xfr_ack_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_byte_st;
+ end
+ end
+
+ /*mii_tx_byte_st:
+ // This state picks up a byte from the transmit block
+ // before transmitting on the line
+ begin
+ if(tx2mi_end_transmit && byte_boundary_tx )
+ begin
+ tx_en_in = 1'b1;
+ tx_xfr_ack_in = 1'b0;
+ mii_tx_nxt_st = mii_tx_end_st;
+ end
+ else
+ begin
+ tx_en_in = 1'b1;
+ tx_xfr_ack_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_byte_st;
+ end
+ end*/
+
+ mii_tx_end_st:
+ // This state checks for the end of transfer
+ // and extend for carrier extension
+ begin
+ if(tx2mi_strt_preamble)
+ begin
+ tx_en_in = 1'b1;
+ tx_pre_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_pre_st;
+ end
+ else
+ begin
+ tx_en_in = 1'b0;
+ mii_tx_nxt_st = mii_tx_idle_st;
+ end
+ end
+
+ /*mii_tx_nibble_st:
+ // This state picks up a byte from the transmit block
+ // before transmitting on the line
+ begin
+ if(tx2mi_end_transmit && !byte_boundary_tx )
+ begin
+ tx_en_in = 1'b1;
+ tx_xfr_ack_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_nibble_end_st;
+ end
+ else
+ begin
+ tx_en_in = 1'b1;
+ tx_xfr_ack_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_nibble_st;
+ end
+ end*/
+
+ mii_tx_nibble_st:
+ // This state picks up a byte from the transmit block
+ // before transmitting on the line
+ begin
+ if(tx2mi_end_transmit && !byte_boundary_tx )
+ begin
+ tx_en_in = 1'b1;
+ tx_xfr_ack_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_nibble_end_st;
+ end
+ else if (cf_mac_mode & cfg_uni_mac_mode_change)
+ begin
+ tx_en_in = 1'b1;
+ tx_xfr_ack_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_byte_st;
+ end
+ else
+ begin
+ tx_en_in = 1'b1;
+ tx_xfr_ack_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_nibble_st;
+ end
+ end
+
+ mii_tx_nibble_end_st:
+ // This state checks for the end of transfer
+ // and extend for carrier extension
+ begin
+ if(tx2mi_strt_preamble)
+ begin
+ tx_en_in = 1'b1;
+ tx_pre_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_pre_st;
+ end
+ else
+ begin
+ tx_en_in = 1'b0;
+ mii_tx_nxt_st = mii_tx_idle_st;
+ end
+ end
+
+ mii_tx_dibit_st:
+ // This state picks up a byte from the transmit block
+ // before transmitting on the line
+ begin
+ if(tx2mi_end_transmit && (tx_xfr_cnt[0]) && (tx_xfr_cnt[1]) )
+ begin
+ tx_en_in = 1'b1;
+ tx_xfr_ack_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_dibit_end_st;
+ end
+ else
+ begin
+ tx_en_in = 1'b1;
+ tx_xfr_ack_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_dibit_st;
+ end
+ end
+
+ mii_tx_dibit_end_st:
+ // This state checks for the end of transfer
+ // and extend for carrier extension
+ begin
+ if(tx2mi_strt_preamble)
+ begin
+ tx_en_in = 1'b1;
+ tx_pre_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_pre_st;
+ end
+ else
+ begin
+ tx_en_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_idle_st;
+ end
+ end
+ endcase
+ end // end always
+
+ // All the data, enable and ack signals leaving this blocks are
+ // registered tx_data and tx_en are outputs going to PHY tx_nibble_ack
+ // is indicating to the TX block of acceptance of data nibble
+ always @(posedge phy_tx_clk or negedge tx_reset_n)
+ begin
+ if(!tx_reset_n)
+ begin
+ lb_tx_en <= 1'b0;
+ lb_tx_er <= 1'b0;
+ phy_tx_en <= 1'b0;
+ phy_tx_er <= 1'b0;
+ mi2tx_byte_ack <= 1'b0;
+ mi2tx_slot_vld <= 1'b0;
+ end
+ else
+ begin
+ lb_tx_en <= tx_en_in;
+ lb_tx_er <= tx_err_in;
+ phy_tx_en <= (cf_silent_mode) ? 1'b0 : tx_en_in;
+ phy_tx_er <= (cf_silent_mode) ? 1'b0 : tx_err_in;
+ mi2tx_byte_ack <= (cf_mac_mode || (cf2mi_rmii_en && tx_xfr_cnt[1] && !tx_xfr_cnt[0]) ||
+ (!cf2mi_rmii_en && nibble_check_tx)) ? tx_xfr_ack_in : 1'b0;
+ mi2tx_slot_vld <= (cf_mac_mode || (cf2mi_rmii_en && tx_slot_xfr_cnt[1] && !tx_slot_xfr_cnt[0]) ||
+ (!cf2mi_rmii_en && tx_slot_xfr_cnt[0] )) ? (tx_xfr_ack_in || inc_preamble_cntr) : 1'b0;
+ end
+ end
+
+ always @(posedge phy_tx_clk or negedge tx_reset_n)
+ begin
+ if(!tx_reset_n)
+ begin
+ phy_txd[7:0] <= 8'b00000000;
+ end
+ else
+ begin
+ if (cf_mac_mode)
+ phy_txd[7:0] <= (tx_pre_in) ? 8'b01010101 : ((tx_sfd_in) ?
+ 8'b11010101 : ((tx_ext_in) ? 8'b00001111: tx2mi_tx_byte));
+ else if (!cf_mac_mode && !cf2mi_rmii_en)
+ phy_txd[3:0] <= (tx_pre_in) ? 4'b0101 : ((tx_sfd_in) ?
+ 4'b1101 : tx_nibble_in) ;
+ else if (!cf_mac_mode && cf2mi_rmii_en)
+ phy_txd[1:0] <= (tx_pre_in) ? 2'b01 : ((tx_sfd_in) ?
+ 2'b11 : tx_dibit_in) ;
+ end
+ end
+ assign receive_detect_pulse = receive_detect && !d_receive_detect;
+
+
+ always @(posedge phy_tx_clk or negedge tx_reset_n)
+ begin
+ if(!tx_reset_n)
+ d_receive_detect <= 0;
+ else
+ d_receive_detect <= receive_detect;
+ end
+ // counter for the number transfers
+ always @(posedge phy_tx_clk or negedge tx_reset_n)
+ begin
+ if(!tx_reset_n)
+ tx_xfr_cnt <= 2'd0;
+ else if(tx2mi_strt_preamble)
+ tx_xfr_cnt <= 2'd0;
+ else if(tx_xfr_ack_in)
+ tx_xfr_cnt <= tx_xfr_cnt + 1;
+ end
+
+ // phy_tx_en_dly
+ reg phy_tx_en_dly;
+ always @(posedge phy_tx_clk or negedge tx_reset_n)
+ begin
+ if(!tx_reset_n)
+ phy_tx_en_dly <= 1'd0;
+ else
+ phy_tx_en_dly <= phy_tx_en;
+ end
+
+ wire phy_tx_en_fall;
+ assign phy_tx_en_fall = phy_tx_en_dly && !phy_tx_en;
+
+ // counter for the number transfers ...
+ always @(posedge phy_tx_clk or negedge tx_reset_n)
+ begin
+ if(!tx_reset_n)
+ tx_slot_xfr_cnt <= 2'd0;
+ else if(phy_tx_en_fall)
+ tx_slot_xfr_cnt <= 2'd0;
+ else if(inc_preamble_cntr || tx_xfr_ack_in)
+ tx_slot_xfr_cnt <= tx_slot_xfr_cnt + 1;
+ end
+
+ assign nibble_check_tx = tx_xfr_cnt[0];
+ assign dibit_check_tx= tx_xfr_cnt[0] && tx_xfr_cnt[1];
+ assign byte_boundary_tx = (cf_mac_mode) ? 1'b1:
+ ((!cf_mac_mode && !cf2mi_rmii_en) ? nibble_check_tx : dibit_check_tx);
+
+ assign tx_nibble_in = (tx_xfr_cnt[0]) ? tx2mi_tx_byte[3:0] : tx2mi_tx_byte[7:4];
+
+/* always @(tx_xfr_cnt or tx2mi_tx_byte or phy_tx_clk)
+ begin
+ if (!tx_xfr_cnt[1] && !tx_xfr_cnt[0])
+ tx_dibit_in <= tx2mi_tx_byte[1:0];
+ else if (!tx_xfr_cnt[1] && tx_xfr_cnt[0])
+ tx_dibit_in <= tx2mi_tx_byte[3:2];
+ else if (tx_xfr_cnt[1] && !tx_xfr_cnt[0])
+ tx_dibit_in <= tx2mi_tx_byte[5:4];
+ else if (tx_xfr_cnt[1] && tx_xfr_cnt[0])
+ tx_dibit_in <= tx2mi_tx_byte[7:6];
+ else
+ tx_dibit_in <= tx2mi_tx_byte[1:0];
+ end
+*/
+ always @(posedge phy_tx_clk or negedge tx_reset_n)
+ begin
+ if(!tx_reset_n)
+ tx_dibit_in <= 2'b0;
+ else if(tx2mi_strt_preamble)
+ tx_dibit_in <= 2'b0;
+ else
+ begin
+ if (!tx_xfr_cnt[1] && !tx_xfr_cnt[0])
+ tx_dibit_in <= tx2mi_tx_byte[1:0];
+ else if (!tx_xfr_cnt[1] && tx_xfr_cnt[0])
+ tx_dibit_in <= tx2mi_tx_byte[3:2];
+ else if (tx_xfr_cnt[1] && !tx_xfr_cnt[0])
+ tx_dibit_in <= tx2mi_tx_byte[5:4];
+ else if (tx_xfr_cnt[1] && tx_xfr_cnt[0])
+ tx_dibit_in <= tx2mi_tx_byte[7:6];
+ end
+ end
+
+ // counter for the number of preamble to be sent
+ // before transmitting the sfd
+ always @(posedge phy_tx_clk or negedge tx_reset_n)
+ begin
+ if(!tx_reset_n)
+ tx_preamble_cnt_val <= 5'd0;
+ else if(rst_preamble_cntr)
+ tx_preamble_cnt_val <= 5'd0;
+ else if(inc_preamble_cntr)
+ tx_preamble_cnt_val <= tx_preamble_cnt_val + 1;
+ end
+
+
+
+ always @(posedge phy_rx_clk or negedge rx_reset_n)
+ begin
+ if(!rx_reset_n)
+ rx_dfl_dn_reg <= 1'b0;
+ else if (df2rx_dfl_dn)
+ rx_dfl_dn_reg <= 1'b1;
+ else
+ begin
+ if (!phy_rx_dv && !phy_rx_er)
+ rx_dfl_dn_reg <= 1'b0;
+ end
+ end
+
+ assign mi2rx_rx_byte = mi2rx_rx_byte_in;
+ //assign rxd = (!cf_mac_mode && cf2mi_rmii_en)? mi2rx_rx_byte : mi2rx_rx_byte_in;
+
+ assign pre_condition_gmii = (!rxd[7] && rxd[6] && !rxd[5] && rxd[4]
+ && !rxd[3] && rxd[2] && !rxd[1] && rxd[0] && rx_dv
+ && !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
+
+ assign pre_condition_mii = (!rxd[3] && rxd[2] && !rxd[1] && rxd[0] && rx_dv
+ && !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
+
+ assign pre_condition_rmii = (!rxd[1] && rxd[0] && rx_dv
+ && !rxd_del[1] && rxd_del[0] && rx_dv_del
+ && !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
+
+ assign sfd_condition_gmii = (rxd[7] && rxd[6] && !rxd[5] && rxd[4]
+ && !rxd[3] && rxd[2] && !rxd[1] && rxd[0] && rx_dv
+ && !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
+
+ assign sfd_condition_mii = (rxd[3] && rxd[2] && !rxd[1] && rxd[0] && rx_dv
+ && !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
+
+ assign sfd_condition_rmii = (rxd[1] && rxd[0] && rx_dv
+ && !rxd_del[1] && rxd_del[0] && rx_dv_del
+ && !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
+
+
+
+ assign pre_condition = (cf_mac_mode) ? pre_condition_gmii :
+ ((cf2mi_rmii_en) ? pre_condition_rmii : pre_condition_mii);
+
+ assign sfd_condition = (cf_mac_mode) ? sfd_condition_gmii :
+ ((cf2mi_rmii_en) ? sfd_condition_rmii : sfd_condition_mii);
+
+ // Following state machine is to detect strt preamble and
+ // receive preamble and sfd and then the data.
+ always @(posedge phy_rx_clk or negedge rx_reset_n)
+ begin
+ if(!rx_reset_n)
+ begin
+ mii_rx_cur_st <= mii_rx_idle_st;
+ end
+ else
+ begin
+ mii_rx_cur_st <= mii_rx_nxt_st;
+ end
+ end
+
+ always @(mii_rx_cur_st or rx_dv or rx_er or pre_condition or sfd_condition
+ or byte_boundary_rx or rxd or rx_xfr_cnt or cf2mi_rmii_en or cf_mac_mode)
+ begin
+ mii_rx_nxt_st = mii_rx_cur_st;
+ strt_rcv_in = 1'b0;
+ end_rcv_in = 1'b0;
+ rcv_valid_in = 1'b0;
+ rcv_err_in = 1'b0;
+ mi2rx_extend_in = 1'b0;
+ mi2rx_extend_err_in = 1'b0;
+ mi2rx_end_frame_in = 1'b0;
+
+ casex(mii_rx_cur_st) // synopsys parallel_case full_case
+
+ mii_rx_idle_st:
+ // This state is waiting for pre-amble to
+ // appear on the line in Receive mode
+ begin
+ if(pre_condition)
+ mii_rx_nxt_st = mii_rx_pre_st;
+ else
+ mii_rx_nxt_st = mii_rx_idle_st;
+ end
+
+ mii_rx_pre_st:
+ // This state checks the pre-amble and Waits for SFD on the line
+ begin
+ if(sfd_condition)
+ begin
+ strt_rcv_in = 1'b1;
+ if(cf_mac_mode)
+ mii_rx_nxt_st = mii_rx_byte_st;
+ else if(!cf_mac_mode && !cf2mi_rmii_en)
+ mii_rx_nxt_st = mii_rx_nibble_st;
+ else if(!cf_mac_mode && cf2mi_rmii_en)
+ mii_rx_nxt_st = mii_rx_dibit_st;
+ end
+ else if(pre_condition)
+ begin
+ mii_rx_nxt_st = mii_rx_pre_st;
+ end
+ else if(!rx_dv && rx_er && cf_mac_mode)
+ begin
+ mi2rx_extend_in = (rxd == 8'h0F) ? 1'b1: 1'b0;
+ mi2rx_extend_err_in = (rxd == 8'h1F) ? 1'b1: 1'b0;
+ mii_rx_nxt_st = mii_rx_pre_st;
+ end
+ else
+ begin
+ mi2rx_end_frame_in = 1'b1;
+ mii_rx_nxt_st = mii_rx_idle_st;
+ end
+ end
+
+ mii_rx_byte_st:
+ // This state looks for data validity and latches di-bit2 and
+ // sends it to the receiver
+ begin
+ if(rx_dv)
+ begin
+ rcv_valid_in = 1'b1;
+ mii_rx_nxt_st = mii_rx_byte_st;
+ end
+ else if (!rx_dv && rx_er && cf_mac_mode)
+ begin
+ mi2rx_extend_in = (rxd == 8'h0F) ? 1'b1: 1'b0;
+ mi2rx_extend_err_in = (rxd == 8'h1F) ? 1'b1: 1'b0;
+ end_rcv_in = 1'b1;
+ mii_rx_nxt_st = mii_rx_pre_st;
+ end
+ else
+ begin
+ end_rcv_in = 1'b1;
+ mii_rx_nxt_st = mii_rx_end_st;
+ end
+ end
+
+ mii_rx_end_st:
+ // This state looks for data validity and latches di-bit2 and
+ // sends it to the receiver
+ mii_rx_nxt_st = mii_rx_idle_st;
+
+ mii_rx_nibble_st:
+ begin
+ if(rx_dv)
+ begin
+ rcv_valid_in = 1'b1;
+ mii_rx_nxt_st = mii_rx_nibble_st;
+ end
+ else
+ begin
+ end_rcv_in = 1'b1;
+ mii_rx_nxt_st = mii_rx_end_st;
+ if(rx_xfr_cnt[0])
+ rcv_err_in = 1'b1;
+ end
+ end
+
+ mii_rx_dibit_st:
+ begin
+ if(rx_dv)
+ begin
+ rcv_valid_in = 1'b1;
+ mii_rx_nxt_st = mii_rx_dibit_st;
+ end
+ else
+ begin
+ end_rcv_in = 1'b1;
+ mii_rx_nxt_st = mii_rx_end_st;
+ if(!(!rx_xfr_cnt[0] && !rx_xfr_cnt[1]))
+ rcv_err_in = 1'b1;
+ end
+ end
+
+ endcase
+ end // always @ (mii_rx_cur_st...
+
+ // counter for the number receives
+ always @(posedge phy_rx_clk or negedge rx_reset_n)
+ begin
+ if(!rx_reset_n)
+ rx_xfr_cnt <= 2'd0;
+ else if(mi2rx_end_rcv)
+ rx_xfr_cnt <= 2'd0;
+ else if(rcv_valid_in)
+ rx_xfr_cnt <= rx_xfr_cnt + 1;
+ end
+
+ always @(posedge phy_rx_clk or negedge rx_reset_n)
+ begin
+ if(!rx_reset_n)
+ begin
+ mi2rx_rx_byte_in <= 8'b0;
+ rxd <= 8'b0;
+ rxd_del <= 2'b0;
+ end
+ else
+ begin
+ rxd <= rxd_in;
+// rxd_del <= rxd_in[1:0];
+ rxd_del <= rxd[1:0];
+
+ if (cf_mac_mode)
+ mi2rx_rx_byte_in <= rxd;
+ else if (!cf_mac_mode && !cf2mi_rmii_en)
+ begin
+ if(!rx_xfr_cnt[0])
+ mi2rx_rx_byte_in[3:0] <= rxd[3:0];
+ else
+ mi2rx_rx_byte_in[7:4] <= rxd[3:0];
+ end
+ else if(!cf_mac_mode && cf2mi_rmii_en)
+ begin
+ if(!rx_xfr_cnt[1] && !rx_xfr_cnt[0])
+ mi2rx_rx_byte_in[1:0] <= rxd[1:0];
+ else if(!rx_xfr_cnt[1] && rx_xfr_cnt[0])
+ mi2rx_rx_byte_in[3:2] <= rxd[1:0];
+ else if(rx_xfr_cnt[1] && !rx_xfr_cnt[0])
+ mi2rx_rx_byte_in[5:4] <= rxd[1:0];
+ else if(rx_xfr_cnt[1] && rx_xfr_cnt[0])
+ mi2rx_rx_byte_in[7:6] <= rxd[1:0];
+ end
+ end
+ end
+
+ reg rx_sts_rx_er_reg;
+ always @(posedge phy_rx_clk or negedge rx_reset_n) begin
+ if(!rx_reset_n) begin
+ rx_sts_rx_er_reg <= 1'b0;
+ end
+ else if (mi2rx_strt_rcv) begin
+ rx_sts_rx_er_reg <= 1'b0;
+ end
+ else if(phy_rx_dv && phy_rx_er) begin
+ rx_sts_rx_er_reg <= 1'b1;
+ end
+ end
+
+ always @(posedge phy_rx_clk
+ or negedge rx_reset_n)
+ begin
+ if(!rx_reset_n)
+ begin
+ mi2rx_rcv_vld <= 1'b0;
+ end
+ else if(cf_mac_mode)
+ mi2rx_rcv_vld <= rcv_valid_in;
+ else if(!cf_mac_mode && cf2mi_rmii_en && rx_xfr_cnt[0] && rx_xfr_cnt[1])
+ mi2rx_rcv_vld <= rcv_valid_in;
+ else if(!cf_mac_mode && !cf2mi_rmii_en && rx_xfr_cnt[0])
+ mi2rx_rcv_vld <= rcv_valid_in;
+ else
+ mi2rx_rcv_vld <= 1'b0;
+ end
+ // All the data, enable and ack signals out of RX block are
+ // registered
+ always @(posedge phy_rx_clk or negedge rx_reset_n)
+ begin
+ if(!rx_reset_n)
+ begin
+ mi2rx_strt_rcv <= 1'b0;
+ mi2rx_end_rcv <= 1'b0;
+ //mi2rx_rcv_vld <= 1'b0;
+ mi2rx_frame_err <= 1'b0;
+ mi2rx_extend <= 1'b0;
+ mi2rx_extend_err <= 1'b0;
+ mi2rx_end_frame <= 1'b0;
+ rx_dv <= 1'b0;
+ rx_er <= 1'b0;
+ rx_dv_del <= 1'b0;
+ end
+ else
+ begin
+ mi2rx_strt_rcv <= strt_rcv_in;
+ mi2rx_end_rcv <= end_rcv_in;
+ //mi2rx_rcv_vld <= rcv_valid_in;
+ mi2rx_frame_err <= rcv_err_in;
+ mi2rx_extend <= mi2rx_extend_in;
+ mi2rx_extend_err <= mi2rx_extend_err_in;
+ mi2rx_end_frame <= mi2rx_end_frame_in;
+ rx_dv <= rx_dv_in;
+ rx_er <= rx_er_in;
+ rx_dv_del <= rx_dv;
+ end
+ end
+
+
+
+ half_dup_dble_reg U_dble_reg1 (
+ //outputs
+ .sync_out_pulse(receive_detect),
+ //inputs
+ .in_pulse(rx_dv_in),
+ .dest_clk(phy_tx_clk),
+ .reset_n(tx_reset_n)
+ );
+
+
+wire test;
+
+ half_dup_dble_reg U_dble_reg5 (
+ //outputs
+ .sync_out_pulse(tx_en),
+ //inputs
+ .in_pulse(lb_tx_en),
+ .dest_clk(phy_rx_clk),
+ .reset_n(rx_reset_n)
+ );
+
+ half_dup_dble_reg U_dble_reg6 (
+ //outputs
+ .sync_out_pulse(txd[0]),
+ //inputs
+ .in_pulse(phy_txd[0]),
+ .dest_clk(phy_rx_clk),
+ .reset_n(rx_reset_n)
+ );
+
+ half_dup_dble_reg U_dble_reg7 (
+ //outputs
+ .sync_out_pulse(txd[1]),
+ //inputs
+ .in_pulse(phy_txd[1]),
+ .dest_clk(phy_rx_clk),
+ .reset_n(rx_reset_n)
+ );
+
+ half_dup_dble_reg U_dble_reg8 (
+ //outputs
+ .sync_out_pulse(txd[2]),
+ //inputs
+ .in_pulse(phy_txd[2]),
+ .dest_clk(phy_rx_clk),
+ .reset_n(rx_reset_n)
+ );
+
+ half_dup_dble_reg U_dble_reg9 (
+ //outputs
+ .sync_out_pulse(txd[3]),
+ //inputs
+ .in_pulse(phy_txd[3]),
+ .dest_clk(phy_rx_clk),
+ .reset_n(rx_reset_n)
+ );
+
+ half_dup_dble_reg U_dble_reg10 (
+ //outputs
+ .sync_out_pulse(txd[4]),
+ //inputs
+ .in_pulse(phy_txd[4]),
+ .dest_clk(phy_rx_clk),
+ .reset_n(rx_reset_n)
+ );
+
+
+ half_dup_dble_reg U_dble_reg11 (
+ //outputs
+ .sync_out_pulse(txd[5]),
+ //inputs
+ .in_pulse(phy_txd[5]),
+ .dest_clk(phy_rx_clk),
+ .reset_n(rx_reset_n)
+ );
+
+
+ half_dup_dble_reg U_dble_reg12 (
+ //outputs
+ .sync_out_pulse(txd[6]),
+ //inputs
+ .in_pulse(phy_txd[6]),
+ .dest_clk(phy_rx_clk),
+ .reset_n(rx_reset_n)
+ );
+
+
+ half_dup_dble_reg U_dble_reg13 (
+ //outputs
+ .sync_out_pulse(txd[7]),
+ //inputs
+ .in_pulse(phy_txd[7]),
+ .dest_clk(phy_rx_clk),
+ .reset_n(rx_reset_n)
+ );
+
+
+ half_dup_dble_reg U_dble_reg14 (
+ //outputs
+ .sync_out_pulse(tx_er),
+ //inputs
+ .in_pulse(lb_tx_er),
+ .dest_clk(phy_rx_clk),
+ .reset_n(rx_reset_n)
+ );
+
+
+ half_dup_dble_reg U_dble_reg15 (
+ //outputs
+ .sync_out_pulse(mi2rx_crs),
+ //inputs
+ .in_pulse(crs_in),
+ .dest_clk(phy_rx_clk),
+ .reset_n(rx_reset_n)
+ );
+
+endmodule
+
diff --git a/verilog/rtl/gmac/mac/g_rx_fsm.v b/verilog/rtl/gmac/mac/g_rx_fsm.v
new file mode 100755
index 0000000..97df8dd
--- /dev/null
+++ b/verilog/rtl/gmac/mac/g_rx_fsm.v
@@ -0,0 +1,1109 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Mar 2, 2011 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+/***************************************************************
+ Description:
+
+ rx_fsm.v: This verilog file is the receive state machine for the MAC
+ block. It receives nibbles from rmii block. It assembles
+ double words from bytes. Generates writes to Receive FIFO
+ Removes padding and generates appropriate signals to the
+ CRC and Address Filtering block. It also generates the necessary
+ signals to generate status for every frame.
+
+ ***************************************************************/
+/************** MODULE DECLARATION ****************************/
+module g_rx_fsm(
+ // Status information to Applications
+ rx_sts_vld,
+ rx_sts_bytes_rcvd,
+ rx_sts_large_pkt,
+ rx_sts_lengthfield_err,
+ rx_sts_crc_err,
+ rx_sts_runt_pkt_rcvd,
+ rx_sts_rx_overrun,
+ rx_sts_frm_length_err,
+ rx_sts_len_mismatch,
+ // Data Signals to Fifo Management Block
+ clr_rx_error_from_rx_fsm,
+ rx2ap_rx_fsm_wrt,
+ rx2ap_rx_fsm_dt,
+ // Fifo Control Signal to Fifo Management Block
+ rx2ap_commit_write,
+ rx2ap_rewind_write,
+ // To address filtering block
+ //commit
+ commit_write_done,
+
+ // Global Signals
+ reset_n,
+ phy_rx_clk,
+ // Signals from Mii/Rmii block for Receive data
+ mi2rx_strt_rcv,
+ mi2rx_rcv_vld,
+ mi2rx_rx_byte,
+ mi2rx_end_rcv,
+ mi2rx_extend,
+ mi2rx_frame_err,
+ mi2rx_end_frame,
+ // Rx fifo management signal to indicate overrun
+ rx_fifo_full,
+ ap2rx_rx_fifo_err,
+ // Signal from CRC check block
+ rc2rx_crc_ok,
+ // Signals from Config Management Block
+ cf2rx_max_pkt_sz,
+ cf2rx_rx_ch_en,
+ cf2rx_strp_pad_en,
+ cf2rx_snd_crc,
+ cf2rx_rcv_runt_pkt_en,
+ cf2rx_gigabit_xfr,
+ //for crs based flow control
+ phy_crs
+
+ );
+
+
+parameter MIN_FRM_SIZE = 6'h2e ;
+ /******* INPUT & OUTPUT DECLARATIONS *************************/
+ output rx_sts_vld; // Receive status is available for the application
+ output [15:0] rx_sts_bytes_rcvd;
+ output rx_sts_large_pkt;
+ output rx_sts_lengthfield_err;
+ output rx_sts_crc_err;
+ output rx_sts_runt_pkt_rcvd;
+ output rx_sts_rx_overrun;
+ output rx_sts_frm_length_err;
+ output rx_sts_len_mismatch;
+
+ output rx2ap_rx_fsm_wrt; // Receive Fifo Write
+ output [8:0] rx2ap_rx_fsm_dt; // This is 32 bit assembled receive data
+ // with EOP and valid bytes information in it.
+ output rx2ap_commit_write; // This is to RX fifo MGMT to indicate
+ // that the current packet
+ // has to be sent to application
+ output rx2ap_rewind_write; // This indicates the previous packet
+ // in the FIFO has a error
+ // Ignore the packet and restart from the
+ // end of previous packet
+ output clr_rx_error_from_rx_fsm;
+ output commit_write_done;
+
+ input reset_n; // reset from mac application interface
+ input phy_rx_clk; // Reference clock used for RX
+
+ input mi2rx_strt_rcv; // Receive data from the PHY
+ input mi2rx_rcv_vld; // Received nibble is valid
+ input [7:0] mi2rx_rx_byte; // Rx nibble from the RMII/MII block
+ input mi2rx_end_rcv; // This is provided by the RMII/MII
+ // block to indicate
+ // end of receieve
+ input mi2rx_frame_err;
+ input mi2rx_end_frame;
+ input rx_fifo_full;
+ input ap2rx_rx_fifo_err; // Receive error generated by the
+ // RX FIFO MGMT block
+
+ input rc2rx_crc_ok; // CRC of the receiving packet is OK.
+ // Generated by CRC block
+
+ input [15:0] cf2rx_max_pkt_sz; // max packet size
+
+ input cf2rx_rx_ch_en; // Receive Enabled
+ input cf2rx_strp_pad_en; // Do not Append padding after the data
+ input cf2rx_snd_crc; // Append CRC to the data
+ // ( This automatically means padding
+ // will be enabled)
+ input cf2rx_rcv_runt_pkt_en; // Receive needs to receive
+ input cf2rx_gigabit_xfr;
+ input mi2rx_extend;
+
+ //for crs based flow control
+ input phy_crs;
+
+
+ /******* WIRE & REG DECLARATION FOR INPUT AND OUTPUTS ********/
+ reg rx2ap_commit_write;
+ reg rx2ap_rewind_write;
+ reg [8:0] rx2ap_rx_fsm_dt;
+ reg rx2ap_rx_fsm_wrt;
+ wire [31:0] rx_sts_dt;
+ reg [31:0] rx_sts;
+
+ /*** REG & WIRE DECLARATIONS FOR LOCAL SIGNALS ***************/
+ reg commit_write;
+ reg rewind_write;
+ wire look_at_length_field;
+ reg send_crc;
+ reg rcv_pad_data;
+ reg first_dword;
+ wire [15:0] inc_rcv_byte_count;
+ reg [15:0] rcv_byte_count;
+ reg reset_tmp_count;
+ reg ld_length_byte_1,ld_length_byte_2;
+ reg set_crc_error;
+ reg set_byte_allgn_error;
+ reg rx_sts_vld,e_rx_sts_vld;
+ reg padding_needed;
+ reg dec_data_len;
+ reg dec_pad_len;
+ reg gen_eop;
+ reg set_frm_lngth_error;
+ reg set_incomplete_frm;
+ reg byte_boundary;
+ reg error;
+ reg error_seen;
+ reg commit_write_done;
+ reg check_padding;
+ reg check_padding_in;
+ reg [2:0] padding_len_reg;
+ reg [15:0] rcv_length_reg;
+ reg [15:0] length_counter;
+
+ reg [18:0] rx_fsm_cur_st;
+ reg [18:0] rx_fsm_nxt_st;
+ reg crc_stat_reg;
+ reg rx_runt_pkt_reg;
+ reg large_pkt_reg;
+ reg rx_fifo_overrun_reg;
+ reg frm_length_err_reg;
+ reg [2:0] crc_count;
+ reg inc_shift_counter;
+ reg send_data_to_fifo;
+ wire send_runt_packet;
+ reg [2:0] shift_counter;
+ reg [2:0] bytes_to_fifo;
+ reg [7:0] buf_latch4,buf_latch3,buf_latch2,buf_latch1,buf_latch0;
+ wire ld_buf,ld_buf1,ld_buf2,ld_buf3,ld_buf4;
+ reg lengthfield_error;
+ reg lengthfield_err_reg;
+ reg addr_stat_chk;
+ reg clr_rx_error_from_rx_fsm;
+
+ wire [15:0] adj_rcv_length_reg;
+ wire [15:0] adj_rcv_byte_count;
+ wire [15:0] adj_cf2rx_max_pkt_sz;
+ reg set_tag1_flag, set_tag2_flag;
+
+ parameter rx_fsm_idle_st= 19'b0000000000000000000,
+ rx_fsm_chkdestad_nib1_st = 19'b0000000000000000001,
+ rx_fsm_lk4srcad_nib1_st = 19'b0000000000000000010,
+ rx_fsm_lk4len_byte1_st = 19'b0000000000000000100,
+ rx_fsm_lk4len_byte2_st = 19'b0000000000000001000,
+ rx_fsm_getdt_nib1_st = 19'b0000000000000010000,
+ rx_fsm_getpaddt_nib1_st = 19'b0000000000000100000,
+ rx_fsm_updstat_st = 19'b0000000000001000000,
+ rx_fsm_chkval_st = 19'b0000000000010000000,
+ rx_fsm_extend_st = 19'b0000000100000000000;
+
+ /***************** WIRE ASSIGNMENTS *************************/
+ wire [6:0] dec_pad_length;
+ wire [15:0] inc_length_counter;
+ wire rx_overrun_error;
+ wire commit_condition;
+
+//COMMIT_WRITE CONDITION
+assign commit_condition = ((inc_rcv_byte_count[14:0] == 15'd65)&& !commit_write_done );
+
+
+
+ /******** SEQUENTIAL LOGIC **********************************/
+ half_dup_dble_reg U_dble_reg1 (
+ //outputs
+ .sync_out_pulse(rx_ch_en),
+ //inputs
+ .in_pulse(cf2rx_rx_ch_en),
+ .dest_clk(phy_rx_clk),
+ .reset_n(reset_n)
+ );
+
+ // ap2rx_rx_fifo_err signal is generated in rx_clk domain
+ assign rx_overrun_error = ap2rx_rx_fifo_err;
+
+ reg rx_sts_vld_delayed;
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ begin
+ if(!reset_n)
+ begin
+ rx_sts <= 32'b0;
+ rx_sts_vld <= 1'b0;
+ rx_sts_vld_delayed <= 1'b0;
+ end
+ else
+ begin
+ rx_sts_vld <= rx_sts_vld_delayed;
+ rx_sts_vld_delayed <= e_rx_sts_vld;
+ if (e_rx_sts_vld)
+ rx_sts <= rx_sts_dt;
+ end
+ end
+
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ begin
+ if(!reset_n)
+ begin
+ rx_fsm_cur_st <= rx_fsm_idle_st;
+ check_padding <= 1'b0;
+ end
+ else
+ begin
+ rx_fsm_cur_st <= rx_fsm_nxt_st;
+ check_padding <= check_padding_in;
+ end
+ end
+ reg first_byte_seen;
+
+
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ if(!reset_n)
+ first_byte_seen <= 1'b0;
+ else if(mi2rx_strt_rcv)
+ first_byte_seen <= 1'b1;
+ else if(mi2rx_rcv_vld)
+ first_byte_seen <= 1'b0;
+
+
+
+// adjust rcv_length reg for packet sizes < 64 bytes
+assign adj_rcv_length_reg = (rcv_length_reg < 8'h2E) ? 8'h2E : rcv_length_reg;
+
+// subtr 18 bytes (sa + da + fcs + t/l)
+assign adj_rcv_byte_count = rcv_byte_count - 8'd18;
+
+// configured max packet size should be 16'd1518.
+assign adj_cf2rx_max_pkt_sz = cf2rx_max_pkt_sz;
+
+
+
+ // Following state machine is to receive nibbles from the RMII/MII
+ // block and packetize them to 32 bits with information of EOP and
+ // valid bytes. It also discards packets which are less than minimum
+ // frame size. It performs Address validity and Data validity.
+ always @(rx_fsm_cur_st or mi2rx_strt_rcv or rx_ch_en or cf2rx_strp_pad_en
+ or cf2rx_snd_crc or look_at_length_field
+ or mi2rx_rcv_vld or first_dword or rc2rx_crc_ok
+ or mi2rx_end_rcv or mi2rx_rx_byte or mi2rx_extend
+ or inc_length_counter or rcv_length_reg or commit_write_done
+ or crc_count or shift_counter or bytes_to_fifo
+ or cf2rx_rcv_runt_pkt_en
+ or inc_rcv_byte_count or send_runt_packet
+ or rcv_byte_count or first_dword
+ or commit_condition or rx_fifo_full or ap2rx_rx_fifo_err )
+ begin
+ rx_fsm_nxt_st = rx_fsm_cur_st;
+ set_tag1_flag = 1'b0;
+ set_tag2_flag = 1'b0;
+ reset_tmp_count = 1'b0;
+ ld_length_byte_1 = 1'b0;
+ ld_length_byte_2 = 1'b0;
+ dec_data_len = 1'b0;
+ dec_pad_len = 1'b0;
+ commit_write = 1'b0;
+ rewind_write = 1'b0;
+ e_rx_sts_vld = 1'b0;
+ set_crc_error = 1'b0;
+ check_padding_in = 1'b0;
+ set_byte_allgn_error = 1'b0;
+ set_incomplete_frm = 1'b0;
+ set_frm_lngth_error = 1'b0;
+ gen_eop = 1'b0;
+ error = 1'b0;
+ byte_boundary= 1'b0;
+ send_crc = 1'b0;
+ rcv_pad_data = 1'b0;
+ inc_shift_counter = 1'b0;
+ send_data_to_fifo = 1'b0;
+ lengthfield_error = 1'b0;
+ addr_stat_chk = 1'b0;
+ clr_rx_error_from_rx_fsm = 1'b0;
+
+
+ case(rx_fsm_cur_st)
+ rx_fsm_idle_st:
+ // Waiting for packet from mii block
+ // Continues accepting data only if
+ // receive has been enabled
+ begin
+ if(ap2rx_rx_fifo_err)
+ begin
+ clr_rx_error_from_rx_fsm = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end
+ else if (rx_fifo_full)
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ else if(mi2rx_strt_rcv && rx_ch_en )
+ rx_fsm_nxt_st = rx_fsm_chkdestad_nib1_st;
+ else
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end
+
+ rx_fsm_chkdestad_nib1_st:
+ begin
+ // collecting the nibbles of destination
+ // address
+ if(ap2rx_rx_fifo_err)
+ begin
+ rewind_write = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end
+ else if(mi2rx_end_rcv)
+ begin
+ if(cf2rx_rcv_runt_pkt_en)
+ begin
+ rx_fsm_nxt_st = rx_fsm_chkval_st;
+ commit_write = 1'b1;
+ end
+ else
+ begin
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ if (rcv_byte_count[2:0] > 5)
+ rewind_write = 1'b1;
+ end
+ end // if (mi2rx_end_rcv)
+
+ else if(mi2rx_rcv_vld && inc_rcv_byte_count[14:0] == 15'd6)
+ begin
+ rx_fsm_nxt_st = rx_fsm_lk4srcad_nib1_st;
+ end
+ else
+ begin
+ rx_fsm_nxt_st = rx_fsm_chkdestad_nib1_st;
+ end
+ end
+
+ rx_fsm_lk4srcad_nib1_st:
+ // collecting nibbles of source address
+ // in case of termination of packet
+ // or carrier sense error then generate eop
+ // and generate status
+ begin
+ if(ap2rx_rx_fifo_err )
+ begin
+ rewind_write = 1;
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end // else: !if(mi2rx_end_rcv)
+ else if(mi2rx_end_rcv)
+ begin
+ if(cf2rx_rcv_runt_pkt_en)
+ begin
+ rx_fsm_nxt_st = rx_fsm_chkval_st;
+ commit_write = 1'b1;
+ end
+ else
+ begin
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ rewind_write = 1'b1;
+ end
+ end
+ else if(mi2rx_rcv_vld && inc_rcv_byte_count[14:0] == 15'd12)
+ begin
+ rx_fsm_nxt_st = rx_fsm_lk4len_byte1_st;
+ end
+ else
+ begin
+ rx_fsm_nxt_st = rx_fsm_lk4srcad_nib1_st;
+ end
+ end
+
+ rx_fsm_lk4len_byte1_st:
+ // this state collects the odd nibbles of the length
+ // field.
+ begin
+ if(ap2rx_rx_fifo_err)
+ begin
+ rewind_write = 1;
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end // else: !if(mi2rx_end_rcv)
+ else if(mi2rx_end_rcv)
+ begin
+ if(cf2rx_rcv_runt_pkt_en)
+ begin
+ rx_fsm_nxt_st = rx_fsm_chkval_st;
+ commit_write = 1'b1;
+ end
+ else
+ begin
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ rewind_write = 1'b1;
+ end
+ end
+ else if(mi2rx_rcv_vld)
+ begin
+ ld_length_byte_1 = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_lk4len_byte2_st;
+ end
+ else
+ rx_fsm_nxt_st = rx_fsm_lk4len_byte1_st;
+ end
+
+ rx_fsm_lk4len_byte2_st:
+ // This state generates the even nibbles of the length
+ // field
+ begin
+ if(ap2rx_rx_fifo_err )
+ begin
+ rewind_write = 1;
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end // else: !if(mi2rx_end_rcv)
+ else if(mi2rx_end_rcv)
+ begin
+ if(cf2rx_rcv_runt_pkt_en)
+ begin
+ rx_fsm_nxt_st = rx_fsm_chkval_st;
+ commit_write = 1'b1;
+ end
+ else
+ begin
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ rewind_write = 1'b1;
+ end
+ end
+ else if(mi2rx_rcv_vld )
+ begin
+ ld_length_byte_2 = 1'b1;
+ check_padding_in = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_getdt_nib1_st;
+ end
+ else
+ rx_fsm_nxt_st = rx_fsm_lk4len_byte2_st;
+ end // rx_fsm_lk4len_byte2_st
+
+ rx_fsm_getdt_nib1_st: //state number 7
+ // This state collects the nibbles of the receive data
+ // This state makes a determination to remove padding
+ // only if strip padding is enabled and the length field
+ // detected is less than 64
+ begin
+ if (commit_condition)
+ commit_write = 1'b1;
+
+ if((ap2rx_rx_fifo_err) && !commit_write_done)
+ begin
+ rewind_write = 1;
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end // else: !if(mi2rx_end_rcv)
+ else if (ap2rx_rx_fifo_err)
+ begin
+ rx_fsm_nxt_st = rx_fsm_updstat_st;
+ end
+ else if(mi2rx_end_rcv)
+ begin
+ if(cf2rx_rcv_runt_pkt_en && !(commit_write_done | commit_condition))
+ begin
+ commit_write = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_chkval_st;
+ end
+ else if(!(commit_write_done | commit_condition) && !cf2rx_rcv_runt_pkt_en)
+ begin
+ rewind_write = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end
+ else
+ rx_fsm_nxt_st = rx_fsm_chkval_st;
+ end
+ else if(mi2rx_rcv_vld && (inc_length_counter == rcv_length_reg) &&
+ look_at_length_field)
+ begin
+ dec_data_len = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_getpaddt_nib1_st;
+ end
+ else if(mi2rx_rcv_vld && look_at_length_field)
+ begin
+ dec_data_len = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_getdt_nib1_st;
+ end
+ else
+ rx_fsm_nxt_st = rx_fsm_getdt_nib1_st;
+ end
+
+ rx_fsm_getpaddt_nib1_st:
+ // This state handles the padded data in case of less than 64
+ // byte packets This handles the odd nibbles
+ begin
+ if(ap2rx_rx_fifo_err)
+ begin
+ if(rcv_byte_count[14:0] <= 15'd64) // mfilardo
+ //if(inc_rcv_byte_count[14:0] <= 15'd64)
+ begin
+ rewind_write = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end
+ else
+ rx_fsm_nxt_st = rx_fsm_updstat_st;
+ end
+ else if(mi2rx_end_rcv)
+ begin
+ //if(inc_rcv_byte_count[14:0] == 15'd64)
+ if(rcv_byte_count[14:0] == 15'd64) // mfilardo
+ lengthfield_error = 0;
+ else
+ lengthfield_error = 1;
+
+ rx_fsm_nxt_st = rx_fsm_extend_st;
+ end
+ else if(mi2rx_rcv_vld)
+ begin
+ if(cf2rx_strp_pad_en)
+ rcv_pad_data = 1'b1;
+ end
+ else
+ rx_fsm_nxt_st = rx_fsm_getpaddt_nib1_st;
+ end // case: rx_fsm_getpaddt_nib1_st
+
+
+ rx_fsm_extend_st:
+ //This state handles the first extend conditon in the
+ //cf2rx_gigabit_xfr
+ //transfer
+ begin
+ if (mi2rx_extend)
+ begin
+ rx_fsm_nxt_st = rx_fsm_extend_st;
+ end
+ else
+ begin
+ commit_write = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_chkval_st;
+ end
+ end
+ rx_fsm_chkval_st:
+ // This packet generates the validity of the packet
+ // This is reached either on clean or error type
+ // completion of packet.
+ begin
+ if(ap2rx_rx_fifo_err)
+ begin
+ rx_fsm_nxt_st = rx_fsm_updstat_st;
+ end
+ else if(cf2rx_rcv_runt_pkt_en && first_dword)
+ begin
+ rx_fsm_nxt_st = rx_fsm_chkval_st;
+ case(rcv_byte_count[2:0])
+ 3'd1:
+ begin
+ if(shift_counter == 3'd4)
+ begin
+ if(bytes_to_fifo == rcv_byte_count[2:0])
+ begin
+ gen_eop = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_updstat_st;
+ end // if (bytes_to_fifo == rcv_nibble_count[3:1])
+ else
+ send_data_to_fifo = 1'b1;
+ end // if (shift_counter == 3'd4)
+ else
+ inc_shift_counter = 1;
+ end // case: 3'd1
+
+ 3'd2:
+ begin
+ if(shift_counter == 3'd3)
+ begin
+ if(bytes_to_fifo == rcv_byte_count[2:0])
+ begin
+ gen_eop = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_updstat_st;
+ end // if (bytes_to_fifo == rcv_nibble_count[3:1])
+ else
+ send_data_to_fifo = 1'b1;
+ end // if (shift_counter == 3'd3)
+ else
+ inc_shift_counter = 1;
+ end // case: 3'd2
+
+ 3'd3:
+ begin
+ if(shift_counter == 3'd2)
+ begin
+ if(bytes_to_fifo == rcv_byte_count[2:0])
+ begin
+ gen_eop = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_updstat_st;
+ end
+ else
+ send_data_to_fifo = 1'b1;
+ end // if (shift_counter == 3'd2)
+ else
+ inc_shift_counter = 1;
+ end // case: 3'd3
+
+ 3'd4:
+ begin
+ if(shift_counter == 3'd1)
+ begin
+ if(bytes_to_fifo == rcv_byte_count[2:0])
+ begin
+ gen_eop = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_updstat_st;
+ end // if (bytes_to_fifo == rcv_nibble_count[3:1])
+ else
+ send_data_to_fifo = 1'b1;
+ end
+ else
+ inc_shift_counter = 1;
+ end // case: 3'd4
+ default:
+ begin
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ gen_eop = 1'b0;
+ end
+ endcase // case(rcv_nibble_count[3
+ end // if (cf2rx_rcv_runt_pkt_en && first_dword)
+ else if(((cf2rx_snd_crc || send_runt_packet || look_at_length_field)
+ && crc_count == 3'd4))
+ begin
+ gen_eop = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_updstat_st;
+ end
+ else if(send_runt_packet || look_at_length_field)
+ begin
+ send_crc = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_chkval_st;
+ end
+ else if(!cf2rx_snd_crc)
+ begin
+ gen_eop = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_updstat_st;
+ end
+ else
+ begin
+ send_crc = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_chkval_st;
+ end
+ end // case: rx_fsm_chkval_st
+
+ rx_fsm_updstat_st:
+ // This state updates the status to the application
+ // This allows the application to determine the validity
+ // of the packet so that it can take the necessary action
+ begin
+ e_rx_sts_vld = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end
+
+ default:
+ begin
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end
+ endcase // casex(rx_fsm_cur_st)
+ end // always @ (rx_fsm_cur_st or mi2rx_strt_rcv or rx_ch_en or cf2rx_strp_pad_en...
+
+ always @(inc_rcv_byte_count)
+ begin
+ if(inc_rcv_byte_count[14:0] < 15'd6)
+ first_dword = 1'b1;
+ else
+ first_dword = 1'b0;
+ end // always @ (inc_rcv_nibble_count or...
+
+
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ begin
+ if(!reset_n)
+ crc_count <= 3'b000;
+ else if(mi2rx_strt_rcv)
+ crc_count <= 3'b000;
+ else if(send_crc)
+ crc_count <= crc_count + 1;
+ end // always @ (posedge phy_rx_clk...
+
+ // These signals are used as intermediate flags to determine
+ // whether to commit pointer or not to commit pointers
+ // to the application
+ // error_seen helps in tracking errors which could occurs in between
+ // packet transfer
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ begin
+ if(!reset_n)
+ begin
+ commit_write_done <= 1'b1;
+ error_seen <= 1'b0;
+ end
+ else if(mi2rx_strt_rcv)
+ begin
+ commit_write_done <= 1'b0;
+ error_seen <= 1'b0;
+ end
+ else
+ begin
+ if(commit_write)
+ commit_write_done <= 1'b1;
+ if(error)
+ error_seen <= 1'b1;
+ end
+ end // always @ (posedge phy_rx_clk...
+
+ assign look_at_length_field = cf2rx_strp_pad_en &&
+ (rcv_length_reg < MIN_FRM_SIZE) && (|rcv_length_reg);
+ assign send_runt_packet = cf2rx_rcv_runt_pkt_en &&
+ (rcv_byte_count[15:8] == 8'd0 && rcv_byte_count[7:0] < 8'd64);
+
+
+
+
+ assign inc_rcv_byte_count = rcv_byte_count + 16'h1;
+
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ begin
+ if(!reset_n)
+ rcv_byte_count <= 16'h0000;
+ else if(mi2rx_strt_rcv)
+ rcv_byte_count <= 16'h0000;
+ else if(mi2rx_rcv_vld)
+ rcv_byte_count <= inc_rcv_byte_count;
+ end // always @ (posedge phy_rx_clk...
+
+ // This signal is asserted wheneven there is no valid transfer on the
+ // line. Valid transfer is only between mi2rx_strt_rcv and
+ // mi2rx_end_rcv. In case
+ // of rewind write transfer becomes invalid. Such data should not be
+ // written in to the fifo
+ reg dt_xfr_invalid;
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ begin
+ if(!reset_n)
+ dt_xfr_invalid <= 1;
+ else if(rewind_write || ap2rx_rx_fifo_err)
+ dt_xfr_invalid <= 1;
+ else if(mi2rx_strt_rcv)
+ dt_xfr_invalid <= 0;
+ end
+ // This is the mux to gather nibbles to two octets for the length field
+ // of the register
+ assign inc_length_counter = length_counter + 16'h1;
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ begin
+ if(!reset_n)
+ begin
+ rcv_length_reg <= 16'b0;
+ length_counter <= 16'b0;
+ end // if (reset_n)
+ else if (rx_ch_en)
+ begin
+ if(mi2rx_strt_rcv)
+ begin
+ length_counter <= 16'b0;
+ rcv_length_reg <= 16'b0;
+ end
+ else if(dec_data_len )
+ length_counter <= inc_length_counter;
+ else
+ begin
+ if(ld_length_byte_1)
+ begin
+ rcv_length_reg[15:8] <= mi2rx_rx_byte;
+ end
+ else if(ld_length_byte_2)
+ begin
+ rcv_length_reg[7:0] <= mi2rx_rx_byte;
+ end
+ end // else: !if(dec_data_len)
+ end // else: !if(!reset_n)
+ end // always @ (posedge phy_rx_clk...
+
+ // This signal helps in making sure that when packets are received the
+ // channel is enabled else ignore the complete packet until next start
+ // of packet
+ reg enable_channel;
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ begin
+ if(!reset_n)
+ enable_channel <= 0;
+ else if(gen_eop)
+ enable_channel <= 0;
+ else if(mi2rx_strt_rcv && rx_ch_en)
+ enable_channel <= 1;
+ end
+
+ // This is the decremented padding length register
+ // Once it reaches zero CRC should follow
+ assign dec_pad_length = padding_len_reg - 7'h1;
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ begin
+ if(!reset_n)
+ begin
+ padding_needed <= 1'b0;
+ padding_len_reg <= 6'b0;
+ end
+ else if(mi2rx_strt_rcv)
+ begin
+ padding_needed <= 1'b0;
+ padding_len_reg <= 6'b0;
+ end
+ else if(look_at_length_field &&
+ check_padding)
+ begin
+ padding_len_reg <= MIN_FRM_SIZE - rcv_length_reg[5:0];
+ padding_needed <= 1'b1;
+ end
+ else if(dec_pad_len)
+ begin
+ padding_len_reg <= dec_pad_len;
+ padding_needed <= padding_needed;
+ end
+ end // always @ (posedge phy_rx_clk...
+
+ /*********************************************************
+ Status Generation for Receive packets
+ Statuses in this case are checked at end of receive packets
+ and are registered and provided inthe next state along with
+ rx_sts_valid bit asserted
+ *********************************************************/
+
+ reg[14:0] fifo_byte_count;
+ wire [14:0] inc_fifo_byte_count;
+ wire [14:0] dec_fifo_byte_count;
+ assign inc_fifo_byte_count = fifo_byte_count + 15'h1;
+ assign dec_fifo_byte_count = fifo_byte_count - 15'h1;
+
+ always @(posedge phy_rx_clk or negedge reset_n)
+ begin
+ if(!reset_n)
+ fifo_byte_count <= 15'd0;
+ else if(rewind_write || mi2rx_strt_rcv)
+ fifo_byte_count <= 15'd0;
+ else if(rx2ap_rx_fsm_wrt)
+ fifo_byte_count <= inc_fifo_byte_count;
+ end
+
+ reg length_sz_mismatch;
+
+ assign rx_sts_dt[31:16] = (e_rx_sts_vld && ap2rx_rx_fifo_err) ?
+ {dec_fifo_byte_count + 16'h1} : {fifo_byte_count + 16'h1};
+ assign rx_sts_dt[15:13] = 3'd0;
+ assign rx_sts_dt[12] = length_sz_mismatch;
+ assign rx_sts_dt[11] = 1'b0;
+ assign rx_sts_dt[10] = large_pkt_reg;
+ assign rx_sts_dt[7] = lengthfield_err_reg;
+ assign rx_sts_dt[6] = crc_stat_reg;
+ assign rx_sts_dt[5] = rx_runt_pkt_reg;
+ assign rx_sts_dt[4] = rx_fifo_overrun_reg;
+ assign rx_sts_dt[2] = frm_length_err_reg;
+ assign rx_sts_dt[1:0] = 2'd0;
+
+ wire rx_sts_large_pkt;
+ wire [15:0] rx_sts_bytes_rcvd;
+ wire rx_sts_lengthfield_err;
+ wire rx_sts_crc_err;
+ wire rx_sts_runt_pkt_rcvd;
+ wire rx_sts_rx_overrun;
+ wire rx_sts_frm_length_err;
+ wire rx_sts_len_mismatch;
+
+ assign rx_sts_bytes_rcvd = rx_sts[31:16];
+ assign rx_sts_len_mismatch = rx_sts[12];
+ assign rx_sts_large_pkt = rx_sts[10];
+ assign rx_sts_lengthfield_err = rx_sts[7];
+ assign rx_sts_crc_err = rx_sts[6];
+ assign rx_sts_runt_pkt_rcvd = rx_sts[5];
+ assign rx_sts_rx_overrun = rx_sts[4];
+ assign rx_sts_frm_length_err = rx_sts[2];
+
+
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ begin
+ if(!reset_n)
+ begin
+ crc_stat_reg <= 1'b0;
+ frm_length_err_reg <= 1'b0;
+ lengthfield_err_reg <= 1'b0;
+ rx_fifo_overrun_reg <= 1'b0;
+ rx_runt_pkt_reg <= 1'b0;
+ large_pkt_reg <= 1'b0;
+ length_sz_mismatch <= 1'b0;
+ end
+ else if(mi2rx_strt_rcv)
+ begin
+ crc_stat_reg <= 1'b0;
+ frm_length_err_reg <= 1'b0;
+ lengthfield_err_reg <= 1'b0;
+ rx_fifo_overrun_reg <= 1'b0;
+ rx_runt_pkt_reg <= 1'b0;
+ large_pkt_reg <= 1'b0;
+ length_sz_mismatch <= 1'b0;
+ end
+ else
+ begin
+ if(rx_overrun_error)
+ rx_fifo_overrun_reg <= 1'b1;
+
+ if(lengthfield_error)
+ lengthfield_err_reg <= 1'b1;
+
+ if(mi2rx_end_rcv && mi2rx_frame_err)
+ frm_length_err_reg <= 1'b1;
+
+ if(mi2rx_end_rcv)
+ begin
+ if(!rc2rx_crc_ok)
+ crc_stat_reg <= 1'b1;
+ if(rcv_byte_count[14:0] < 15'd64)
+ rx_runt_pkt_reg <= 1'b1;
+ if(rcv_byte_count[14:0] > adj_cf2rx_max_pkt_sz)
+ large_pkt_reg <= 1'b1;
+ if( (adj_rcv_byte_count[15:0] != adj_rcv_length_reg) && (adj_rcv_length_reg <= 16'd1500) )
+ length_sz_mismatch <= 1'b1;
+ end // if (mi2rx_end_rcv)
+ end // else: !if(mi2rx_strt_rcv)
+ end // always @ (posedge phy_rx_clk...
+
+ /***************************************************/
+ //
+ // Additions for Byte operation
+ //
+ /***************************************************/
+ always @(posedge phy_rx_clk or
+ negedge reset_n)
+ begin
+ if(!reset_n)
+ shift_counter <= 3'd0;
+ else if(mi2rx_strt_rcv)
+ shift_counter <= 3'd0;
+ else if(inc_shift_counter)
+ shift_counter <= shift_counter + 1;
+ end // always @ (posedge phy_rx_clk or...
+
+ always @(posedge phy_rx_clk or
+ negedge reset_n)
+ begin
+ if(!reset_n)
+ bytes_to_fifo <= 3'd0;
+ else if(mi2rx_strt_rcv)
+ bytes_to_fifo <= 3'd1;
+ else if(send_data_to_fifo)
+ bytes_to_fifo <= bytes_to_fifo + 1;
+ end // always @ (posedge phy_rx_clk or...
+
+ wire[8:0] e_rx_fsm_dt;
+ wire e_rx_fsm_wrt;
+ assign e_rx_fsm_dt[7:0] = buf_latch4;
+// assign e_rx_fsm_dt[8] = (rx_fifo_full) ? 1'b1 :gen_eop;
+ assign e_rx_fsm_dt[8] = gen_eop;
+
+ always @(posedge phy_rx_clk or
+ negedge reset_n)
+ begin
+ if(!reset_n)
+ begin
+ rx2ap_rx_fsm_dt <= 9'd0;
+ rx2ap_rx_fsm_wrt <= 1'b0;
+ rx2ap_commit_write <= 1'b0;
+ rx2ap_rewind_write <= 1'b0;
+ end
+ else
+ begin
+ rx2ap_rx_fsm_wrt <= e_rx_fsm_wrt && (!ap2rx_rx_fifo_err);
+ rx2ap_rx_fsm_dt <= e_rx_fsm_dt;
+ rx2ap_commit_write <= commit_write;
+ rx2ap_rewind_write <= rewind_write;
+ end
+ end // always @ (posedge phy_rx_clk or...
+
+ assign e_rx_fsm_wrt = ((enable_channel &&
+ mi2rx_rcv_vld && !first_dword) ||
+ (enable_channel &&
+ (gen_eop || send_crc)) ||
+ (enable_channel && send_data_to_fifo)) && !rcv_pad_data
+ && !dt_xfr_invalid && !rewind_write;
+ assign ld_buf = enable_channel && !rcv_pad_data && (|rcv_byte_count == 1) &&
+ (mi2rx_rcv_vld) || send_crc || inc_shift_counter || send_data_to_fifo;
+
+ assign ld_buf4 = ld_buf ;
+ assign ld_buf3 = ld_buf ;
+ assign ld_buf2 = ld_buf ;
+ assign ld_buf1 = ld_buf ;
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ begin
+ if(!reset_n)
+ begin
+ buf_latch4 <= 8'b0;
+ buf_latch3 <= 8'b0;
+ buf_latch2 <= 8'b0;
+ buf_latch1 <= 8'b0;
+ buf_latch0 <= 8'b0;
+ end
+ else
+ begin
+ if(ld_buf4)
+ buf_latch4 <= buf_latch3;
+
+ if(ld_buf3)
+ buf_latch3 <= buf_latch2;
+
+ if(ld_buf2)
+ buf_latch2 <= buf_latch1;
+
+ if(ld_buf1)
+ buf_latch1 <= buf_latch0;
+
+ if (rx_ch_en)
+ begin
+ if(mi2rx_strt_rcv)
+ begin
+ buf_latch0 <= 8'b0;
+ end
+ else
+ begin
+ if(mi2rx_rcv_vld && !rcv_pad_data)
+ begin
+ buf_latch0 <= mi2rx_rx_byte;
+ end
+ end // else: !if(mi2rx_strt_rcv)
+ end // if (rx_ch_en)
+ end // else: !if(!reset_n)
+ end // always @ (posedge phy_rx_clk...
+
+endmodule
diff --git a/verilog/rtl/gmac/mac/g_rx_top.v b/verilog/rtl/gmac/mac/g_rx_top.v
new file mode 100755
index 0000000..5f36379
--- /dev/null
+++ b/verilog/rtl/gmac/mac/g_rx_top.v
@@ -0,0 +1,208 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Mar 2, 2011 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+ module g_rx_top(
+ app_reset_n,
+ phy_rx_clk,
+ rx_reset_n,
+ app_clk,
+ scan_mode,
+ rx_sts_vld,
+ rx_sts_bytes_rcvd,
+ rx_sts_large_pkt,
+ rx_sts_lengthfield_err,
+ rx_sts_len_mismatch,
+ rx_sts_crc_err,
+ rx_sts_runt_pkt_rcvd,
+ rx_sts_rx_overrun,
+ rx_sts_frm_length_err,
+ clr_rx_error_from_rx_fsm,
+ rx_fifo_full,
+ rx_dt_wrt,
+ rx_dt_out,
+ rx_commit_wr,
+ commit_write_done,
+ rx_rewind_wr,
+ mi2rx_strt_rcv,
+ mi2rx_rcv_vld,
+ mi2rx_rx_byte,
+ mi2rx_end_rcv,
+ mi2rx_extend,
+ mi2rx_frame_err,
+ mi2rx_end_frame,
+ phy_rx_dv,
+ cf2rx_max_pkt_sz,
+ cf2rx_rx_ch_en,
+ cf2rx_strp_pad_en,
+ cf2rx_snd_crc,
+ cf2df_dfl_single_rx,
+ cf2rx_rcv_runt_pkt_en,
+ cf_macmode,
+ mi2rx_crs,
+ df2rx_dfl_dn,
+ ap2rx_rx_fifo_err,
+ //for crs based flow control
+ phy_crs
+ );
+
+ input app_reset_n;
+ input phy_rx_clk;
+ input rx_reset_n;
+ input app_clk;
+ input scan_mode;
+
+ output rx_sts_vld;
+ output [15:0] rx_sts_bytes_rcvd;
+ output rx_sts_large_pkt;
+ output rx_sts_lengthfield_err;
+ output rx_sts_len_mismatch;
+ output rx_sts_crc_err;
+ output rx_sts_runt_pkt_rcvd;
+ output rx_sts_rx_overrun;
+ output rx_sts_frm_length_err;
+
+ output clr_rx_error_from_rx_fsm;
+ input rx_fifo_full;
+ output rx_dt_wrt;
+ output [8:0] rx_dt_out;
+ output rx_commit_wr;
+ output commit_write_done;
+ output rx_rewind_wr;
+ input mi2rx_strt_rcv;
+ input mi2rx_rcv_vld;
+ input [7:0] mi2rx_rx_byte;
+ input mi2rx_end_rcv;
+ input mi2rx_extend;
+ input mi2rx_frame_err;
+ input mi2rx_end_frame;
+ input phy_rx_dv;
+ input [15:0] cf2rx_max_pkt_sz;
+ input cf2rx_rx_ch_en;
+ input cf2rx_strp_pad_en;
+ input cf2rx_snd_crc;
+ input cf2rx_rcv_runt_pkt_en;
+ input cf_macmode;
+ input [7:0] cf2df_dfl_single_rx;
+ input ap2rx_rx_fifo_err;
+ input mi2rx_crs;
+ output df2rx_dfl_dn;
+
+ //for crs based flow control
+ input phy_crs;
+
+
+
+ g_rx_fsm u_rx_fsm(
+ // Status information to Applications
+ .rx_sts_vld(rx_sts_vld),
+ .rx_sts_bytes_rcvd(rx_sts_bytes_rcvd),
+ .rx_sts_large_pkt(rx_sts_large_pkt),
+ .rx_sts_lengthfield_err(rx_sts_lengthfield_err),
+ .rx_sts_len_mismatch(rx_sts_len_mismatch),
+ .rx_sts_crc_err(rx_sts_crc_err),
+ .rx_sts_runt_pkt_rcvd(rx_sts_runt_pkt_rcvd),
+ .rx_sts_rx_overrun(rx_sts_rx_overrun),
+ .rx_sts_frm_length_err(rx_sts_frm_length_err),
+ // Data Signals to Fifo Management Block
+ .clr_rx_error_from_rx_fsm(clr_rx_error_from_rx_fsm),
+ .rx2ap_rx_fsm_wrt(rx_dt_wrt),
+ .rx2ap_rx_fsm_dt(rx_dt_out),
+ // Fifo Control Signal to Fifo Management Block
+ .rx2ap_commit_write(rx_commit_wr),
+ .rx2ap_rewind_write(rx_rewind_wr),
+ // To address filtering block
+ .commit_write_done(commit_write_done),
+
+ // Global Signals
+ .reset_n(rx_reset_n),
+ .phy_rx_clk(phy_rx_clk),
+ // Signals from Mii/Rmii block for Receive data
+ .mi2rx_strt_rcv(mi2rx_strt_rcv),
+ .mi2rx_rcv_vld(mi2rx_rcv_vld),
+ .mi2rx_rx_byte(mi2rx_rx_byte),
+ .mi2rx_end_rcv(mi2rx_end_rcv),
+ .mi2rx_extend(mi2rx_extend),
+ .mi2rx_end_frame(mi2rx_end_frame),
+ .mi2rx_frame_err(mi2rx_frame_err),
+ // Rx fifo management signal to indicate overrun
+ .rx_fifo_full(rx_fifo_full),
+ .ap2rx_rx_fifo_err(ap2rx_rx_fifo_err),
+ // Signal from CRC check block
+ .rc2rx_crc_ok(rc2rx_crc_ok),
+ // Signals from Address filtering block
+ // Signals from Config Management Block
+ .cf2rx_max_pkt_sz(cf2rx_max_pkt_sz),
+ .cf2rx_rx_ch_en(cf2rx_rx_ch_en),
+ .cf2rx_strp_pad_en(cf2rx_strp_pad_en),
+ .cf2rx_snd_crc(cf2rx_snd_crc),
+ .cf2rx_rcv_runt_pkt_en(cf2rx_rcv_runt_pkt_en),
+ .cf2rx_gigabit_xfr(cf_macmode),
+ //for crs based flow control
+ .phy_crs(phy_crs)
+ );
+
+
+ g_rx_crc32 u_rx_crc32 (
+ // CRC Valid signal to rx_fsm
+ .rc2rf_crc_ok(rc2rx_crc_ok),
+
+ // Global Signals
+ .phy_rx_clk(phy_rx_clk),
+ .reset_n(rx_reset_n),
+ // CRC Data signals
+ .mi2rc_strt_rcv(mi2rx_strt_rcv),
+ .mi2rc_rcv_valid(mi2rx_rcv_vld),
+ .mi2rc_rx_byte(mi2rx_rx_byte)
+ );
+
+
+ g_deferral_rx U_deferral_rx (
+ .rx_dfl_dn(df2rx_dfl_dn),
+ .dfl_single(cf2df_dfl_single_rx),
+ .rx_dv(phy_rx_dv),
+ .rx_clk(phy_rx_clk),
+ .reset_n(rx_reset_n));
+
+ endmodule
diff --git a/verilog/rtl/gmac/mac/g_tx_fsm.v b/verilog/rtl/gmac/mac/g_tx_fsm.v
new file mode 100755
index 0000000..c28a2e6
--- /dev/null
+++ b/verilog/rtl/gmac/mac/g_tx_fsm.v
@@ -0,0 +1,775 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Mar 2, 2011 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+/***************************************************************
+ Description:
+
+ tx_fsm.v: Frames are queued in TX FIFO, when the TX FIFO has enough
+ data to sustain a 100Mb or 10 Mb transfer on the TX transmit is enabled.
+ Each dword has 3 extra bits, which indicate the end of the frame and
+ the number of valid bytes in the current dword.
+
+ ***********************************************************************/
+
+
+module g_tx_fsm (
+ //Outputs
+ //FIFO
+ tx_commit_read,
+ tx_dt_rd,
+
+ //FCS
+ tx2tc_fcs_active,
+ tx2tc_gen_crc,
+
+ //MII interface
+ tx2mi_strt_preamble,
+ tx2mi_byte_valid,
+ tx2mi_byte,
+ tx2mi_end_transmit,
+ phy_tx_en,
+ tx_ch_en,
+
+ //Application
+ tx_sts_vld,
+ tx_sts_byte_cntr,
+ tx_sts_fifo_underrun,
+
+ //Inputs
+ //FIFO
+ app_tx_rdy,
+ tx_end_frame,
+ app_tx_dt_in,
+ app_tx_fifo_empty,
+
+ //dfl and back
+ df2tx_dfl_dn,
+
+ //FCS
+ tc2tx_fcs,
+
+ //Configuration
+ cf2tx_ch_en,
+ cf2tx_pad_enable,
+ cf2tx_append_fcs,
+ cf_mac_mode,
+ cf_mac_sa,
+ cf2tx_force_bad_fcs,
+
+ app_clk,
+ set_fifo_undrn,
+
+ //MII interface
+ mi2tx_byte_ack,
+ tx_clk,
+ tx_reset_n,
+ app_reset_n);
+
+
+parameter CORE_MIN_FRAME_SIZE = 16'h40; //64 bytes =>
+// (12(add)+2(len)+46(pay) + 4CRC)*2
+parameter CORE_MIN_FRAME_COL_SIZE = 16'h40; //63 bytes =>
+// tx_fsm lags MII by one byte
+parameter CORE_PAYLOAD_SIZE = 16'h3C ; //60 bytes =>
+// (12(add)+2(len)+46(pay))*2
+
+
+ input cf2tx_ch_en; //transmit enable application clock
+ input app_tx_rdy; //tx fifo management, enough buffer to tx
+ input tx_end_frame; //Current DWORD marks end of frame
+ input [7:0] app_tx_dt_in; //double word data from the TX fifo mgmt
+ input app_tx_fifo_empty; //TX fifo is empty, if there were a data
+ //data request when app_tx_fifo_empty is asserted
+ //would result in FIFO underrun and error cond
+ input [31:0] tc2tx_fcs;
+
+ //defferral inputs
+ input df2tx_dfl_dn; //IPG time between frames is satisfied
+
+ //configuration inputs
+ input cf2tx_pad_enable; //pad the TX frame if they are small
+ input cf2tx_append_fcs; //on every TX, compute and append FCS, when
+ //cf2tx_pad_enable and the current frame is small
+ //FCS is computed and appended to the frame
+ //irrespective of this signal
+ input cf_mac_mode; // 1 is GMII 0 10/100
+ input [47:0] cf_mac_sa;
+ input cf2tx_force_bad_fcs;
+ input mi2tx_byte_ack; //MII interface accepted last byte
+ input tx_clk;
+ input tx_reset_n;
+ input app_reset_n;
+
+ //tx fifo management outputs
+ output tx_commit_read; //64 bytes have been transmitted successfully
+ //hence advance the rd pointer
+ output tx_dt_rd; //get net dword from the TX FIFO
+ //FCS interface
+ output tx2tc_fcs_active; //FCS being shipped to RMII or MII interface
+ output tx2tc_gen_crc; //update the CRC with new byte
+
+
+ //MII or RMII interface signals
+ output tx2mi_strt_preamble; //ask RMII or MII interface to send preamable
+ output tx2mi_byte_valid; //current byte to RMII or MII is valid
+ output [7:0] tx2mi_byte; //data to RMII and MII interface
+ output tx2mi_end_transmit; //frame transfer done
+ output tx_sts_vld; //tx status is valid
+ output [15:0] tx_sts_byte_cntr;
+ output tx_sts_fifo_underrun;
+ output tx_ch_en;
+
+ input phy_tx_en;
+
+ input app_clk;
+ output set_fifo_undrn;
+
+
+ parameter mn_idle_st = 3'd0;
+ parameter mn_snd_full_dup_frm_st = 3'd1;
+
+ parameter fcs_idle_st = 0;
+ parameter fcs_snd_st = 1;
+
+ parameter dt_idle_st = 12'b000000000000;
+ parameter dt_xfr_st = 12'b000000000001;
+ parameter dt_pad_st = 12'b000000000010;
+ parameter dt_fcs_st = 12'b000000000100;
+
+
+ wire tx_commit_read;
+ wire tx_dt_rd; //request TX FIFO for more data
+ wire tx2tc_fcs_active; //FCS is currently transmitted
+ wire tx2tc_gen_crc;
+ wire tx2mi_strt_preamble;
+ wire tx2mi_end_transmit;
+ wire [7:0] tx2mi_byte;
+ wire tx2mi_byte_valid;
+ wire cfg_force_bad_fcs_pulse;
+ reg [15:0] tx_sts_byte_cntr;
+ reg tx_sts_fifo_underrun;
+
+
+ reg [11:0] curr_dt_st, nxt_dt_st;
+ reg tx_fcs_dn, tx_fcs_dn_reg; //FCS fsm on completion of appending FCS
+ reg curr_fcs_st, nxt_fcs_st; //FSM for FCS
+ reg fcs_active; //FCS is currently transmitted
+
+ reg init_fcs_select; //initiliaze FCS mux select
+ reg clr_bad_fcs; //tx_reset the bad FCS requirement
+ reg clr_pad_byte; //clear the padded condition
+ reg [2:0] fcs_mux_select; //mux select for FCS
+ reg send_bad_fcs; //registered send bad FCS requirement
+ reg set_bad_fcs; //set the above register
+ reg [15:0] tx_byte_cntr; //count the number of bytes xfr'ed
+ reg tx_fsm_rd; //request TX FIFO for more data
+ reg tx_byte_valid; //current byte to MII is valdi
+ reg strt_fcs, strt_fcs_reg; //data is done, send FCS
+ reg frm_padded; //current frame is padded
+
+
+ reg set_pad_byte; //send zero filled bytes
+ reg e_tx_sts_vld; //current packet is transferred
+ reg tx_sts_vld;
+ reg strt_preamble;
+ reg [7:0] tx_byte;
+ reg [7:0] tx_fsm_dt_reg;
+ reg tx_end_frame_reg;
+ reg tx_lst_xfr_dt, tx_lst_xfr_fcs;
+ reg commit_read;
+ reg set_max_retry_reached;
+ reg gen_tx_crc;
+ reg set_fifo_undrn, clr_fifo_undrn, fifo_undrn;
+ reg commit_read_sent;
+ reg clr_first_dfl, set_first_dfl;
+
+ wire tx_lst_xfr;
+
+
+ reg tx_lst_xfr_fcs_reg;
+ wire [15:0] tx_byte_cntr_int;
+
+ reg cur_idle_st_del;
+
+ reg app_tx_rdy_dly;
+
+
+ always @(posedge tx_clk or negedge tx_reset_n) begin
+ if (!tx_reset_n) begin
+ app_tx_rdy_dly <= 1'b0;
+ end
+ else begin
+ app_tx_rdy_dly <= app_tx_rdy;
+ end
+ end
+
+
+
+ assign tx_commit_read = commit_read;
+ assign tx_dt_rd = tx_fsm_rd;
+ assign tx2tc_fcs_active = fcs_active;
+ assign tx2tc_gen_crc = gen_tx_crc;
+ assign tx2mi_strt_preamble = strt_preamble;
+ assign tx2mi_byte_valid = tx_byte_valid;
+ assign tx2mi_byte = tx_byte;
+ assign tx2mi_end_transmit = tx_lst_xfr;
+
+ assign tx_lst_xfr = tx_lst_xfr_dt || tx_lst_xfr_fcs;
+
+//To take care of 1 less byte count when fcs is not appended.
+ assign tx_byte_cntr_int = (curr_dt_st == dt_fcs_st) ? tx_byte_cntr : tx_byte_cntr + 16'h1;
+
+ always @(posedge tx_clk or negedge tx_reset_n)
+ begin
+ if (!tx_reset_n)
+ begin
+ tx_sts_vld <= 1'b0;
+ tx_sts_byte_cntr <= 16'b0;
+ tx_sts_fifo_underrun <= 1'b0;
+ end // if (!tx_reset_n)
+ else
+ begin
+ tx_sts_vld <= e_tx_sts_vld;
+ if (e_tx_sts_vld)
+ begin
+ tx_sts_byte_cntr <= tx_byte_cntr_int;
+ tx_sts_fifo_underrun <= fifo_undrn || set_fifo_undrn;
+ end
+ end // else: !if(!tx_reset_n)
+ end // always @ (posedge tx_clk or negedge tx_reset_n)
+
+
+
+
+ half_dup_dble_reg U_dble_reg2 (
+ //outputs
+ .sync_out_pulse(tx_ch_en),
+ //inputs
+ .in_pulse(cf2tx_ch_en),
+ .dest_clk(tx_clk),
+ .reset_n(tx_reset_n)
+ );
+
+
+
+ half_dup_dble_reg U_dble_reg4 (
+ //outputs
+ .sync_out_pulse(cfg_force_bad_fcs_pulse),
+ //inputs
+ .in_pulse(cf2tx_force_bad_fcs),
+ .dest_clk(tx_clk),
+ .reset_n(tx_reset_n)
+ );
+
+ always @(posedge tx_clk or negedge tx_reset_n)
+ begin
+ if (!tx_reset_n)
+ cur_idle_st_del <= 1'b1;
+ else
+ cur_idle_st_del <= (curr_dt_st==dt_idle_st);
+ end
+
+ //Data pump, this state machine gets triggered by TX FIFO
+ //This FSM control's the MUX loging to channel the 32 bit
+ //data to byte wide and also keeps track of the end of the
+ //frame and the valid bytes for the last double word. tx_sts_vld
+ //is generated by this fsm.
+ //Collission handling, retry operations are done in this FSM.
+ always @(posedge tx_clk or negedge tx_reset_n)
+ begin
+ if (!tx_reset_n)
+ curr_dt_st <= dt_idle_st;
+ else if (tx_ch_en)
+ curr_dt_st <= nxt_dt_st;
+ else
+ curr_dt_st <= dt_idle_st;
+ end // always @ (posedge tx_clk or negedge tx_reset_n)
+
+ //combinatorial process
+ //always @(curr_dt_st or mi2tx_byte_ack or app_tx_fifo_empty
+ always @(curr_dt_st or mi2tx_byte_ack or app_tx_fifo_empty
+ or tx_end_frame_reg or commit_read_sent
+ or tx_byte_cntr or tx_fcs_dn_reg or cf2tx_pad_enable or tx_ch_en
+ or df2tx_dfl_dn or app_tx_rdy
+ or strt_fcs_reg
+ or tx_end_frame or tx_clk
+ or cf2tx_append_fcs
+ or app_tx_rdy_dly or cur_idle_st_del)
+ begin
+ nxt_dt_st = curr_dt_st;
+ tx_fsm_rd = 0;
+ tx_byte_valid = 0;
+ set_bad_fcs = 0;
+ strt_fcs = 0;
+ set_pad_byte = 0;
+ set_max_retry_reached = 0;
+ e_tx_sts_vld = 0;
+ commit_read = 0;
+ strt_preamble = 0;
+ tx_lst_xfr_dt = 0;
+ clr_pad_byte = 0;
+ set_fifo_undrn = 0;
+ clr_fifo_undrn = 0;
+ clr_first_dfl = 0;
+ set_first_dfl = 0;
+ case (curr_dt_st)
+ dt_idle_st :
+ begin
+ //clear early state
+ clr_pad_byte = 1;
+ clr_fifo_undrn = 1;
+ clr_first_dfl = 1'b1;
+ //wait until there is enough data in the TX FIFO
+ //and tx_enabled and not waiting for pause period
+ //in the case of full duplex
+ if (tx_ch_en) //config, channel enable
+ begin
+ if (app_tx_rdy && df2tx_dfl_dn)
+ begin
+ tx_fsm_rd = 1;
+ nxt_dt_st = dt_xfr_st;
+ strt_preamble = 1;
+ end
+ else
+ nxt_dt_st = dt_idle_st;
+ end // if (tx_ch_en)
+ else
+ nxt_dt_st = dt_idle_st;
+ end // case: dt_idle_st
+
+ dt_xfr_st :
+ begin
+ tx_byte_valid = 1;
+ //compare the mux_select to max bytes to be transmitted
+ //on the last dword of the frame
+ if (mi2tx_byte_ack && (tx_end_frame_reg))
+ begin
+ // If it is end of frame detection and the count
+ // indicates that there is no need for padding then if
+ // pad is enabled dont check for cf2tx_append_fcs and Append
+ // the CRC with the data packet
+ if ((tx_byte_cntr >= ( CORE_PAYLOAD_SIZE - 1)) && cf2tx_append_fcs)
+ begin
+ strt_fcs = 1;
+ nxt_dt_st = dt_fcs_st;
+ end // if (cf2tx_append_fcs)
+ else
+ //ending the current transfer, check the frame size
+ //padding or FCS needs to be performed
+ if (tx_byte_cntr < ( CORE_PAYLOAD_SIZE - 1))
+ begin
+ //less than min frame size, check to see if
+ //padding can be done
+ if(cf2tx_pad_enable)
+ begin
+ nxt_dt_st = dt_pad_st;
+ end // if (cf2tx_pad_enable)
+ else
+ begin
+ //if no padding, check to see if FCS needs
+ //to be computed
+ if (cf2tx_append_fcs)
+ begin
+ strt_fcs = 1;
+ nxt_dt_st = dt_fcs_st;
+ end // if (cf2tx_append_fcs)
+ else
+ //if no FCS, complete the transfer
+ begin
+ e_tx_sts_vld = 1;
+ commit_read = 1;
+ nxt_dt_st = dt_idle_st;
+ end // else: !if(cf2tx_append_fcs)
+ end // else: !if(cf2tx_pad_enable)
+ end // if (tx_byte_cntr < ( CORE_MIN_FRAME_SIZE - 1))
+ else
+ //minimmum frame sent, check to see if FCS needs to
+ //be computed else transfer is done
+ begin
+ if (cf2tx_append_fcs)
+ begin
+ strt_fcs = 1;
+ nxt_dt_st = dt_fcs_st;
+ end // if (cf2tx_append_fcs)
+ else
+ begin
+ commit_read = !commit_read_sent;
+ e_tx_sts_vld = 1;
+ nxt_dt_st = dt_idle_st;
+ end // else: !if(cf2tx_append_fcs)
+ end // else: !if(tx_byte_cntr < ( CORE_MIN_FRAME_SIZE - 1))
+ end
+ else if (mi2tx_byte_ack)
+ begin
+ //time to fetch the new dword
+ //check to see if the fifo is empty
+ //if it is then send the crc with last bit
+ //inverted as bad CRC so that the destination
+ //can throw away the frame
+ if (app_tx_fifo_empty)
+ begin
+ //TX has encountered error, finish the current byte
+ //append wrong fcs
+ set_bad_fcs = 1;
+ strt_fcs = 1;
+ nxt_dt_st = dt_fcs_st;
+ set_fifo_undrn = 1;
+ end // if (mi2tx_byte_ack && ((mux_select == 1) ||...
+ tx_fsm_rd = 1; //just to set error, or
+ //get next word
+ end // if (mi2tx_byte_ack && mux_selectl == 1)
+ //provide end of transfer to MII/RMII interface
+ //commit_read pointer
+ if (mi2tx_byte_ack )
+ commit_read = !commit_read_sent;
+
+ if (tx_end_frame_reg)
+ begin
+ if (tx_byte_cntr < (CORE_PAYLOAD_SIZE - 1))
+ begin
+ if(!cf2tx_pad_enable)
+ begin
+ if (!cf2tx_append_fcs)
+ tx_lst_xfr_dt = 1;
+ end // if (!cf2tx_pad_enable)
+ end // if (tx_byte_cntr < (CORE_MIN_FRAME_SIZE - 1))
+ else
+ begin
+ if (!cf2tx_append_fcs)
+ tx_lst_xfr_dt = 1;
+ end
+ end // if ((mux_select == mux_max_select) && (tx_end_frame_reg))
+ end // case: dt_xfr_st
+
+ dt_pad_st :
+ begin
+ //wait until the padded data is enough to satisfy
+ //the minimum packet size and then return to idle
+ tx_byte_valid = 1;
+ set_pad_byte = 1;
+ //check to see if the 48 bytes are sent and then move to the
+ //crc state
+ if (mi2tx_byte_ack && (tx_byte_cntr == CORE_PAYLOAD_SIZE - 1))
+ begin
+ strt_fcs = 1;
+ nxt_dt_st = dt_fcs_st;
+ end // if (mi2tx_byte_ack && (tx_byte_cntr == CORE_PAYLOAD_SIZE - 1))
+ end // case: dt_pad_st
+
+ dt_fcs_st :
+ begin
+ if (tx_fcs_dn_reg && !strt_fcs_reg)
+ //last byte of crc is transmitted to MII and
+ //a new set of CRC is not transmitted to MII (this
+ //could be because of JAM sequence)
+ begin
+ //In the case of MII, while in this state the
+ //MII interface will be transferring the last
+ //byte to the PHY. If a collision is seen in this
+ //state then do the appropriate
+ commit_read = !commit_read_sent;
+ nxt_dt_st = dt_idle_st;
+ e_tx_sts_vld = 1;
+ end // if (tx_fcs_dn)
+ else
+ begin
+ nxt_dt_st = dt_fcs_st;
+ end // else: !if(tx_fcs_dn)
+ end // case: dt_fcs_st
+
+
+
+ default :
+ begin
+ nxt_dt_st = dt_idle_st;
+ end
+ endcase // case (curr_dt_st)
+ end // always @ (curr_dt_st or )
+
+ //counter to track the number of bytes transferred excluding
+ //the preamble and SOF
+ always @(posedge tx_clk or negedge tx_reset_n)
+ begin
+ if (!tx_reset_n)
+ begin
+ tx_byte_cntr <= 16'd0;
+ end // if (!tx_reset_n)
+ else
+ begin
+ if (mi2tx_byte_ack)
+ begin
+ tx_byte_cntr <= tx_byte_cntr + 1;
+ end // if (mi2tx_byte_ack)
+ else if (strt_preamble)
+ begin
+ tx_byte_cntr <= 16'd0;
+ end // else: !if(mi2tx_byte_ack)
+ end // else: !if(!tx_reset_n)
+ end // always @ (posedge tx_clk or negedge tx_reset_n)
+
+// So, introduce strt_preamble_pls to compensate for delay.
+ reg s_p_d1, s_p_d2, s_p_d3;
+ wire strt_preamble_pls;
+ always @(posedge tx_clk or negedge tx_reset_n) begin
+ if (!tx_reset_n) begin
+ s_p_d1 <= 1'b0;
+ s_p_d2 <= 1'b0;
+ s_p_d3 <= 1'b0;
+ end // if (!tx_reset_n)
+ else begin
+ s_p_d1 <= strt_preamble;
+ s_p_d2 <= s_p_d1;
+ s_p_d3 <= s_p_d2;
+ end
+ end // always
+
+ wire strt_preamble_prog;
+ assign strt_preamble_pls = strt_preamble || s_p_d1 || s_p_d2 || s_p_d3;
+ assign strt_preamble_prog = strt_preamble;
+
+ //fsm to transmit the FCS
+ //synchronous process
+ always @(posedge tx_clk or negedge tx_reset_n)
+ begin
+ if (!tx_reset_n)
+ curr_fcs_st <= fcs_idle_st;
+ else
+ curr_fcs_st <= nxt_fcs_st;
+ end // always @ (posedge tx_clk or negedge tx_reset_n)
+
+ //set bad fcs requirement
+ always @(posedge tx_clk or negedge tx_reset_n)
+ begin
+ if (!tx_reset_n)
+ send_bad_fcs <= 0;
+ else
+ begin
+ //if (set_bad_fcs)
+ if (set_bad_fcs | cfg_force_bad_fcs_pulse)
+ send_bad_fcs <= 1;
+ else if (clr_bad_fcs)
+ send_bad_fcs <= 0;
+ end // else: !if(!tx_reset_n)
+ end // always @ (posedge tx_clk or negedge tx_reset_n)
+ //set the error condition flags
+ always @(posedge tx_clk or negedge tx_reset_n)
+ begin
+ if (!tx_reset_n)
+ begin
+ fifo_undrn <= 0;
+ end // if (!tx_reset_n)
+ else
+ begin
+
+ if (set_fifo_undrn)
+ fifo_undrn <= 1;
+ else if (clr_fifo_undrn)
+ fifo_undrn <= 0;
+ end // else: !if(!tx_reset_n)
+ end // always @ (posedge tx_clk or negedge tx_reset_n)
+
+ //sync block for tx_fcs_dn
+
+ always @(posedge tx_clk or negedge tx_reset_n)
+ begin
+ if (!tx_reset_n)
+ begin
+ strt_fcs_reg <= 0;
+ tx_fcs_dn_reg <= 0;
+ tx_lst_xfr_fcs_reg <= 0;
+ end // if (!tx_reset_n)
+ else
+ begin
+ tx_fcs_dn_reg <= tx_fcs_dn;
+ strt_fcs_reg <= strt_fcs;
+ tx_lst_xfr_fcs_reg <= tx_lst_xfr_fcs;
+ end // else: !if(!tx_reset_n)
+ end // always @ (posedge tx_clk or negedge tx_reset_n)
+
+ //combinatorial process
+ //bad fcs or good fcs could have been requested, in either case
+ //the 8 bytes have to be shifted out, in the case of bad fcs
+ //the last bit of the last byte will up toggled.
+ always @(curr_fcs_st or mi2tx_byte_ack or fcs_mux_select or
+ strt_fcs or strt_fcs_reg)
+ begin
+ nxt_fcs_st = curr_fcs_st;
+ fcs_active = 0;
+ init_fcs_select = 0;
+ tx_fcs_dn = 0;
+ clr_bad_fcs = 0;
+ tx_lst_xfr_fcs = 0;
+ case (curr_fcs_st)
+ fcs_idle_st :
+ if (strt_fcs || strt_fcs_reg)
+ begin
+ nxt_fcs_st = fcs_snd_st;
+ init_fcs_select = 1;
+ end // if (strt_fcs)
+ fcs_snd_st :
+ begin
+ fcs_active = 1;
+ if (fcs_mux_select == 3'd3)
+ tx_lst_xfr_fcs = 1;
+ if (mi2tx_byte_ack && fcs_mux_select == 3'd3)
+ begin
+ tx_fcs_dn = 1;
+ clr_bad_fcs = 1;
+ nxt_fcs_st = fcs_idle_st;
+ end // if (mi2tx_byte_ack)
+ end // case: fcs_snd_st
+ default :
+ begin
+ nxt_fcs_st = fcs_idle_st;
+ end
+ endcase // case (curr_fcs_st)
+ end // always @ (curr_fcs_st or)
+
+ //fcs mux select counter
+ always @(posedge tx_clk or negedge tx_reset_n)
+ begin
+ if (!tx_reset_n)
+ fcs_mux_select <= 3'd0;
+ else
+ begin
+ if (strt_fcs)
+ fcs_mux_select <= 3'd0;
+ else if (mi2tx_byte_ack)
+ fcs_mux_select <= fcs_mux_select + 1 ;
+ end // else: !if(!tx_reset_n)
+ end // always @ (posedge tx_clk or negedge tx_reset_n)
+
+ //if frame is padded
+ always @(posedge tx_clk or negedge tx_reset_n)
+ begin
+ if (!tx_reset_n)
+ frm_padded <= 0;
+ else
+ begin
+ if (clr_pad_byte)
+ frm_padded <= 0;
+ else if (set_pad_byte)
+ frm_padded <= 1;
+ end // else: !if(!tx_reset_n)
+ end // always @ (posedge tx_clk or negedge tx_reset_n)
+
+
+ //register the TX fifo data on tx_fsm_rd and demux
+ //it for byte access
+ always @(posedge tx_clk or negedge tx_reset_n)
+ begin
+ if (!tx_reset_n)
+ begin
+ tx_fsm_dt_reg <= 8'd0;
+ tx_end_frame_reg <= 0;
+ end // if (!tx_reset_n)
+ else
+ begin
+ if (tx_fsm_rd)
+ begin
+ tx_fsm_dt_reg <= app_tx_dt_in;
+ tx_end_frame_reg <= tx_end_frame;
+ end // if (tx_fsm_rd)
+ if (e_tx_sts_vld)
+ tx_end_frame_reg <= 0;
+ end // else: !if(!tx_reset_n)
+ end // always @ (posedge tx_clk or negedge tx_reset_n)
+
+
+ //Data mux, is controlled either by the mux select from the
+ //primary data flow or from the FCS mux select. When PAD
+ //data option is used bytes of all zeros are transmitted
+ always @(fcs_active or app_tx_dt_in or tc2tx_fcs
+ or send_bad_fcs or fcs_mux_select or
+ set_pad_byte or tx_fsm_dt_reg )
+ begin
+ if (!fcs_active && !set_pad_byte)
+ begin
+ //primary data flow
+ tx_byte = tx_fsm_dt_reg[7:0];
+ end // if (!fcs_active)
+ else if (fcs_active)
+ begin
+ tx_byte = tc2tx_fcs[7:0];
+ case (fcs_mux_select)
+ 3'd0 :
+ tx_byte = tc2tx_fcs[7:0];
+ 3'd1 :
+ tx_byte = tc2tx_fcs[15:8];
+ 3'd2 :
+ tx_byte = tc2tx_fcs[23:16];
+ default :
+ begin
+ if (send_bad_fcs)
+ tx_byte = {!tc2tx_fcs[31], tc2tx_fcs[30:24]};
+ else
+ tx_byte = tc2tx_fcs[31:24];
+ end // case: 3'd7
+ endcase // case (mux_select)
+ end // else: !if(!fcs_active)
+ else if (set_pad_byte)
+ tx_byte = 8'd0;
+ else
+ tx_byte = 8'd0;
+ end // always @ (fcs_active or app_tx_dt_in or tc2tx_fcs or mux_select...
+
+ //generate fcs computation enable. One cycle after the
+ //strt_preamble the tx_byte is stable and a cycle after the
+ //mi2tx_byte_ack also a new byte is stable
+ always @(posedge tx_clk or negedge tx_reset_n)
+ begin
+ if (!tx_reset_n)
+ gen_tx_crc <= 1'b0;
+ else
+ begin
+ if (fcs_active || strt_fcs)
+ gen_tx_crc <= 1'b0;
+ else
+ gen_tx_crc <= strt_preamble || mi2tx_byte_ack;
+ end // else: !if(!tx_reset_n)
+ end // always (posedge tx_clk or negedge tx_reset_n)
+
+
+endmodule // tx_fsm
diff --git a/verilog/rtl/gmac/mac/g_tx_top.v b/verilog/rtl/gmac/mac/g_tx_top.v
new file mode 100755
index 0000000..5e8173e
--- /dev/null
+++ b/verilog/rtl/gmac/mac/g_tx_top.v
@@ -0,0 +1,231 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Mar 2, 2011 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+/***************************************************************
+ Description:
+
+ tx_top.v: This module has the top level of the transmit block
+ It instantiates the following blocks
+ 1. tx_fsm
+ 2. tx_crc
+ 3. tx_fifo_mgmt
+ 4. deferral
+ 5. backoff
+ ***********************************************************************/
+module g_tx_top(
+ app_clk,
+ set_fifo_undrn,
+
+
+ //Outputs
+ //TX FIFO management
+ tx_commit_read,
+ tx_dt_rd,
+
+ //MII interface
+ tx2mi_strt_preamble,
+ tx2mi_byte_valid,
+ tx2mi_byte,
+ tx2mi_end_transmit,
+ tx_ch_en,
+
+ //Status to application
+ tx_sts_vld,
+ tx_sts_byte_cntr,
+ tx_sts_fifo_underrun,
+
+
+ //Inputs
+ //MII interface
+ phy_tx_en,
+ phy_tx_er,
+
+ //configuration
+ cf2tx_ch_en,
+ cf2df_dfl_single,
+ cf2tx_pad_enable,
+ cf2tx_append_fcs,
+ cf_mac_mode,
+ cf_mac_sa,
+ cf2tx_force_bad_fcs,
+ //FIFO data
+ app_tx_dt_in,
+ app_tx_fifo_empty,
+ app_tx_rdy,
+
+ //MII
+ mi2tx_byte_ack,
+ app_reset_n,
+ tx_reset_n,
+ tx_clk);
+ input app_reset_n; // Global app_reset for the MAC
+ input tx_reset_n;
+ input tx_clk; // Transmit clock
+
+ input [8:0] app_tx_dt_in;
+ input app_tx_fifo_empty;
+ input app_tx_rdy;
+
+ input phy_tx_en; // Transmit data Enable
+ input phy_tx_er; // Transmit Error
+ input cf2tx_ch_en; // Transmit channel Enable
+ input [7:0] cf2df_dfl_single;
+ input cf2tx_pad_enable; // Padding Enabled
+ input cf2tx_append_fcs; // Append CRC to packets
+ input cf2tx_force_bad_fcs; // force bad fcs
+ input [47:0] cf_mac_sa; // MAC Source Address
+ input cf_mac_mode; // Gigabit or 10/100
+
+
+
+ input mi2tx_byte_ack; // Transmit byte ack from RMII
+ output tx_commit_read;
+ output tx_dt_rd; //get the next fsm data
+
+
+ output tx2mi_strt_preamble; // Start preamble indicated to RMII
+ output tx2mi_byte_valid; // Byte valid from the Tx State Macine
+ output [7:0] tx2mi_byte; // Transmit byte to RMII
+ output tx2mi_end_transmit; // Transmit complete
+
+ output tx_sts_vld; //tx_sts is valid on valid tx_sts_vld
+ output [15:0] tx_sts_byte_cntr;
+ output tx_sts_fifo_underrun;
+
+ output tx_ch_en;
+
+ output set_fifo_undrn;
+
+ input app_clk;
+
+ wire [31:0] tc2tx_fcs;
+ wire set_fifo_undrn;
+
+
+
+
+
+ // Instantiate Defferal block
+ g_deferral U_deferral (
+ //Outputs
+ .df2tx_dfl_dn(df2tx_dfl_dn),
+ .cf2df_dfl_single(cf2df_dfl_single),
+ .phy_tx_en(phy_tx_en),
+ .phy_tx_er(phy_tx_er),
+ .tx_clk(tx_clk),
+ .app_reset_n(tx_reset_n));
+
+
+
+ // Instantiate Transmit State machine block
+ g_tx_fsm U_tx_fsm(
+ .app_clk(app_clk),
+ .set_fifo_undrn(set_fifo_undrn),
+
+ //Outputs
+ .tx_commit_read(tx_commit_read),
+ .tx_dt_rd(tx_dt_rd),
+ //FCS block interface
+ .tx2tc_fcs_active(tx2tc_fcs_active),
+ .tx2tc_gen_crc(tx2tc_gen_crc),
+ //MII or RMII interface signals
+ .tx2mi_strt_preamble(tx2mi_strt_preamble),
+ .tx2mi_byte_valid(tx2mi_byte_valid),
+ .tx2mi_byte(tx2mi_byte),
+ .tx2mi_end_transmit(tx2mi_end_transmit),
+ .tx_ch_en(tx_ch_en),
+ .phy_tx_en(phy_tx_en),
+ //tx fifo management outputs
+ .tx_sts_vld(tx_sts_vld),
+ .tx_sts_byte_cntr(tx_sts_byte_cntr),
+ .tx_sts_fifo_underrun(tx_sts_fifo_underrun),
+ .app_tx_rdy(app_tx_rdy),
+ .tx_end_frame(app_tx_dt_in[8]),
+ .app_tx_dt_in(app_tx_dt_in[7:0]),
+ .app_tx_fifo_empty(app_tx_fifo_empty),
+ //dfl and back off
+ .df2tx_dfl_dn(df2tx_dfl_dn),
+ //inputs from FCS
+ .tc2tx_fcs(tc2tx_fcs),
+ .cf2tx_ch_en(cf2tx_ch_en),
+ .cf2tx_pad_enable(cf2tx_pad_enable),
+ .cf2tx_append_fcs(cf2tx_append_fcs),
+ .cf_mac_mode(cf_mac_mode),
+ .cf_mac_sa(cf_mac_sa),
+ .cf2tx_force_bad_fcs(cf2tx_force_bad_fcs),
+ //MII
+ .mi2tx_byte_ack(mi2tx_byte_ack),
+ .tx_clk(tx_clk),
+ .tx_reset_n(tx_reset_n),
+ .app_reset_n(app_reset_n));
+
+
+
+
+ // Instantiate CRC 32 block for Transmit
+ g_tx_crc32 U_tx_crc32 (
+ // List of outputs.
+ .tx_fcs (tc2tx_fcs),
+ // List of inputs
+ .gen_tx_crc(tx2tc_gen_crc),
+ .tx_reset_crc(tx2mi_strt_preamble),
+ .tx_data(tx2mi_byte),
+ .sclk(tx_clk),
+ .reset_n(tx_reset_n)
+ );
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/verilog/rtl/gmac/mac/s2f_sync.v b/verilog/rtl/gmac/mac/s2f_sync.v
new file mode 100755
index 0000000..0ea7b49
--- /dev/null
+++ b/verilog/rtl/gmac/mac/s2f_sync.v
@@ -0,0 +1,87 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Mar 2, 2011 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+/***************************************************************
+ Description:
+ Synchronizes the pulse from one clock to another
+ * clock domain
+***********************************************************************/
+module s2f_sync (
+ //outputs
+ sync_out_pulse,
+ //inputs
+ in_pulse,
+ dest_clk,
+ reset_n);
+
+ output sync_out_pulse; //output synchronised to slow clock
+ input in_pulse; //input based on fast clock, pulse
+ input dest_clk; //slow clock
+ input reset_n;
+
+ reg sync1_out, sync2_out, sync3_out;
+
+ always @(posedge dest_clk or negedge reset_n)
+ begin
+ if (!reset_n)
+ begin
+ sync1_out <= 0;
+ sync2_out <= 0;
+ sync3_out <= 0;
+ end // if (!reset_n)
+ else
+ begin
+ sync1_out <= in_pulse;
+ sync2_out <= sync1_out;
+ sync3_out <= sync2_out;
+ end // else: !if(reset_n)
+ end // always @ (posedge dest_clk or negedge reset_n)
+
+ assign sync_out_pulse = sync2_out && !sync3_out;
+endmodule // s2f_sync
+
+
+
+
+
diff --git a/verilog/rtl/gmac/top/filelist_top.f b/verilog/rtl/gmac/top/filelist_top.f
new file mode 100644
index 0000000..9db1813
--- /dev/null
+++ b/verilog/rtl/gmac/top/filelist_top.f
@@ -0,0 +1,22 @@
+g_mac_top.v
+dble_reg.v
+g_tx_fsm.v
+g_deferral.v
+g_tx_top.v
+g_rx_fsm.v
+g_cfg_mgmt.v
+s2f_sync.v
+g_md_intf.v
+g_deferral_rx.v
+g_rx_top.v
+g_mii_intf.v
+g_mac_core.v
+g_rx_crc32.v
+g_tx_crc32.v
+async_fifo.v
+eth_parser.v
+-v registers.v
+-v stat_counter.v
+-v toggle_sync.v
++lint=all
++v2k
diff --git a/verilog/rtl/gmac/top/g_mac_top.v b/verilog/rtl/gmac/top/g_mac_top.v
new file mode 100644
index 0000000..2f393f4
--- /dev/null
+++ b/verilog/rtl/gmac/top/g_mac_top.v
@@ -0,0 +1,443 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+// ------------------------------------------------------------------------
+// Description :
+// This module instantiates the MAC block and the FIFO interface
+//
+// ------------------------------------------------------------------------
+module g_mac_top (
+ scan_mode,
+ s_reset_n,
+ tx_reset_n,
+ rx_reset_n,
+ reset_mdio_clk_n,
+ app_reset_n,
+
+ app_clk,
+
+ // Application RX FIFO Interface
+ app_txfifo_wren_i,
+ app_txfifo_wrdata_i,
+ app_txfifo_addr,
+ app_txfifo_full_o,
+ app_txfifo_afull_o,
+ app_txfifo_space_o,
+
+ // Application TX FIFO Interface
+ app_rxfifo_rden_i,
+ app_rxfifo_empty_o,
+ app_rxfifo_aempty_o,
+ app_rxfifo_cnt_o,
+ app_rxfifo_rdata_o,
+ app_rxfifo_addr,
+
+ app_rx_desc_req ,
+ app_rx_desc_ack ,
+ app_rx_desc_discard ,
+ app_rx_desc_data ,
+
+ // Conntrol Bus Sync with Application Clock
+ reg_cs,
+ reg_wr,
+ reg_addr,
+ reg_wdata,
+ reg_be,
+
+ // Outputs
+ reg_rdata,
+ reg_ack,
+
+
+ // Phy Signals
+
+ // Line Side Interface TX Path
+ phy_tx_en,
+ phy_tx_er,
+ phy_txd,
+ phy_tx_clk,
+
+ // Line Side Interface RX Path
+ phy_rx_clk,
+ phy_rx_er,
+ phy_rx_dv,
+ phy_rxd,
+ phy_crs,
+
+ //MDIO interface
+ mdio_clk,
+ mdio_in,
+ mdio_out_en,
+ mdio_out,
+
+ // QCounter
+ rx_buf_qbase_addr,
+ tx_buf_qbase_addr,
+
+ tx_qcnt_inc,
+ tx_qcnt_dec,
+ rx_qcnt_inc,
+ rx_qcnt_dec,
+
+ tx_qcnt,
+ rx_qcnt
+
+ );
+
+parameter W = 8'd9;
+parameter DP = 8'd32;
+parameter AW = (DP == 2) ? 1 :
+ (DP == 4) ? 2 :
+ (DP == 8) ? 3 :
+ (DP == 16) ? 4 :
+ (DP == 32) ? 5 :
+ (DP == 64) ? 6 :
+ (DP == 128) ? 7 :
+ (DP == 256) ? 8 : 0;
+
+
+//-----------------------------------------------------------------------
+// INPUT/OUTPUT DECLARATIONS
+//-----------------------------------------------------------------------
+input scan_mode;
+input s_reset_n;
+input tx_reset_n;
+input rx_reset_n;
+input reset_mdio_clk_n;
+input app_reset_n;
+
+//-----------------------------------------------------------------------
+// Application Clock Related Declaration
+//-----------------------------------------------------------------------
+input app_clk;
+
+
+// Application RX FIFO Interface
+input app_txfifo_wren_i;
+input [8:0] app_txfifo_wrdata_i;
+output [15:0] app_txfifo_addr;
+
+output app_txfifo_full_o;
+output app_txfifo_afull_o;
+output [AW:0] app_txfifo_space_o;
+
+// Application TX FIFO Interface
+input app_rxfifo_rden_i;
+output app_rxfifo_empty_o;
+output app_rxfifo_aempty_o;
+output [AW:0] app_rxfifo_cnt_o;
+output [8:0] app_rxfifo_rdata_o;
+output [15:0] app_rxfifo_addr;
+
+// descriptor interface
+output app_rx_desc_req ; // descriptor request
+input app_rx_desc_ack ; // descriptor ack
+output app_rx_desc_discard ; // descriptor discard
+output [31:0] app_rx_desc_data ; // descriptor data
+
+// Conntrol Bus Sync with Application Clock
+//---------------------------------
+// Reg Bus Interface Signal
+//---------------------------------
+input reg_cs ;
+input reg_wr ;
+input [3:0] reg_addr ;
+input [31:0] reg_wdata ;
+input [3:0] reg_be ;
+
+ // Outputs
+output [31:0] reg_rdata ;
+output reg_ack ;
+
+//-----------------------------------------------------------------------
+// Line-Tx Signal
+//-----------------------------------------------------------------------
+output phy_tx_en;
+output phy_tx_er;
+output [7:0] phy_txd;
+input phy_tx_clk;
+
+//-----------------------------------------------------------------------
+// Line-Rx Signal
+//-----------------------------------------------------------------------
+input phy_rx_clk;
+input phy_rx_er;
+input phy_rx_dv;
+input [7:0] phy_rxd;
+input phy_crs;
+
+
+//-----------------------------------------------------------------------
+// MDIO Signal
+//-----------------------------------------------------------------------
+ input mdio_clk;
+ input mdio_in;
+ output mdio_out_en;
+ output mdio_out;
+
+//--------------------------------------
+// QCounter, Better to move to seperate global reg block
+//-------------------------------------
+output [9:0] rx_buf_qbase_addr; // Rx QBase Address
+output [9:0] tx_buf_qbase_addr; // TX QBase Address
+
+input tx_qcnt_inc; // Tx QCounter Increment indication
+input tx_qcnt_dec; // Tx QCounter Decrement indication
+input rx_qcnt_inc; // Rx QCounter Increment indication
+input rx_qcnt_dec; // Rx QCounter Decrement indication
+
+output [3:0] tx_qcnt ;
+output [3:0] rx_qcnt ;
+
+//---------------------
+// RX FIFO Interface Signal
+ wire clr_rx_error_from_rx_fsm_o;
+ wire rx_fifo_full_i;
+ wire rx_fifo_wr_o;
+ wire [8:0] rx_fifo_data_o;
+ wire rx_commit_wr_o;
+ wire rx_commit_write_done_o;
+ wire rx_rewind_wr_o;
+ wire rx_fifo_error = 1'b0;
+
+//-----------------------------------------------------------------------
+// TX-Clock Domain Status Signal
+//-----------------------------------------------------------------------
+ wire tx_commit_read;
+ wire tx_fifo_rd;
+
+ wire [8:0] tx_fifo_data;
+ wire tx_fifo_empty;
+ wire tx_fifo_rdy;
+ wire [AW:0] tx_fifo_aval;
+
+ wire [47:0] cf_mac_sa;
+ wire [31:0] cfg_ip_sa;
+ wire [31:0] cfg_mac_filter;
+ wire [3:0] tx_buf_base_addr;
+ wire [3:0] rx_buf_base_addr;
+ wire [11:0] g_rx_pkt_len;
+ wire [15:0] pkt_status;
+ wire app_rxfifo_empty;
+ wire g_rx_block_rxrd;
+ wire [15:0] g_rx_pkt_status ; // Packet Status
+
+assign app_rxfifo_empty_o = app_rxfifo_empty | g_rx_block_rxrd;
+g_dpath_ctrl m_g_dpath_ctrl (
+ .rst_n ( s_reset_n ),
+ .clk ( app_clk ),
+
+ .rx_buf_base_addr (rx_buf_base_addr ),
+ .tx_buf_base_addr (tx_buf_base_addr ),
+
+ // gmac core to memory write interface
+ .g_rx_mem_rd ( app_rxfifo_rden_i ),
+ .g_rx_mem_eop ( app_rxfifo_rdata_o[8] ),
+ .g_rx_mem_addr ( app_rxfifo_addr ),
+ .g_rx_block_rxrd ( g_rx_block_rxrd ),
+
+ // descr handshake
+ .g_rx_desc_req (app_rx_desc_req ),
+ .g_rx_desc_discard (app_rx_desc_discard ),
+ .g_rx_desc_data (app_rx_desc_data ),
+ .g_rx_desc_ack (app_rx_desc_ack ),
+
+
+ .g_rx_pkt_done (g_rx_pkt_done ),
+ .g_rx_pkt_len (g_rx_pkt_len ),
+ .g_rx_pkt_status (g_rx_pkt_status ),
+ .g_rx_pkt_drop (g_rx_pkt_drop )
+
+
+ );
+
+
+g_eth_parser u_eth_parser (
+ .s_reset_n (app_reset_n),
+ .app_clk (app_clk),
+
+ // Configuration
+ .cfg_filters (cfg_mac_filter),
+ .cfg_mac_sa (cf_mac_sa),
+ .cfg_ip_sa (cfg_ip_sa),
+
+ // Input Control Information
+ .eop (app_rxfifo_rdata_o[8]),
+ .dval (app_rxfifo_rden_i),
+ .data (app_rxfifo_rdata_o[7:0]),
+
+ // output status
+ .pkt_done (g_rx_pkt_done ),
+ .pkt_len (g_rx_pkt_len ),
+ .pkt_status (g_rx_pkt_status ),
+ .pkt_drop_ind (g_rx_pkt_drop ),
+ .pkt_drop_reason ()
+ );
+
+
+
+g_mac_core u_mac_core (
+ .scan_mode (scan_mode),
+ .s_reset_n (s_reset_n) ,
+ .tx_reset_n (tx_reset_n) ,
+ .rx_reset_n (rx_reset_n) ,
+ .reset_mdio_clk_n (reset_mdio_clk_n) ,
+ .app_reset_n (app_reset_n) ,
+
+ // Reg Bus Interface Signal
+ . reg_cs (reg_cs),
+ . reg_wr (reg_wr),
+ . reg_addr (reg_addr),
+ . reg_wdata (reg_wdata),
+ . reg_be (reg_be),
+
+ // Outputs
+ . reg_rdata (reg_rdata),
+ . reg_ack (reg_ack),
+
+ .app_clk (app_clk) ,
+
+ // Conntrol Bus Sync with Application Clock
+
+
+
+ // RX FIFO Interface Signal
+ .rx_fifo_full_i (rx_fifo_full_i) ,
+ .rx_fifo_wr_o (rx_fifo_wr_o) ,
+ .rx_fifo_data_o (rx_fifo_data_o) ,
+ .rx_commit_wr_o (rx_commit_wr_o) ,
+ .rx_rewind_wr_o (rx_rewind_wr_o) ,
+ .rx_commit_write_done_o (rx_commit_write_done_o) ,
+ .clr_rx_error_from_rx_fsm_o(clr_rx_error_from_rx_fsm_o) ,
+ .rx_fifo_error_i (rx_fifo_error) ,
+
+ // TX FIFO Interface Signal
+ .tx_fifo_data_i (tx_fifo_data) ,
+ .tx_fifo_empty_i (tx_fifo_empty) ,
+ .tx_fifo_rdy_i (tx_fifo_rdy) , // See to connect to config
+ .tx_fifo_rd_o (tx_fifo_rd) ,
+ .tx_commit_read_o (tx_commit_read) ,
+
+ // Phy Signals
+
+ // Line Side Interface TX Path
+ .phy_tx_en (phy_tx_en) ,
+ .phy_tx_er (phy_tx_er) ,
+ .phy_txd (phy_txd) ,
+ .phy_tx_clk (phy_tx_clk) ,
+
+ // Line Side Interface RX Path
+ .phy_rx_clk (phy_rx_clk) ,
+ .phy_rx_er (phy_rx_er) ,
+ .phy_rx_dv (phy_rx_dv) ,
+ .phy_rxd (phy_rxd) ,
+ .phy_crs (phy_crs) ,
+
+ //MDIO interface
+ .mdio_clk (mdio_clk) ,
+ .mdio_in (mdio_in) ,
+ .mdio_out_en (mdio_out_en) ,
+ .mdio_out (mdio_out),
+
+ .cf_mac_sa (cf_mac_sa),
+ .cfg_ip_sa (cfg_ip_sa),
+ .cfg_mac_filter (cfg_mac_filter),
+
+ .rx_buf_base_addr (rx_buf_base_addr),
+ .tx_buf_base_addr (tx_buf_base_addr),
+
+ .rx_buf_qbase_addr (rx_buf_qbase_addr),
+ .tx_buf_qbase_addr (tx_buf_qbase_addr),
+
+ .tx_qcnt_inc (tx_qcnt_inc),
+ .tx_qcnt_dec (tx_qcnt_dec),
+ .tx_qcnt (tx_qcnt),
+
+ .rx_qcnt_inc (rx_qcnt_inc),
+ .rx_qcnt_dec (rx_qcnt_dec),
+ .rx_qcnt (rx_qcnt)
+
+ );
+
+assign tx_fifo_rdy = (tx_fifo_aval > 8) ; // Dinesh-A Change it to config
+
+async_fifo #(W,DP,0,0) u_mac_txfifo (
+ .wr_clk (app_clk),
+ .wr_reset_n (app_reset_n),
+ .wr_en (app_txfifo_wren_i),
+ .wr_data (app_txfifo_wrdata_i),
+ .full (app_txfifo_full_o), // sync'ed to wr_clk
+ .afull (app_txfifo_afull_o), // sync'ed to wr_clk
+ .wr_total_free_space (app_txfifo_space_o),
+
+ .rd_clk (phy_tx_clk),
+ .rd_reset_n (tx_reset_n),
+ .rd_en (tx_fifo_rd),
+ .empty (tx_fifo_empty), // sync'ed to rd_clk
+ .aempty (tx_fifo_aempty), // sync'ed to rd_clk
+ .rd_total_aval (tx_fifo_aval),
+ .rd_data (tx_fifo_data)
+ );
+
+async_fifo #(W,DP,0,0) u_mac_rxfifo (
+ .wr_clk (phy_rx_clk),
+ .wr_reset_n (rx_reset_n),
+ .wr_en (rx_fifo_wr_o),
+ .wr_data (rx_fifo_data_o),
+ .full (rx_fifo_full_i), // sync'ed to wr_clk
+ .afull (rx_fifo_afull_i), // sync'ed to wr_clk
+ .wr_total_free_space (),
+
+ .rd_clk (app_clk),
+ .rd_reset_n (app_reset_n),
+ .rd_en (app_rxfifo_rden_i),
+ .empty (app_rxfifo_empty), // sync'ed to rd_clk
+ .aempty (app_rxfifo_aempty_o), // sync'ed to rd_clk
+ .rd_total_aval (app_rxfifo_cnt_o),
+ .rd_data (app_rxfifo_rdata_o)
+ );
+
+
+
+endmodule
+
diff --git a/verilog/rtl/lbist/src/lbist_core.sv b/verilog/rtl/lbist/src/lbist_core.sv
new file mode 100644
index 0000000..3c4e945
--- /dev/null
+++ b/verilog/rtl/lbist/src/lbist_core.sv
@@ -0,0 +1,313 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// LBIST CORE ////
+//// ////
+//// This file is part of the logic_bist project ////
+//// https://github.com/dineshannayya/logic_bist.git ////
+//// ////
+//// Description ////
+//// This block manages all the lbist sequence ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 29 Nov 2021 Dinesh A ////
+//// Initial version ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module lbist_core
+ #(parameter SCW = 8 // SCAN CHAIN WIDTH
+ )
+
+ (
+
+ input logic mclk,
+ input logic mclk_skew,
+ input logic rst_n,
+ input logic srst, // software reset
+
+
+ // Reg Bus Interface Signal
+ input logic lbist_start, // lbist start
+ input logic [15:0] cfg_lbist_pat, // Total Scan pattern to be run
+ input logic [15:0] cfg_chain_depth, // Scan Chain Depth
+ input logic cfg_lbist_rsb, // Option to bypass First scan shift compare
+ output logic lbist_done, // End of Ltest
+ output logic [31:0] lbist_sig, // scan signature
+
+
+ // Scan Control Signal
+ output logic scan_clk,
+ output logic scan_rst_n,
+ output logic scan_mode,
+ output logic scan_en,
+ output logic [SCW-1:0] scan_in,
+ input logic [SCW-1:0] scan_out
+
+);
+
+// FSM STATE
+
+parameter FSM_IDLE = 4'b0000;
+parameter FSM_RESET_WAIT = 4'b0001;
+parameter FSM_IDLE_WAIT = 4'b0010;
+parameter FSM_ASSERT_SCAN_EN = 4'b0011;
+parameter FSM_SCAN_SHIFT = 4'b0100;
+parameter FSM_DEASSERT_SCAN_EN = 4'b0101;
+parameter FSM_DEASSERT_SCAN_CLK = 4'b0110;
+parameter FSM_SCAN_CAPTURE = 4'b0111;
+
+// Scan Sequence
+// 1. scan_reset_n = 0, scan_clk_enb = 0, scan_en = 0, Wait 4 Cycle
+// 2. scan_reset_n = 1, scan_clk_enb = 0, scan_en = 0, Wait 4 Cycle
+// 3. scan_en = 1, Wait 4 Cycle
+// 4. scan_clk_enb = 1 , Wait for Scan Depth, If Total Pattern over, Then Exit
+// 5. scan_clk_enb = 0, scan_en = 0, Wait for 4 Cycle
+// 6. scan_clk_en = 1 , Wait for 1 Cycle
+// 7. scan_clk_en = 0 Go to #3
+
+logic [3:0] state, next_state;
+logic next_scan_en;
+logic scan_clk_enb,next_scan_clk_enb;
+logic [15:0]clk_cnt, next_clk_cnt;
+logic next_scan_rst_n;
+logic [15:0]scan_pat_cnt,next_scan_pat_cnt;
+logic next_lbist_done;
+logic lbist_start_d;
+logic next_scan_mode;
+logic r_sshift_done; // Indicate Reset Scan shift done, This is first pattern
+
+always_ff @(negedge rst_n or posedge mclk_skew)
+begin
+ if(rst_n == 1'b0) begin
+ state <= FSM_IDLE;
+ scan_en <= '0;
+ scan_clk_enb <= '0;
+ clk_cnt <= '0;
+ scan_rst_n <= '1;
+ scan_pat_cnt <= '0;
+ lbist_done <= '0;
+ lbist_start_d <= 0;
+ scan_mode <= 0;
+ r_sshift_done <= 0;
+ end else if(srst) begin
+ state <= FSM_IDLE;
+ scan_en <= '0;
+ scan_clk_enb <= '0;
+ clk_cnt <= '0;
+ scan_rst_n <= '1;
+ scan_pat_cnt <= '0;
+ lbist_done <= '0;
+ lbist_start_d <= 0;
+ scan_mode <= 0;
+ r_sshift_done <= 0;
+ end else begin
+ state <= next_state;
+ scan_en <= next_scan_en;
+ scan_clk_enb <= next_scan_clk_enb;
+ clk_cnt <= next_clk_cnt;
+ scan_rst_n <= next_scan_rst_n;
+ scan_pat_cnt <= next_scan_pat_cnt;
+ lbist_done <= next_lbist_done;
+ lbist_start_d <= lbist_start;
+ scan_mode <= next_scan_mode;
+ // After first scan capture, set reset scan shift done indication
+ if(state == FSM_SCAN_CAPTURE)
+ r_sshift_done <= 1;
+
+ end
+end
+
+
+wire lbist_pos_edge = (lbist_start_d ==0) && (lbist_start == 1);
+
+always_comb begin
+ next_state = state;
+ next_scan_en = scan_en;
+ next_scan_clk_enb = scan_clk_enb;
+ next_clk_cnt = clk_cnt;
+ next_scan_rst_n = scan_rst_n;
+ next_scan_pat_cnt = scan_pat_cnt;
+ next_lbist_done = lbist_done;
+ next_scan_mode = scan_mode;
+ case(state)
+ FSM_IDLE:
+ if(lbist_pos_edge) begin
+ next_lbist_done = 0;
+ next_scan_pat_cnt = cfg_lbist_pat;
+ next_scan_mode = 1;
+ next_scan_rst_n = 0;
+ next_scan_en = 0;
+ next_scan_clk_enb = 0;
+ next_clk_cnt = 4;
+ next_state = FSM_RESET_WAIT;
+ end
+ FSM_RESET_WAIT:
+ if(clk_cnt == 0) begin
+ next_scan_rst_n = 1;
+ next_scan_en = 0;
+ next_clk_cnt = 4;
+ next_state = FSM_IDLE_WAIT;
+ end else begin
+ next_clk_cnt = next_clk_cnt - 1;
+ end
+ FSM_IDLE_WAIT:
+ if(clk_cnt == 0) begin
+ next_scan_en = 1;
+ next_clk_cnt = 4;
+ next_state = FSM_ASSERT_SCAN_EN;
+ end else begin
+ next_clk_cnt = next_clk_cnt - 1;
+ end
+ FSM_ASSERT_SCAN_EN:
+ if(clk_cnt == 0) begin
+ next_scan_clk_enb = 1;
+ next_clk_cnt = cfg_chain_depth;
+ next_state = FSM_SCAN_SHIFT;
+ end else begin
+ next_clk_cnt = next_clk_cnt - 1;
+ end
+ FSM_SCAN_SHIFT:
+ if(clk_cnt == 0) begin
+ if(scan_pat_cnt == 0) begin
+ next_lbist_done = 1;
+ next_scan_mode = 0;
+ next_state = FSM_IDLE ;
+ end else begin
+ next_scan_pat_cnt= next_scan_pat_cnt-1;
+ next_scan_clk_enb= 0;
+ next_clk_cnt = 1;
+ next_state = FSM_DEASSERT_SCAN_EN;
+ end
+ end else begin
+ next_clk_cnt = next_clk_cnt - 1;
+ end
+ FSM_DEASSERT_SCAN_EN:
+ if(clk_cnt == 0) begin
+ next_scan_en = 0;
+ next_clk_cnt = 4;
+ next_state = FSM_DEASSERT_SCAN_CLK;
+ end else begin
+ next_clk_cnt = next_clk_cnt - 1;
+ end
+ FSM_DEASSERT_SCAN_CLK:
+ if(clk_cnt == 0) begin
+ next_scan_clk_enb= 1;
+ next_scan_en = 0;
+ next_clk_cnt = 0;
+ next_state = FSM_SCAN_CAPTURE;
+ end else begin
+ next_clk_cnt = next_clk_cnt - 1;
+ end
+ FSM_SCAN_CAPTURE: begin
+ next_scan_clk_enb= 0;
+ next_scan_en = 0;
+ next_clk_cnt = 4;
+ next_state = FSM_IDLE_WAIT;
+ end
+ endcase
+
+end
+
+
+//--------------------------------
+// Scan clock generation
+//--------------------------------
+clk_gate u_scan_gate (
+
+ .GCLK (scan_clk),
+ .TE (1'b0),
+ .EN (scan_clk_enb),
+ .CLK (mclk)
+ );
+
+
+
+//--------------------------------
+// Scan Pattern Generation
+//--------------------------------
+logic [31:0] tx_crc_out;
+
+assign scan_in = (clk_cnt[1:0] == 2'b00) ? tx_crc_out[7:0] :
+ (clk_cnt[1:0] == 2'b01) ? tx_crc_out[15:8] :
+ (clk_cnt[1:0] == 2'b10) ? tx_crc_out[23:16] : tx_crc_out[31:24];
+
+
+// Run CRC at SCAN SHIFT PHASE at every once in 4 cycles
+wire crc_tx_run = (state == FSM_SCAN_SHIFT) & (clk_cnt[1:0] == 2'b11);
+wire crc_rx_run = (cfg_lbist_rsb) ? r_sshift_done & (state == FSM_SCAN_SHIFT) & (clk_cnt[1:0] == 2'b11):
+ (state == FSM_SCAN_SHIFT) & (clk_cnt[1:0] == 2'b11);
+wire crc_clear = lbist_pos_edge;
+
+crc_32 u_tx_crc(
+ // List of outputs.
+ .crc_out (tx_crc_out),
+
+ // List of inputs
+ .run (crc_tx_run), // when asserted, crc is generated
+ .clear (crc_clear), // When asserted crc is re-initialized
+ .data_in (8'h0),
+ .mclk (mclk_skew),
+ .reset_n (rst_n)
+ );
+
+crc_32 u_rx_crc(
+ // List of outputs.
+ .crc_out (lbist_sig),
+
+ // List of inputs
+ .run (crc_rx_run), // when asserted, crc is generated
+ .clear (crc_clear), // When asserted crc is re-initialized
+ .data_in (scan_out),
+ .mclk (mclk_skew),
+ .reset_n (rst_n)
+ );
+
+endmodule
diff --git a/verilog/rtl/lbist/src/lbist_reg.sv b/verilog/rtl/lbist/src/lbist_reg.sv
new file mode 100644
index 0000000..9b02226
--- /dev/null
+++ b/verilog/rtl/lbist/src/lbist_reg.sv
@@ -0,0 +1,218 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Logic Bist register ////
+//// ////
+//// This file is part of the logic bist project ////
+//// https://github.com/dineshannayya/logic_bist.git ////
+//// ////
+//// Description ////
+//// This block manges all the LBIST Register and Status ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 29 Nov 2021 Dinesh A ////
+//// Initial version ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module lbist_reg (
+
+ input logic mclk,
+ input logic reset_n,
+
+
+ // Reg Bus Interface Signal
+ input logic reg_cs,
+ input logic reg_wr,
+ input logic [1:0] reg_addr,
+ input logic [31:0] reg_wdata,
+ input logic [3:0] reg_be,
+
+ // Outputs
+ output logic [31:0] reg_rdata,
+ output logic reg_ack,
+
+ // BIST I/F
+ output logic cfg_lbist_rst,
+ output logic cfg_lbist_start, // lbist start
+ output logic cfg_lbist_rsb, // lbist reset scan compare bypass
+ output logic [15:0] cfg_lbist_pat, // Total Scan pattern to be run
+ output logic [15:0] cfg_chain_depth, // Scan Chain Depth
+
+
+ input logic lbist_done,
+ input logic [31:0] lbist_sig
+
+
+ );
+
+
+
+//-----------------------------------------------------------------------
+// Internal Wire Declarations
+//-----------------------------------------------------------------------
+
+logic sw_rd_en ;
+logic sw_wr_en ;
+logic [1:0] sw_addr ; // addressing 16 registers
+logic [3:0] wr_be ;
+logic [31:0] sw_reg_wdata;
+
+
+
+logic [31:0] reg_0; // Reg 0
+logic [31:0] reg_1; // Reg 1
+
+logic [31:0] reg_out;
+
+//-----------------------------------------------------------------------
+// Main code starts here
+//-----------------------------------------------------------------------
+
+
+//-----------------------------------------------------------------------
+// register read enable and write enable decoding logic
+//-----------------------------------------------------------------------
+
+assign sw_addr = reg_addr [1:0];
+assign sw_rd_en = reg_cs & !reg_wr;
+assign sw_wr_en = reg_cs & reg_wr;
+assign wr_be = reg_be;
+assign sw_reg_wdata = reg_wdata;
+
+
+wire sw_wr_en_0 = sw_wr_en & (sw_addr == 2'h0);
+wire sw_rd_en_0 = sw_rd_en & (sw_addr == 2'h0);
+wire sw_wr_en_1 = sw_wr_en & (sw_addr == 2'h1);
+wire sw_rd_en_1 = sw_rd_en & (sw_addr == 2'h1);
+wire sw_wr_en_2 = sw_wr_en & (sw_addr == 2'h2);
+wire sw_rd_en_2 = sw_rd_en & (sw_addr == 2'h2);
+wire sw_wr_en_3 = sw_wr_en & (sw_addr == 2'h3);
+wire sw_rd_en_3 = sw_rd_en & (sw_addr == 2'h3);
+
+logic wb_req;
+
+always_ff @(negedge reset_n or posedge mclk) begin
+ if ( reset_n == 1'b0 ) begin
+ wb_req <= '0;
+ end else begin
+ wb_req <= reg_cs && (reg_ack == 0) ;
+ end
+end
+
+
+always @ (posedge mclk or negedge reset_n)
+begin : preg_out_Seq
+ if (reset_n == 1'b0) begin
+ reg_rdata <= 'h0;
+ reg_ack <= 1'b0;
+ end else if (reg_cs && !reg_ack) begin
+ reg_rdata <= reg_out ;
+ reg_ack <= 1'b1;
+ end else begin
+ reg_ack <= 1'b0;
+ end
+end
+
+always @( *)
+begin
+ reg_out [31:0] = 32'h0;
+
+ case (sw_addr [1:0])
+ 2'b00 : reg_out [31:0] = reg_0;
+ 2'b01 : reg_out [31:0] = reg_1;
+ 2'b10 : reg_out [31:0] = lbist_sig;
+ default : reg_out [31:0] = 'h0;
+ endcase
+end
+
+
+//-----------------------------------------------------------------------
+// Individual register assignments
+//-----------------------------------------------------------------------
+//-----------------------------------------------------------------------
+// reg-0
+// -----------------------------------------------------------------
+generic_register #(8,8'h0 ) u_reg0_be0 (
+ .we ({8{sw_wr_en_0 &
+ wr_be[0] }} ),
+ .data_in (sw_reg_wdata[7:0] ),
+ .reset_n (reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (reg_0[7:0] )
+ );
+
+
+assign cfg_lbist_rst = reg_0[0];
+assign cfg_lbist_start = reg_0[1];
+assign cfg_lbist_rsb = reg_0[2];
+assign reg_0[31:8] = {lbist_done,23'b0};
+
+//--------------------------------------------
+// Reg-1
+// ------------------------------------------
+
+assign cfg_chain_depth = reg_1[15:0];
+assign cfg_lbist_pat = reg_1[31:16];
+
+gen_32b_reg #(32'h4C66_8354) u_reg_1 (
+ //List of Inputs
+ .reset_n (reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_1 ),
+ .we (wr_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_1 )
+ );
+endmodule
diff --git a/verilog/rtl/lbist/src/lbist_top.sv b/verilog/rtl/lbist/src/lbist_top.sv
new file mode 100644
index 0000000..caffbb7
--- /dev/null
+++ b/verilog/rtl/lbist/src/lbist_top.sv
@@ -0,0 +1,184 @@
+module lbist_top
+ #(parameter SCW = 8 // SCAN CHAIN WIDTH
+ )
+ (
+ // Wishbone Reg I/F
+ input logic wb_clk,
+ input logic wb_rst_n,
+ input logic wb_cs,
+ input logic [1:0] wb_addr,
+ input logic wb_wr,
+ input logic [31:0] wb_wdata,
+ input logic [3:0] wb_be,
+
+ output logic [31:0] wb_rdata,
+ output logic wb_ack,
+ output logic wb_err,
+
+ // LBIST I/F
+ input logic lbist_clk,
+ input logic lbist_clk_skew, // bist clock with additional clock skew
+
+
+ // Scan Control Signal
+ output logic scan_clk,
+ output logic scan_rst_n,
+ output logic scan_mode,
+ output logic scan_en,
+ output logic [SCW-1:0] scan_in,
+ input logic [SCW-1:0] scan_out
+
+);
+
+//----------------------------------------------
+// Local Decleration
+// ---------------------------------------------
+
+logic lbist_rst_n ;
+logic lbist_reg_cs ;
+logic [1:0] lbist_reg_addr ;
+logic lbist_reg_wr ;
+logic [31:0] lbist_reg_wdata ;
+logic [3:0] lbist_reg_be ;
+
+logic [31:0] lbist_reg_rdata ;
+logic lbist_reg_ack ;
+
+logic cfg_lbist_srst ;
+logic cfg_lbist_start ; // lbist start
+logic cfg_lbist_rsb ; // lbist reset scan compare bypass
+
+logic [15:0] cfg_lbist_pat ; // Total Scan pattern to be run
+logic [15:0] cfg_chain_depth ; // Scan chain depth
+
+
+logic lbist_done ;
+logic [31:0] lbist_sig ;
+
+//------------------------------------
+// LBIST Reset Synchronizer
+// -----------------------------------
+
+reset_sync u_lbist_reset (
+ .scan_mode (1'b0 ),
+ .dclk (lbist_clk_skew), // Destination clock domain
+ .arst_n (wb_rst_n ), // active low async reset
+ .srst_n (lbist_rst_n )
+ );
+
+// -------------------------------------------------
+// Wishbone to LBIST register Synchronizer
+// ------------------------------------------------
+
+async_reg_bus #(.AW(2)) u_async_reg (
+ // Initiator declartion
+ .in_clk (wb_clk),
+ .in_reset_n (wb_rst_n),
+ // Reg Bus Master
+ // outputs
+ .in_reg_rdata (wb_rdata),
+ .in_reg_ack (wb_ack),
+ .in_reg_timeout (wb_err),
+
+ // Inputs
+ .in_reg_cs (wb_cs),
+ .in_reg_addr (wb_addr),
+ .in_reg_wdata (wb_wdata),
+ .in_reg_wr (wb_wr),
+ .in_reg_be (wb_be),
+
+ // Target Declaration
+ .out_clk (lbist_clk_skew),
+ .out_reset_n (lbist_rst_n),
+ // Reg Bus Slave
+ // output
+ .out_reg_cs (lbist_reg_cs),
+ .out_reg_addr (lbist_reg_addr),
+ .out_reg_wdata (lbist_reg_wdata),
+ .out_reg_wr (lbist_reg_wr),
+ .out_reg_be (lbist_reg_be),
+
+ // Inputs
+ .out_reg_rdata (lbist_reg_rdata),
+ .out_reg_ack (lbist_reg_ack)
+ );
+
+//------------------------------
+// LBIST local Register
+// ----------------------------
+
+lbist_reg u_reg (
+ .mclk (lbist_clk_skew ),
+ .reset_n (lbist_rst_n ),
+
+
+ // Reg Bus Interface Signal
+ .reg_cs (lbist_reg_cs ),
+ .reg_wr (lbist_reg_wr ),
+ .reg_addr (lbist_reg_addr ),
+ .reg_wdata (lbist_reg_wdata ),
+ .reg_be (lbist_reg_be ),
+
+ // Outputs
+ .reg_rdata (lbist_reg_rdata ),
+ .reg_ack (lbist_reg_ack ),
+
+ // BIST I/F
+ .cfg_lbist_rst (cfg_lbist_srst ),
+ .cfg_lbist_start (cfg_lbist_start ), // lbist start
+ .cfg_lbist_rsb (cfg_lbist_rsb ), // lbist reset scan bypass
+ .cfg_lbist_pat (cfg_lbist_pat ), // Total Scan pattern to be run
+ .cfg_chain_depth (cfg_chain_depth ), // Scan Chain Depth
+
+
+ .lbist_done (lbist_done ),
+ .lbist_sig (lbist_sig )
+
+
+ );
+
+//-----------------------------------------------------
+// LBIST core manges all the scan sequence
+//-----------------------------------------------------
+
+lbist_core
+ #(.SCW(SCW) // SCAN CHAIN WIDTH
+ )
+
+ u_lbist_core (
+
+ .mclk (lbist_clk ),
+ .mclk_skew (lbist_clk_skew ),
+ .rst_n (lbist_rst_n ),
+ .srst (cfg_lbist_srst ), // software reset
+
+
+ // Reg Bus Interface Signal
+ .lbist_start (cfg_lbist_start ),// ltest start
+ .cfg_lbist_rsb (cfg_lbist_rsb ), // lbist reset scan bypass
+ .cfg_lbist_pat (cfg_lbist_pat ),// Total Scan pattern to be run
+ .cfg_chain_depth (cfg_chain_depth ), // Scan Chain Depth
+ .lbist_done (lbist_done ),// End of Ltest
+ .lbist_sig (lbist_sig ),// scan signature
+
+
+ // Scan Control Signal
+ .scan_clk (scan_clk ),
+ .scan_rst_n (scan_rst_n ),
+ .scan_mode (scan_mode ),
+ .scan_en (scan_en ),
+ .scan_in (scan_in ),
+ .scan_out (scan_out )
+
+);
+
+
+
+
+
+
+
+
+endmodule
+
+
diff --git a/verilog/rtl/lbist/src/run_compile b/verilog/rtl/lbist/src/run_compile
new file mode 100644
index 0000000..f2b14af
--- /dev/null
+++ b/verilog/rtl/lbist/src/run_compile
@@ -0,0 +1,2 @@
+iverilog lbist_top.sv ../../lib/crc_32.sv ../../lib/clk_gate.sv lbist_core.sv lbist_reg.sv ../../lib/registers.v ../../lib/async_reg_bus.sv ../../lib/reset_sync.sv -g2005-sv
+verilator -cc lbist_top.sv ../../lib/crc_32.sv ../../lib/clk_gate.sv lbist_core.sv lbist_reg.sv ../../lib/registers.v ../../lib/async_reg_bus.sv ../../lib/reset_sync.sv --top-module lbist_top
diff --git a/verilog/rtl/lib/async_fifo.sv b/verilog/rtl/lib/async_fifo.sv
new file mode 100755
index 0000000..fd59cfa
--- /dev/null
+++ b/verilog/rtl/lib/async_fifo.sv
@@ -0,0 +1,341 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+/*********************************************************************
+
+ ASYNC FIFO
+
+ This file is part of the sdram controller project
+ https://github.com/dineshannayya/yifive_r0.git
+ http://www.opencores.org/cores/sdr_ctrl/
+
+ Description: ASYNC FIFO
+
+ To Do:
+ nothing
+
+ Author(s): Dinesh Annayya, dinesha@opencores.org
+
+ Copyright (C) 2000 Authors and OPENCORES.ORG
+
+ This source file may be used and distributed without
+ restriction provided that this copyright statement is not
+ removed from the file and that any derivative work contains
+ the original copyright notice and the associated disclaimer.
+
+ This source file is free software; you can redistribute it
+ and/or modify it under the terms of the GNU Lesser General
+ Public License as published by the Free Software Foundation;
+ either version 2.1 of the License, or (at your option) any
+later version.
+
+ This source is distributed in the hope that it will be
+ useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+ PURPOSE. See the GNU Lesser General Public License for more
+ details.
+
+ You should have received a copy of the GNU Lesser General
+ Public License along with this source; if not, download it
+ from http://www.opencores.org/lgpl.shtml
+
+*******************************************************************/
+
+//-------------------------------------------
+// async FIFO
+//-----------------------------------------------
+//`timescale 1ns/1ps
+
+module async_fifo (wr_clk,
+ wr_reset_n,
+ wr_en,
+ wr_data,
+ full, // sync'ed to wr_clk
+ afull, // sync'ed to wr_clk
+ rd_clk,
+ rd_reset_n,
+ rd_en,
+ empty, // sync'ed to rd_clk
+ aempty, // sync'ed to rd_clk
+ rd_data);
+
+ parameter W = 4'd8;
+ parameter DP = 3'd4;
+ parameter WR_FAST = 1'b1;
+ parameter RD_FAST = 1'b1;
+ parameter FULL_DP = DP;
+ parameter EMPTY_DP = 1'b0;
+
+ parameter AW = (DP == 2) ? 1 :
+ (DP == 4) ? 2 :
+ (DP == 8) ? 3 :
+ (DP == 16) ? 4 :
+ (DP == 32) ? 5 :
+ (DP == 64) ? 6 :
+ (DP == 128) ? 7 :
+ (DP == 256) ? 8 : 0;
+
+ output [W-1 : 0] rd_data;
+ input [W-1 : 0] wr_data;
+ input wr_clk, wr_reset_n, wr_en, rd_clk, rd_reset_n,
+ rd_en;
+ output full, empty;
+ output afull, aempty; // about full and about to empty
+
+
+ // synopsys translate_off
+
+ initial begin
+ if (AW == 0) begin
+ $display ("%m : ERROR!!! Fifo depth %d not in range 2 to 256", DP);
+ end // if (AW == 0)
+ end // initial begin
+
+ // synopsys translate_on
+
+ reg [W-1 : 0] mem[DP-1 : 0];
+
+ /*********************** write side ************************/
+ reg [AW:0] sync_rd_ptr_0, sync_rd_ptr_1;
+ wire [AW:0] sync_rd_ptr;
+ reg [AW:0] wr_ptr, grey_wr_ptr;
+ reg [AW:0] grey_rd_ptr;
+ reg full_q;
+ wire full_c;
+ wire afull_c;
+ wire [AW:0] wr_ptr_inc = wr_ptr + 1'b1;
+ wire [AW:0] wr_cnt = get_cnt(wr_ptr, sync_rd_ptr);
+
+ assign full_c = (wr_cnt == FULL_DP) ? 1'b1 : 1'b0;
+ assign afull_c = (wr_cnt == FULL_DP-1) ? 1'b1 : 1'b0;
+
+
+ always @(posedge wr_clk or negedge wr_reset_n) begin
+ if (!wr_reset_n) begin
+ wr_ptr <= 0;
+ grey_wr_ptr <= 0;
+ full_q <= 0;
+ end
+ else if (wr_en) begin
+ wr_ptr <= wr_ptr_inc;
+ grey_wr_ptr <= bin2grey(wr_ptr_inc);
+ if (wr_cnt == (FULL_DP-1)) begin
+ full_q <= 1'b1;
+ end
+ end
+ else begin
+ if (full_q && (wr_cnt<FULL_DP)) begin
+ full_q <= 1'b0;
+ end
+ end
+ end
+
+ assign full = (WR_FAST == 1) ? full_c : full_q;
+ assign afull = afull_c;
+
+ always @(posedge wr_clk) begin
+ if (wr_en) begin
+ mem[wr_ptr[AW-1:0]] <= wr_data;
+ end
+ end
+
+ wire [AW:0] grey_rd_ptr_dly ;
+ assign #1 grey_rd_ptr_dly = grey_rd_ptr;
+
+ // read pointer synchronizer
+ always @(posedge wr_clk or negedge wr_reset_n) begin
+ if (!wr_reset_n) begin
+ sync_rd_ptr_0 <= 0;
+ sync_rd_ptr_1 <= 0;
+ end
+ else begin
+ sync_rd_ptr_0 <= grey_rd_ptr_dly;
+ sync_rd_ptr_1 <= sync_rd_ptr_0;
+ end
+ end
+
+ assign sync_rd_ptr = grey2bin(sync_rd_ptr_1);
+
+ /************************ read side *****************************/
+ reg [AW:0] sync_wr_ptr_0, sync_wr_ptr_1;
+ wire [AW:0] sync_wr_ptr;
+ reg [AW:0] rd_ptr;
+ reg empty_q;
+ wire empty_c;
+ wire aempty_c;
+ wire [AW:0] rd_ptr_inc = rd_ptr + 1'b1;
+ wire [AW:0] sync_wr_ptr_dec = sync_wr_ptr - 1'b1;
+ wire [AW:0] rd_cnt = get_cnt(sync_wr_ptr, rd_ptr);
+
+ assign empty_c = (rd_cnt == 0) ? 1'b1 : 1'b0;
+ assign aempty_c = (rd_cnt == 1) ? 1'b1 : 1'b0;
+
+ always @(posedge rd_clk or negedge rd_reset_n) begin
+ if (!rd_reset_n) begin
+ rd_ptr <= 0;
+ grey_rd_ptr <= 0;
+ empty_q <= 1'b1;
+ end
+ else begin
+ if (rd_en) begin
+ rd_ptr <= rd_ptr_inc;
+ grey_rd_ptr <= bin2grey(rd_ptr_inc);
+ if (rd_cnt==(EMPTY_DP+1)) begin
+ empty_q <= 1'b1;
+ end
+ end
+ else begin
+ if (empty_q && (rd_cnt!=EMPTY_DP)) begin
+ empty_q <= 1'b0;
+ end
+ end
+ end
+ end
+
+ assign empty = (RD_FAST == 1) ? empty_c : empty_q;
+ assign aempty = aempty_c;
+
+ reg [W-1 : 0] rd_data_q;
+
+ wire [W-1 : 0] rd_data_c = mem[rd_ptr[AW-1:0]];
+ always @(posedge rd_clk) begin
+ rd_data_q <= rd_data_c;
+ end
+ assign rd_data = (RD_FAST == 1) ? rd_data_c : rd_data_q;
+
+ wire [AW:0] grey_wr_ptr_dly ;
+ assign #1 grey_wr_ptr_dly = grey_wr_ptr;
+
+ // write pointer synchronizer
+ always @(posedge rd_clk or negedge rd_reset_n) begin
+ if (!rd_reset_n) begin
+ sync_wr_ptr_0 <= 0;
+ sync_wr_ptr_1 <= 0;
+ end
+ else begin
+ sync_wr_ptr_0 <= grey_wr_ptr_dly;
+ sync_wr_ptr_1 <= sync_wr_ptr_0;
+ end
+ end
+ assign sync_wr_ptr = grey2bin(sync_wr_ptr_1);
+
+
+/************************ functions ******************************/
+function [AW:0] bin2grey;
+input [AW:0] bin;
+reg [8:0] bin_8;
+reg [8:0] grey_8;
+begin
+ bin_8 = bin;
+ grey_8[1:0] = do_grey(bin_8[2:0]);
+ grey_8[3:2] = do_grey(bin_8[4:2]);
+ grey_8[5:4] = do_grey(bin_8[6:4]);
+ grey_8[7:6] = do_grey(bin_8[8:6]);
+ grey_8[8] = bin_8[8];
+ bin2grey = grey_8;
+end
+endfunction
+
+function [AW:0] grey2bin;
+input [AW:0] grey;
+reg [8:0] grey_8;
+reg [8:0] bin_8;
+begin
+ grey_8 = grey;
+ bin_8[8] = grey_8[8];
+ bin_8[7:6] = do_bin({bin_8[8], grey_8[7:6]});
+ bin_8[5:4] = do_bin({bin_8[6], grey_8[5:4]});
+ bin_8[3:2] = do_bin({bin_8[4], grey_8[3:2]});
+ bin_8[1:0] = do_bin({bin_8[2], grey_8[1:0]});
+ grey2bin = bin_8;
+end
+endfunction
+
+
+function [1:0] do_grey;
+input [2:0] bin;
+begin
+ if (bin[2]) begin // do reverse grey
+ case (bin[1:0])
+ 2'b00: do_grey = 2'b10;
+ 2'b01: do_grey = 2'b11;
+ 2'b10: do_grey = 2'b01;
+ 2'b11: do_grey = 2'b00;
+ endcase
+ end
+ else begin
+ case (bin[1:0])
+ 2'b00: do_grey = 2'b00;
+ 2'b01: do_grey = 2'b01;
+ 2'b10: do_grey = 2'b11;
+ 2'b11: do_grey = 2'b10;
+ endcase
+ end
+end
+endfunction
+
+function [1:0] do_bin;
+input [2:0] grey;
+begin
+ if (grey[2]) begin // actually bin[2]
+ case (grey[1:0])
+ 2'b10: do_bin = 2'b00;
+ 2'b11: do_bin = 2'b01;
+ 2'b01: do_bin = 2'b10;
+ 2'b00: do_bin = 2'b11;
+ endcase
+ end
+ else begin
+ case (grey[1:0])
+ 2'b00: do_bin = 2'b00;
+ 2'b01: do_bin = 2'b01;
+ 2'b11: do_bin = 2'b10;
+ 2'b10: do_bin = 2'b11;
+ endcase
+ end
+end
+endfunction
+
+function [AW:0] get_cnt;
+input [AW:0] wr_ptr, rd_ptr;
+begin
+ if (wr_ptr >= rd_ptr) begin
+ get_cnt = (wr_ptr - rd_ptr);
+ end
+ else begin
+ get_cnt = DP*2 - (rd_ptr - wr_ptr);
+ end
+end
+endfunction
+
+// synopsys translate_off
+always @(posedge wr_clk) begin
+ if (wr_en && full) begin
+ $display($time, "%m Error! afifo overflow!");
+ $stop;
+ end
+end
+
+always @(posedge rd_clk) begin
+ if (rd_en && empty) begin
+ $display($time, "%m error! afifo underflow!");
+ $stop;
+ end
+end
+// synopsys translate_on
+
+endmodule
diff --git a/verilog/rtl/lib/async_fifo.v b/verilog/rtl/lib/async_fifo.v
new file mode 100755
index 0000000..2233fb1
--- /dev/null
+++ b/verilog/rtl/lib/async_fifo.v
@@ -0,0 +1,385 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores common library Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Mar 2, 2011 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+//-------------------------------------------
+// async_fifo:: async FIFO
+// Following two ports are newly added
+// 1. At write clock domain:
+// wr_total_free_space --> Indicate total free transfer available
+// 2. At read clock domain:
+// rd_total_aval --> Indicate total no of transfer available
+//-----------------------------------------------
+
+module async_fifo (wr_clk,
+ wr_reset_n,
+ wr_en,
+ wr_data,
+ full, // sync'ed to wr_clk
+ afull, // sync'ed to wr_clk
+ wr_total_free_space,
+ rd_clk,
+ rd_reset_n,
+ rd_en,
+ empty, // sync'ed to rd_clk
+ aempty, // sync'ed to rd_clk
+ rd_total_aval,
+ rd_data);
+
+ parameter W = 4'd8;
+ parameter DP = 3'd4;
+ parameter WR_FAST = 1'b1;
+ parameter RD_FAST = 1'b1;
+ parameter FULL_DP = DP;
+ parameter EMPTY_DP = 1'b0;
+
+ parameter AW = (DP == 2) ? 1 :
+ (DP == 4) ? 2 :
+ (DP == 8) ? 3 :
+ (DP == 16) ? 4 :
+ (DP == 32) ? 5 :
+ (DP == 64) ? 6 :
+ (DP == 128) ? 7 :
+ (DP == 256) ? 8 : 0;
+
+ output [W-1 : 0] rd_data;
+ input [W-1 : 0] wr_data;
+ input wr_clk, wr_reset_n, wr_en, rd_clk, rd_reset_n,
+ rd_en;
+ output full, empty;
+ output afull, aempty; // about full and about to empty
+ output [AW:0] wr_total_free_space; // Total Number of free space aval
+ // w.r.t write clk
+ // note: Without accounting byte enables
+ output [AW:0] rd_total_aval; // Total Number of words avaialble
+ // w.r.t rd clock,
+ // note: Without accounting byte enables
+ // synopsys translate_off
+
+ initial begin
+ if (AW == 0) begin
+ $display ("%m : ERROR!!! Fifo depth %d not in range 2 to 256", DP);
+ end // if (AW == 0)
+ end // initial begin
+
+ // synopsys translate_on
+ reg [W-1 : 0] mem[DP-1 : 0];
+
+ /*********************** write side ************************/
+ reg [AW:0] sync_rd_ptr_0, sync_rd_ptr_1;
+ wire [AW:0] sync_rd_ptr;
+ reg [AW:0] wr_ptr, grey_wr_ptr;
+ reg [AW:0] grey_rd_ptr;
+ reg full_q;
+ wire full_c;
+ wire afull_c;
+ wire [AW:0] wr_ptr_inc = wr_ptr + 1'b1;
+ wire [AW:0] wr_cnt = get_cnt(wr_ptr, sync_rd_ptr);
+
+ assign full_c = (wr_cnt == FULL_DP) ? 1'b1 : 1'b0;
+ assign afull_c = (wr_cnt == FULL_DP-1) ? 1'b1 : 1'b0;
+
+ //--------------------------
+ // Shows total number of words
+ // of free space available w.r.t write clock
+ //---------------------------
+ assign wr_total_free_space = FULL_DP - wr_cnt;
+
+ always @(posedge wr_clk or negedge wr_reset_n) begin
+ if (!wr_reset_n) begin
+ wr_ptr <= 0;
+ grey_wr_ptr <= 0;
+ full_q <= 0;
+ end
+ else if (wr_en) begin
+ wr_ptr <= wr_ptr_inc;
+ grey_wr_ptr <= bin2grey(wr_ptr_inc);
+ if (wr_cnt == (FULL_DP-1)) begin
+ full_q <= 1'b1;
+ end
+ end
+ else begin
+ if (full_q && (wr_cnt<FULL_DP)) begin
+ full_q <= 1'b0;
+ end
+ end
+ end
+
+ assign full = (WR_FAST == 1) ? full_c : full_q;
+ assign afull = afull_c;
+
+ always @(posedge wr_clk) begin
+ if (wr_en) begin
+ mem[wr_ptr[AW-1:0]] <= wr_data;
+ end
+ end
+
+ wire [AW:0] grey_rd_ptr_dly ;
+ assign #1 grey_rd_ptr_dly = grey_rd_ptr;
+
+ // read pointer synchronizer
+ always @(posedge wr_clk or negedge wr_reset_n) begin
+ if (!wr_reset_n) begin
+ sync_rd_ptr_0 <= 0;
+ sync_rd_ptr_1 <= 0;
+ end
+ else begin
+ sync_rd_ptr_0 <= grey_rd_ptr_dly;
+ sync_rd_ptr_1 <= sync_rd_ptr_0;
+ end
+ end
+
+ assign sync_rd_ptr = grey2bin(sync_rd_ptr_1);
+
+ /************************ read side *****************************/
+ reg [AW:0] sync_wr_ptr_0, sync_wr_ptr_1;
+ wire [AW:0] sync_wr_ptr;
+ reg [AW:0] rd_ptr;
+ reg empty_q;
+ wire empty_c;
+ wire aempty_c;
+ wire [AW:0] rd_ptr_inc = rd_ptr + 1'b1;
+ wire [AW:0] sync_wr_ptr_dec = sync_wr_ptr - 1'b1;
+ wire [AW:0] rd_cnt = get_cnt(sync_wr_ptr, rd_ptr);
+
+ assign empty_c = (rd_cnt == 0) ? 1'b1 : 1'b0;
+ assign aempty_c = (rd_cnt == 1) ? 1'b1 : 1'b0;
+ //--------------------------
+ // Shows total number of words
+ // space available w.r.t write clock
+ //---------------------------
+ assign rd_total_aval = rd_cnt;
+
+ always @(posedge rd_clk or negedge rd_reset_n) begin
+ if (!rd_reset_n) begin
+ rd_ptr <= 0;
+ grey_rd_ptr <= 0;
+ empty_q <= 1'b1;
+ end
+ else begin
+ if (rd_en) begin
+ rd_ptr <= rd_ptr_inc;
+ grey_rd_ptr <= bin2grey(rd_ptr_inc);
+ if (rd_cnt==(EMPTY_DP+1)) begin
+ empty_q <= 1'b1;
+ end
+ end
+ else begin
+ if (empty_q && (rd_cnt!=EMPTY_DP)) begin
+ empty_q <= 1'b0;
+ end
+ end
+ end
+ end
+
+ assign empty = (RD_FAST == 1) ? empty_c : empty_q;
+ assign aempty = aempty_c;
+
+ assign rd_data = mem[rd_ptr[AW-1:0]];
+
+ wire [AW:0] grey_wr_ptr_dly ;
+ assign #1 grey_wr_ptr_dly = grey_wr_ptr;
+
+ // write pointer synchronizer
+ always @(posedge rd_clk or negedge rd_reset_n) begin
+ if (!rd_reset_n) begin
+ sync_wr_ptr_0 <= 0;
+ sync_wr_ptr_1 <= 0;
+ end
+ else begin
+ sync_wr_ptr_0 <= grey_wr_ptr_dly;
+ sync_wr_ptr_1 <= sync_wr_ptr_0;
+ end
+ end
+ assign sync_wr_ptr = grey2bin(sync_wr_ptr_1);
+
+
+/************************ functions ******************************/
+function [AW:0] bin2grey;
+input [AW:0] bin;
+reg [8:0] bin_8;
+reg [8:0] grey_8;
+begin
+ bin_8 = bin;
+ grey_8[1:0] = do_grey(bin_8[2:0]);
+ grey_8[3:2] = do_grey(bin_8[4:2]);
+ grey_8[5:4] = do_grey(bin_8[6:4]);
+ grey_8[7:6] = do_grey(bin_8[8:6]);
+ grey_8[8] = bin_8[8];
+ bin2grey = grey_8;
+end
+endfunction
+
+function [AW:0] grey2bin;
+input [AW:0] grey;
+reg [8:0] grey_8;
+reg [8:0] bin_8;
+begin
+ grey_8 = grey;
+ bin_8[8] = grey_8[8];
+ bin_8[7:6] = do_bin({bin_8[8], grey_8[7:6]});
+ bin_8[5:4] = do_bin({bin_8[6], grey_8[5:4]});
+ bin_8[3:2] = do_bin({bin_8[4], grey_8[3:2]});
+ bin_8[1:0] = do_bin({bin_8[2], grey_8[1:0]});
+ grey2bin = bin_8;
+end
+endfunction
+
+
+function [1:0] do_grey;
+input [2:0] bin;
+begin
+ if (bin[2]) begin // do reverse grey
+ case (bin[1:0])
+ 2'b00: do_grey = 2'b10;
+ 2'b01: do_grey = 2'b11;
+ 2'b10: do_grey = 2'b01;
+ 2'b11: do_grey = 2'b00;
+ endcase
+ end
+ else begin
+ case (bin[1:0])
+ 2'b00: do_grey = 2'b00;
+ 2'b01: do_grey = 2'b01;
+ 2'b10: do_grey = 2'b11;
+ 2'b11: do_grey = 2'b10;
+ endcase
+ end
+end
+endfunction
+
+function [1:0] do_bin;
+input [2:0] grey;
+begin
+ if (grey[2]) begin // actually bin[2]
+ case (grey[1:0])
+ 2'b10: do_bin = 2'b00;
+ 2'b11: do_bin = 2'b01;
+ 2'b01: do_bin = 2'b10;
+ 2'b00: do_bin = 2'b11;
+ endcase
+ end
+ else begin
+ case (grey[1:0])
+ 2'b00: do_bin = 2'b00;
+ 2'b01: do_bin = 2'b01;
+ 2'b11: do_bin = 2'b10;
+ 2'b10: do_bin = 2'b11;
+ endcase
+ end
+end
+endfunction
+
+function [AW:0] get_cnt;
+input [AW:0] wr_ptr, rd_ptr;
+begin
+ if (wr_ptr >= rd_ptr) begin
+ get_cnt = (wr_ptr - rd_ptr);
+ end
+ else begin
+ get_cnt = DP*2 - (rd_ptr - wr_ptr);
+ end
+end
+endfunction
+
+// synopsys translate_off
+always @(posedge wr_clk) begin
+ if (wr_en && full) begin
+ $display($time, "%m Error! afifo overflow!");
+ $stop;
+ end
+end
+
+always @(posedge rd_clk) begin
+ if (rd_en && empty) begin
+ $display($time, "%m error! afifo underflow!");
+ $stop;
+ end
+end
+
+// gray code monitor
+reg [AW:0] last_gwr_ptr;
+always @(posedge wr_clk or negedge wr_reset_n) begin
+ if (!wr_reset_n) begin
+ last_gwr_ptr <= #1 0;
+ end
+ else if (last_gwr_ptr !== grey_wr_ptr) begin
+ check_ptr_chg(last_gwr_ptr, grey_wr_ptr);
+ last_gwr_ptr <= #1 grey_wr_ptr;
+ end
+end
+
+reg [AW:0] last_grd_ptr;
+always @(posedge rd_clk or negedge rd_reset_n) begin
+ if (!rd_reset_n) begin
+ last_grd_ptr <= #1 0;
+ end
+ else if (last_grd_ptr !== grey_rd_ptr) begin
+ check_ptr_chg(last_grd_ptr, grey_rd_ptr);
+ last_grd_ptr <= #1 grey_rd_ptr;
+ end
+end
+
+task check_ptr_chg;
+input [AW:0] last_ptr;
+input [AW:0] cur_ptr;
+integer i;
+integer ptr_diff;
+begin
+ ptr_diff = 0;
+ for (i=0; i<= AW; i=i+ 1'b1) begin
+ if (last_ptr[i] != cur_ptr[i]) begin
+ ptr_diff = ptr_diff + 1'b1;
+ end
+ end
+ if (ptr_diff !== 1) begin
+ $display($time, "%m, ERROR! async fifo ptr has changed more than noe bit, last=%h, cur=%h",
+ last_ptr, cur_ptr);
+ $stop;
+ end
+end
+endtask
+ // synopsys translate_on
+
+endmodule
diff --git a/verilog/rtl/lib/async_fifo_th.sv b/verilog/rtl/lib/async_fifo_th.sv
new file mode 100755
index 0000000..05860f8
--- /dev/null
+++ b/verilog/rtl/lib/async_fifo_th.sv
@@ -0,0 +1,404 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// OMS 8051 cores common library Module ////
+//// ////
+//// This file is part of the OMS 8051 cores project ////
+//// https://github.com/dineshannayya/yifive_r0.git ////
+//// http://www.opencores.org/cores/oms8051mini/ ////
+//// ////
+//// Description ////
+//// Async Fifo with threshold tracking/status ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Nov 26, 2016 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+//-------------------------------------------
+// async_fifo:: async FIFO
+// Following two ports are newly added
+// 1. At write clock domain:
+// wr_total_free_space --> Indicate total free transfer available
+// 2. At read clock domain:
+// rd_total_aval --> Indicate total no of transfer available
+//-----------------------------------------------
+
+module async_fifo_th (
+ wr_clk,
+ wr_reset_n,
+ wr_en,
+ wr_data,
+ full, // sync'ed to wr_clk
+ afull, // sync'ed to wr_clk
+ wr_total_free_space,
+ rd_clk,
+ rd_reset_n,
+ rd_en,
+ empty, // sync'ed to rd_clk
+ aempty, // sync'ed to rd_clk
+ rd_total_aval,
+ rd_data);
+
+ parameter W = 4'd8;
+ parameter DP = 3'd4;
+ parameter WR_FAST = 1'b1;
+ parameter RD_FAST = 1'b1;
+ parameter FULL_DP = DP;
+ parameter EMPTY_DP = 1'b0;
+
+ parameter AW = (DP == 2) ? 1 :
+ (DP == 4) ? 2 :
+ (DP == 8) ? 3 :
+ (DP == 16) ? 4 :
+ (DP == 32) ? 5 :
+ (DP == 64) ? 6 :
+ (DP == 128) ? 7 :
+ (DP == 256) ? 8 : 0;
+
+ output [W-1 : 0] rd_data;
+ input [W-1 : 0] wr_data;
+ input wr_clk, wr_reset_n, wr_en, rd_clk, rd_reset_n,
+ rd_en;
+ output full, empty;
+ output afull, aempty; // about full and about to empty
+ output [AW:0] wr_total_free_space; // Total Number of free space aval
+ // w.r.t write clk
+ // note: Without accounting byte enables
+ output [AW:0] rd_total_aval; // Total Number of words avaialble
+ // w.r.t rd clock,
+ // note: Without accounting byte enables
+ // synopsys translate_off
+
+ initial begin
+ if (AW == 0) begin
+ $display ("%m : ERROR!!! Fifo depth %d not in range 2 to 256", DP);
+ end // if (AW == 0)
+ end // initial begin
+
+ // synopsys translate_on
+ reg [W-1 : 0] mem[DP-1 : 0];
+
+ /*********************** write side ************************/
+ reg [AW:0] sync_rd_ptr_0, sync_rd_ptr_1;
+ wire [AW:0] sync_rd_ptr;
+ reg [AW:0] wr_ptr, grey_wr_ptr;
+ reg [AW:0] grey_rd_ptr;
+ reg full_q;
+ wire full_c;
+ wire afull_c;
+ wire [AW:0] wr_ptr_inc = wr_ptr + 1'b1;
+ wire [AW:0] wr_cnt = get_cnt(wr_ptr, sync_rd_ptr);
+
+ assign full_c = (wr_cnt == FULL_DP) ? 1'b1 : 1'b0;
+ assign afull_c = (wr_cnt == FULL_DP-1) ? 1'b1 : 1'b0;
+
+ //--------------------------
+ // Shows total number of words
+ // of free space available w.r.t write clock
+ //---------------------------
+ assign wr_total_free_space = FULL_DP - wr_cnt;
+
+ always @(posedge wr_clk or negedge wr_reset_n) begin
+ if (!wr_reset_n) begin
+ wr_ptr <= 0;
+ grey_wr_ptr <= 0;
+ full_q <= 0;
+ end
+ else if (wr_en) begin
+ wr_ptr <= wr_ptr_inc;
+ grey_wr_ptr <= bin2grey(wr_ptr_inc);
+ if (wr_cnt == (FULL_DP-1)) begin
+ full_q <= 1'b1;
+ end
+ end
+ else begin
+ if (full_q && (wr_cnt<FULL_DP)) begin
+ full_q <= 1'b0;
+ end
+ end
+ end
+
+ assign full = (WR_FAST == 1) ? full_c : full_q;
+ assign afull = afull_c;
+
+ always @(posedge wr_clk) begin
+ if (wr_en) begin
+ mem[wr_ptr[AW-1:0]] <= wr_data;
+ end
+ end
+
+ wire [AW:0] grey_rd_ptr_dly ;
+ assign #1 grey_rd_ptr_dly = grey_rd_ptr;
+
+ // read pointer synchronizer
+ always @(posedge wr_clk or negedge wr_reset_n) begin
+ if (!wr_reset_n) begin
+ sync_rd_ptr_0 <= 0;
+ sync_rd_ptr_1 <= 0;
+ end
+ else begin
+ sync_rd_ptr_0 <= grey_rd_ptr_dly;
+ sync_rd_ptr_1 <= sync_rd_ptr_0;
+ end
+ end
+
+ assign sync_rd_ptr = grey2bin(sync_rd_ptr_1);
+
+ /************************ read side *****************************/
+ reg [AW:0] sync_wr_ptr_0, sync_wr_ptr_1;
+ wire [AW:0] sync_wr_ptr;
+ reg [AW:0] rd_ptr;
+ reg empty_q;
+ wire empty_c;
+ wire aempty_c;
+ wire [AW:0] rd_ptr_inc = rd_ptr + 1'b1;
+ wire [AW:0] sync_wr_ptr_dec = sync_wr_ptr - 1'b1;
+ wire [AW:0] rd_cnt = get_cnt(sync_wr_ptr, rd_ptr);
+
+ assign empty_c = (rd_cnt == 0) ? 1'b1 : 1'b0;
+ assign aempty_c = (rd_cnt == 1) ? 1'b1 : 1'b0;
+ //--------------------------
+ // Shows total number of words
+ // space available w.r.t write clock
+ //---------------------------
+ assign rd_total_aval = rd_cnt;
+
+ always @(posedge rd_clk or negedge rd_reset_n) begin
+ if (!rd_reset_n) begin
+ rd_ptr <= 0;
+ grey_rd_ptr <= 0;
+ empty_q <= 1'b1;
+ end
+ else begin
+ if (rd_en) begin
+ rd_ptr <= rd_ptr_inc;
+ grey_rd_ptr <= bin2grey(rd_ptr_inc);
+ if (rd_cnt==(EMPTY_DP+1)) begin
+ empty_q <= 1'b1;
+ end
+ end
+ else begin
+ if (empty_q && (rd_cnt!=EMPTY_DP)) begin
+ empty_q <= 1'b0;
+ end
+ end
+ end
+ end
+
+ assign empty = (RD_FAST == 1) ? empty_c : empty_q;
+ assign aempty = aempty_c;
+
+ assign rd_data = mem[rd_ptr[AW-1:0]];
+
+ wire [AW:0] grey_wr_ptr_dly ;
+ assign #1 grey_wr_ptr_dly = grey_wr_ptr;
+
+ // write pointer synchronizer
+ always @(posedge rd_clk or negedge rd_reset_n) begin
+ if (!rd_reset_n) begin
+ sync_wr_ptr_0 <= 0;
+ sync_wr_ptr_1 <= 0;
+ end
+ else begin
+ sync_wr_ptr_0 <= grey_wr_ptr_dly;
+ sync_wr_ptr_1 <= sync_wr_ptr_0;
+ end
+ end
+ assign sync_wr_ptr = grey2bin(sync_wr_ptr_1);
+
+
+/************************ functions ******************************/
+function [AW:0] bin2grey;
+input [AW:0] bin;
+reg [8:0] bin_8;
+reg [8:0] grey_8;
+begin
+ bin_8 = bin;
+ grey_8[1:0] = do_grey(bin_8[2:0]);
+ grey_8[3:2] = do_grey(bin_8[4:2]);
+ grey_8[5:4] = do_grey(bin_8[6:4]);
+ grey_8[7:6] = do_grey(bin_8[8:6]);
+ grey_8[8] = bin_8[8];
+ bin2grey = grey_8;
+end
+endfunction
+
+function [AW:0] grey2bin;
+input [AW:0] grey;
+reg [8:0] grey_8;
+reg [8:0] bin_8;
+begin
+ grey_8 = grey;
+ bin_8[8] = grey_8[8];
+ bin_8[7:6] = do_bin({bin_8[8], grey_8[7:6]});
+ bin_8[5:4] = do_bin({bin_8[6], grey_8[5:4]});
+ bin_8[3:2] = do_bin({bin_8[4], grey_8[3:2]});
+ bin_8[1:0] = do_bin({bin_8[2], grey_8[1:0]});
+ grey2bin = bin_8;
+end
+endfunction
+
+
+function [1:0] do_grey;
+input [2:0] bin;
+begin
+ if (bin[2]) begin // do reverse grey
+ case (bin[1:0])
+ 2'b00: do_grey = 2'b10;
+ 2'b01: do_grey = 2'b11;
+ 2'b10: do_grey = 2'b01;
+ 2'b11: do_grey = 2'b00;
+ endcase
+ end
+ else begin
+ case (bin[1:0])
+ 2'b00: do_grey = 2'b00;
+ 2'b01: do_grey = 2'b01;
+ 2'b10: do_grey = 2'b11;
+ 2'b11: do_grey = 2'b10;
+ endcase
+ end
+end
+endfunction
+
+function [1:0] do_bin;
+input [2:0] grey;
+begin
+ if (grey[2]) begin // actually bin[2]
+ case (grey[1:0])
+ 2'b10: do_bin = 2'b00;
+ 2'b11: do_bin = 2'b01;
+ 2'b01: do_bin = 2'b10;
+ 2'b00: do_bin = 2'b11;
+ endcase
+ end
+ else begin
+ case (grey[1:0])
+ 2'b00: do_bin = 2'b00;
+ 2'b01: do_bin = 2'b01;
+ 2'b11: do_bin = 2'b10;
+ 2'b10: do_bin = 2'b11;
+ endcase
+ end
+end
+endfunction
+
+function [AW:0] get_cnt;
+input [AW:0] wr_ptr, rd_ptr;
+begin
+ if (wr_ptr >= rd_ptr) begin
+ get_cnt = (wr_ptr - rd_ptr);
+ end
+ else begin
+ get_cnt = DP*2 - (rd_ptr - wr_ptr);
+ end
+end
+endfunction
+
+// synopsys translate_off
+always @(posedge wr_clk) begin
+ if (wr_en && full) begin
+ $display($time, "%m Error! afifo overflow!");
+ $stop;
+ end
+end
+
+always @(posedge rd_clk) begin
+ if (rd_en && empty) begin
+ $display($time, "%m error! afifo underflow!");
+ $stop;
+ end
+end
+
+// gray code monitor
+reg [AW:0] last_gwr_ptr;
+always @(posedge wr_clk or negedge wr_reset_n) begin
+ if (!wr_reset_n) begin
+ last_gwr_ptr <= #1 0;
+ end
+ else if (last_gwr_ptr !== grey_wr_ptr) begin
+ check_ptr_chg(last_gwr_ptr, grey_wr_ptr);
+ last_gwr_ptr <= #1 grey_wr_ptr;
+ end
+end
+
+reg [AW:0] last_grd_ptr;
+always @(posedge rd_clk or negedge rd_reset_n) begin
+ if (!rd_reset_n) begin
+ last_grd_ptr <= #1 0;
+ end
+ else if (last_grd_ptr !== grey_rd_ptr) begin
+ check_ptr_chg(last_grd_ptr, grey_rd_ptr);
+ last_grd_ptr <= #1 grey_rd_ptr;
+ end
+end
+
+task check_ptr_chg;
+input [AW:0] last_ptr;
+input [AW:0] cur_ptr;
+integer i;
+integer ptr_diff;
+begin
+ ptr_diff = 0;
+ for (i=0; i<= AW; i=i+ 1'b1) begin
+ if (last_ptr[i] != cur_ptr[i]) begin
+ ptr_diff = ptr_diff + 1'b1;
+ end
+ end
+ if (ptr_diff !== 1) begin
+ $display($time, "%m, ERROR! async fifo ptr has changed more than noe bit, last=%h, cur=%h",
+ last_ptr, cur_ptr);
+ $stop;
+ end
+end
+endtask
+ // synopsys translate_on
+
+endmodule
diff --git a/verilog/rtl/lib/async_reg_bus.sv b/verilog/rtl/lib/async_reg_bus.sv
new file mode 100644
index 0000000..2c02701
--- /dev/null
+++ b/verilog/rtl/lib/async_reg_bus.sv
@@ -0,0 +1,305 @@
+
+
+//----------------------------------------------------------------------------------------------
+// This block translate the Reg Bus transaction from in_clk clock domain to out_clk clock domain.
+// This block also generate and terminate the transfer if 512 cycle transaction is not completed
+// Assumption
+// 1. in_reg_cs will be asserted untill ack is received
+// 2. reg_addr/reg_wdata/reg_be will be available during reg_cs
+// 3. Ever after out_reg_ack de-asserted reg_rdata holds the old data
+//----------------------------------------------------------------------------------------------
+
+module async_reg_bus (
+ // Initiator declartion
+ in_clk ,
+ in_reset_n ,
+ // Reg Bus Master
+ // outputs
+ in_reg_rdata ,
+ in_reg_ack ,
+ in_reg_timeout ,
+
+ // Inputs
+ in_reg_cs ,
+ in_reg_addr ,
+ in_reg_wdata ,
+ in_reg_wr ,
+ in_reg_be ,
+
+ // Target Declaration
+ out_clk ,
+ out_reset_n ,
+ // Reg Bus Slave
+ // output
+ out_reg_cs ,
+ out_reg_addr ,
+ out_reg_wdata ,
+ out_reg_wr ,
+ out_reg_be ,
+
+ // Inputs
+ out_reg_rdata ,
+ out_reg_ack
+ );
+parameter AW = 26 ; // Address width
+parameter DW = 32 ; // DATA WIDTH
+parameter BEW = 4 ; // Byte enable width
+
+//----------------------------------------
+// Reg Bus reg inout declration
+//----------------------------------------
+input in_clk ; // Initiator domain clock
+input in_reset_n ; // Initiator domain reset
+
+input in_reg_cs ; // Initiator Chip Select
+input [AW-1:0] in_reg_addr ; // Address bus
+input [DW-1:0] in_reg_wdata ; // Write data
+input in_reg_wr ; // Read/write indication, 1-> write
+input [BEW-1:0] in_reg_be ; // Byte valid for write
+
+output [DW-1:0] in_reg_rdata ; // Read Data
+output in_reg_ack ; // Reg Access done
+output in_reg_timeout ; // Access error indication pulse
+ // Genererated if no target ack
+ // received
+ // within 512 cycle
+
+//---------------------------------------------
+// Reg Bus target inout declration
+//---------------------------------------------
+
+input out_clk ; // Target domain clock
+input out_reset_n ; // Traget domain reset
+
+input [DW-1:0] out_reg_rdata ; // Read data
+input out_reg_ack ; // target finish
+
+output out_reg_cs ; // Target Start indication
+output [AW-1:0] out_reg_addr ; // Target address
+output [DW-1:0] out_reg_wdata ; // Target write data
+output out_reg_wr ; // Target Read/write ind, 1-> Write
+output [BEW-1:0] out_reg_be ; // Target Byte enable
+
+//-----------------------------------
+// Initiator Local Declaration
+// ----------------------------------
+parameter INI_IDLE = 2'b00;
+parameter INI_WAIT_ACK = 2'b01;
+parameter INI_WAIT_TAR_DONE = 2'b10;
+
+reg [1:0] in_state ; // reg state
+reg [8:0] in_timer ; // reg timout monitor timer
+reg in_flag ; // reg handshake flag
+reg in_reg_ack ; // reg reg access finish ind
+reg [DW-1:0] in_reg_rdata ; // reg reg access read data
+reg in_reg_timeout ; // reg time out error pulse
+
+//-----------------------------------
+// Target Local Declaration
+// ----------------------------------
+parameter TAR_IDLE = 2'b00;
+parameter TAR_WAIT_ACK = 2'b01;
+parameter TAR_WAIT_INI_DONE = 2'b10;
+
+reg [1:0] out_state ; // target state machine
+reg out_flag ; // target handshake flag
+reg out_reg_cs ; // Target Start indication
+
+reg [8:0] inititaor_timer ; // timeout counter
+//-----------------------------------------------
+// Double sync local declaration
+// ----------------------------------------------
+
+reg in_flag_s ; // Initiator handshake flag sync
+ // with target clk
+reg in_flag_ss ; // Initiator handshake flag sync
+ // with target clk
+
+reg out_flag_s ; // target handshake flag sync
+ // with initiator clk
+reg out_flag_ss ; // target handshake flag sync
+ // with initiator clck
+
+
+
+
+assign out_reg_addr = in_reg_addr;
+assign out_reg_wdata = in_reg_wdata;
+assign out_reg_wr = in_reg_wr;
+assign out_reg_be = in_reg_be;
+//------------------------------------------------------
+// Initiator Domain logic
+//------------------------------------------------------
+
+always @(negedge in_reset_n or posedge in_clk)
+begin
+ if(in_reset_n == 1'b0)
+ begin
+ in_state <= INI_IDLE;
+ in_timer <= 9'h0;
+ in_flag <= 1'b0;
+ in_reg_ack <= 1'b0;
+ in_reg_rdata <= {DW {1'b0}};
+ in_reg_timeout<= 1'b0;
+ end
+ else
+ begin
+ case(in_state)
+ INI_IDLE :
+ begin
+ in_reg_ack <= 1'b0;
+ in_reg_timeout <= 1'b0;
+ in_timer <= 'h0;
+ // Wait for Initiator Start Indication
+ // Once the reg start is detected
+ // Set the reg flag and move to WAIT
+ // for ack from Target
+ if(in_reg_cs) begin
+ in_flag <= 1'b1;
+ in_state <= INI_WAIT_ACK;
+ end
+ end
+ INI_WAIT_ACK :
+ begin
+ //--------------------------------------------
+ // 1. Wait for Out Flag == 1
+ // 2. If the Out Flag =1 is not
+ // detected witin 512 cycle, exit with error indication
+ // 3. If Target flag detected, then de-assert
+ // reg_flag = 0 and move the tar_wait_done state
+ // ---------------------------------------------
+ if(out_flag_ss == 1'b1) begin
+ in_flag <= 1'b0;
+ in_reg_rdata <= out_reg_rdata;
+ in_reg_ack <= 1'b1;
+ in_state <= INI_WAIT_TAR_DONE;
+ end
+ else begin
+ if(in_timer == 9'h1FF) begin
+ in_flag <= 1'b0;
+ in_reg_ack <= 1'b1;
+ in_reg_rdata <= 32'h0;
+ in_reg_timeout <= 1'b1;
+ in_state <= INI_IDLE;
+ end
+ else begin
+ in_timer <= in_timer + 1;
+ end
+ end
+ end
+ INI_WAIT_TAR_DONE :
+ begin
+ in_reg_ack <= 1'b0;
+ //--------------------------------------------
+ // 1. Wait for Target Flag == 0
+ // 2. If Target flag = 0 detected, then remove
+ // move the idle state
+ // ---------------------------------------------
+ if(out_flag_ss == 1'b0) begin
+ in_state <= INI_IDLE;
+ end
+ end
+ default:
+ begin
+ in_state <= INI_IDLE;
+ in_timer <= 9'h0;
+ in_flag <= 1'b0;
+ in_reg_rdata <= {DW {1'b0}};
+ in_reg_timeout <= 1'b0;
+ end
+ endcase
+ end
+end
+
+
+//------------------------------------------------------
+// target Domain logic
+//------------------------------------------------------
+always @(negedge out_reset_n or posedge out_clk)
+begin
+ if(out_reset_n == 1'b0)
+ begin
+ out_state <= TAR_IDLE;
+ out_flag <= 1'b0;
+ out_reg_cs <= 1'b0;
+ end
+ else
+ begin
+ case(out_state)
+ TAR_IDLE :
+ begin
+ // 1. Wait for Initiator flag assertion
+ // 2. Once the reg flag = 1 is detected
+ // Set the target_flag and initiate the
+ // target reg bus access
+ out_flag <= 1'b0;
+ if(in_flag_ss) begin
+ out_reg_cs <= 1'b1;
+ out_state <= TAR_WAIT_ACK;
+ end
+ end
+ TAR_WAIT_ACK :
+ begin
+ //--------------------------------------------
+ // 1. Wait for reg Flag == 0
+ // 2. If reg flag = 0 detected, then
+ // move the idle state
+ // ---------------------------------------------
+ if(out_reg_ack == 1'b1)
+ begin
+ out_reg_cs <= 1'b0;
+ out_flag <= 1'b1;
+ out_state <= TAR_WAIT_INI_DONE;
+ end
+ end
+ TAR_WAIT_INI_DONE :
+ begin
+ if(in_flag_ss == 1'b0) begin
+ out_flag <= 1'b0;
+ out_state <= TAR_IDLE;
+ end
+ end
+ default:
+ begin
+ out_state <= TAR_IDLE;
+ out_reg_cs <= 1'b0;
+ out_flag <= 1'b0;
+ end
+ endcase
+ end
+end
+
+//-------------------------------------------------------
+// Double Sync Logic
+// ------------------------------------------------------
+always @(negedge in_reset_n or posedge in_clk)
+begin
+ if(in_reset_n == 1'b0)
+ begin
+ out_flag_s <= 1'b0;
+ out_flag_ss <= 1'b0;
+ end
+ else
+ begin
+ out_flag_s <= out_flag;
+ out_flag_ss <= out_flag_s;
+ end
+end
+
+
+always @(negedge out_reset_n or posedge out_clk)
+begin
+ if(out_reset_n == 1'b0)
+ begin
+ in_flag_s <= 1'b0;
+ in_flag_ss <= 1'b0;
+ end
+ else
+ begin
+ in_flag_s <= in_flag;
+ in_flag_ss <= in_flag_s;
+ end
+end
+
+
+endmodule
diff --git a/verilog/rtl/lib/async_wb.sv b/verilog/rtl/lib/async_wb.sv
new file mode 100644
index 0000000..53eb575
--- /dev/null
+++ b/verilog/rtl/lib/async_wb.sv
@@ -0,0 +1,234 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Async Wishbone Interface ////
+//// ////
+//// This file is part of the YIFive cores project ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description ////
+//// This block does async Wishbone from one clock to other ////
+//// clock domain
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 25th Feb 2021, Dinesh A ////
+//// initial version ////
+//// 0.2 - 28th Feb 2021, Dinesh A ////
+//// reduced the response FIFO path depth to 2 as ////
+//// return path used by only read logic and read is ////
+//// blocking request and expect only one location will ////
+//// be used ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module async_wb
+ #(parameter AW = 32,
+ parameter BW = 4,
+ parameter DW = 32)
+ (
+
+ // Master Port
+ input logic wbm_rst_n , // Regular Reset signal
+ input logic wbm_clk_i , // System clock
+ input logic wbm_cyc_i , // strobe/request
+ input logic wbm_stb_i , // strobe/request
+ input logic [AW-1:0] wbm_adr_i , // address
+ input logic wbm_we_i , // write
+ input logic [DW-1:0] wbm_dat_i , // data output
+ input logic [BW-1:0] wbm_sel_i , // byte enable
+ output logic [DW-1:0] wbm_dat_o , // data input
+ output logic wbm_ack_o , // acknowlegement
+ output logic wbm_err_o , // error
+
+ // Slave Port
+ input logic wbs_rst_n , // Regular Reset signal
+ input logic wbs_clk_i , // System clock
+ output logic wbs_cyc_o , // strobe/request
+ output logic wbs_stb_o , // strobe/request
+ output logic [AW-1:0] wbs_adr_o , // address
+ output logic wbs_we_o , // write
+ output logic [DW-1:0] wbs_dat_o , // data output
+ output logic [BW-1:0] wbs_sel_o , // byte enable
+ input logic [DW-1:0] wbs_dat_i , // data input
+ input logic wbs_ack_i , // acknowlegement
+ input logic wbs_err_i // error
+
+ );
+
+
+
+parameter CFW = AW+DW+BW+1 ; // COMMAND FIFO WIDTH
+
+//-------------------------------------------------
+// Master Interface
+// -------------------------------------------------
+logic PendingRd ; // Pending Read Transaction
+logic m_cmd_wr_en ;
+logic [CFW-1:0] m_cmd_wr_data ;
+logic m_cmd_wr_full ;
+logic m_cmd_wr_afull ;
+
+logic m_resp_rd_empty ;
+logic m_resp_rd_aempty ;
+logic m_resp_rd_en ;
+logic [DW:0] m_resp_rd_data ;
+
+// Master Write Interface
+
+
+assign m_cmd_wr_en = (!PendingRd) && wbm_stb_i && !m_cmd_wr_full && !m_cmd_wr_afull;
+
+assign m_cmd_wr_data = {wbm_adr_i,wbm_we_i,wbm_dat_i,wbm_sel_i};
+
+always@(negedge wbm_rst_n or posedge wbm_clk_i)
+begin
+ if(wbm_rst_n == 0) begin
+ PendingRd <= 1'b0;
+ end else begin
+ if((!PendingRd) && wbm_stb_i && (!wbm_we_i) && m_cmd_wr_en) begin
+ PendingRd <= 1'b1;
+ end else if(PendingRd && wbm_stb_i && (!wbm_we_i) && wbm_ack_o) begin
+ PendingRd <= 1'b0;
+ end
+ end
+end
+
+
+// Master Read Interface
+// For Write is feed through, if there is space in fifo the ack
+// For Read, Wait for Response Path FIFO status
+assign wbm_ack_o = (wbm_stb_i && wbm_we_i) ? m_cmd_wr_en : // Write Logic
+ (wbm_stb_i && (!wbm_we_i)) ? !m_resp_rd_empty : 1'b0; // Read Logic
+
+assign m_resp_rd_en = !m_resp_rd_empty;
+assign wbm_dat_o = m_resp_rd_data[DW-1:0];
+assign wbm_err_o = m_resp_rd_data[DW];
+
+
+//------------------------------
+// Slave Interface
+//-------------------------------
+
+logic [CFW-1:0] s_cmd_rd_data ;
+logic s_cmd_rd_empty ;
+logic s_cmd_rd_aempty ;
+logic s_cmd_rd_en ;
+logic s_resp_wr_en ;
+logic [DW:0] s_resp_wr_data ;
+logic s_resp_wr_full ;
+logic s_resp_wr_afull ;
+logic wbs_ack_f ;
+
+
+always@(negedge wbs_rst_n or posedge wbs_clk_i)
+begin
+ if(wbs_rst_n == 0) begin
+ wbs_ack_f <= 1'b0;
+ end else begin
+ wbs_ack_f <= wbs_ack_i;
+ end
+end
+
+
+// Read Interface
+assign {wbs_adr_o,wbs_we_o,wbs_dat_o,wbs_sel_o} = (s_cmd_rd_empty) ? '0: s_cmd_rd_data;
+// All the downstream logic expect Stobe is getting de-asserted
+// atleast for 1 cycle after ack is generated
+assign wbs_stb_o = (wbs_ack_f) ? 1'b0 : (s_cmd_rd_empty) ? 1'b0: 1'b1;
+assign wbs_cyc_o = (wbs_ack_f) ? 1'b0 : (s_cmd_rd_empty) ? 1'b0: 1'b1;
+
+assign s_cmd_rd_en = wbs_ack_i;
+
+// Write Interface
+// response send only for read logic
+assign s_resp_wr_en = wbs_stb_o & (!wbs_we_o) & wbs_ack_i & !s_resp_wr_full;
+assign s_resp_wr_data = {wbs_err_i,wbs_dat_i};
+
+async_fifo #(.W(CFW), .DP(4), .WR_FAST(1), .RD_FAST(1)) u_cmd_if (
+ // Sync w.r.t WR clock
+ .wr_clk (wbm_clk_i ),
+ .wr_reset_n (wbm_rst_n ),
+ .wr_en (m_cmd_wr_en ),
+ .wr_data (m_cmd_wr_data ),
+ .full (m_cmd_wr_full ),
+ .afull (m_cmd_wr_afull ),
+
+ // Sync w.r.t RD Clock
+ .rd_clk (wbs_clk_i ),
+ .rd_reset_n (wbs_rst_n ),
+ .rd_en (s_cmd_rd_en ),
+ .empty (s_cmd_rd_empty ), // sync'ed to rd_clk
+ .aempty (s_cmd_rd_aempty ), // sync'ed to rd_clk
+ .rd_data (s_cmd_rd_data )
+ );
+
+
+// Response used only read path, read is blocking access, expect
+// only one location used in return path - reduced the depth to 2
+async_fifo #(.W(DW+1), .DP(2), .WR_FAST(1), .RD_FAST(0)) u_resp_if (
+ // Sync w.r.t WR clock
+ .wr_clk (wbs_clk_i ),
+ .wr_reset_n (wbs_rst_n ),
+ .wr_en (s_resp_wr_en ),
+ .wr_data (s_resp_wr_data ),
+ .full (s_resp_wr_full ),
+ .afull (s_resp_wr_afull ),
+
+ // Sync w.r.t RD Clock
+ .rd_clk (wbm_clk_i ),
+ .rd_reset_n (wbm_rst_n ),
+ .rd_en (m_resp_rd_en ),
+ .empty (m_resp_rd_empty ), // sync'ed to rd_clk
+ .aempty (m_resp_rd_aempty ), // sync'ed to rd_clk
+ .rd_data (m_resp_rd_data )
+ );
+
+
+
+endmodule
diff --git a/verilog/rtl/lib/clk_buf.v b/verilog/rtl/lib/clk_buf.v
new file mode 100644
index 0000000..dad8fc6
--- /dev/null
+++ b/verilog/rtl/lib/clk_buf.v
@@ -0,0 +1,85 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Clk Buf ////
+//// ////
+//// This file is part of the YIFive cores project ////
+//// https://github.com/dineshannayya/yifive_r0.git ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description ////
+//// Adding clock buf for manual clock tree at SOC level ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+
+module clk_buf (
+ // Outputs
+ clk_o,
+ // Inputs
+ clk_i
+ );
+
+//---------------------------------------------
+// All the input to this block are declared here
+// --------------------------------------------
+ input clk_i ;//
+
+//---------------------------------------------
+// All the output to this block are declared here
+// --------------------------------------------
+ output clk_o ; // clock out
+
+
+
+sky130_fd_sc_hd__clkbuf_16 u_buf (.A(clk_i),.X(clk_o));
+
+endmodule
+
diff --git a/verilog/rtl/lib/clk_ctl.v b/verilog/rtl/lib/clk_ctl.v
new file mode 100644
index 0000000..7e4478b
--- /dev/null
+++ b/verilog/rtl/lib/clk_ctl.v
@@ -0,0 +1,147 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+////////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores common library Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// https://github.com/dineshannayya/yifive_r0.git ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 1.0 Mar 2, 2011,Dinesh.A ////
+//// Initial Version ////
+//// 1.1 Nov 15,2021,Dinesh A ////
+//// Bug fix in High and Low count width ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+// #################################################################
+// Module: clk_ctl
+//
+// Description: Generic clock control logic , clk-out = mclk/(2+clk_div_ratio)
+//
+//
+// #################################################################
+
+
+module clk_ctl (
+ // Outputs
+ clk_o,
+ // Inputs
+ mclk,
+ reset_n,
+ clk_div_ratio
+ );
+
+//---------------------------------
+// CLOCK Default Divider value.
+// This value will be change from outside
+//---------------------------------
+parameter WD = 'h1;
+
+//---------------------------------------------
+// All the input to this block are declared here
+// --------------------------------------------
+ input mclk ;//
+ input reset_n ;// primary reset signal
+ input [WD:0] clk_div_ratio ;// primary clock divide ratio
+ // output clock = selected clock / (div_ratio+1)
+
+//---------------------------------------------
+// All the output to this block are declared here
+// --------------------------------------------
+ output clk_o ; // clock out
+
+
+
+//------------------------------------
+// Clock Divide func is done here
+//------------------------------------
+reg [WD:0] high_count ; // high level counter
+reg [WD:0] low_count ; // low level counter
+reg mclk_div ; // divided clock
+
+
+assign clk_o = mclk_div;
+
+always @ (posedge mclk or negedge reset_n)
+begin // {
+ if(reset_n == 1'b0)
+ begin
+ high_count <= 'h0;
+ low_count <= 'h0;
+ mclk_div <= 'b0;
+ end
+ else
+ begin
+ if(high_count != 0)
+ begin // {
+ high_count <= high_count - 1;
+ mclk_div <= 1'b1;
+ end // }
+ else if(low_count != 0)
+ begin // {
+ low_count <= low_count - 1;
+ mclk_div <= 1'b0;
+ end // }
+ else
+ begin // {
+ high_count <= clk_div_ratio[WD:1] + clk_div_ratio[0];
+ low_count <= clk_div_ratio[WD:1] + 1;
+ mclk_div <= ~mclk_div;
+ end // }
+ end // }
+end // }
+
+
+endmodule
+
diff --git a/verilog/rtl/lib/clk_div8.v b/verilog/rtl/lib/clk_div8.v
new file mode 100644
index 0000000..d4731b7
--- /dev/null
+++ b/verilog/rtl/lib/clk_div8.v
@@ -0,0 +1,62 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesh.annayya@gmail.com>
+////////////////////////////////////////////////////////////////////////
+
+// #################################################################
+// Module: clock div by 2,4,8 supported
+//
+//
+//
+// #################################################################
+
+
+module clk_div8 (
+ // Outputs
+ output logic clk_div_8,
+ output logic clk_div_4,
+ output logic clk_div_2,
+ // Inputs
+ input logic mclk,
+ input logic reset_n
+ );
+
+
+
+
+//------------------------------------
+// Clock Divide func is done here
+//------------------------------------
+reg [2:0] clk_cnt ; // high level counter
+
+
+assign clk_div_2 = clk_cnt[0];
+assign clk_div_4 = clk_cnt[1];
+assign clk_div_8 = clk_cnt[2];
+
+always @ (posedge mclk or negedge reset_n)
+begin // {
+ if(reset_n == 1'b0)
+ begin
+ clk_cnt <= 'h0;
+ end else begin
+ clk_cnt <= clk_cnt + 1;
+ end // }
+end // }
+
+
+endmodule
+
diff --git a/verilog/rtl/lib/clk_gate.sv b/verilog/rtl/lib/clk_gate.sv
new file mode 100644
index 0000000..b7600f4
--- /dev/null
+++ b/verilog/rtl/lib/clk_gate.sv
@@ -0,0 +1,57 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Clock Gate with Scan over-ride ////
+//// ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 28 Nov 2021, Dinesh A ////
+//// Initial Version ////
+//////////////////////////////////////////////////////////////////////
+module clk_gate (
+ output logic GCLK, // Gated Clock Out
+
+ input logic CLK, // Functional Clock
+ input logic EN, // Functional Enable
+ input logic TE // SCAN MODE/SCAN Enable
+ );
+
+`ifndef SYNTHESIS
+ reg clk_enb;
+ always_latch begin
+ if(CLK == 0)
+ clk_enb = EN | TE;
+ end
+
+ assign GCLK = clk_enb & CLK;
+`else
+ sky130_fd_sc_hd__sdlclkp_2 u_clk_gate (
+ .GCLK (GCLK),
+ .SCE (TE),
+ .GATE (EN),
+ .CLK (CLK)
+ );
+
+`endif
+
+endmodule
+
diff --git a/verilog/rtl/lib/clk_skew_adjust.gv b/verilog/rtl/lib/clk_skew_adjust.gv
new file mode 100644
index 0000000..fc811c0
--- /dev/null
+++ b/verilog/rtl/lib/clk_skew_adjust.gv
@@ -0,0 +1,205 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// clock skew adjust ////
+//// ////
+//// This file is part of the YIFive cores project ////
+//// https://github.com/dineshannayya/yifive_r0.git ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description ////
+//// This block is useful for global clock skew adjustment ////
+//// logic implementation: ////
+//// clk_out = (sel=0) ? clk_in : ////
+//// (sel=1) ? clk_d1 : ////
+//// (sel=1) ? clk_d2 : ////
+//// ..... ////
+//// (sel=15)? clk_d15 :clk_in ////
+//// ////
+//// Note: each d* indicate clk buf delay ////
+//// ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 29th Feb 2021, Dinesh A ////
+//// Initial version ////
+///
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+// Clock-in is east pad direction
+// clock out give in other three direction for better placement
+/////////////////////////////////////////////////////////////////////
+module clk_skew_adjust(
+`ifdef USE_POWER_PINS
+ vccd1,// User area 1 1.8V supply
+ vssd1,// User area 1 digital ground
+`endif
+clk_in, sel, clk_out);
+
+
+`ifdef USE_POWER_PINS
+ input vccd1;// User area 1 1.8V supply
+ input vssd1;// User area 1 digital ground
+`endif
+ input clk_in;
+ output clk_out;
+ input [3:0] sel;
+ wire in0;
+ wire in1;
+ wire in2;
+ wire in3;
+ wire in4;
+ wire in5;
+ wire in6;
+ wire in7;
+ wire in8;
+ wire in9;
+ wire in10;
+ wire in11;
+ wire in12;
+ wire in13;
+ wire in14;
+ wire in15;
+
+ wire clk_d1;
+ wire clk_d2;
+ wire clk_d3;
+ wire clk_d4;
+ wire clk_d5;
+ wire clk_d6;
+ wire clk_d7;
+ wire clk_d8;
+ wire clk_d9;
+ wire clk_d10;
+ wire clk_d11;
+ wire clk_d12;
+ wire clk_d13;
+ wire clk_d14;
+ wire clk_d15;
+
+ wire d00;
+ wire d01;
+ wire d02;
+ wire d03;
+ wire d04;
+ wire d05;
+ wire d06;
+ wire d07;
+ wire d10;
+ wire d11;
+ wire d12;
+ wire d13;
+ wire d20;
+ wire d21;
+ wire d30;
+
+
+ ctech_delay_clkbuf clkbuf_1 (.A(clk_in), .X(clk_d1));
+ ctech_delay_clkbuf clkbuf_2 (.A(clk_d1), .X(clk_d2));
+ ctech_delay_clkbuf clkbuf_3 (.A(clk_d2), .X(clk_d3));
+ ctech_delay_clkbuf clkbuf_4 (.A(clk_d3), .X(clk_d4));
+ ctech_delay_clkbuf clkbuf_5 (.A(clk_d4), .X(clk_d5));
+ ctech_delay_clkbuf clkbuf_6 (.A(clk_d5), .X(clk_d6));
+ ctech_delay_clkbuf clkbuf_7 (.A(clk_d6), .X(clk_d7));
+ ctech_delay_clkbuf clkbuf_8 (.A(clk_d7), .X(clk_d8));
+ ctech_delay_clkbuf clkbuf_9 (.A(clk_d8), .X(clk_d9));
+ ctech_delay_clkbuf clkbuf_10 (.A(clk_d9), .X(clk_d10));
+ ctech_delay_clkbuf clkbuf_11 (.A(clk_d10), .X(clk_d11));
+ ctech_delay_clkbuf clkbuf_12 (.A(clk_d11), .X(clk_d12));
+ ctech_delay_clkbuf clkbuf_13 (.A(clk_d12), .X(clk_d13));
+ ctech_delay_clkbuf clkbuf_14 (.A(clk_d13), .X(clk_d14));
+ ctech_delay_clkbuf clkbuf_15 (.A(clk_d14), .X(clk_d15));
+
+
+ // Tap point selection
+ assign in0 = clk_in;
+ assign in1 = clk_d1;
+ assign in2 = clk_d2;
+ assign in3 = clk_d3;
+ assign in4 = clk_d4;
+ assign in5 = clk_d5;
+ assign in6 = clk_d6;
+ assign in7 = clk_d7;
+ assign in8 = clk_d8;
+ assign in9 = clk_d9;
+ assign in10 = clk_d10;
+ assign in11 = clk_d11;
+ assign in12 = clk_d12;
+ assign in13 = clk_d13;
+ assign in14 = clk_d14;
+ assign in15 = clk_d15;
+
+
+ // first level mux - 8
+ ctech_mux2x1_2 u_mux_level_00 ( .X (d00) , .A0 (in0), .A1(in1), .S(sel[0]));
+ ctech_mux2x1_2 u_mux_level_01 ( .X (d01) , .A0 (in2), .A1(in3), .S(sel[0]));
+ ctech_mux2x1_2 u_mux_level_02 ( .X (d02) , .A0 (in4), .A1(in5), .S(sel[0]));
+ ctech_mux2x1_2 u_mux_level_03 ( .X (d03) , .A0 (in6), .A1(in7), .S(sel[0]));
+ ctech_mux2x1_2 u_mux_level_04 ( .X (d04) , .A0 (in8), .A1(in9), .S(sel[0]));
+ ctech_mux2x1_2 u_mux_level_05 ( .X (d05) , .A0 (in10), .A1(in11), .S(sel[0]));
+ ctech_mux2x1_2 u_mux_level_06 ( .X (d06) , .A0 (in12), .A1(in13), .S(sel[0]));
+ ctech_mux2x1_2 u_mux_level_07 ( .X (d07) , .A0 (in14), .A1(in15), .S(sel[0]));
+
+ // second level mux - 4
+ ctech_mux2x1_2 u_mux_level_10 ( .X (d10) , .A0 (d00), .A1(d01), .S(sel[1]));
+ ctech_mux2x1_2 u_mux_level_11 ( .X (d11) , .A0 (d02), .A1(d03), .S(sel[1]));
+ ctech_mux2x1_2 u_mux_level_12 ( .X (d12) , .A0 (d04), .A1(d05), .S(sel[1]));
+ ctech_mux2x1_2 u_mux_level_13 ( .X (d13) , .A0 (d06), .A1(d07), .S(sel[1]));
+
+ // third level mux - 2
+ ctech_mux2x1_2 u_mux_level_20 ( .X (d20) , .A0 (d10), .A1(d11), .S(sel[2]));
+ ctech_mux2x1_2 u_mux_level_21 ( .X (d21) , .A0 (d12), .A1(d13), .S(sel[2]));
+
+ // fourth level mux - 1
+ ctech_mux2x1_4 u_mux_level_30 ( .X (d30) , .A0 (d20), .A1(d21), .S(sel[3]));
+
+
+ assign clk_out = d30;
+
+endmodule
diff --git a/verilog/rtl/lib/crc_32.sv b/verilog/rtl/lib/crc_32.sv
new file mode 100755
index 0000000..db0d1c7
--- /dev/null
+++ b/verilog/rtl/lib/crc_32.sv
@@ -0,0 +1,194 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// crc_32.v: CRC is generated on when run is asserted. ////
+//// The 32-bit crc shift register is reset to ////
+//// all 1's when either clear asserted ////
+//// ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 28 Nov 2021, Dinesh A ////
+//// Initial Version ////
+//////////////////////////////////////////////////////////////////////
+
+module crc_32 (
+ // List of outputs.
+ output logic [31:0] crc_out,
+
+ // List of inputs
+ input logic run, // when asserted, crc is generated
+ input logic clear , // When asserted crc is re-initialized
+ input logic [7:0] data_in,
+ input logic mclk,
+ input logic reset_n
+ );
+
+
+//----------------------------------
+// define local signals here.
+//----------------------------------
+
+ logic[31:0] current_crc, next_crc;
+
+
+ assign crc_out = ~current_crc;
+
+ // 32-bit crc shift register for crc calculation.
+
+ always @(posedge mclk or negedge reset_n)
+ begin
+ if (!reset_n)
+ begin
+ current_crc <= 32'hffffffff;
+ end
+ else
+ begin
+ if (clear )
+ begin
+ current_crc <= 32'hffffffff;
+ end
+ else if (run) // generate crc
+ begin
+ current_crc <= next_crc;
+ end // else: !if(tx_reset_crc )
+ end // else: !if(reset_n)
+ end // always @ (posedge mclk or negedge reset_n)
+
+ // combinational logic to generate next_crc
+
+ always_comb
+ begin
+
+ next_crc[0] = current_crc[8] ^ current_crc[2] ^ data_in[2];
+ next_crc[1] = current_crc[9] ^ current_crc[0] ^ data_in[0] ^
+ current_crc[3] ^ data_in[3];
+ next_crc[2] = current_crc[10] ^ current_crc[0] ^ data_in[0] ^
+ current_crc[1] ^ data_in[1] ^ current_crc[4] ^
+ data_in[4];
+ next_crc[3] = current_crc[11] ^ current_crc[1] ^ data_in[1] ^
+ current_crc[2] ^ data_in[2] ^ current_crc[5] ^
+ data_in[5];
+ next_crc[4] = current_crc[12] ^ current_crc[2] ^ data_in[2] ^
+ current_crc[3] ^ data_in[3] ^ current_crc[6] ^
+ current_crc[0] ^ data_in[0] ^ data_in[6];
+ next_crc[5] = current_crc[13] ^ current_crc[3] ^ data_in[3] ^
+ current_crc[4] ^ data_in[4] ^ current_crc[7] ^
+ current_crc[1] ^ data_in[1] ^ data_in[7];
+ next_crc[6] = current_crc[14] ^ current_crc[4] ^ data_in[4] ^
+ current_crc[5] ^ data_in[5];
+ next_crc[7] = current_crc[15] ^ current_crc[5] ^ data_in[5] ^
+ current_crc[6] ^ current_crc[0] ^ data_in[0] ^
+ data_in[6];
+ next_crc[8] = current_crc[16] ^ current_crc[0] ^ data_in[0] ^
+ current_crc[6] ^ current_crc[0] ^ data_in[0] ^
+ data_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ data_in[1] ^ data_in[7];
+ next_crc[9] = current_crc[17] ^ current_crc[1] ^ data_in[1] ^
+ current_crc[7] ^ current_crc[1] ^ data_in[1] ^
+ data_in[7];
+ next_crc[10] = current_crc[18] ^ current_crc[2] ^ data_in[2];
+ next_crc[11] = current_crc[19] ^ current_crc[3] ^ data_in[3];
+ next_crc[12] = current_crc[20] ^ current_crc[0] ^ data_in[0] ^
+ current_crc[4] ^ data_in[4];
+ next_crc[13] = current_crc[21] ^ current_crc[0] ^ data_in[0] ^
+ current_crc[1] ^ data_in[1] ^ current_crc[5] ^
+ data_in[5];
+ next_crc[14] = current_crc[22] ^ current_crc[0] ^ data_in[0] ^
+ current_crc[1] ^ data_in[1] ^ current_crc[2] ^
+ data_in[2] ^ current_crc[6] ^ current_crc[0] ^
+ data_in[0] ^ data_in[6];
+ next_crc[15] = current_crc[23] ^ current_crc[1] ^ data_in[1] ^
+ current_crc[2] ^ data_in[2] ^ current_crc[3] ^
+ data_in[3] ^ current_crc[7] ^ current_crc[1] ^
+ data_in[1] ^ data_in[7];
+ next_crc[16] = current_crc[24] ^ current_crc[0] ^ data_in[0] ^
+ current_crc[2] ^ data_in[2] ^ current_crc[3] ^
+ data_in[3] ^ current_crc[4] ^ data_in[4];
+ next_crc[17] = current_crc[25] ^ current_crc[0] ^ data_in[0] ^
+ current_crc[1] ^ data_in[1] ^ current_crc[3] ^
+ data_in[3] ^ current_crc[4] ^ data_in[4] ^
+ current_crc[5] ^ data_in[5];
+ next_crc[18] = current_crc[26] ^ current_crc[1] ^ data_in[1] ^
+ current_crc[2] ^ data_in[2] ^ current_crc[4] ^
+ data_in[4] ^ current_crc[5] ^ data_in[5] ^
+ current_crc[6] ^ current_crc[0] ^ data_in[0] ^
+ data_in[6];
+ next_crc[19] = current_crc[27] ^ current_crc[0] ^ data_in[0] ^
+ current_crc[2] ^ data_in[2] ^ current_crc[3] ^
+ data_in[3] ^ current_crc[5] ^ data_in[5] ^
+ current_crc[6] ^ current_crc[0] ^ data_in[0] ^
+ data_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ data_in[1] ^ data_in[7];
+ next_crc[20] = current_crc[28] ^ current_crc[0] ^ data_in[0] ^
+ current_crc[1] ^ data_in[1] ^ current_crc[3] ^
+ data_in[3] ^ current_crc[4] ^ data_in[4] ^
+ current_crc[6] ^ current_crc[0] ^ data_in[0] ^
+ data_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ data_in[1] ^ data_in[7];
+ next_crc[21] = current_crc[29] ^ current_crc[1] ^ data_in[1] ^
+ current_crc[2] ^ data_in[2] ^ current_crc[4] ^
+ data_in[4] ^ current_crc[5] ^ data_in[5] ^
+ current_crc[7] ^ current_crc[1] ^ data_in[1] ^
+ data_in[7];
+ next_crc[22] = current_crc[30] ^ current_crc[0] ^ data_in[0] ^
+ current_crc[2] ^ data_in[2] ^ current_crc[3] ^
+ data_in[3] ^ current_crc[5] ^ data_in[5] ^
+ current_crc[6] ^ current_crc[0] ^ data_in[0] ^
+ data_in[6];
+ next_crc[23] = current_crc[31] ^ current_crc[0] ^ data_in[0] ^
+ current_crc[1] ^ data_in[1] ^ current_crc[3] ^
+ data_in[3] ^ current_crc[4] ^ data_in[4] ^
+ current_crc[6] ^ current_crc[0] ^ data_in[0] ^
+ data_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ data_in[1] ^ data_in[7];
+ next_crc[24] = current_crc[0] ^ data_in[0] ^ current_crc[1] ^
+ data_in[1] ^ current_crc[2] ^ data_in[2] ^
+ current_crc[4] ^ data_in[4] ^ current_crc[5] ^
+ data_in[5] ^ current_crc[7] ^ current_crc[1] ^
+ data_in[1] ^ data_in[7];
+ next_crc[25] = current_crc[1] ^ data_in[1] ^ current_crc[2] ^
+ data_in[2] ^ current_crc[3] ^ data_in[3] ^
+ current_crc[5] ^ data_in[5] ^ current_crc[6] ^
+ current_crc[0] ^ data_in[0] ^ data_in[6];
+ next_crc[26] = current_crc[2] ^ data_in[2] ^ current_crc[3] ^
+ data_in[3] ^ current_crc[4] ^ data_in[4] ^
+ current_crc[6] ^ current_crc[0] ^ data_in[0] ^
+ data_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ data_in[1] ^ data_in[7];
+ next_crc[27] = current_crc[3] ^ data_in[3] ^ current_crc[4] ^
+ data_in[4] ^ current_crc[5] ^ data_in[5] ^
+ current_crc[7] ^ current_crc[1] ^ data_in[1] ^
+ data_in[7];
+ next_crc[28] = current_crc[4] ^data_in[4] ^ current_crc[5] ^
+ data_in[5] ^ current_crc[6] ^ current_crc[0] ^
+ data_in[0] ^ data_in[6];
+ next_crc[29] = current_crc[5] ^ data_in[5] ^ current_crc[6] ^
+ current_crc[0] ^ data_in[0] ^ data_in[6] ^
+ current_crc[7] ^ current_crc[1] ^ data_in[1] ^
+ data_in[7];
+ next_crc[30] = current_crc[6] ^ current_crc[0] ^ data_in[0] ^
+ data_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ data_in[1] ^ data_in[7];
+ next_crc[31] = current_crc[7] ^ current_crc[1] ^ data_in[1] ^
+ data_in[7];
+ end // always
+
+endmodule
diff --git a/verilog/rtl/lib/ctech_cells.sv b/verilog/rtl/lib/ctech_cells.sv
new file mode 100644
index 0000000..8e3b0de
--- /dev/null
+++ b/verilog/rtl/lib/ctech_cells.sv
@@ -0,0 +1,51 @@
+
+module ctech_mux2x1 (
+ input logic A0,
+ input logic A1,
+ input logic S ,
+ output logic X);
+
+`ifndef SYNTHESIS
+assign X = (S) ? A1 : A0;
+`else
+sky130_fd_sc_hd__mux2_8 u_mux (.A0 (A0), .A1 (A1), .S (S), .X (X));
+`endif
+
+endmodule
+
+module ctech_buf (
+ input logic A,
+ output logic X);
+
+`ifndef SYNTHESIS
+assign X = A;
+`else
+ sky130_fd_sc_hd__bufbuf_8 u_buf (.A(A),.X(X));
+`endif
+
+endmodule
+
+module ctech_clk_buf (
+ input logic A,
+ output logic X);
+
+`ifndef SYNTHESIS
+assign X = A;
+`else
+ sky130_fd_sc_hd__clkbuf_8 u_buf (.A(A),.X(X));
+`endif
+
+endmodule
+
+module ctech_delay_buf (
+ input logic A,
+ output logic X);
+
+`ifndef SYNTHESIS
+ assign X = A;
+`else
+ sky130_fd_sc_hd__dlygate4sd3_1 u_dly (.X(X),.A(A));
+`endif
+
+endmodule
+
diff --git a/verilog/rtl/lib/dble_reg.v b/verilog/rtl/lib/dble_reg.v
new file mode 100755
index 0000000..b8364f8
--- /dev/null
+++ b/verilog/rtl/lib/dble_reg.v
@@ -0,0 +1,92 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores common library Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Mar 2, 2011 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+
+/***************************************************************
+ Description:
+ Synchronizes the pulse from one clock to another
+ * clock domain
+***********************************************************************/
+module half_dup_dble_reg (
+ //outputs
+ sync_out_pulse,
+ //inputs
+ in_pulse,
+ dest_clk,
+ reset_n);
+
+ output sync_out_pulse; //output synchronised to slow clock
+ input in_pulse; //input based on fast clock, pulse
+ input dest_clk; //slow clock
+ input reset_n;
+
+ reg s1_sync_out,d_sync_out,s2_sync_out;
+
+ //double register the data in the slow clock domain
+ always @(posedge dest_clk or negedge reset_n)
+ begin
+ if (!reset_n)
+ begin
+ s1_sync_out <= 0;
+ s2_sync_out <= 0;
+ d_sync_out <= 0;
+ end // if (reset_n)
+ else
+ begin
+ s1_sync_out <= in_pulse;
+ s2_sync_out <= s1_sync_out;
+ d_sync_out <= s2_sync_out;
+ end // else: !if(reset_n)
+ end // always @ (posedge dest_clk or negedge reset_n)
+
+ assign sync_out_pulse = d_sync_out;
+
+endmodule // dble_reg
+
+
+
+
+
+
diff --git a/verilog/rtl/lib/double_sync_high.v b/verilog/rtl/lib/double_sync_high.v
new file mode 100755
index 0000000..d1d2ca6
--- /dev/null
+++ b/verilog/rtl/lib/double_sync_high.v
@@ -0,0 +1,106 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// OMS 8051 cores common library Module ////
+//// ////
+//// This file is part of the OMS 8051 cores project ////
+//// http://www.opencores.org/cores/oms8051mini/ ////
+//// https://github.com/dineshannayya/yifive_r0.git ////
+//// ////
+//// Description ////
+//// OMS 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Nov 26, 2016 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//----------------------------------------------------------------------------
+// Simple Double sync logic with Reset value = 0
+// This double signal should be used for signal transiting from low to high
+//----------------------------------------------------------------------------
+
+module double_sync_high (
+ in_data ,
+ out_clk ,
+ out_rst_n ,
+ out_data
+ );
+
+parameter WIDTH = 1;
+
+input [WIDTH-1:0] in_data ; // Input from Different clock domain
+input out_clk ; // Output clock
+input out_rst_n ; // Active low Reset
+output[WIDTH-1:0] out_data ; // Output Data
+
+
+reg [WIDTH-1:0] in_data_s ; // One Cycle sync
+reg [WIDTH-1:0] in_data_2s ; // two Cycle sync
+reg [WIDTH-1:0] in_data_3s ; // three Cycle sync
+
+assign out_data = in_data_3s;
+
+always @(negedge out_rst_n or posedge out_clk)
+begin
+ if(out_rst_n == 1'b0)
+ begin
+ in_data_s <= {WIDTH{1'b0}};
+ in_data_2s <= {WIDTH{1'b0}};
+ in_data_3s <= {WIDTH{1'b0}};
+ end
+ else
+ begin
+ in_data_s <= in_data;
+ in_data_2s <= in_data_s;
+ in_data_3s <= in_data_2s;
+ end
+end
+
+
+endmodule
diff --git a/verilog/rtl/lib/double_sync_low.v b/verilog/rtl/lib/double_sync_low.v
new file mode 100755
index 0000000..efd4269
--- /dev/null
+++ b/verilog/rtl/lib/double_sync_low.v
@@ -0,0 +1,106 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// OMS 8051 cores common library Module ////
+//// ////
+//// This file is part of the OMS 8051 cores project ////
+//// http://www.opencores.org/cores/oms8051mini/ ////
+//// https://github.com/dineshannayya/yifive_r0.git ////
+//// ////
+//// Description ////
+//// OMS 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Nov 26, 2016 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//----------------------------------------------------------------------------
+// Simple Double sync logic with Reset value = 1
+// This double signal should be used for signal transiting from low to high
+//----------------------------------------------------------------------------
+
+module double_sync_low (
+ in_data ,
+ out_clk ,
+ out_rst_n ,
+ out_data
+ );
+
+parameter WIDTH = 1;
+
+input [WIDTH-1:0] in_data ; // Input from Different clock domain
+input out_clk ; // Output clock
+input out_rst_n ; // Active low Reset
+output[WIDTH-1:0] out_data ; // Output Data
+
+
+reg [WIDTH-1:0] in_data_s ; // One Cycle sync
+reg [WIDTH-1:0] in_data_2s ; // two Cycle sync
+reg [WIDTH-1:0] in_data_3s ; // three Cycle sync
+
+assign out_data = in_data_3s;
+
+always @(negedge out_rst_n or posedge out_clk)
+begin
+ if(out_rst_n == 1'b0)
+ begin
+ in_data_s <= {WIDTH{1'b1}};
+ in_data_2s <= {WIDTH{1'b1}};
+ in_data_3s <= {WIDTH{1'b1}};
+ end
+ else
+ begin
+ in_data_s <= in_data;
+ in_data_2s <= in_data_s;
+ in_data_3s <= in_data_2s;
+ end
+end
+
+
+endmodule
diff --git a/verilog/rtl/lib/g_dpath_ctrl.v b/verilog/rtl/lib/g_dpath_ctrl.v
new file mode 100644
index 0000000..846d65b
--- /dev/null
+++ b/verilog/rtl/lib/g_dpath_ctrl.v
@@ -0,0 +1,168 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores Data Path controller ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Mar 2, 2011 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module g_dpath_ctrl (
+ rst_n ,
+ clk ,
+
+ rx_buf_base_addr ,
+ tx_buf_base_addr ,
+
+ // gmac core to memory write interface
+ g_rx_mem_rd ,
+ g_rx_mem_eop ,
+ g_rx_mem_addr ,
+ g_rx_block_rxrd ,
+
+ // descr handshake
+ g_rx_desc_req ,
+ g_rx_desc_discard ,
+ g_rx_desc_data ,
+ g_rx_desc_ack ,
+
+ g_rx_pkt_done ,
+ g_rx_pkt_len ,
+ g_rx_pkt_status ,
+ g_rx_pkt_drop
+
+
+ );
+
+
+input rst_n ;
+input clk ;
+
+input [3:0] rx_buf_base_addr ; // 8K Rx Base Address
+input [3:0] tx_buf_base_addr ; // 8K tx Base Address
+
+// gmac core to memory write interface
+input g_rx_mem_rd ;
+input g_rx_mem_eop ;
+output [15:0] g_rx_mem_addr ;
+output g_rx_block_rxrd ; // Block Rx Read between EOP and PktDone
+
+input g_rx_pkt_done ; // End of current Packet
+input [11:0] g_rx_pkt_len ; // Packet Length
+input [15:0] g_rx_pkt_status ; // Packet Status
+input g_rx_pkt_drop ; // Packet drop and rewind the pointer
+
+
+//-----------------------------------
+// Descriptor handshake
+//----------------------------------
+output g_rx_desc_req ; // rx desc request
+output g_rx_desc_discard ; // rx desc discard indication
+output [31:0] g_rx_desc_data ; // rx desc data
+input g_rx_desc_ack ; // rx desc ack
+
+
+reg g_rx_desc_req ;
+reg g_rx_desc_discard ; // rx desc discard indication
+reg [31:0] g_rx_desc_data ; // rx desc data
+
+reg [11:0] g_rx_mem_addr_int ;
+
+wire [15:0] g_rx_mem_addr = {rx_buf_base_addr,g_rx_mem_addr_int[11:0]};
+
+
+reg bStartFlag; // Indicate a SOP transaction, used for registering Start Address
+reg g_rx_block_rxrd; // Block Rx Read at the end of EOP and Enable on Packet Done
+reg [11:0] g_rx_saddr;
+
+always @(negedge rst_n or posedge clk) begin
+ if(rst_n == 0) begin
+ g_rx_mem_addr_int <= 0;
+ bStartFlag <= 1;
+ g_rx_block_rxrd <= 0;
+ g_rx_saddr <= 0;
+ g_rx_desc_discard <= 0;
+ g_rx_desc_data <= 0;
+ g_rx_desc_req <= 0;
+ end
+ else begin
+ if(bStartFlag && g_rx_mem_rd) begin
+ g_rx_saddr <= g_rx_mem_addr_int[11:0];
+ bStartFlag <= 0;
+ end else if (g_rx_mem_rd && g_rx_mem_eop) begin
+ bStartFlag <= 1;
+ end
+
+ if(g_rx_mem_rd && g_rx_mem_eop)
+ g_rx_block_rxrd <= 1;
+ else if(g_rx_pkt_done)
+ g_rx_block_rxrd <= 0;
+
+ //-----------------------------
+ // Finding the Frame Size
+ //----------------------------
+ if(g_rx_pkt_done && g_rx_pkt_drop) begin
+ g_rx_mem_addr_int <= g_rx_saddr;
+ end else if(g_rx_mem_rd && g_rx_mem_eop) begin
+ // Realign to 32 bit boundary and add one free space at eop
+ g_rx_mem_addr_int[1:0] <= 0;
+ g_rx_mem_addr_int[11:2] <= g_rx_mem_addr_int[11:2]+1;
+ end else if(g_rx_mem_rd ) begin
+ g_rx_mem_addr_int <= g_rx_mem_addr_int+1;
+ end
+ // Descriptor Request Generation
+ if(g_rx_pkt_done) begin
+ g_rx_desc_req <= 1;
+ if(g_rx_pkt_drop) begin
+ g_rx_desc_discard <= 1;
+ end else begin
+ g_rx_desc_discard <= 0;
+ g_rx_desc_data <= {g_rx_pkt_status[5:0],rx_buf_base_addr[3:0],
+ g_rx_saddr[11:2],g_rx_pkt_len[11:0]};
+ end
+ end
+ else if (g_rx_desc_ack) begin
+ g_rx_desc_req <= 0;
+ g_rx_desc_discard <= 0;
+ end
+ end
+end
+
+
+endmodule
diff --git a/verilog/rtl/lib/pulse_gen_type1.sv b/verilog/rtl/lib/pulse_gen_type1.sv
new file mode 100644
index 0000000..b209ca0
--- /dev/null
+++ b/verilog/rtl/lib/pulse_gen_type1.sv
@@ -0,0 +1,54 @@
+///////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//------------------------------------------------------------------------
+// This module is used to generate 1ms and 1sec pulse based on 1us trigger
+// pulse
+//------------------------------------------------------------------------
+
+module pulse_gen_type1(
+ output logic clk_pulse,
+
+ input logic clk,
+ input logic reset_n,
+ input logic trigger
+);
+
+parameter WD= 10; // This will count from 0 to 1023
+parameter MAX_CNT = 999;
+
+logic [WD-1:0] cnt;
+
+assign clk_pulse = (cnt == 0) && trigger;
+
+always @ (posedge clk or negedge reset_n)
+begin
+ if (reset_n == 1'b0) begin
+ cnt <= 'b0;
+ end else begin
+ if(trigger) begin
+ if(cnt >= MAX_CNT)
+ cnt <= 0;
+ else
+ cnt <= cnt +1;
+ end
+ end
+end
+
+endmodule
+
diff --git a/verilog/rtl/lib/pulse_gen_type2.sv b/verilog/rtl/lib/pulse_gen_type2.sv
new file mode 100644
index 0000000..f9bcae3
--- /dev/null
+++ b/verilog/rtl/lib/pulse_gen_type2.sv
@@ -0,0 +1,53 @@
+///////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//------------------------------------------------------------------------
+// This module is used to generate 1us based on config value
+//------------------------------------------------------------------------
+
+module pulse_gen_type2 #(parameter WD = 10)
+ (
+ output logic clk_pulse,
+
+ input logic clk,
+ input logic reset_n,
+ input logic [WD-1:0] cfg_max_cnt
+);
+
+
+logic [WD-1:0] cnt;
+
+
+always @ (posedge clk or negedge reset_n)
+begin
+ if (reset_n == 1'b0) begin
+ cnt <= 'b0;
+ clk_pulse <= 'b0;
+ end else begin
+ if(cnt == cfg_max_cnt) begin
+ cnt <= 0;
+ clk_pulse <= 1'b1;
+ end else begin
+ cnt <= cnt +1;
+ clk_pulse <= 1'b0;
+ end
+ end
+end
+
+endmodule
+
diff --git a/verilog/rtl/lib/registers.v b/verilog/rtl/lib/registers.v
new file mode 100755
index 0000000..e4a87a1
--- /dev/null
+++ b/verilog/rtl/lib/registers.v
@@ -0,0 +1,329 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores common library Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Mar 2, 2011 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+/*********************************************************************
+** module: bit register
+
+** description: infers a register, make it modular
+ ***********************************************************************/
+module bit_register (
+ //inputs
+ we,
+ clk,
+ reset_n,
+ data_in,
+
+ //outputs
+ data_out
+ );
+
+//---------------------------------
+// Reset Default value
+//---------------------------------
+parameter RESET_DEFAULT = 1'h0;
+
+ input we;
+ input clk;
+ input reset_n;
+ input data_in;
+ output data_out;
+
+ reg data_out;
+
+ //infer the register
+ always @(posedge clk or negedge reset_n)
+ begin
+ if (!reset_n)
+ data_out <= RESET_DEFAULT;
+ else if (we)
+ data_out <= data_in;
+ end // always @ (posedge clk or negedge reset_n)
+endmodule // register
+
+
+/*********************************************************************
+** module: req register.
+
+** description: This register is set by cpu writting 1 and reset by
+ harward req = 1
+
+ Note: When there is a clash between cpu and hardware, cpu is given higher
+ priority
+
+ ***********************************************************************/
+module req_register (
+ //inputs
+ clk,
+ reset_n,
+ cpu_we,
+ cpu_req,
+ hware_ack,
+
+ //outputs
+ data_out
+ );
+
+//---------------------------------
+// Reset Default value
+//---------------------------------
+parameter RESET_DEFAULT = 1'h0;
+
+ input clk ;
+ input reset_n ;
+ input cpu_we ; // cpu write enable
+ input cpu_req ; // CPU Request
+ input hware_ack; // Hardware Ack
+ output data_out ;
+
+ reg data_out;
+
+ //infer the register
+ always @(posedge clk or negedge reset_n)
+ begin
+ if (!reset_n)
+ data_out <= RESET_DEFAULT;
+ else if (cpu_we & cpu_req) // Set on CPU Request
+ data_out <= 1'b1;
+ else if (hware_ack) // Reset the flag on Hardware ack
+ data_out <= 1'b0;
+ end // always @ (posedge clk or negedge reset_n)
+endmodule // register
+
+
+/*********************************************************************
+** module: req register.
+
+** description: This register is cleared by cpu writting 1 and set by
+ harward req = 1
+
+ Note: When there is a clash between cpu and hardware,
+ hardware is given higher priority
+
+ ***********************************************************************/
+module stat_register (
+ //inputs
+ clk,
+ reset_n,
+ cpu_we,
+ cpu_ack,
+ hware_req,
+
+ //outputs
+ data_out
+ );
+
+//---------------------------------
+// Reset Default value
+//---------------------------------
+parameter RESET_DEFAULT = 1'h0;
+
+ input clk ;
+ input reset_n ;
+ input cpu_we ; // cpu write enable
+ input cpu_ack ; // CPU Ack
+ input hware_req; // Hardware Req
+ output data_out ;
+
+ reg data_out;
+
+ //infer the register
+ always @(posedge clk or negedge reset_n)
+ begin
+ if (!reset_n)
+ data_out <= RESET_DEFAULT;
+ else if (hware_req) // Set the flag on Hardware Req
+ data_out <= 1'b1;
+ else if (cpu_we & cpu_ack) // Clear on CPU Ack
+ data_out <= 1'b0;
+ end // always @ (posedge clk or negedge reset_n)
+endmodule // register
+
+
+
+
+
+/*********************************************************************
+ module: generic register
+***********************************************************************/
+module generic_register (
+ //List of Inputs
+ we,
+ data_in,
+ reset_n,
+ clk,
+
+ //List of Outs
+ data_out
+ );
+
+ parameter WD = 1;
+ parameter RESET_DEFAULT = 0;
+ input [WD-1:0] we;
+ input [WD-1:0] data_in;
+ input reset_n;
+ input clk;
+ output [WD-1:0] data_out;
+
+
+generate
+ genvar i;
+ for (i = 0; i < WD; i = i + 1) begin : gen_bit_reg
+ bit_register #(RESET_DEFAULT[i]) u_bit_reg (
+ .we (we[i]),
+ .clk (clk),
+ .reset_n (reset_n),
+ .data_in (data_in[i]),
+ .data_out (data_out[i])
+ );
+ end
+endgenerate
+
+
+endmodule
+
+
+/*********************************************************************
+ module: generic interrupt status
+***********************************************************************/
+module generic_intr_stat_reg (
+ //inputs
+ clk,
+ reset_n,
+ reg_we,
+ reg_din,
+ hware_req,
+
+ //outputs
+ data_out
+ );
+
+ parameter WD = 1;
+ parameter RESET_DEFAULT = 0;
+ input [WD-1:0] reg_we;
+ input [WD-1:0] reg_din;
+ input [WD-1:0] hware_req;
+ input reset_n;
+ input clk;
+ output [WD-1:0] data_out;
+
+
+generate
+ genvar i;
+ for (i = 0; i < WD; i = i + 1) begin : gen_bit_reg
+ stat_register #(RESET_DEFAULT[i]) u_bit_reg (
+ //inputs
+ . clk (clk ),
+ . reset_n (reset_n ),
+ . cpu_we (reg_we[i] ),
+ . cpu_ack (reg_din[i] ),
+ . hware_req (hware_req[i] ),
+
+ //outputs
+ . data_out (data_out[i] )
+ );
+
+ end
+endgenerate
+
+
+endmodule
+
+/*********************************************************************
+ module: generic 32b register
+***********************************************************************/
+module gen_32b_reg (
+ //List of Inputs
+ cs,
+ we,
+ data_in,
+ reset_n,
+ clk,
+
+ //List of Outs
+ data_out
+ );
+
+ parameter RESET_DEFAULT = 32'h0;
+ input [3:0] we;
+ input cs;
+ input [31:0] data_in;
+ input reset_n;
+ input clk;
+ output [31:0] data_out;
+
+
+ reg [31:0] data_out;
+
+always @ (posedge clk or negedge reset_n) begin
+ if (reset_n == 1'b0) begin
+ data_out <= RESET_DEFAULT ;
+ end
+ else begin
+ if(cs && we[0]) data_out[7:0] <= data_in[7:0];
+ if(cs && we[1]) data_out[15:8] <= data_in[15:8];
+ if(cs && we[2]) data_out[23:16] <= data_in[23:16];
+ if(cs && we[3]) data_out[31:24] <= data_in[31:24];
+ end
+end
+
+
+endmodule
diff --git a/verilog/rtl/lib/reset_sync.sv b/verilog/rtl/lib/reset_sync.sv
new file mode 100644
index 0000000..d96c719
--- /dev/null
+++ b/verilog/rtl/lib/reset_sync.sv
@@ -0,0 +1,101 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Active low reset synchronization ////
+//// ////
+//// This file is part of the yifive cores project ////
+//// https://github.com/dineshannayya/yifive_r0.git ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description: ////
+//// Synchronize the active low reset to destination clock ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// v0: June 17, 2021, Dinesh A ////
+//// Initial version ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module reset_sync (
+ scan_mode ,
+ dclk , // Destination clock domain
+ arst_n , // active low async reset
+ srst_n
+ );
+
+parameter WIDTH = 1;
+
+input scan_mode ; // test mode
+input dclk ; // Destination clock
+input arst_n ; // Async Reset
+output srst_n ; // Sync Reset w.r.t dclk
+
+
+reg in_data_s ; // One Cycle sync
+reg in_data_2s ; // two Cycle sync
+
+assign srst_n = (scan_mode) ? arst_n : in_data_2s;
+
+always @(negedge arst_n or posedge dclk)
+begin
+ if(arst_n == 1'b0)
+ begin
+ in_data_s <= 1'b0;
+ in_data_2s <= 1'b0;
+ end
+ else
+ begin
+ in_data_s <= 1'b1;
+ in_data_2s <= in_data_s;
+ end
+end
+
+
+endmodule
diff --git a/verilog/rtl/lib/ser_inf_32b.sv b/verilog/rtl/lib/ser_inf_32b.sv
new file mode 100644
index 0000000..8228852
--- /dev/null
+++ b/verilog/rtl/lib/ser_inf_32b.sv
@@ -0,0 +1,121 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// ser_inf_32 ////
+//// ////
+//// This file is part of the mbist_ctrl cores project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block manages the serial to Parallel conversion ////
+//// This block usefull for Bist SDI/SDO access ////
+//// Function: ////
+//// 1. When reg_wr=1, this block set shift=1 and shift ////
+//// reg_wdata serial through sdi for 32 cycles and ////
+//// asserts Reg Ack ////
+//// 2. When reg_rd=1, this block set shoft=1 and serial ////
+//// capture the sdo to reg_rdata for 32 cycles and ////
+//// asserts Reg Ack ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 20th Oct 2021, Dinesh A ////
+//// Initial integration ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module ser_inf_32b
+ (
+
+ // Master Port
+ input logic rst_n , // Regular Reset signal
+ input logic clk , // System clock
+ input logic reg_wr , // Write Request
+ input logic reg_rd , // Read Request
+ input logic [31:0] reg_wdata , // data output
+ output logic [31:0] reg_rdata , // data input
+ output logic reg_ack , // acknowlegement
+
+ // Slave Port
+ output logic sdi , // Serial SDI
+ output logic shift , // Shift Signal
+ input logic sdo // Serial SDO
+
+ );
+
+
+ parameter IDLE = 1'b0;
+ parameter SHIFT_DATA = 1'b1;
+
+ logic state;
+ logic [5:0] bit_cnt;
+ logic [31:0] shift_data;
+
+
+always@(negedge rst_n or posedge clk)
+begin
+ if(rst_n == 0) begin
+ state <= IDLE;
+ reg_rdata <= 'h0;
+ reg_ack <= 1'b0;
+ sdi <= 1'b0;
+ bit_cnt <= 6'h0;
+ shift <= 'b0;
+ shift_data <= 32'h0;
+ end else begin
+ case(state)
+ IDLE: begin
+ reg_ack <= 1'b0;
+ bit_cnt <= 6'h0;
+ if(reg_wr) begin
+ shift <= 'b1;
+ shift_data <= reg_wdata;
+ state <= SHIFT_DATA;
+ end else if(reg_rd) begin
+ shift <= 'b1;
+ shift_data <= 'h0;
+ state <= SHIFT_DATA;
+ end
+ end
+ SHIFT_DATA: begin
+ shift_data <= {1'b0,shift_data[31:1]};
+ reg_rdata <= {sdo,reg_rdata[31:1]};
+ sdi <= shift_data[0];
+ if(bit_cnt < 31) begin
+ bit_cnt <= bit_cnt +1;
+ end else begin
+ reg_ack <= 1'b1;
+ shift <= 'b0;
+ state <= IDLE;
+ end
+ end
+ endcase
+ end
+end
+
+
+
+
+endmodule
diff --git a/verilog/rtl/lib/ser_shift.sv b/verilog/rtl/lib/ser_shift.sv
new file mode 100644
index 0000000..21ef9dc
--- /dev/null
+++ b/verilog/rtl/lib/ser_shift.sv
@@ -0,0 +1,76 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// ser_shift ////
+//// ////
+//// This file is part of the mbist_ctrl cores project ////
+//// https://github.com/dineshannayya/riscdunio.git ////
+//// ////
+//// Description ////
+//// This block manages the parallel to serial conversion ////
+//// This block usefull for Bist SDI/SDO access ////
+//// asserts Reg Ack ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 16th Dec 2021, Dinesh A ////
+//// Initial integration ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module ser_shift
+ #(parameter WD = 32)
+ (
+
+ // Master Port
+ input logic rst_n , // Regular Reset signal
+ input logic clk , // System clock
+ input logic load , // load request
+ input logic shift , // shift
+ input logic [WD-1:0] load_data , // load data
+ input logic sdi , // sdi
+ output logic sdo // sdo
+
+
+ );
+
+logic [WD-1:0] shift_reg;
+
+always@(negedge rst_n or posedge clk)
+begin
+ if(rst_n == 0) begin
+ shift_reg <= 'h0;
+ end else if(load) begin
+ shift_reg <= load_data;
+ end else if(shift) begin
+ shift_reg <= {sdi,shift_reg[WD-1:1]};
+ end
+end
+
+assign sdo = shift_reg[0];
+
+
+
+endmodule
diff --git a/verilog/rtl/lib/sfifo.v b/verilog/rtl/lib/sfifo.v
new file mode 100644
index 0000000..b0ea8c1
--- /dev/null
+++ b/verilog/rtl/lib/sfifo.v
@@ -0,0 +1,77 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores common library Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Mar 2, 2011 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module sfifo (QA,CLKA,CENA,AA,CLKB,CENB,AB,DB);
+
+parameter DW = 10; // Data Width
+parameter AW = 5; // Address Width
+parameter FW = 32; // FIFO DEPTH
+
+output [DW-1:0] QA;
+
+input CLKA;
+input CENA;
+input [AW-1:0] AA;
+input CLKB;
+input CENB;
+input [AW-1:0] AB;
+input [DW-1:0] DB;
+
+reg [DW-1:0] QA;
+reg [DW-1:0] ram [FW-1:0];
+
+always @ (posedge CLKB)
+begin
+ if (!CENB)
+ ram[AB] <= DB;
+end
+
+always @ (posedge CLKA)
+begin
+ if (!CENA)
+ QA <= ram[AA];
+end
+
+endmodule
diff --git a/verilog/rtl/lib/stat_counter.v b/verilog/rtl/lib/stat_counter.v
new file mode 100755
index 0000000..60c121f
--- /dev/null
+++ b/verilog/rtl/lib/stat_counter.v
@@ -0,0 +1,127 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores common library Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Mar 2, 2011 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+// -----------------------------------------------------------------------
+// Module Name : stat_counter.v
+// Company :
+// Creation date :
+// -----------------------------------------------------------------------
+// Description : This is the general purpose statistics counter.
+//
+//
+// References :
+// ------------------------------------------------------------------------
+
+//----------------- compiler directives -----------------------------------
+
+// ------------------------------------------------------------------------
+module stat_counter
+ (
+ // Clock and Reset Signals
+ sys_clk,
+ s_reset_n,
+
+ count_inc,
+ count_dec,
+
+ reg_sel,
+ reg_wr_data,
+ reg_wr,
+
+ cntr_intr,
+ cntrout
+
+
+ );
+
+parameter CWD = 1; // Counter Width
+ //-------------------- Parameters -------------------------------------
+
+ // ------------------- Clock and Reset Signals ------------------------
+ input sys_clk;
+ input s_reset_n;
+ input count_inc; // Counter Increment
+ input count_dec; // counter decrement, assuption does not under flow
+ input reg_sel;
+ input reg_wr;
+ input [CWD-1:0] reg_wr_data;
+ output cntr_intr;
+ output [CWD-1:0] cntrout;
+ // ------------------- Register Declarations --------------------------
+ reg [CWD-1:0] reg_trig_cntr;
+
+
+// ------------------- Logic Starts Here ----------------------------------
+
+
+
+always @ (posedge sys_clk or negedge s_reset_n)
+begin
+ if (s_reset_n == 1'b0) begin
+ reg_trig_cntr <= 'b0;
+ end
+ else begin
+ if (reg_sel && reg_wr) begin
+ reg_trig_cntr <= reg_wr_data;
+ end
+ else begin
+ if (count_inc && count_dec)
+ reg_trig_cntr <= reg_trig_cntr;
+ else if (count_inc)
+ reg_trig_cntr <= reg_trig_cntr + 1'b1;
+ else if (count_dec)
+ reg_trig_cntr <= reg_trig_cntr - 1'b1;
+ else
+ reg_trig_cntr <= reg_trig_cntr;
+ end
+ end
+end
+// only increment overflow is assumed
+// decrement underflow is not handled
+assign cntr_intr = ((reg_trig_cntr + 1) == 'h0 && count_inc) ;
+
+assign cntrout = reg_trig_cntr;
+
+endmodule // must_stat_counter
diff --git a/verilog/rtl/lib/sync_fifo.sv b/verilog/rtl/lib/sync_fifo.sv
new file mode 100644
index 0000000..464a26c
--- /dev/null
+++ b/verilog/rtl/lib/sync_fifo.sv
@@ -0,0 +1,167 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+/*********************************************************************
+
+ This file is part of the sdram controller project
+ http://www.opencores.org/cores/sdr_ctrl/
+ https://github.com/dineshannayya/yifive_r0.git
+
+ Description: SYNC FIFO
+ Parameters:
+ W : Width (integer)
+ D : Depth (integer, power of 2, 4 to 256)
+
+ To Do:
+ nothing
+
+ Author(s): Dinesh Annayya, dinesha@opencores.org
+
+ Copyright (C) 2000 Authors and OPENCORES.ORG
+
+ This source file may be used and distributed without
+ restriction provided that this copyright statement is not
+ removed from the file and that any derivative work contains
+ the original copyright notice and the associated disclaimer.
+
+ This source file is free software; you can redistribute it
+ and/or modify it under the terms of the GNU Lesser General
+ Public License as published by the Free Software Foundation;
+ either version 2.1 of the License, or (at your option) any
+later version.
+
+ This source is distributed in the hope that it will be
+ useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+ PURPOSE. See the GNU Lesser General Public License for more
+ details.
+
+ You should have received a copy of the GNU Lesser General
+ Public License along with this source; if not, download it
+ from http://www.opencores.org/lgpl.shtml
+
+*******************************************************************/
+
+
+module sync_fifo (clk,
+ reset_n,
+ wr_en,
+ wr_data,
+ full,
+ empty,
+ rd_en,
+ rd_data);
+
+ parameter W = 8;
+ parameter D = 4;
+
+ parameter AW = (D == 2) ? 1 :
+ (D == 4) ? 2 :
+ (D == 8) ? 3 :
+ (D == 16) ? 4 :
+ (D == 32) ? 5 :
+ (D == 64) ? 6 :
+ (D == 128) ? 7 :
+ (D == 256) ? 8 : 0;
+
+ output [W-1 : 0] rd_data;
+ input [W-1 : 0] wr_data;
+ input clk, reset_n, wr_en, rd_en;
+ output full, empty;
+
+ // synopsys translate_off
+
+ initial begin
+ if (AW == 0) begin
+ $display ("%m : ERROR!!! Fifo depth %d not in range 4 to 256", D);
+ end // if (AW == 0)
+ end // initial begin
+
+ // synopsys translate_on
+
+
+ reg [W-1 : 0] mem[D-1 : 0];
+ reg [AW-1 : 0] rd_ptr, wr_ptr;
+ reg full, empty;
+
+ wire [W-1 : 0] rd_data;
+
+ always @ (posedge clk or negedge reset_n)
+ if (reset_n == 1'b0) begin
+ wr_ptr <= {AW{1'b0}} ;
+ end
+ else begin
+ if (wr_en & !full) begin
+ wr_ptr <= wr_ptr + 1'b1 ;
+ end
+ end
+
+ always @ (posedge clk or negedge reset_n)
+ if (reset_n == 1'b0) begin
+ rd_ptr <= {AW{1'b0}} ;
+ end
+ else begin
+ if (rd_en & !empty) begin
+ rd_ptr <= rd_ptr + 1'b1 ;
+ end
+ end
+
+
+ always @ (posedge clk or negedge reset_n)
+ if (reset_n == 1'b0) begin
+ empty <= 1'b1 ;
+ end
+ else begin
+ empty <= (((wr_ptr - rd_ptr) == {{(AW-1){1'b0}}, 1'b1}) & rd_en & ~wr_en) ? 1'b1 :
+ ((wr_ptr == rd_ptr) & ~rd_en & wr_en) ? 1'b0 : empty ;
+ end
+
+ always @ (posedge clk or negedge reset_n)
+ if (reset_n == 1'b0) begin
+ full <= 1'b0 ;
+ end
+ else begin
+ full <= (((wr_ptr - rd_ptr) == {{(AW-1){1'b1}}, 1'b0}) & ~rd_en & wr_en) ? 1'b1 :
+ (((wr_ptr - rd_ptr) == {AW{1'b1}}) & rd_en & ~wr_en) ? 1'b0 : full ;
+ end
+
+ always @ (posedge clk)
+ if (wr_en)
+ mem[wr_ptr] <= wr_data;
+
+assign rd_data = mem[rd_ptr];
+
+
+// synopsys translate_off
+ always @(posedge clk) begin
+ if (wr_en && full) begin
+ $display("%m : Error! sfifo overflow!");
+ end
+ end
+
+ always @(posedge clk) begin
+ if (rd_en && empty) begin
+ $display("%m : error! sfifo underflow!");
+ end
+ end
+
+// synopsys translate_on
+//---------------------------------------
+
+endmodule
+
+
diff --git a/verilog/rtl/lib/sync_fifo2.sv b/verilog/rtl/lib/sync_fifo2.sv
new file mode 100755
index 0000000..f71ad30
--- /dev/null
+++ b/verilog/rtl/lib/sync_fifo2.sv
@@ -0,0 +1,222 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+/*********************************************************************
+
+ SYNC FIFO with empty,aempty,full,afull
+
+
+ Description: SYNC FIFO
+
+ To Do:
+ nothing
+
+ Author(s): Dinesh Annayya, dinesha@opencores.org
+
+ Copyright (C) 2000 Authors and OPENCORES.ORG
+
+ This source file may be used and distributed without
+ restriction provided that this copyright statement is not
+ removed from the file and that any derivative work contains
+ the original copyright notice and the associated disclaimer.
+
+ This source file is free software; you can redistribute it
+ and/or modify it under the terms of the GNU Lesser General
+ Public License as published by the Free Software Foundation;
+ either version 2.1 of the License, or (at your option) any
+later version.
+
+ This source is distributed in the hope that it will be
+ useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+ PURPOSE. See the GNU Lesser General Public License for more
+ details.
+
+ You should have received a copy of the GNU Lesser General
+ Public License along with this source; if not, download it
+ from http://www.opencores.org/lgpl.shtml
+
+*******************************************************************/
+
+//-------------------------------------------
+// sync FIFO
+//-----------------------------------------------
+//`timescale 1ns/1ps
+
+module sync_fifo2 (clk,
+ reset_n,
+ wr_en,
+ wr_data,
+ full,
+ afull,
+ rd_en,
+ empty,
+ aempty,
+ rd_data);
+
+ parameter W = 4'd8;
+ parameter DP = 3'd4;
+ parameter WR_FAST = 1'b1;
+ parameter RD_FAST = 1'b1;
+ parameter FULL_DP = DP;
+ parameter EMPTY_DP = 1'b0;
+
+ parameter AW = (DP == 2) ? 1 :
+ (DP == 4) ? 2 :
+ (DP == 8) ? 3 :
+ (DP == 16) ? 4 :
+ (DP == 32) ? 5 :
+ (DP == 64) ? 6 :
+ (DP == 128) ? 7 :
+ (DP == 256) ? 8 : 0;
+
+ output [W-1 : 0] rd_data;
+ input [W-1 : 0] wr_data;
+ input clk, reset_n, wr_en, rd_en;
+ output full, empty;
+ output afull, aempty; // about full and about to empty
+
+
+ // synopsys translate_off
+
+ initial begin
+ if (AW == 0) begin
+ $display ("%m : ERROR!!! Fifo depth %d not in range 2 to 256", DP);
+ end // if (AW == 0)
+ end // initial begin
+
+ // synopsys translate_on
+
+ reg [W-1 : 0] mem[DP-1 : 0];
+
+ /*********************** write side ************************/
+ reg [AW:0] wr_ptr;
+ reg full_q;
+ wire full_c;
+ wire afull_c;
+ wire [AW:0]wr_ptr_inc = wr_ptr + 1'b1;
+ wire [AW:0]wr_cnt = get_cnt(wr_ptr, rd_ptr);
+
+ assign full_c = (wr_cnt == FULL_DP) ? 1'b1 : 1'b0;
+ assign afull_c = (wr_cnt == FULL_DP-1) ? 1'b1 : 1'b0;
+
+
+ always @(posedge clk or negedge reset_n) begin
+ if (!reset_n) begin
+ wr_ptr <= 0;
+ full_q <= 0;
+ end
+ else if (wr_en) begin
+ wr_ptr <= wr_ptr_inc;
+ if (wr_cnt == (FULL_DP-1)) begin
+ full_q <= 1'b1;
+ end
+ end
+ else begin
+ if (full_q && (wr_cnt<FULL_DP)) begin
+ full_q <= 1'b0;
+ end
+ end
+ end
+
+ assign full = (WR_FAST == 1) ? full_c : full_q;
+ assign afull = afull_c;
+
+ always @(posedge clk) begin
+ if (wr_en) begin
+ mem[wr_ptr[AW-1:0]] <= wr_data;
+ end
+ end
+
+
+
+ /************************ read side *****************************/
+ reg [AW:0] rd_ptr;
+ reg empty_q;
+ wire empty_c;
+ wire aempty_c;
+ wire [AW:0] rd_ptr_inc = rd_ptr + 1'b1;
+ wire [AW:0] rd_cnt = get_cnt(wr_ptr, rd_ptr);
+
+ assign empty_c = (rd_cnt == 0) ? 1'b1 : 1'b0;
+ assign aempty_c = (rd_cnt == 1) ? 1'b1 : 1'b0;
+
+ always @(posedge clk or negedge reset_n) begin
+ if (!reset_n) begin
+ rd_ptr <= 0;
+ empty_q <= 1'b1;
+ end
+ else begin
+ if (rd_en) begin
+ rd_ptr <= rd_ptr_inc;
+ if (rd_cnt==(EMPTY_DP+1)) begin
+ empty_q <= 1'b1;
+ end
+ end
+ else begin
+ if (empty_q && (rd_cnt!=EMPTY_DP)) begin
+ empty_q <= 1'b0;
+ end
+ end
+ end
+ end
+
+ assign empty = (RD_FAST == 1) ? empty_c : empty_q;
+ assign aempty = aempty_c;
+
+ reg [W-1 : 0] rd_data_q;
+
+ wire [W-1 : 0] rd_data_c = mem[rd_ptr[AW-1:0]];
+
+
+ always @(posedge clk) begin
+ rd_data_q <= rd_data_c;
+ end
+ assign rd_data = (RD_FAST == 1) ? rd_data_c : rd_data_q;
+
+
+
+
+function [AW:0] get_cnt;
+input [AW:0] wr_ptr, rd_ptr;
+begin
+ if (wr_ptr >= rd_ptr) begin
+ get_cnt = (wr_ptr - rd_ptr);
+ end
+ else begin
+ get_cnt = DP*2 - (rd_ptr - wr_ptr);
+ end
+end
+endfunction
+
+// synopsys translate_off
+always @(posedge clk) begin
+ if (wr_en && full) begin
+ $display($time, "%m Error! afifo overflow!");
+ $stop;
+ end
+end
+
+always @(posedge clk) begin
+ if (rd_en && empty) begin
+ $display($time, "%m error! afifo underflow!");
+ $stop;
+ end
+end
+// synopsys translate_on
+
+endmodule
diff --git a/verilog/rtl/lib/sync_wbb.sv b/verilog/rtl/lib/sync_wbb.sv
new file mode 100644
index 0000000..e2cc794
--- /dev/null
+++ b/verilog/rtl/lib/sync_wbb.sv
@@ -0,0 +1,336 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// sync Wishbone Interface iBurst Enable and lack ////
+//// ////
+//// This file is part of the YIFive cores project ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description ////
+//// This block does async Wishbone from one clock to other ////
+//// clock domain
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 25th Feb 2021, Dinesh A ////
+//// initial version ////
+//// 0.2 - 28th Feb 2021, Dinesh A ////
+//// reduced the response FIFO path depth to 2 as ////
+//// return path used by only read logic and read is ////
+//// blocking request and expect only one location will ////
+//// be used ////
+//// 0.3 - 20 Jan 2022, Dinesh A ////
+//// added wishbone burst mode. Additional signal added ////
+//// A. *bl - 10 Bit word Burst count, 1 - 1 DW(32 bit)////
+//// B. *lack - Last Burst ack ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module sync_wbb
+ #(parameter AW = 32,
+ parameter BW = 4,
+ parameter BL = 10,
+ parameter DW = 32)
+ (
+
+ // Master Port
+ input logic rst_n , // Regular Reset signal
+ input logic clk_i , // System clock
+ input logic wbm_cyc_i , // strobe/request
+ input logic wbm_stb_i , // strobe/request
+ input logic [AW-1:0] wbm_adr_i , // address
+ input logic wbm_we_i , // write
+ input logic [DW-1:0] wbm_dat_i , // data output
+ input logic [BW-1:0] wbm_sel_i , // byte enable
+ input logic [3:0] wbm_tid_i ,
+ input logic [BL-1:0] wbm_bl_i , // Burst Count
+ input logic wbm_bry_i , // Burst Ready
+ output logic [DW-1:0] wbm_dat_o , // data input
+ output logic wbm_ack_o , // acknowlegement
+ output logic wbm_lack_o , // Last Burst access
+ output logic wbm_err_o , // error
+
+ // Slave Port
+ output logic wbs_cyc_o , // strobe/request
+ output logic wbs_stb_o , // strobe/request
+ output logic [AW-1:0] wbs_adr_o , // address
+ output logic wbs_we_o , // write
+ output logic [DW-1:0] wbs_dat_o , // data output
+ output logic [BW-1:0] wbs_sel_o , // byte enable
+ output logic [3:0] wbs_tid_o ,
+ output logic [BL-1:0] wbs_bl_o , // Burst Count
+ output logic wbs_bry_o , // Busrt WData Avialble Or Ready To accept Rdata
+ input logic [DW-1:0] wbs_dat_i , // data input
+ input logic wbs_ack_i , // acknowlegement
+ input logic wbs_lack_i , // Last Ack
+ input logic wbs_err_i // error
+
+ );
+
+
+
+parameter CFW = AW+DW+BW+BL+4+1 ; // COMMAND FIFO WIDTH
+parameter RFW = DW+1+1 ; // RESPONSE FIFO WIDTH
+
+parameter IDLE = 2'b00;
+parameter WRITE_DATA = 2'b01;
+parameter READ_DATA = 2'b10;
+
+
+//-------------------------------------------------
+// Master Interface
+// -------------------------------------------------
+logic m_cmd_wr_en ;
+logic [CFW-1:0] m_cmd_wr_data ;
+logic m_cmd_wr_full ;
+logic m_cmd_wr_afull ;
+
+logic m_resp_rd_empty ;
+logic m_resp_rd_aempty ;
+logic m_resp_rd_en ;
+logic [RFW-1:0] m_resp_rd_data ;
+logic [BL-1:0] m_bl_cnt ;
+logic [1:0] m_state ;
+
+// Master Write Interface
+
+
+
+assign m_cmd_wr_data = {wbm_adr_i,wbm_we_i,wbm_dat_i,wbm_sel_i,wbm_tid_i,wbm_bl_i};
+
+assign wbm_dat_o = m_resp_rd_data[DW-1:0];
+assign wbm_err_o = 'b0;
+
+always@(negedge rst_n or posedge clk_i)
+begin
+ if(rst_n == 0) begin
+ m_cmd_wr_en <= 'b0;
+ m_resp_rd_en <= 'b0;
+ m_state <= 'h0;
+ m_bl_cnt <= 'h0;
+ wbm_ack_o <= 'b0;
+ wbm_lack_o <= 'b0;
+ end else begin
+ case(m_state)
+ IDLE: begin
+ // Read DATA
+ // Make sure that FIFO is not overflow and there is no previous
+ // pending write + fifo is about to full
+ if(wbm_stb_i && !wbm_we_i && wbm_bry_i && !m_cmd_wr_full && !(m_cmd_wr_afull && m_cmd_wr_en) && !wbm_lack_o) begin
+ m_bl_cnt <= wbm_bl_i;
+ m_cmd_wr_en <= 'b1;
+ m_state <= READ_DATA;
+ end else if(wbm_stb_i && wbm_we_i && wbm_bry_i && !m_cmd_wr_full && !(m_cmd_wr_afull && m_cmd_wr_en) && !wbm_lack_o) begin
+ wbm_ack_o <= 'b1;
+ m_cmd_wr_en <= 'b1;
+ m_bl_cnt <= wbm_bl_i-1;
+ if(wbm_bl_i == 'h1) begin
+ wbm_lack_o <= 'b1;
+ m_state <= IDLE;
+ end else begin
+ m_bl_cnt <= wbm_bl_i-1;
+ m_state <= WRITE_DATA;
+ end
+ end else begin
+ m_resp_rd_en <= 'b0;
+ m_cmd_wr_en <= 'b0;
+ wbm_ack_o <= 'b0;
+ wbm_lack_o <= 'b0;
+ end
+ end
+
+ // Write next Transaction
+ WRITE_DATA: begin
+ if(m_cmd_wr_full != 1 && !(m_cmd_wr_afull && m_cmd_wr_en) && wbm_bry_i) begin
+ wbm_ack_o <= 'b1;
+ m_cmd_wr_en <= 'b1;
+ if(m_bl_cnt == 1) begin
+ wbm_lack_o <= 'b1;
+ m_state <= IDLE;
+ end else begin
+ m_bl_cnt <= m_bl_cnt-1;
+ end
+ end else begin
+ m_cmd_wr_en <= 'b0;
+ wbm_ack_o <= 'b0;
+ wbm_lack_o <= 'b0;
+ end
+ end
+
+ // Read Transaction
+ READ_DATA: begin
+ // Check Back to Back Ack and last Location case
+ if(((wbm_ack_o == 0 && m_resp_rd_empty != 1) ||
+ (wbm_ack_o == 1 && m_resp_rd_aempty != 1)) && wbm_bry_i) begin
+ m_resp_rd_en <= 'b1;
+ wbm_ack_o <= 'b1;
+ if(m_bl_cnt == 1) begin
+ wbm_lack_o <= 'b1;
+ m_state <= IDLE;
+ end else begin
+ m_bl_cnt <= m_bl_cnt-1;
+ end
+ end else begin
+ m_resp_rd_en <= 'b0;
+ m_cmd_wr_en <= 'b0;
+ wbm_ack_o <= 'b0;
+ wbm_lack_o <= 'b0;
+ end
+ end
+ endcase
+ end
+end
+
+
+//------------------------------
+// Slave Interface
+//-------------------------------
+
+logic [CFW-1:0] s_cmd_rd_data ;
+logic [CFW-1:0] s_cmd_rd_data_l ;
+logic s_cmd_rd_empty ;
+logic s_cmd_rd_aempty ;
+logic s_cmd_rd_en ;
+logic s_resp_wr_en ;
+logic [RFW-1:0] s_resp_wr_data ;
+logic s_resp_wr_full ;
+logic s_resp_wr_afull ;
+logic wbs_ack_f ;
+logic wbs_stb_l ;
+logic wbs_burst ;
+
+wire wbs_stb_pedge = (wbs_stb_l == 1'b0) && wbs_stb_o;
+
+
+always@(negedge rst_n or posedge clk_i)
+begin
+ if(rst_n == 0) begin
+ wbs_ack_f <= 1'b0;
+ wbs_stb_l <= 1'b0;
+ wbs_burst <= 'h0;
+ s_cmd_rd_data_l <= 'h0;
+ end else begin
+ wbs_ack_f <= wbs_lack_i;
+ wbs_stb_l <= wbs_stb_o;
+ if(s_cmd_rd_en)
+ s_cmd_rd_data_l <= s_cmd_rd_data;
+ if(wbs_stb_pedge && wbs_bl_o > 'h1)
+ wbs_burst <= 1'b1;
+ else if(wbs_lack_i)
+ wbs_burst <= 1'b0;
+ end
+end
+
+
+// Read Interface
+
+
+assign {wbs_adr_o,wbs_we_o,wbs_dat_o,wbs_sel_o,wbs_tid_o,wbs_bl_o} = (s_cmd_rd_empty) ? s_cmd_rd_data_l: s_cmd_rd_data;
+// All the downstream logic expect Stobe is getting de-asserted
+// atleast for 1 cycle after ack is generated
+assign wbs_stb_o = (wbs_burst) ? 1'b1 : ((wbs_ack_f) ? 1'b0 : (s_cmd_rd_empty) ? 1'b0: 1'b1);
+assign wbs_cyc_o = (wbs_burst) ? 1'b1 : ((wbs_ack_f) ? 1'b0 : (s_cmd_rd_empty) ? 1'b0: 1'b1);
+
+// Generate bust ready only we have space inside response fifo
+// In Write Phase,
+// Generate burst ready, only when we have wdata & space in response fifo
+// In Read Phase
+// Generate burst ready, only when space in response fifo
+//
+assign wbs_bry_o = (wbs_we_o) ? ((s_cmd_rd_empty || (s_cmd_rd_en && s_cmd_rd_aempty)) ? 1'b0: 1'b1) :
+ (s_resp_wr_full || (s_resp_wr_en && s_resp_wr_afull)) ? 1'b0: 1'b1;
+
+// During Write phase, cmd fifo will have wdata, so dequeue for every ack
+// During Read Phase, cmd fifo will be written only one time, hold the bus
+// untill last ack received
+assign s_cmd_rd_en = (wbs_stb_o && wbs_we_o) ? wbs_ack_i: wbs_lack_i;
+
+// Write Interface
+// response send only for read logic
+assign s_resp_wr_en = wbs_stb_o & (!wbs_we_o) & wbs_ack_i ;
+assign s_resp_wr_data = {wbs_err_i,wbs_lack_i,wbs_dat_i};
+
+sync_fifo2 #(.W(CFW), .DP(4),.WR_FAST(1), .RD_FAST(1)) u_cmd_if (
+ // Sync w.r.t WR clock
+ .clk (clk_i ),
+ .reset_n (rst_n ),
+ .wr_en (m_cmd_wr_en ),
+ .wr_data (m_cmd_wr_data ),
+ .full (m_cmd_wr_full ),
+ .afull (m_cmd_wr_afull ),
+
+ // Sync w.r.t RD Clock
+ .rd_en (s_cmd_rd_en ),
+ .empty (s_cmd_rd_empty ), // sync'ed to rd_clk
+ .aempty (s_cmd_rd_aempty ), // sync'ed to rd_clk
+ .rd_data (s_cmd_rd_data )
+ );
+
+
+// Response used only for read path,
+// As cache access will be busrt of 512 location, To
+// support continous ack, depth is increase to 8 location
+sync_fifo2 #(.W(RFW), .DP(4), .WR_FAST(1), .RD_FAST(1)) u_resp_if (
+ // Sync w.r.t WR clock
+ .clk (clk_i ),
+ .reset_n (rst_n ),
+ .wr_en (s_resp_wr_en ),
+ .wr_data (s_resp_wr_data ),
+ .full (s_resp_wr_full ),
+ .afull (s_resp_wr_afull ),
+
+ // Sync w.r.t RD Clock
+ .rd_en (m_resp_rd_en ),
+ .empty (m_resp_rd_empty ), // sync'ed to rd_clk
+ .aempty (m_resp_rd_aempty ), // sync'ed to rd_clk
+ .rd_data (m_resp_rd_data )
+ );
+
+
+
+endmodule
diff --git a/verilog/rtl/lib/toggle_sync.v b/verilog/rtl/lib/toggle_sync.v
new file mode 100755
index 0000000..1280374
--- /dev/null
+++ b/verilog/rtl/lib/toggle_sync.v
@@ -0,0 +1,93 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores common library Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Mar 2, 2011 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module toggle_sync (in_clk,
+ in_rst_n,
+ out_clk,
+ out_rst_n,
+ in,
+ out_req,
+ out_ack);
+
+ output out_req;
+ input in_clk, in_rst_n, out_clk, out_rst_n, in, out_ack;
+
+ reg in_flag, out_flag;
+
+ always @ (posedge in_clk or negedge in_rst_n)
+ if (~in_rst_n)
+ in_flag <= 1'b0;
+ else
+ in_flag <= (in) ? ~in_flag : in_flag;
+
+ always @ (posedge out_clk or negedge out_rst_n)
+ if (~out_rst_n)
+ out_flag <= 1'b0;
+ else
+ out_flag <= (out_ack & out_req) ? ~out_flag : out_flag;
+
+
+ wire raw_req_pend;
+
+ assign raw_req_pend = in_flag ^ out_flag;
+
+ reg s1_out_req, s2_out_req;
+
+ always @ (posedge out_clk or negedge out_rst_n)
+ if (~out_rst_n) begin
+ s1_out_req <= 1'b0;
+ s2_out_req <= 1'b0;
+ end // if (~out_rst_n)
+ else begin
+ s1_out_req <= ~out_ack & raw_req_pend;
+ s2_out_req <= ~out_ack & s1_out_req;
+ end // else: !if(~out_rst_n)
+
+ wire out_req;
+
+ assign out_req = s2_out_req;
+
+endmodule // toggle_sync
+
diff --git a/verilog/rtl/lib/wb_arb.sv b/verilog/rtl/lib/wb_arb.sv
new file mode 100644
index 0000000..0ad8bbf
--- /dev/null
+++ b/verilog/rtl/lib/wb_arb.sv
@@ -0,0 +1,135 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Wishbone Arbitor ////
+//// ////
+//// This file is part of the YIFive cores project ////
+//// https://github.com/dineshannayya/yifive_r0.git ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description ////
+//// This block implement simple round robine request ////
+// arbitor for wishbone interface. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 12th June 2021, Dinesh A ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+
+module wb_arb(clk, rstn, req, gnt);
+
+input clk;
+input rstn;
+input [2:0] req; // Req input
+output [1:0] gnt; // Grant output
+
+///////////////////////////////////////////////////////////////////////
+//
+// Parameters
+//
+
+
+parameter [1:0]
+ grant0 = 3'h0,
+ grant1 = 3'h1,
+ grant2 = 3'h2;
+
+///////////////////////////////////////////////////////////////////////
+// Local Registers and Wires
+//////////////////////////////////////////////////////////////////////
+
+reg [1:0] state, next_state;
+
+///////////////////////////////////////////////////////////////////////
+// Misc Logic
+//////////////////////////////////////////////////////////////////////
+
+assign gnt = state;
+
+always@(posedge clk or negedge rstn)
+ if(!rstn) state <= grant0;
+ else state <= next_state;
+
+///////////////////////////////////////////////////////////////////////
+//
+// Next State Logic
+// - implements round robin arbitration algorithm
+// - switches grant if current req is dropped or next is asserted
+// - parks at last grant
+//////////////////////////////////////////////////////////////////////
+
+always_comb
+ begin
+ next_state = state; // Default Keep State
+ case(state)
+ grant0:
+ // if this req is dropped or next is asserted, check for other req's
+ if(!req[0] ) begin
+ if(req[1]) next_state = grant1;
+ else if(req[2]) next_state = grant2;
+ end
+ grant1:
+ // if this req is dropped or next is asserted, check for other req's
+ if(!req[1] ) begin
+ if(req[2]) next_state = grant2;
+ else if(req[0]) next_state = grant0;
+ end
+ grant2:
+ // if this req is dropped or next is asserted, check for other req's
+ if(!req[2] ) begin
+ if(req[0]) next_state = grant0;
+ else if(req[1]) next_state = grant1;
+ end
+ endcase
+ end
+
+endmodule
+
diff --git a/verilog/rtl/lib/wb_crossbar.v b/verilog/rtl/lib/wb_crossbar.v
new file mode 100644
index 0000000..07aeb3e
--- /dev/null
+++ b/verilog/rtl/lib/wb_crossbar.v
@@ -0,0 +1,384 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores common library Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Mar 2, 2011 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+/**********************************************
+ Web-bone cross bar M-Master By S-Slave
+**********************************************/
+
+module wb_crossbar (
+
+ rst_n ,
+ clk ,
+
+
+ // Master Interface Signal
+ wbd_taddr_master ,
+ wbd_din_master ,
+ wbd_dout_master ,
+ wbd_adr_master ,
+ wbd_be_master ,
+ wbd_we_master ,
+ wbd_ack_master ,
+ wbd_stb_master ,
+ wbd_cyc_master ,
+ wbd_err_master ,
+ wbd_rty_master ,
+
+ // Slave Interface Signal
+ wbd_din_slave ,
+ wbd_dout_slave ,
+ wbd_adr_slave ,
+ wbd_be_slave ,
+ wbd_we_slave ,
+ wbd_ack_slave ,
+ wbd_stb_slave ,
+ wbd_cyc_slave ,
+ wbd_err_slave ,
+ wbd_rty_slave
+ );
+
+parameter WB_SLAVE = 4 ;
+parameter WB_MASTER = 4 ;
+
+parameter D_WD = 16; // Data Width
+parameter BE_WD = 2; // Byte Enable
+parameter ADR_WD = 28; // Address Width
+parameter TAR_WD = 4; // Target Width
+
+input clk; // CLK_I The clock input [CLK_I] coordinates all activities
+ // for the internal logic within the WISHBONE interconnect.
+ // All WISHBONE output signals are registered at the
+ // rising edge of [CLK_I].
+ // All WISHBONE input signals must be stable before the
+ // rising edge of [CLK_I].
+input rst_n; // RST_I The reset input [RST_I] forces the WISHBONE interface
+ // to restart. Furthermore, all internal self-starting state
+ // machines will be forced into an initial state.
+
+input [(WB_MASTER *TAR_WD)-1:0] wbd_taddr_master; // target address from master
+input [WB_MASTER-1:0] wbd_stb_master;
+ // STB_O The strobe output [STB_O] indicates a valid data
+ // transfer cycle. It is used to qualify various other signals
+ // on the interface such as [SEL_O(7..0)]. The SLAVE must
+ // assert either the [ACK_I], [ERR_I] or [RTY_I] signals in
+ // response to every assertion of the [STB_O] signal.
+output [WB_SLAVE-1:0] wbd_stb_slave;
+ // STB_O The strobe output [STB_O] indicates a valid data
+ // transfer cycle. It is used to qualify various other signals
+ // on the interface such as [SEL_O(7..0)]. The SLAVE must
+ // assert either the [ACK_I], [ERR_I] or [RTY_I] signals in
+ // response to every assertion of the [STB_O] signal.
+
+input [WB_MASTER-1:0] wbd_we_master;
+ // WE_O The write enable output [WE_O] indicates whether the
+ // current local bus cycle is a READ or WRITE cycle. The
+ // signal is negated during READ cycles, and is asserted
+ // during WRITE cycles.
+output [WB_SLAVE-1:0] wbd_we_slave;
+ // WE_O The write enable output [WE_O] indicates whether the
+ // current local bus cycle is a READ or WRITE cycle. The
+ // signal is negated during READ cycles, and is asserted
+ // during WRITE cycles.
+
+output [WB_MASTER-1:0] wbd_ack_master;
+ // The acknowledge input [ACK_I], when asserted,
+ // indicates the termination of a normal bus cycle.
+ // Also see the [ERR_I] and [RTY_I] signal descriptions.
+input [WB_SLAVE-1:0] wbd_ack_slave;
+ // The acknowledge input [ACK_I], when asserted,
+ // indicates the termination of a normal bus cycle.
+ // Also see the [ERR_I] and [RTY_I] signal descriptions.
+
+input [(WB_MASTER *ADR_WD)-1:0] wbd_adr_master;
+ // The address output array [ADR_O(63..0)] is used
+ // to pass a binary address, with the most significant
+ // address bit at the higher numbered end of the signal array.
+ // The lower array boundary is specific to the data port size.
+ // The higher array boundary is core-specific.
+ // In some cases (such as FIFO interfaces)
+ // the array may not be present on the interface.
+
+output [(WB_SLAVE *ADR_WD)-1:0] wbd_adr_slave;
+ // The address output array [ADR_O(63..0)] is used
+ // to pass a binary address, with the most significant
+ // address bit at the higher numbered end of the signal array.
+ // The lower array boundary is specific to the data port size.
+ // The higher array boundary is core-specific.
+ // In some cases (such as FIFO interfaces)
+ // the array may not be present on the interface.
+
+input [(WB_MASTER * BE_WD)-1:0] wbd_be_master; // Byte Enable
+ // SEL_O(7..0) The select output array [SEL_O(7..0)] indicates
+ // where valid data is expected on the [DAT_I(63..0)] signal
+ // array during READ cycles, and where it is placed on the
+ // [DAT_O(63..0)] signal array during WRITE cycles.
+ // Also see the [DAT_I(63..0)], [DAT_O(63..0)] and [STB_O]
+ // signal descriptions.
+output [(WB_SLAVE * BE_WD)-1:0] wbd_be_slave; // Byte Enable
+ // SEL_O(7..0) The select output array [SEL_O(7..0)] indicates
+ // where valid data is expected on the [DAT_I(63..0)] signal
+ // array during READ cycles, and where it is placed on the
+ // [DAT_O(63..0)] signal array during WRITE cycles.
+ // Also see the [DAT_I(63..0)], [DAT_O(63..0)] and [STB_O]
+ // signal descriptions.
+
+input [WB_SLAVE -1:0] wbd_cyc_master;
+ // CYC_O The cycle output [CYC_O], when asserted,
+ // indicates that a valid bus cycle is in progress.
+ // The signal is asserted for the duration of all bus cycles.
+ // For example, during a BLOCK transfer cycle there can be
+ // multiple data transfers. The [CYC_O] signal is asserted
+ // during the first data transfer, and remains asserted
+ // until the last data transfer. The [CYC_O] signal is useful
+ // for interfaces with multi-port interfaces
+ // (such as dual port memories). In these cases,
+ // the [CYC_O] signal requests use of a common bus from an
+ // arbiter. Once the arbiter grants the bus to the MASTER,
+ // it is held until [CYC_O] is negated.
+output [WB_SLAVE -1:0] wbd_cyc_slave;
+ // CYC_O The cycle output [CYC_O], when asserted,
+ // indicates that a valid bus cycle is in progress.
+ // The signal is asserted for the duration of all bus cycles.
+ // For example, during a BLOCK transfer cycle there can be
+ // multiple data transfers. The [CYC_O] signal is asserted
+ // during the first data transfer, and remains asserted
+ // until the last data transfer. The [CYC_O] signal is useful
+ // for interfaces with multi-port interfaces
+ // (such as dual port memories). In these cases,
+ // the [CYC_O] signal requests use of a common bus from an
+ // arbiter. Once the arbiter grants the bus to the MASTER,
+ // it is held until [CYC_O] is negated.
+
+input [(WB_MASTER * D_WD)-1:0] wbd_din_master;
+ // DAT_I(63..0) The data input array [DAT_I(63..0)] is
+ // used to pass binary data. The array boundaries are
+ // determined by the port size. Also see the [DAT_O(63..0)]
+ // and [SEL_O(7..0)] signal descriptions.
+
+output [(WB_SLAVE * D_WD)-1:0] wbd_din_slave;
+ // DAT_I(63..0) The data input array [DAT_I(63..0)] is
+ // used to pass binary data. The array boundaries are
+ // determined by the port size. Also see the [DAT_O(63..0)]
+ // and [SEL_O(7..0)] signal descriptions.
+
+output [(WB_MASTER * D_WD)-1:0] wbd_dout_master;
+ // DAT_O(63..0) The data output array [DAT_O(63..0)] is
+ // used to pass binary data. The array boundaries are
+ // determined by the port size. Also see the [DAT_I(63..0)]
+ // and [SEL_O(7..0)] signal descriptions.
+input [(WB_SLAVE * D_WD)-1:0] wbd_dout_slave;
+ // DAT_O(63..0) The data output array [DAT_O(63..0)] is
+ // used to pass binary data. The array boundaries are
+ // determined by the port size. Also see the [DAT_I(63..0)]
+ // and [SEL_O(7..0)] signal descriptions.
+
+output [WB_MASTER -1:0] wbd_err_master;
+ // ERR_I The error input [ERR_I] indicates an abnormal
+ // cycle termination. The source of the error, and the
+ // response generated by the MASTER is defined by the IP core
+ // supplier in the WISHBONE DATASHEET. Also see the [ACK_I]
+ // and [RTY_I] signal descriptions.
+input [WB_SLAVE -1:0] wbd_err_slave;
+ // ERR_I The error input [ERR_I] indicates an abnormal
+ // cycle termination. The source of the error, and the
+ // response generated by the MASTER is defined by the IP core
+ // supplier in the WISHBONE DATASHEET. Also see the [ACK_I]
+ // and [RTY_I] signal descriptions.
+
+output [WB_MASTER -1:0] wbd_rty_master;
+ // RTY_I The retry input [RTY_I] indicates that the indicates
+ // that the interface is not ready to accept or send data, and
+ // that the cycle should be retried. When and how the cycle is
+ // retried is defined by the IP core supplier in the WISHBONE
+ // DATASHEET. Also see the [ERR_I] and [RTY_I] signal
+ // descriptions.
+input [WB_SLAVE -1:0] wbd_rty_slave;
+ // RTY_I The retry input [RTY_I] indicates that the indicates
+ // that the interface is not ready to accept or send data, and
+ // that the cycle should be retried. When and how the cycle is
+ // retried is defined by the IP core supplier in the WISHBONE
+ // DATASHEET. Also see the [ERR_I] and [RTY_I] signal
+ // descriptions.
+
+
+reg [WB_MASTER-1:0] wbd_ack_master;
+reg [WB_MASTER-1:0] wbd_err_master;
+reg [WB_MASTER-1:0] wbd_rty_master;
+
+
+reg [WB_MASTER-1:0] master_busy; // master busy flag
+reg [WB_SLAVE-1:0] slave_busy; // slave busy flag
+reg [TAR_WD -1:0] master_mx_id[WB_MASTER-1:0];
+reg [TAR_WD -1:0] slave_mx_id [WB_SLAVE-1:0];
+
+reg [TAR_WD-1 :0] cur_target_id;
+wire [TAR_WD-1:0] wbd_taddr_master_t[WB_MASTER:0]; // target address from master
+wire [D_WD-1:0] wbd_din_master_t[WB_MASTER-1:0]; // target address from master
+reg [D_WD-1:0] wbd_dout_master_t[WB_MASTER-1:0]; // target address from master
+wire [ADR_WD-1:0] wbd_adr_master_t[WB_MASTER-1:0]; // target address from master
+wire [BE_WD-1:0] wbd_be_master_t[WB_MASTER-1:0]; // target address from master
+
+
+reg [WB_SLAVE-1:0] wbd_stb_slave;
+reg [WB_SLAVE-1:0] wbd_we_slave;
+reg [WB_SLAVE-1:0] wbd_cyc_slave;
+wire [D_WD-1:0] wbd_dout_slave_t[WB_SLAVE-1:0]; // target data towards master
+
+
+reg [D_WD-1:0] wbd_din_slave_t[WB_SLAVE-1:0]; // target address from master
+reg [ADR_WD-1:0] wbd_adr_slave_t[WB_SLAVE-1:0]; // target address from master
+reg [BE_WD-1:0] wbd_be_slave_t[WB_SLAVE-1:0]; // target address from master
+
+integer i,k,l;
+
+
+/**********************************************************
+ Re-Arraging the array in seperate two dimensional information
+***********************************************************/
+
+genvar j,m;
+generate
+
+ // Connect the Master Mux
+ for(j=0; j < WB_MASTER ; j = j + 1) begin : master_expand
+ assign wbd_taddr_master_t[j] = wbd_taddr_master[((j+1)*TAR_WD)-1:j * TAR_WD];
+ assign wbd_din_master_t[j] = wbd_din_master[((j+1)*D_WD)-1:j * D_WD];
+ assign wbd_adr_master_t[j] = wbd_adr_master[((j+1)*ADR_WD)-1:j * ADR_WD];
+ assign wbd_be_master_t[j] = wbd_be_master[((j+1)*BE_WD)-1:j * BE_WD];
+
+ assign wbd_dout_master[((j+1)*D_WD)-1:j * D_WD] = wbd_dout_master_t[j];
+ end
+
+ // Connect the Slave Mux
+ for(m=0; m < WB_SLAVE ; m = m + 1) begin : slave_expand
+ assign wbd_din_slave[((m+1)*D_WD)-1:m * D_WD] = wbd_din_slave_t[m];
+ assign wbd_adr_slave[((m+1)*ADR_WD)-1:m * ADR_WD] = wbd_adr_slave_t[m];
+ assign wbd_be_slave[((m+1)*BE_WD)-1:m * BE_WD] = wbd_be_slave_t[m];
+
+ assign wbd_dout_slave_t[m] = wbd_dout_slave[((m+1)*D_WD)-1:m * D_WD];
+
+ end
+endgenerate
+
+always @* begin
+ for(k = 0; k < WB_MASTER; k = k + 1) begin
+ if(master_busy[k] == 1) begin
+ wbd_dout_master_t[k] = wbd_dout_slave_t[master_mx_id[k]];
+ wbd_ack_master[k] = wbd_ack_slave[master_mx_id[k]];
+ wbd_err_master[k] = wbd_err_slave[master_mx_id[k]];
+ wbd_rty_master[k] = wbd_rty_slave[master_mx_id[k]];
+ end else begin
+ wbd_dout_master_t[k] = 0;
+ wbd_ack_master[k] = 0;
+ wbd_err_master[k] = 0;
+ wbd_rty_master[k] = 0;
+ end
+ end
+ for(l = 0; l < WB_SLAVE; l = l + 1) begin
+ if(slave_busy[l] == 1) begin
+ wbd_din_slave_t[l] = wbd_din_master_t[slave_mx_id[l]];
+ wbd_adr_slave_t[l] = wbd_adr_master_t[slave_mx_id[l]];
+ wbd_be_slave_t[l] = wbd_be_master_t[slave_mx_id[l]];
+ wbd_stb_slave[l] = wbd_stb_master[slave_mx_id[l]];
+ wbd_we_slave[l] = wbd_we_master[slave_mx_id[l]];
+ wbd_cyc_slave[l] = wbd_cyc_master[slave_mx_id[l]];
+ end else begin
+ wbd_din_slave_t[l] = 0;
+ wbd_adr_slave_t[l] = 0;
+ wbd_be_slave_t[l] = 0;
+ wbd_stb_slave[l] = 0;
+ wbd_we_slave[l] = 0;
+ wbd_cyc_slave[l] = 0;
+ end
+ end
+end
+
+/*******************************************************
+ Parsing through the master and deciding on mux connectio
+ Step-1: analysis the master from 0 to total master
+ Step-2: If the previously master is not busy,
+ Then check for any new request from the master and
+ check corresponding slave is free or not. If there is
+ master request and requesting slave is free.
+ Then set the master max id to slave id &
+ requesting slave to master number & set the master
+ and slave busy flag
+ Step-3: If the previous state of master is busy and bus-cycle
+ is de-asserted, then reset the master and corresponding
+ slave busy flag
+
+*********************************************************/
+
+always @(negedge rst_n or posedge clk) begin
+ if(rst_n == 0) begin
+ master_busy = 0;
+ slave_busy = 0;
+ cur_target_id = 0;
+
+ end
+ else begin
+ for(i = 0; i < WB_MASTER; i = i + 1) begin
+ cur_target_id = wbd_taddr_master_t[i];
+ if(master_busy[i] == 0) begin
+ if(wbd_stb_master[i] & slave_busy[cur_target_id] == 0) begin
+ master_mx_id[i] <= cur_target_id;
+ slave_mx_id [cur_target_id] = i;
+ slave_busy[cur_target_id] = 1;
+ master_busy[i] = 1;
+ // synopsys translate_off
+ // $display("%m:%t: Locking Master : %d with Slave : %d",$time,i,cur_target_id);
+ // synopsys translate_on
+ end
+ end else if(wbd_cyc_master[i] == 0) begin
+ master_busy[i] = 0;
+ slave_busy[cur_target_id] = 0;
+ end
+ end
+ end
+end
+
+
+
+endmodule
diff --git a/verilog/rtl/lib/wb_interface.v b/verilog/rtl/lib/wb_interface.v
new file mode 100644
index 0000000..f25b147
--- /dev/null
+++ b/verilog/rtl/lib/wb_interface.v
@@ -0,0 +1,404 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// yifive common library Module ////
+//// ////
+//// This file is part of the yifive cores project ////
+//// https://github.com/dineshannayya/yifive_r0.git ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description: ////
+//// This module does the DMA to wishbone I/f ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// v0: Nov 26, 2016, Dinesh A ////
+//// This files copied from my open core ////
+//// turbo8051 project ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module wb_interface (
+ rst ,
+ clk ,
+
+ dma_req_i ,
+ dma_write_i ,
+ dma_addr_i ,
+ dma_length_i ,
+ dma_ack_o ,
+ dma_done_o ,
+
+ dma_start_o ,
+ dma_wr_o ,
+ dma_rd_o ,
+ dma_last_o ,
+ dma_wdata_i ,
+ dma_rdata_o ,
+
+ // external memory
+ wbd_dat_i ,
+ wbd_dat_o ,
+ wbd_adr_o ,
+ wbd_be_o ,
+ wbd_we_o ,
+ wbd_ack_i ,
+ wbd_stb_o ,
+ wbd_cyc_o ,
+ wbd_err_i
+
+
+ );
+
+
+
+input rst ;
+input clk ;
+
+input dma_req_i ;
+input dma_write_i ;
+input [25:0] dma_addr_i ;
+input [7:0] dma_length_i ;
+output dma_ack_o ;
+output dma_done_o ; // indicates end of DMA transaction
+
+output dma_start_o ;
+output dma_wr_o ;
+output dma_rd_o ;
+output dma_last_o ;
+input [31:0] dma_wdata_i ;
+output [31:0] dma_rdata_o ;
+
+//--------------------------------
+// WB interface
+//--------------------------------
+input [31:0] wbd_dat_i ; // data input
+output [31:0] wbd_dat_o ; // data output
+output [23:0] wbd_adr_o ; // address
+output [3:0] wbd_be_o ; // byte enable
+output wbd_we_o ; // write
+input wbd_ack_i ; // acknowlegement
+output wbd_stb_o ; // strobe/request
+output wbd_cyc_o ; // wb cycle
+input wbd_err_i ; // we error
+
+//------------------------------------
+// Reg Declaration
+//--------------------------------
+reg [2:0] state ;
+reg [2:0] state_d ;
+reg [7:0] preq_len ; // pending request length in bytes
+reg wbd_we_o ; // westbone write req
+reg [23:0] wbd_adr_o ; // westnone address
+reg dma_ack_o ; // dma ack
+reg [7:0] twbtrans ; // total westbone transaction
+reg dma_wr_o ; // dma write request
+reg dma_rd_o ; // dma read request
+reg [31:0] temp_data ; // temp holding data
+reg [1:0] be_sof ; // Byte enable starting alignment
+reg [31:0] wbd_dat_o ; // westbone data out
+reg [3:0] wbd_be_o ; // west bone byte enable
+reg [31:0] dma_rdata_o ; // dma read data
+reg wbd_stb_o ;
+reg dma_start_o ; // dma first transfer
+reg dma_last_o ; // dma last transfer
+
+parameter WB_IDLE = 3'b000;
+parameter WB_REQ = 3'b001;
+parameter WB_WR_PHASE = 3'b010;
+parameter WB_RD_PHASE_SOF = 3'b011;
+parameter WB_RD_PHASE_CONT = 3'b100;
+
+assign dma_done_o = (state == WB_IDLE) && (state_d != WB_IDLE);
+
+always @(posedge rst or posedge clk)
+begin
+ if(rst) begin
+ state <= WB_IDLE;
+ state_d <= WB_IDLE;
+ wbd_we_o <= 0;
+ wbd_adr_o <= 0;
+ preq_len <= 0;
+ dma_ack_o <= 0;
+ twbtrans <= 0;
+ dma_wr_o <= 0;
+ dma_rd_o <= 0;
+ temp_data <= 0;
+ be_sof <= 0;
+ wbd_dat_o <= 0;
+ wbd_be_o <= 0;
+ dma_rdata_o <= 0;
+ wbd_stb_o <= 0;
+ dma_start_o <= 0;
+ dma_last_o <= 0;
+ end
+ else begin
+ state_d <= state;
+ case(state)
+ WB_IDLE :
+ begin
+ if(dma_req_i)
+ begin
+ dma_ack_o <= 1;
+ wbd_we_o <= dma_write_i;
+ wbd_adr_o <= dma_addr_i[25:2];
+ be_sof <= dma_addr_i[1] << 1 + dma_addr_i[0];
+ preq_len <= dma_length_i;
+ // total wb transfer
+ twbtrans <= dma_length_i[7:2] +
+ |(dma_length_i[1:0]) +
+ |(dma_addr_i[1:0]);
+ state <= WB_REQ;
+ end
+ dma_wr_o <= 0;
+ dma_rd_o <= 0;
+ wbd_stb_o <= 0;
+ dma_start_o <= 0;
+ end
+ WB_REQ :
+ begin
+ dma_ack_o <= 0;
+ wbd_stb_o <= 1;
+ if(wbd_we_o) begin
+ dma_wr_o <= 1;
+ dma_start_o <= 1;
+ temp_data <= dma_wdata_i;
+ if(be_sof == 0) begin
+ wbd_dat_o <= dma_wdata_i;
+ wbd_be_o <= 4'b1111;
+ preq_len <= preq_len - 4;
+ end
+ else if(be_sof == 1) begin
+ wbd_dat_o <= {dma_wdata_i[23:0],8'h0};
+ wbd_be_o <= 4'b1110;
+ preq_len <= preq_len - 3;
+ end
+ else if(be_sof == 2) begin
+ wbd_dat_o <= {dma_wdata_i[15:0],16'h0};
+ wbd_be_o <= 4'b1100;
+ preq_len <= preq_len - 2;
+ end
+ else begin
+ wbd_dat_o <= {dma_wdata_i[7:0],23'h0};
+ wbd_be_o <= 4'b1000;
+ preq_len <= preq_len - 1;
+ end
+ twbtrans <= twbtrans -1;
+ state <= WB_WR_PHASE;
+ if(twbtrans == 1)
+ dma_last_o <= 1;
+ end
+ else begin
+ state <= WB_RD_PHASE_SOF;
+ end
+ end
+ WB_WR_PHASE :
+ begin
+ dma_start_o <= 0;
+ if(wbd_ack_i) begin
+ if(twbtrans == 1)
+ dma_last_o <= 1;
+ else
+ dma_last_o <= 0;
+ if(twbtrans > 0) begin
+ temp_data <= dma_wdata_i;
+ twbtrans <= twbtrans -1;
+ if(be_sof == 0) begin
+ wbd_dat_o <= dma_wdata_i;
+ end
+ else if(be_sof == 1) begin
+ wbd_dat_o <= {dma_wdata_i[23:0],temp_data[31:24]};
+ end
+ else if(be_sof == 2) begin
+ wbd_dat_o <= {dma_wdata_i[15:0],temp_data[31:16]};
+ end
+ else begin
+ wbd_dat_o <= {dma_wdata_i[7:0],temp_data[31:8]};
+ end
+
+ if(twbtrans > 1) begin // If the Pending Transfer is more than 1
+ dma_wr_o <= 1;
+ wbd_be_o <= 4'b1111;
+ preq_len <= preq_len - 4;
+ end
+ else begin // for last write access
+ wbd_be_o <= preq_len[1:0] == 2'b00 ? 4'b1111:
+ preq_len[1:0] == 2'b01 ? 4'b0001:
+ preq_len[1:0] == 2'b10 ? 4'b0011: 4'b0111;
+
+ case({be_sof[1:0],preq_len[1:0]})
+ // Start alignment = 0
+ 4'b0001 : dma_wr_o <= 1;
+ 4'b0010 : dma_wr_o <= 1;
+ 4'b0011 : dma_wr_o <= 1;
+ 4'b0000 : dma_wr_o <= 1;
+ // Start alignment = 1
+ 4'b0101 : dma_wr_o <= 0;
+ 4'b0110 : dma_wr_o <= 1;
+ 4'b0111 : dma_wr_o <= 1;
+ 4'b0100 : dma_wr_o <= 1;
+ // Start alignment = 2
+ 4'b1001 : dma_wr_o <= 0;
+ 4'b1010 : dma_wr_o <= 0;
+ 4'b1011 : dma_wr_o <= 1;
+ 4'b1000 : dma_wr_o <= 1;
+ // Start alignment = 3
+ 4'b1101 : dma_wr_o <= 0;
+ 4'b1110 : dma_wr_o <= 0;
+ 4'b1111 : dma_wr_o <= 0;
+ 4'b1100 : dma_wr_o <= 1;
+ endcase
+ end
+ end
+ else begin
+ dma_wr_o <= 0;
+ wbd_stb_o <= 0;
+ state <= WB_IDLE;
+ end
+ end
+ else begin
+ dma_last_o <= 0;
+ dma_wr_o <= 0;
+ end
+ end
+ WB_RD_PHASE_SOF :
+ begin
+ if(wbd_ack_i) begin
+ twbtrans <= twbtrans -1;
+ if(twbtrans == 1) begin // If the Pending Transfer is 1
+ dma_rd_o <= 1;
+ dma_start_o<= 1;
+ if(be_sof == 0) begin
+ dma_rdata_o <= wbd_dat_i;
+ preq_len <= preq_len - 4;
+ end
+ else if(be_sof == 1) begin
+ dma_rdata_o <= {8'h0,wbd_dat_i[31:24]};
+ preq_len <= preq_len - 3;
+ end
+ else if(be_sof == 2) begin
+ dma_rdata_o <= {16'h0,wbd_dat_i[31:16]};
+ preq_len <= preq_len - 2;
+ end
+ else begin
+ dma_rdata_o <= {23'h0,wbd_dat_i[31:8]};
+ preq_len <= preq_len - 0;
+ end
+ dma_last_o <= 1;
+ state <= WB_IDLE;
+ end
+ else begin // pending transction is more than 1
+ if(be_sof == 0) begin
+ dma_rdata_o <= wbd_dat_i;
+ dma_rd_o <= 1;
+ dma_start_o <= 1;
+ preq_len <= preq_len - 4;
+ end
+ else if(be_sof == 1) begin
+ temp_data <= {8'h0,wbd_dat_i[31:24]};
+ dma_rd_o <= 0;
+ preq_len <= preq_len - 3;
+ end
+ else if(be_sof == 2) begin
+ temp_data <= {16'h0,wbd_dat_i[31:16]};
+ preq_len <= preq_len - 2;
+ end
+ else begin
+ temp_data <= {23'h0,wbd_dat_i[31:8]};
+ preq_len <= preq_len - 0;
+ end
+ state <= WB_RD_PHASE_CONT;
+ end
+ end
+ else begin
+ dma_rd_o <= 0;
+ end
+ end
+ WB_RD_PHASE_CONT:
+ begin
+ dma_start_o <= 0;
+ if(wbd_ack_i) begin
+ dma_rd_o <= 1;
+ twbtrans <= twbtrans -1;
+ if(be_sof == 0) begin
+ dma_rdata_o <= wbd_dat_i;
+ preq_len <= preq_len - 4;
+ end
+ else if(be_sof == 1) begin
+ dma_rdata_o <= {wbd_dat_i[7:0],temp_data[23:0]};
+ temp_data <= {8'h0,wbd_dat_i[31:8]};
+ preq_len <= preq_len - 3;
+ end
+ else if(be_sof == 2) begin
+ dma_rdata_o <= {wbd_dat_i[15:0],temp_data[15:0]};
+ temp_data <= {16'h0,wbd_dat_i[31:16]};
+ preq_len <= preq_len - 2;
+ end
+ else begin
+ dma_rdata_o <= {wbd_dat_i[23:0],temp_data[7:0]};
+ temp_data <= {24'h0,wbd_dat_i[31:23]};
+ preq_len <= preq_len - 1;
+ end
+ if(twbtrans == 1) begin // If the it's last transfer
+ dma_last_o <= 1;
+ state <= WB_IDLE;
+ end
+ end
+ else begin
+ dma_last_o <= 0;
+ dma_rd_o <= 0;
+ end
+ end
+ endcase
+ end
+end
+
+
+
+endmodule
diff --git a/verilog/rtl/lib/wb_rd_mem2mem.v b/verilog/rtl/lib/wb_rd_mem2mem.v
new file mode 100644
index 0000000..d7c20b1
--- /dev/null
+++ b/verilog/rtl/lib/wb_rd_mem2mem.v
@@ -0,0 +1,348 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores common library Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Mar 2, 2011 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+/**********************************************
+ Web-bone , Read from Wishbone Memory and Write to internal Memory
+
+ This block handles following task
+ 1. Check the Descriptor Q for not empty
+ 2. If the Descriptor Q is not empty, the read the 32 bit descriptor
+ 3. The 32 bit descriptor holds following information
+ [11:0] - Packet Length
+ [25:12] - MSB [15:2] of Packet Start Location
+ [31:26] - Packet Status
+ 4. Based on the Packet Length, Read the data from external Data memory
+ and write it to Internal Memory
+
+**********************************************/
+
+module wb_rd_mem2mem (
+
+ rst_n ,
+ clk ,
+
+ // descriptor handshake
+ cfg_desc_baddr ,
+ desc_q_empty ,
+
+ // Master Interface Signal
+ mem_taddr ,
+ mem_full ,
+ mem_afull ,
+ mem_wr ,
+ mem_din ,
+
+ // Slave Interface Signal
+ wbo_dout ,
+ wbo_taddr ,
+ wbo_addr ,
+ wbo_be ,
+ wbo_we ,
+ wbo_ack ,
+ wbo_stb ,
+ wbo_cyc ,
+ wbo_err ,
+ wbo_rty
+ );
+
+
+parameter D_WD = 16; // Data Width
+parameter BE_WD = 2; // Byte Enable
+parameter ADR_WD = 28; // Address Width
+parameter TAR_WD = 4; // Target Width
+
+//---------------------
+// State Machine Parameter
+//--------------------
+
+parameter IDLE = 0;
+parameter DESC_RD = 1;
+parameter DATA_WAIT = 2;
+parameter TXFR = 3;
+parameter MEM_WRITE2 = 4;
+parameter MEM_WRITE3 = 5;
+parameter MEM_WRITE4 = 6;
+
+
+//-------------------------------------------
+// Input Declaration
+//------------------------------------------
+
+input clk ; // CLK_I The clock input [CLK_I] coordinates all activities
+ // for the internal logic within the WISHBONE interconnect.
+ // All WISHBONE output signals are registered at the
+ // rising edge of [CLK_I].
+ // All WISHBONE input signals must be stable before the
+ // rising edge of [CLK_I].
+input rst_n ; // RST_I The reset input [RST_I] forces the WISHBONE interface
+ // to restart. Furthermore, all internal self-starting state
+ // machines will be forced into an initial state.
+
+//---------------------------------
+// Descriptor Interface
+//---------------------------------
+input [15:6] cfg_desc_baddr ; // descriptor Base Address
+input desc_q_empty ;
+
+//------------------------------------------
+// Stanard Memory Interface
+//------------------------------------------
+
+input [TAR_WD-1:0] mem_taddr ; // target address
+input mem_full ; // memory full
+input mem_afull ; // memory afull
+output mem_wr ; // memory Write
+output [8:0] mem_din ; // memory read data
+
+//------------------------------------------
+// External Memory WB Interface
+//------------------------------------------
+output wbo_stb ; // STB_O The strobe output [STB_O] indicates a valid data
+ // transfer cycle. It is used to qualify various other signals
+ // on the interface such as [SEL_O(7..0)]. The SLAVE must
+ // assert either the [ACK_I], [ERR_I] or [RTY_I] signals in
+ // response to every assertion of the [STB_O] signal.
+output wbo_we ; // WE_O The write enable output [WE_O] indicates whether the
+ // current local bus cycle is a READ or WRITE cycle. The
+ // signal is negated during READ cycles, and is asserted
+ // during WRITE cycles.
+input wbo_ack ; // The acknowledge input [ACK_I], when asserted,
+ // indicates the termination of a normal bus cycle.
+ // Also see the [ERR_I] and [RTY_I] signal descriptions.
+
+output [TAR_WD-1:0] wbo_taddr;
+output [ADR_WD-1:0] wbo_addr ; // The address output array [ADR_O(63..0)] is used
+ // to pass a binary address, with the most significant
+ // address bit at the higher numbered end of the signal array.
+ // The lower array boundary is specific to the data port size.
+ // The higher array boundary is core-specific.
+ // In some cases (such as FIFO interfaces)
+ // the array may not be present on the interface.
+
+output [BE_WD-1:0] wbo_be ; // Byte Enable
+ // SEL_O(7..0) The select output array [SEL_O(7..0)] indicates
+ // where valid data is expected on the [DAT_I(63..0)] signal
+ // array during READ cycles, and where it is placed on the
+ // [DAT_O(63..0)] signal array during WRITE cycles.
+ // Also see the [DAT_I(63..0)], [DAT_O(63..0)] and [STB_O]
+ // signal descriptions.
+
+output wbo_cyc ; // CYC_O The cycle output [CYC_O], when asserted,
+ // indicates that a valid bus cycle is in progress.
+ // The signal is asserted for the duration of all bus cycles.
+ // For example, during a BLOCK transfer cycle there can be
+ // multiple data transfers. The [CYC_O] signal is asserted
+ // during the first data transfer, and remains asserted
+ // until the last data transfer. The [CYC_O] signal is useful
+ // for interfaces with multi-port interfaces
+ // (such as dual port memories). In these cases,
+ // the [CYC_O] signal requests use of a common bus from an
+ // arbiter. Once the arbiter grants the bus to the MASTER,
+ // it is held until [CYC_O] is negated.
+
+input [D_WD-1:0] wbo_dout; // DAT_I(63..0) The data input array [DAT_I(63..0)] is
+ // used to pass binary data. The array boundaries are
+ // determined by the port size. Also see the [DAT_O(63..0)]
+ // and [SEL_O(7..0)] signal descriptions.
+
+input wbo_err; // ERR_I The error input [ERR_I] indicates an abnormal
+ // cycle termination. The source of the error, and the
+ // response generated by the MASTER is defined by the IP core
+ // supplier in the WISHBONE DATASHEET. Also see the [ACK_I]
+ // and [RTY_I] signal descriptions.
+
+input wbo_rty; // RTY_I The retry input [RTY_I] indicates that the indicates
+ // that the interface is not ready to accept or send data, and
+ // that the cycle should be retried. When and how the cycle is
+ // retried is defined by the IP core supplier in the WISHBONE
+ // DATASHEET. Also see the [ERR_I] and [RTY_I] signal
+ // descriptions.
+
+//----------------------------------------
+// Register Declration
+//----------------------------------------
+
+reg [2:0] state ;
+reg [15:0] cnt ;
+reg [TAR_WD-1:0] wbo_taddr ;
+reg [ADR_WD-1:0] wbo_addr ;
+reg wbo_stb ;
+reg wbo_we ;
+reg [BE_WD-1:0] wbo_be ;
+reg wbo_cyc ;
+reg [15:0] mem_addr ;
+
+
+
+
+reg [3:0] desc_ptr;
+reg [23:0] tWrData; // Temp Write Data
+reg [8:0] mem_din;
+reg mem_wr;
+
+always @(negedge rst_n or posedge clk) begin
+ if(rst_n == 0) begin
+ state <= IDLE;
+ wbo_taddr <= 0;
+ wbo_addr <= 0;
+ wbo_stb <= 0;
+ wbo_we <= 0;
+ wbo_be <= 0;
+ wbo_cyc <= 0;
+ desc_ptr <= 0;
+ mem_addr <= 0;
+ mem_din <= 0;
+ tWrData <= 0;
+ mem_wr <= 0;
+ end
+ else begin
+ case(state)
+ IDLE: begin
+ mem_wr <= 0;
+ // Check for Descriptor Q not empty
+ if(!desc_q_empty) begin
+ wbo_taddr <= mem_taddr;
+ wbo_addr <= {cfg_desc_baddr[15:6],desc_ptr[3:0]};
+ wbo_be <= 4'hF;
+ wbo_we <= 1'b0;
+ wbo_stb <= 1'b1;
+ wbo_cyc <= 1;
+ state <= DESC_RD;
+ desc_ptr <= desc_ptr+1;
+ end
+ end
+ DESC_RD: begin
+ // wait for web-bone ack
+ if(wbo_ack) begin
+ wbo_cyc <= 1'b0;
+ wbo_stb <= 1'b0;
+ state <= IDLE;
+ cnt <= wbo_dout[11:0];
+ mem_addr <= {wbo_dout[27:12],2'b0};
+ state <= DATA_WAIT;
+ end
+ end
+
+ DATA_WAIT: begin
+ mem_wr <= 0; // Reset the write for handling interburst
+ // check for internal memory not full and initiate
+ // the transfer
+ if(!(mem_full || mem_afull)) begin
+ wbo_taddr <= mem_taddr;
+ wbo_addr <= mem_addr[14:2];
+ wbo_stb <= 1'b1;
+ wbo_we <= 1'b0;
+ wbo_be <= 4'hF;
+ wbo_cyc <= 1'b1;
+ state <= TXFR;
+ end
+ end
+ TXFR: begin
+ if(wbo_ack) begin
+ wbo_cyc <= 1'b0;
+ wbo_stb <= 1'b0;
+ mem_addr <= mem_addr+4;
+ mem_din[7:0] <= wbo_dout[7:0]; // Write First Byte
+ tWrData <= wbo_dout[31:8];
+ mem_din[8] <= (cnt == 1) ? 1'b1 : 1'b0; // EOP generation at last transfer
+ mem_wr <= 1;
+ cnt <= cnt-1;
+ if(cnt == 1) begin
+ state <= IDLE;
+ end else begin
+ state <= MEM_WRITE2;
+ end
+ end
+ end
+ MEM_WRITE2: begin // Write 2nd Byte
+ if(!(mem_full || mem_afull)) begin // to handle the interburst fifo full case
+ mem_din[7:0] <= tWrData[7:0];
+ mem_din[8] <= (cnt == 1) ? 1'b1 : 1'b0; // EOP generation at last transfer
+ mem_wr <= 1;
+ cnt <= cnt-1;
+ if(cnt == 1) begin
+ state <= IDLE;
+ end else begin
+ state <= MEM_WRITE3;
+ end
+ end else begin
+ mem_wr <= 0;
+ end
+ end
+ MEM_WRITE3: begin // Write 3rd Byte
+ if(!(mem_full || mem_afull)) begin // to handle the interburst fifo full case
+ mem_din[7:0] <= tWrData[15:8];
+ mem_din[8] <= (cnt == 1) ? 1'b1 : 1'b0; // EOP generation at last transfer
+ mem_wr <= 1;
+ cnt <= cnt-1;
+ if(cnt == 1) begin
+ state <= IDLE;
+ end else begin
+ state <= MEM_WRITE4;
+ end
+ end else begin
+ mem_wr <= 0;
+ end
+ end
+ MEM_WRITE4: begin // Write 4th Byte
+ if(!(mem_full || mem_afull)) begin // to handle the interburst fifo full case
+ mem_din[7:0] <= tWrData[23:16];
+ mem_din[8] <= (cnt == 1) ? 1'b1 : 1'b0; // EOP generation at last transfer
+ mem_wr <= 1;
+ cnt <= cnt-1;
+ if(cnt == 1) begin
+ state <= IDLE;
+ end else begin
+ state <= DATA_WAIT;
+ end
+ end else begin
+ mem_wr <= 0;
+ end
+ end
+ endcase
+ end
+end
+
+endmodule
diff --git a/verilog/rtl/lib/wb_stagging.sv b/verilog/rtl/lib/wb_stagging.sv
new file mode 100644
index 0000000..8f54f0f
--- /dev/null
+++ b/verilog/rtl/lib/wb_stagging.sv
@@ -0,0 +1,173 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//----------------------------------------------------------------------
+// This logic create a holding register for Wishbone interface.
+// This is usefull to break timing issue at interconnect
+//
+// Limitation: Due to stagging FF, Continous Burst of Wishbone will have one
+// cycle break between each transaction
+//----------------------------------------------------------------------
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Wishbone Stagging FF ////
+//// ////
+//// This file is part of the YIFive cores project ////
+//// https://github.com/dineshannayya/yifive_r0.git ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description ////
+//// This logic create a holding FF for Wishbone interface. ////
+//// This is usefull to break timing issue at interconnect ////
+//// ////
+//// Limitation: Due to stagging FF, Continous Burst of ////
+//// Wishbone will have one cycle break between each transaction ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 12th June 2021, Dinesh A ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+
+module wb_stagging (
+ input logic clk_i,
+ input logic rst_n,
+ // WishBone Input master I/P
+ input logic [31:0] m_wbd_dat_i,
+ input logic [31:0] m_wbd_adr_i,
+ input logic [3:0] m_wbd_sel_i,
+ input logic m_wbd_we_i,
+ input logic m_wbd_cyc_i,
+ input logic m_wbd_stb_i,
+ input logic [3:0] m_wbd_tid_i,
+ output logic [31:0] m_wbd_dat_o,
+ output logic m_wbd_ack_o,
+ output logic m_wbd_err_o,
+
+ // Slave Interface
+ input logic [31:0] s_wbd_dat_i,
+ input logic s_wbd_ack_i,
+ input logic s_wbd_err_i,
+ output logic [31:0] s_wbd_dat_o,
+ output logic [31:0] s_wbd_adr_o,
+ output logic [3:0] s_wbd_sel_o,
+ output logic s_wbd_we_o,
+ output logic s_wbd_cyc_o,
+ output logic s_wbd_stb_o,
+ output logic [3:0] s_wbd_tid_o
+
+);
+
+logic holding_busy ; // Indicate Stagging for Free or not
+logic [31:0] m_wbd_dat_i_ff ; // Flopped vesion of m_wbd_dat_i
+logic [31:0] m_wbd_adr_i_ff ; // Flopped vesion of m_wbd_adr_i
+logic [3:0] m_wbd_sel_i_ff ; // Flopped vesion of m_wbd_sel_i
+logic m_wbd_we_i_ff ; // Flopped vesion of m_wbd_we_i
+logic m_wbd_cyc_i_ff ; // Flopped vesion of m_wbd_cyc_i
+logic m_wbd_stb_i_ff ; // Flopped vesion of m_wbd_stb_i
+logic [3:0] m_wbd_tid_i_ff ; // Flopped vesion of m_wbd_tid_i
+logic [31:0] s_wbd_dat_i_ff ; // Flopped vesion of s_wbd_dat_i
+logic s_wbd_ack_i_ff ; // Flopped vesion of s_wbd_ack_i
+logic s_wbd_err_i_ff ; // Flopped vesion of s_wbd_err_i
+
+
+assign s_wbd_dat_o = m_wbd_dat_i_ff;
+assign s_wbd_adr_o = m_wbd_adr_i_ff;
+assign s_wbd_sel_o = m_wbd_sel_i_ff;
+assign s_wbd_we_o = m_wbd_we_i_ff;
+assign s_wbd_cyc_o = m_wbd_cyc_i_ff;
+assign s_wbd_stb_o = m_wbd_stb_i_ff;
+assign s_wbd_tid_o = m_wbd_tid_i_ff;
+
+assign m_wbd_dat_o = s_wbd_dat_i_ff;
+assign m_wbd_ack_o = s_wbd_ack_i_ff;
+assign m_wbd_err_o = s_wbd_err_i_ff;
+
+always @(negedge rst_n or posedge clk_i)
+begin
+ if(rst_n == 1'b0) begin
+ holding_busy <= 1'b0;
+ m_wbd_dat_i_ff <= 'h0;
+ m_wbd_adr_i_ff <= 'h0;
+ m_wbd_sel_i_ff <= 'h0;
+ m_wbd_we_i_ff <= 'h0;
+ m_wbd_cyc_i_ff <= 'h0;
+ m_wbd_stb_i_ff <= 'h0;
+ m_wbd_tid_i_ff <= 'h0;
+ s_wbd_dat_i_ff <= 'h0;
+ s_wbd_ack_i_ff <= 'h0;
+ s_wbd_err_i_ff <= 'h0;
+ end else begin
+ s_wbd_dat_i_ff <= s_wbd_dat_i;
+ s_wbd_ack_i_ff <= s_wbd_ack_i;
+ s_wbd_err_i_ff <= s_wbd_err_i;
+ if(m_wbd_stb_i && holding_busy == 0 && m_wbd_ack_o == 0) begin
+ holding_busy <= 1'b1;
+ m_wbd_dat_i_ff <= m_wbd_dat_i;
+ m_wbd_adr_i_ff <= m_wbd_adr_i;
+ m_wbd_sel_i_ff <= m_wbd_sel_i;
+ m_wbd_we_i_ff <= m_wbd_we_i;
+ m_wbd_cyc_i_ff <= m_wbd_cyc_i;
+ m_wbd_stb_i_ff <= m_wbd_stb_i;
+ m_wbd_tid_i_ff <= m_wbd_tid_i;
+ end else if (holding_busy && s_wbd_ack_i) begin
+ holding_busy <= 1'b0;
+ m_wbd_dat_i_ff <= 'h0;
+ m_wbd_adr_i_ff <= 'h0;
+ m_wbd_sel_i_ff <= 'h0;
+ m_wbd_we_i_ff <= 'h0;
+ m_wbd_cyc_i_ff <= 'h0;
+ m_wbd_stb_i_ff <= 'h0;
+ m_wbd_tid_i_ff <= 'h0;
+ end
+ end
+end
+
+
+endmodule
+
diff --git a/verilog/rtl/lib/wb_wr_mem2mem.v b/verilog/rtl/lib/wb_wr_mem2mem.v
new file mode 100644
index 0000000..0972b4f
--- /dev/null
+++ b/verilog/rtl/lib/wb_wr_mem2mem.v
@@ -0,0 +1,370 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores common library Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : Mar 2, 2011 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+/**********************************************
+ Web-bone , Read from Memory and Write to WebBone External Memory
+**********************************************/
+
+module wb_wr_mem2mem (
+
+ rst_n ,
+ clk ,
+
+
+ // Master Interface Signal
+ mem_taddr ,
+ mem_addr ,
+ mem_empty ,
+ mem_aempty ,
+ mem_rd ,
+ mem_dout ,
+ mem_eop ,
+
+ cfg_desc_baddr ,
+ desc_req ,
+ desc_ack ,
+ desc_disccard ,
+ desc_data ,
+
+
+ // Slave Interface Signal
+ wbo_din ,
+ wbo_taddr ,
+ wbo_addr ,
+ wbo_be ,
+ wbo_we ,
+ wbo_ack ,
+ wbo_stb ,
+ wbo_cyc ,
+ wbo_err ,
+ wbo_rty
+ );
+
+
+parameter D_WD = 16; // Data Width
+parameter BE_WD = 2; // Byte Enable
+parameter ADR_WD = 28; // Address Width
+parameter TAR_WD = 4; // Target Width
+
+// State Machine
+parameter IDLE = 3'h0;
+parameter RD_BYTE1 = 3'h1;
+parameter RD_BYTE2 = 3'h2;
+parameter RD_BYTE3 = 3'h3;
+parameter RD_BYTE4 = 3'h4;
+parameter WB_XFR = 3'h5;
+parameter DESC_WAIT = 3'h6;
+parameter DESC_XFR = 3'h7;
+
+input clk ; // CLK_I The clock input [CLK_I] coordinates all activities
+ // for the internal logic within the WISHBONE interconnect.
+ // All WISHBONE output signals are registered at the
+ // rising edge of [CLK_I].
+ // All WISHBONE input signals must be stable before the
+ // rising edge of [CLK_I].
+input rst_n ; // RST_I The reset input [RST_I] forces the WISHBONE interface
+ // to restart. Furthermore, all internal self-starting state
+ // machines will be forced into an initial state.
+
+//------------------------------------------
+// Stanard Memory Interface
+//------------------------------------------
+input [TAR_WD-1:0] mem_taddr; // target address
+input [15:0] mem_addr; // memory address
+input mem_empty; // memory empty
+input mem_aempty; // memory empty
+output mem_rd; // memory read
+input [7:0] mem_dout; // memory read data
+input mem_eop; // Last Transfer indication
+
+//----------------------------------------
+// Discriptor defination
+//----------------------------------------
+input desc_req; // descriptor request
+output desc_ack; // descriptor ack
+input desc_disccard;// descriptor discard
+input [15:6] cfg_desc_baddr; // descriptor memory base address
+input [31:0] desc_data; // descriptor data
+
+//------------------------------------------
+// External Memory WB Interface
+//------------------------------------------
+output [TAR_WD-1:0] wbo_taddr ;
+output wbo_stb ; // STB_O The strobe output [STB_O] indicates a valid data
+ // transfer cycle. It is used to qualify various other signals
+ // on the interface such as [SEL_O(7..0)]. The SLAVE must
+ // assert either the [ACK_I], [ERR_I] or [RTY_I] signals in
+ // response to every assertion of the [STB_O] signal.
+output wbo_we ; // WE_O The write enable output [WE_O] indicates whether the
+ // current local bus cycle is a READ or WRITE cycle. The
+ // signal is negated during READ cycles, and is asserted
+ // during WRITE cycles.
+input wbo_ack ; // The acknowledge input [ACK_I], when asserted,
+ // indicates the termination of a normal bus cycle.
+ // Also see the [ERR_I] and [RTY_I] signal descriptions.
+
+output [ADR_WD-1:0] wbo_addr ; // The address output array [ADR_O(63..0)] is used
+ // to pass a binary address, with the most significant
+ // address bit at the higher numbered end of the signal array.
+ // The lower array boundary is specific to the data port size.
+ // The higher array boundary is core-specific.
+ // In some cases (such as FIFO interfaces)
+ // the array may not be present on the interface.
+
+output [BE_WD-1:0] wbo_be ; // Byte Enable
+ // SEL_O(7..0) The select output array [SEL_O(7..0)] indicates
+ // where valid data is expected on the [DAT_I(63..0)] signal
+ // array during READ cycles, and where it is placed on the
+ // [DAT_O(63..0)] signal array during WRITE cycles.
+ // Also see the [DAT_I(63..0)], [DAT_O(63..0)] and [STB_O]
+ // signal descriptions.
+
+output wbo_cyc ; // CYC_O The cycle output [CYC_O], when asserted,
+ // indicates that a valid bus cycle is in progress.
+ // The signal is asserted for the duration of all bus cycles.
+ // For example, during a BLOCK transfer cycle there can be
+ // multiple data transfers. The [CYC_O] signal is asserted
+ // during the first data transfer, and remains asserted
+ // until the last data transfer. The [CYC_O] signal is useful
+ // for interfaces with multi-port interfaces
+ // (such as dual port memories). In these cases,
+ // the [CYC_O] signal requests use of a common bus from an
+ // arbiter. Once the arbiter grants the bus to the MASTER,
+ // it is held until [CYC_O] is negated.
+
+output [D_WD-1:0] wbo_din; // DAT_I(63..0) The data input array [DAT_I(63..0)] is
+ // used to pass binary data. The array boundaries are
+ // determined by the port size. Also see the [DAT_O(63..0)]
+ // and [SEL_O(7..0)] signal descriptions.
+
+input wbo_err; // ERR_I The error input [ERR_I] indicates an abnormal
+ // cycle termination. The source of the error, and the
+ // response generated by the MASTER is defined by the IP core
+ // supplier in the WISHBONE DATASHEET. Also see the [ACK_I]
+ // and [RTY_I] signal descriptions.
+
+input wbo_rty; // RTY_I The retry input [RTY_I] indicates that the indicates
+ // that the interface is not ready to accept or send data, and
+ // that the cycle should be retried. When and how the cycle is
+ // retried is defined by the IP core supplier in the WISHBONE
+ // DATASHEET. Also see the [ERR_I] and [RTY_I] signal
+ // descriptions.
+
+//-------------------------------------------
+// Register Dec
+//-------------------------------------------
+
+reg [TAR_WD-1:0] wbo_taddr ;
+reg [ADR_WD-1:0] wbo_addr ;
+reg wbo_stb ;
+reg wbo_we ;
+reg [BE_WD-1:0] wbo_be ;
+reg wbo_cyc ;
+reg [D_WD-1:0] wbo_din ;
+reg [2:0] state ;
+
+reg mem_rd ;
+reg [3:0] desc_ptr ; // descriptor pointer, in 32 bit mode
+reg mem_eop_l ; // delayed eop signal
+reg desc_ack ; // delayed eop signal
+
+reg [23:0] tWrData; // Temp 24 Bit Data
+always @(negedge rst_n or posedge clk) begin
+ if(rst_n == 0) begin
+ wbo_taddr <= 0;
+ wbo_addr <= 0;
+ wbo_stb <= 0;
+ wbo_we <= 0;
+ wbo_be <= 0;
+ wbo_cyc <= 0;
+ wbo_din <= 0;
+ mem_rd <= 0;
+ desc_ptr <= 0;
+ mem_eop_l <= 0;
+ desc_ack <= 0;
+ tWrData <= 0;
+ state <= IDLE;
+ end
+ else begin
+ case(state)
+ IDLE: begin
+ desc_ack <= 0;
+ if(!mem_empty) begin
+ mem_rd <= 1;
+ mem_eop_l <= 0;
+ tWrData[7:0] <= mem_dout[7:0];
+ state <= RD_BYTE1;
+ end
+ end
+ RD_BYTE1: begin // End of First Transfer
+ if(mem_rd && mem_eop) begin
+ mem_rd <= 0;
+ mem_eop_l <= mem_eop;
+ wbo_taddr <= mem_taddr;
+ wbo_addr <= mem_addr[14:2];
+ wbo_stb <= 1'b1;
+ wbo_we <= 1'b1;
+ wbo_be <= 4'h1; // Assigned Aligned 32bit address
+ wbo_din <= {24'h0,mem_dout[7:0]};
+ wbo_cyc <= 1;
+ state <= WB_XFR;
+ end else if(!(mem_empty || (mem_rd && mem_aempty))) begin
+ mem_rd <= 1;
+ state <= RD_BYTE2;
+ end else begin
+ mem_rd <= 0;
+ end
+ if(mem_rd) begin
+ tWrData[7:0] <= mem_dout[7:0];
+ end
+ end
+
+ RD_BYTE2: begin // End of Second Transfer
+ if(mem_rd && mem_eop) begin
+ mem_rd <= 0;
+ mem_eop_l <= mem_eop;
+ wbo_taddr <= mem_taddr;
+ wbo_addr <= mem_addr[14:2];
+ wbo_stb <= 1'b1;
+ wbo_we <= 1'b1;
+ wbo_be <= 4'h3; // Assigned Aligned 32bit address
+ wbo_din <= {16'h0,mem_dout[7:0],tWrData[7:0]};
+ wbo_cyc <= 1;
+ state <= WB_XFR;
+ end else if(!(mem_empty || (mem_rd && mem_aempty))) begin
+ mem_rd <= 1;
+ state <= RD_BYTE3;
+ end else begin
+ mem_rd <= 0;
+ end
+ if(mem_rd) begin
+ tWrData[15:8] <= mem_dout[7:0];
+ end
+ end
+
+
+ RD_BYTE3: begin // End of Third Transfer
+ if(mem_rd && mem_eop) begin
+ mem_rd <= 0;
+ mem_eop_l <= mem_eop;
+ wbo_taddr <= mem_taddr;
+ wbo_addr <= mem_addr[14:2];
+ wbo_stb <= 1'b1;
+ wbo_we <= 1'b1;
+ wbo_be <= 4'h7; // Assigned Aligned 32bit address
+ wbo_din <= {8'h0,mem_dout[7:0],tWrData[15:0]};
+ wbo_cyc <= 1;
+ state <= WB_XFR;
+ end else if(!(mem_empty || (mem_rd && mem_aempty))) begin
+ mem_rd <= 1;
+ state <= RD_BYTE4;
+ end else begin
+ mem_rd <= 0;
+ end
+ if(mem_rd) begin
+ tWrData[23:16] <= mem_dout[7:0];
+ end
+ end
+
+ RD_BYTE4: begin // End of Fourth Transfer
+ mem_rd <= 0;
+ mem_eop_l <= mem_eop;
+ wbo_taddr <= mem_taddr;
+ wbo_addr <= mem_addr[14:2];
+ wbo_stb <= 1'b1;
+ wbo_we <= 1'b1;
+ wbo_be <= 4'hF; // Assigned Aligned 32bit address
+ wbo_din <= {mem_dout[7:0],tWrData[23:0]};
+ wbo_cyc <= 1;
+ state <= WB_XFR;
+ end
+
+ WB_XFR: begin
+ if(wbo_ack) begin
+ wbo_stb <= 0;
+ wbo_cyc <= 0;
+ if(mem_eop_l) begin
+ state <= DESC_WAIT;
+ end else begin
+ state <= IDLE; // Next Byte
+ end
+ end
+ end
+
+
+ DESC_WAIT: begin
+ if(desc_req) begin
+ desc_ack <= 1;
+ if(desc_disccard) begin // if the Desc is discarded
+ state <= IDLE;
+ end
+ else begin
+ wbo_addr <= {cfg_desc_baddr[15:6],desc_ptr[3:0]}; // Each Transfer is 32bit
+ wbo_be <= 4'hF;
+ wbo_din <= desc_data;
+ wbo_we <= 1'b1;
+ wbo_stb <= 1'b1;
+ wbo_cyc <= 1;
+ state <= DESC_XFR;
+ desc_ptr <= desc_ptr+1;
+ end
+ end
+ end
+ DESC_XFR: begin
+ desc_ack <= 0;
+ if(wbo_ack) begin
+ wbo_stb <= 1'b0;
+ wbo_cyc <= 1'b0;
+ state <= IDLE;
+ end
+ end
+
+ endcase
+ end
+end
+
+
+
+endmodule
diff --git a/verilog/rtl/mbist/include/mbist_def.svh b/verilog/rtl/mbist/include/mbist_def.svh
new file mode 100644
index 0000000..10fb2ea
--- /dev/null
+++ b/verilog/rtl/mbist/include/mbist_def.svh
@@ -0,0 +1,66 @@
+///////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+`ifndef BIST_DEFINE_SVH
+`define BIST_DEFINE_SVH
+
+// BIST ADDRESS CONTRL
+//
+//parameter BIST_ADDR_WD = 9 ;
+//parameter BIST_ADDR_START = 10'h000 ;
+//parameter BIST_ADDR_END = 10'h3FB ;
+
+// BIST DATA CONTRL
+//parameter BIST_DATA_WD = 32;
+parameter BIST_DATA_PAT_SIZE = 8;
+parameter BIST_DATA_PAT_TYPE1 = 64'h5555_5555_5555_5555;
+parameter BIST_DATA_PAT_TYPE2 = 64'h3333_3333_3333_3333;
+parameter BIST_DATA_PAT_TYPE3 = 64'h0F0F_0F0F_0F0F_0F0F;
+parameter BIST_DATA_PAT_TYPE4 = 64'h00FF_00FF_00FF_00FF;
+parameter BIST_DATA_PAT_TYPE5 = 64'h0000_FFFF_0000_FFFF;
+parameter BIST_DATA_PAT_TYPE6 = 64'h0000_0000_FFFF_FFFF;
+parameter BIST_DATA_PAT_TYPE7 = 64'hFFFF_FFFF_FFFF_FFFF;
+parameter BIST_DATA_PAT_TYPE8 = 64'h0000_0000_0000_0000;
+
+// BIST STIMULATION SELECT
+
+parameter BIST_STI_SIZE = 5;
+parameter BIST_STI_WD = 15;
+// Additional 3'b000 added at end of each stimulus to flush out the comparion
+// result + to handle error fix case
+parameter BIST_STIMULUS_TYPE1 = 15'b100100100100000;
+parameter BIST_STIMULUS_TYPE2 = 15'b100010101011000;
+parameter BIST_STIMULUS_TYPE3 = 15'b110011100010000;
+parameter BIST_STIMULUS_TYPE4 = 15'b000010101011000;
+parameter BIST_STIMULUS_TYPE5 = 15'b010011100010000;
+parameter BIST_STIMULUS_TYPE6 = 15'b000000000000000;
+parameter BIST_STIMULUS_TYPE7 = 15'b000000000000000;
+parameter BIST_STIMULUS_TYPE8 = 15'b000000000000000;
+
+
+// Operation
+parameter BIST_OP_SIZE = 4;
+
+// BIST ADDRESS REPAIR
+//parameter BIST_RAD_WD_I = BIST_ADDR_WD;
+//parameter BIST_RAD_WD_O = BIST_ADDR_WD;
+parameter BIST_ERR_LIMIT = 4;
+// Make Sure that this address in outside the valid address range
+//parameter BIST_REPAIR_ADDR_START = 10'h3FC ;
+
+`endif // BIST_DEFINE_SVH
diff --git a/verilog/rtl/mbist/run_iverilog b/verilog/rtl/mbist/run_iverilog
new file mode 100755
index 0000000..a88ada5
--- /dev/null
+++ b/verilog/rtl/mbist/run_iverilog
@@ -0,0 +1,18 @@
+iverilog -g2005-sv \
+src/top/mbist_top1.sv \
+src/core/mbist_addr_gen.sv \
+src/core/mbist_fsm.sv \
+src/core/mbist_op_sel.sv \
+src/core/mbist_repair_addr.sv \
+src/core/mbist_data_cmp.sv \
+src/core/mbist_mux.sv \
+src/core/mbist_pat_sel.sv \
+src/core/mbist_sti_sel.sv \
+src/core/mbist_mem_wrapper.sv \
+-I include/ \
+../lib/ctech_cells.sv \
+../lib/reset_sync.sv \
+$PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v \
+$PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v \
+--timescale 1ns/100ps \
+--bbox-unsup
diff --git a/verilog/rtl/mbist/run_verilator b/verilog/rtl/mbist/run_verilator
new file mode 100755
index 0000000..1dd5d6b
--- /dev/null
+++ b/verilog/rtl/mbist/run_verilator
@@ -0,0 +1,17 @@
+verilator -cc \
+src/top/mbist_top1.sv \
+src/core/mbist_addr_gen.sv \
+src/core/mbist_fsm.sv \
+src/core/mbist_op_sel.sv \
+src/core/mbist_repair_addr.sv \
+src/core/mbist_data_cmp.sv \
+src/core/mbist_mux.sv \
+src/core/mbist_pat_sel.sv \
+src/core/mbist_sti_sel.sv \
++incdir+include/ \
+../lib/ctech_cells.sv \
+../lib/reset_sync.sv \
+-v $PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v \
+-v $PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v \
+--timescale 1ns/100ps \
+--bbox-unsup
diff --git a/verilog/rtl/mbist/src/core/mbist_addr_gen.sv b/verilog/rtl/mbist/src/core/mbist_addr_gen.sv
new file mode 100644
index 0000000..584a2b6
--- /dev/null
+++ b/verilog/rtl/mbist/src/core/mbist_addr_gen.sv
@@ -0,0 +1,117 @@
+///////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MBIST Address Generator ////
+//// ////
+//// This file is part of the mbist_ctrl cores project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block integrate mbist address gen ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 11th Oct 2021, Dinesh A ////
+//// Initial integration ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`include "mbist_def.svh"
+
+module mbist_addr_gen
+ #( parameter BIST_ADDR_WD = 9,
+ parameter BIST_DATA_WD = 32,
+ parameter BIST_ADDR_START = 9'h000,
+ parameter BIST_ADDR_END = 9'h1F8,
+ parameter BIST_REPAIR_ADDR_START = 9'h1FC,
+ parameter BIST_RAD_WD_I = BIST_ADDR_WD,
+ parameter BIST_RAD_WD_O = BIST_ADDR_WD) (
+
+ output logic last_addr, // Last address access
+ output logic [BIST_ADDR_WD-1:0] bist_addr, // Bist Address
+ output logic sdo, // scan data output
+ input logic clk, // clock input
+ input logic rst_n, // asynchronous reset
+ input logic run, // stop or start state machine
+ input logic updown, // count up or down
+ input logic scan_shift, // shift scan input
+ input logic scan_load, // load scan input
+ input logic sdi // scan data input
+
+);
+
+
+logic [BIST_ADDR_WD-1:0] next_addr; // Next Address
+logic [BIST_ADDR_WD-1:0] start_addr; // Address Start Address
+logic [BIST_ADDR_WD-1:0] end_addr; // Address Stop Address
+
+
+assign last_addr = (((updown == 1'b1)&&(bist_addr == end_addr))||((updown == 1'b0)&&(bist_addr == start_addr)))?1'b1:1'b0;
+
+
+/******************************
+ Address register
+ Basic Assumption: Allways counter start with upcounting
+*********************************/
+
+
+always @(posedge clk or negedge rst_n) begin
+ if(!rst_n) bist_addr <= BIST_ADDR_START ;
+ else if(scan_load) bist_addr <= start_addr;
+ else bist_addr <= next_addr;
+end
+
+/* Input combinational block */
+
+always_comb begin
+ if(run) begin
+ if((bist_addr == end_addr)&&(updown == 1'b1))
+ next_addr = start_addr ;
+ else if((bist_addr == start_addr)&&(updown == 1'b0))
+ next_addr = end_addr ;
+ else next_addr = (updown)?bist_addr+1'b1:bist_addr-1'b1;
+ end
+ else next_addr = bist_addr;
+end
+
+
+/* Start register */
+
+always @(posedge clk or negedge rst_n) begin
+ if(!rst_n) start_addr <= BIST_ADDR_START ;
+ else if(scan_shift) start_addr <= {sdi, start_addr[BIST_ADDR_WD-1:1]};
+end
+
+/* Start register */
+always @(posedge clk or negedge rst_n) begin
+ if(!rst_n) end_addr <= BIST_ADDR_END ;
+ else if(scan_shift) end_addr <= {start_addr[0], end_addr[BIST_ADDR_WD-1:1]};
+end
+
+
+
+assign sdo = end_addr[0];
+
+endmodule
+
diff --git a/verilog/rtl/mbist/src/core/mbist_data_cmp.sv b/verilog/rtl/mbist/src/core/mbist_data_cmp.sv
new file mode 100644
index 0000000..45dd343
--- /dev/null
+++ b/verilog/rtl/mbist/src/core/mbist_data_cmp.sv
@@ -0,0 +1,116 @@
+///////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MBIST Data Comparator ////
+//// ////
+//// This file is part of the mbist_ctrl cores project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block integrate mbist data comparator ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 11th Oct 2021, Dinesh A ////
+//// Initial integration ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+`include "mbist_def.svh"
+
+
+module mbist_data_cmp
+ #( parameter BIST_ADDR_WD = 9,
+ parameter BIST_DATA_WD = 32,
+ parameter BIST_ADDR_START = 9'h000,
+ parameter BIST_ADDR_END = 9'h1F8,
+ parameter BIST_REPAIR_ADDR_START = 9'h1FC,
+ parameter BIST_RAD_WD_I = BIST_ADDR_WD,
+ parameter BIST_RAD_WD_O = BIST_ADDR_WD) (
+
+ output logic error,
+ output logic error_correct,
+ output logic correct,
+ output logic [BIST_ADDR_WD-1:0] error_addr,
+ output logic [3:0] error_cnt,
+ input logic clk,
+ input logic rst_n,
+ input logic compare,
+ input logic addr_inc_phase,
+ input logic read_invert,
+ input logic [BIST_DATA_WD-1:0] comp_data,
+ input logic [BIST_DATA_WD-1:0] rxd_data,
+ input logic [BIST_ADDR_WD-1:0] addr
+
+ );
+
+logic mask_compare;
+logic [BIST_DATA_WD-1:0] exp_data;
+logic comp_status;
+
+assign exp_data = (read_invert) ? ~comp_data: comp_data;
+
+/* Comparison register */
+
+always @(posedge clk or negedge rst_n) begin
+ if(!rst_n) begin
+ comp_status <= 1'b0;
+ error_addr <= 'b0;
+ end else if(compare && !mask_compare) begin
+ comp_status <= |(exp_data ^ rxd_data);
+ error_addr <= addr;
+ end else begin
+ comp_status <= 1'b0;
+ end
+end
+
+// Due to cycle diference between compare and write opperation
+// There is chance two error reported for same address
+// To avoid this, once error is detected, comparision is masked
+// unit the next address phase
+always @(posedge clk or negedge rst_n) begin
+ if(!rst_n) begin
+ error_cnt <= 'b0;
+ correct <='b0;
+ mask_compare <= 'b0;
+ error <= '0;
+ end else if(mask_compare && addr_inc_phase) begin
+ mask_compare <= 1'b0;
+ end else if(comp_status && (error_cnt < BIST_ERR_LIMIT) ) begin
+ error_cnt <= error_cnt+1;
+ mask_compare <= 1'b1;
+ correct <='b1;
+ end else if(comp_status && (error_cnt == BIST_ERR_LIMIT) ) begin
+ error <= '1;
+ end
+end
+
+assign error_correct = (error_cnt < BIST_ERR_LIMIT) ? comp_status : 1'b0;
+
+endmodule
+
+
+
+
+
+
diff --git a/verilog/rtl/mbist/src/core/mbist_fsm.sv b/verilog/rtl/mbist/src/core/mbist_fsm.sv
new file mode 100644
index 0000000..7672ee7
--- /dev/null
+++ b/verilog/rtl/mbist/src/core/mbist_fsm.sv
@@ -0,0 +1,141 @@
+///////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MBIST Main control FSM ////
+//// ////
+//// This file is part of the mbist_ctrl cores project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// MBIST Main control FSM to control Command, Address, Write ////
+//// and Read compare phase ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 11th Oct 2021, Dinesh A ////
+//// Initial integration ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+module mbist_fsm
+ #( parameter BIST_ADDR_WD = 9,
+ parameter BIST_DATA_WD = 32,
+ parameter BIST_ADDR_START = 9'h000,
+ parameter BIST_ADDR_END = 9'h1F8,
+ parameter BIST_REPAIR_ADDR_START = 9'h1FC,
+ parameter BIST_RAD_WD_I = BIST_ADDR_WD,
+ parameter BIST_RAD_WD_O = BIST_ADDR_WD) (
+
+ output logic cmd_phase, // Command Phase
+ output logic cmp_phase, // Compare Phase
+ output logic run_op, // Move to Next Operation
+ output logic run_addr, // Move to Next Address
+ output logic run_sti, // Move to Next Stimulus
+ output logic run_pat, // Move to next pattern
+ output logic bist_done, // Bist Test Done
+
+
+ input logic clk, // Clock
+ input logic rst_n, // Reset
+ input logic bist_run, // Bist Run
+ input logic bist_error, // Bist Error
+ input logic op_reverse, // Address Reverse in Next Cycle
+ input logic last_op, // Last Operation
+ input logic last_addr, // Last Address
+ input logic last_sti, // Last Stimulus
+ input logic last_pat // Last Pattern
+
+
+);
+
+parameter FSM_PHASE1 = 2'b00;
+parameter FSM_PHASE2 = 2'b01;
+parameter FSM_EXIT = 2'b10;
+
+logic [1:0] state;
+
+
+
+always @(posedge clk or negedge rst_n)
+begin
+ if(!rst_n) begin
+ cmd_phase <= 0;
+ cmp_phase <= 0;
+ run_op <= 0;
+ run_addr <= 0;
+ run_sti <= 0;
+ run_pat <= 0;
+ bist_done <= 0;
+ state <= FSM_PHASE1;
+ end else if(bist_run) begin
+ case(state)
+ FSM_PHASE1 :
+ begin
+ cmd_phase <= 1;
+ cmp_phase <= 0;
+ run_op <= 0;
+ run_addr <= 0;
+ run_sti <= 0;
+ run_pat <= 0;
+ state <= FSM_PHASE2;
+ end
+ FSM_PHASE2 :
+ begin
+ if((last_addr && last_op && last_sti && last_pat) || bist_error) begin
+ cmd_phase <= 0;
+ cmp_phase <= 0;
+ run_op <= 0;
+ run_addr <= 0;
+ run_sti <= 0;
+ run_pat <= 0;
+ state <= FSM_EXIT;
+ end else begin
+ cmd_phase <= 0;
+ cmp_phase <= 1;
+ run_op <= 1;
+ if(last_op && !(last_addr && op_reverse))
+ run_addr <= 1;
+ if(last_addr && last_op)
+ run_sti <= 1;
+ if(last_addr && last_op && last_sti)
+ run_pat <= 1;
+ state <= FSM_PHASE1;
+ end
+ end
+ FSM_EXIT: bist_done <= 1;
+ default: state <= FSM_PHASE1;
+ endcase
+ end else begin
+ cmd_phase <= 0;
+ cmp_phase <= 0;
+ run_op <= 0;
+ run_addr <= 0;
+ run_sti <= 0;
+ run_pat <= 0;
+ state <= FSM_PHASE1;
+ end
+end
+
+
+
+endmodule
diff --git a/verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv b/verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv
new file mode 100644
index 0000000..b631626
--- /dev/null
+++ b/verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv
@@ -0,0 +1,120 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Memory wrapper ////
+//// ////
+//// This file is part of the mbist_ctrl project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block does wishbone to SRAM signal mapping ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 18 Nov 2021, Dinesh A ////
+//// initial version ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+module mbist_mem_wrapper #(
+ parameter BIST_ADDR_WD=10,
+ parameter BIST_DATA_WD=32) (
+ input logic rst_n ,
+ // WB I/F
+ input logic wb_clk_i , // System clock
+ input logic wb_cyc_i , // strobe/request
+ input logic wb_stb_i , // strobe/request
+ input logic [BIST_ADDR_WD-1:0] wb_adr_i , // address
+ input logic wb_we_i , // write
+ input logic [BIST_DATA_WD-1:0] wb_dat_i , // data output
+ input logic [BIST_DATA_WD/8-1:0] wb_sel_i , // byte enable
+ output logic [BIST_DATA_WD-1:0] wb_dat_o , // data input
+ output logic wb_ack_o , // acknowlegement
+ output logic wb_err_o , // error
+ // MEM A PORT
+ output logic func_clk_a ,
+ output logic func_cen_a ,
+ output logic [BIST_ADDR_WD-1:0] func_addr_a ,
+ input logic [BIST_DATA_WD-1:0] func_dout_a ,
+
+ // Functional B Port
+ output logic func_clk_b ,
+ output logic func_cen_b ,
+ output logic func_web_b ,
+ output logic [BIST_DATA_WD/8-1:0] func_mask_b ,
+ output logic [BIST_ADDR_WD-1:0] func_addr_b ,
+ output logic [BIST_DATA_WD-1:0] func_din_b
+
+);
+
+
+// Memory Write PORT
+assign func_clk_b = wb_clk_i;
+assign func_cen_b = !wb_stb_i;
+assign func_web_b = !wb_we_i;
+assign func_mask_b = wb_sel_i;
+assign func_addr_b = wb_adr_i;
+assign func_din_b = wb_dat_i;
+
+assign func_clk_a = wb_clk_i;
+assign func_cen_a = (wb_stb_i == 1'b1 && wb_we_i == 1'b0 && wb_ack_o ==0) ? 1'b0 : 1'b1;
+assign func_addr_a = wb_adr_i;
+assign wb_dat_o = func_dout_a;
+
+assign wb_err_o = 1'b0;
+
+// Generate Once cycle delayed ACK to get the data from SRAM
+always_ff @(negedge rst_n or posedge wb_clk_i) begin
+ if ( rst_n == 1'b0 ) begin
+ wb_ack_o<= 'h0;
+ end else begin
+ wb_ack_o <= (wb_stb_i == 1'b1) & (wb_ack_o == 0);
+ end
+end
+
+
+endmodule
diff --git a/verilog/rtl/mbist/src/core/mbist_mux.sv b/verilog/rtl/mbist/src/core/mbist_mux.sv
new file mode 100755
index 0000000..c3064f8
--- /dev/null
+++ b/verilog/rtl/mbist/src/core/mbist_mux.sv
@@ -0,0 +1,247 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MBIST and MEMORY Mux Control Selection ////
+//// ////
+//// This file is part of the mbist_ctrl cores project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block integrate MBIST and Memory control selection ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 11th Oct 2021, Dinesh A ////
+//// Initial integration
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`include "mbist_def.svh"
+module mbist_mux
+ #( parameter BIST_ADDR_WD = 9,
+ parameter BIST_DATA_WD = 32,
+ parameter BIST_ADDR_START = 9'h000,
+ parameter BIST_ADDR_END = 9'h1F8,
+ parameter BIST_REPAIR_ADDR_START = 9'h1FC,
+ parameter BIST_RAD_WD_I = BIST_ADDR_WD,
+ parameter BIST_RAD_WD_O = BIST_ADDR_WD) (
+
+ input logic scan_mode,
+ input logic cfg_mem_lphase,
+
+ input logic rst_n,
+ // MBIST CTRL SIGNAL
+ input logic bist_en,
+ input logic [BIST_ADDR_WD-1:0] bist_addr,
+ input logic [BIST_DATA_WD-1:0] bist_wdata,
+ input logic bist_clk,
+ input logic bist_wr,
+ input logic bist_rd,
+ input logic bist_error,
+ input logic [BIST_ADDR_WD-1:0] bist_error_addr,
+ output logic bist_correct,
+ input logic bist_sdi,
+ input logic bist_shift,
+ output logic bist_sdo,
+
+ // FUNCTIONAL CTRL SIGNAL
+ input logic func_clk_a,
+ input logic func_cen_a,
+ input logic [BIST_ADDR_WD-1:0] func_addr_a,
+ // Common for func and Mbist i/f
+ output logic [BIST_DATA_WD-1:0] func_dout_a,
+
+ input logic func_clk_b,
+ input logic func_cen_b,
+ input logic func_web_b,
+ input logic [BIST_DATA_WD/8-1:0] func_mask_b,
+ input logic [BIST_ADDR_WD-1:0] func_addr_b,
+ input logic [BIST_DATA_WD-1:0] func_din_b,
+
+
+ // towards memory
+ output logic mem_clk_a,
+ output logic mem_cen_a,
+ output logic [BIST_ADDR_WD-1:0] mem_addr_a,
+ input logic [BIST_DATA_WD-1:0] mem_dout_a,
+
+ output logic mem_clk_b,
+ output logic mem_cen_b,
+ output logic mem_web_b,
+ output logic [BIST_DATA_WD/8-1:0] mem_mask_b,
+ output logic [BIST_ADDR_WD-1:0] mem_addr_b,
+ output logic [BIST_DATA_WD-1:0] mem_din_b
+ );
+
+
+parameter BIST_MASK_WD = BIST_DATA_WD/8;
+
+wire [BIST_ADDR_WD-1:0] addr_a;
+wire [BIST_ADDR_WD-1:0] addr_b;
+wire mem_clk_a_cts; // used for internal clock tree
+wire mem_clk_b_cts; // usef for internal clock tree
+
+//----------------------------------------------------------------
+// As there SRAM timing model is not correct. we have created
+// additional position drive data in negedge
+// ----------------------------------------------------------------
+
+logic mem_cen_a_int;
+logic [BIST_ADDR_WD-1:0] mem_addr_a_int;
+
+logic mem_cen_b_int;
+logic mem_web_b_int;
+logic [BIST_DATA_WD/8-1:0] mem_mask_b_int;
+logic [BIST_ADDR_WD-1:0] mem_addr_b_int;
+logic [BIST_DATA_WD-1:0] mem_din_b_int;
+
+logic mem_cen_a_neg;
+logic [BIST_ADDR_WD-1:0] mem_addr_a_neg;
+
+logic mem_cen_b_neg;
+logic mem_web_b_neg;
+logic [BIST_DATA_WD/8-1:0] mem_mask_b_neg;
+logic [BIST_ADDR_WD-1:0] mem_addr_b_neg;
+logic [BIST_DATA_WD-1:0] mem_din_b_neg;
+
+always @(negedge rst_n or negedge mem_clk_a) begin
+ if(rst_n == 0) begin
+ mem_cen_a_neg <= '0;
+ mem_addr_a_neg <= '0;
+ end else begin
+ mem_cen_a_neg <= mem_cen_a_int;
+ mem_addr_a_neg <= mem_addr_a_int;
+ end
+end
+
+always @(negedge rst_n or negedge mem_clk_b) begin
+ if(rst_n == 0) begin
+ mem_cen_b_neg <= '0;
+ mem_web_b_neg <= '0;
+ mem_mask_b_neg <= '0;
+ mem_addr_b_neg <= '0;
+ mem_din_b_neg <= '0;
+ end else begin
+ mem_cen_b_neg <= mem_cen_b_int;
+ mem_web_b_neg <= mem_web_b_int;
+ mem_mask_b_neg <= mem_mask_b_int;
+ mem_addr_b_neg <= mem_addr_b_int;
+ mem_din_b_neg <= mem_din_b_int;
+ end
+end
+
+assign mem_cen_a = (cfg_mem_lphase == 0) ? mem_cen_a_int : mem_cen_a_neg;
+assign mem_addr_a = (cfg_mem_lphase == 0) ? mem_addr_a_int : mem_addr_a_neg;
+
+assign mem_cen_b = (cfg_mem_lphase == 0) ? mem_cen_b_int : mem_cen_b_neg;
+assign mem_web_b = (cfg_mem_lphase == 0) ? mem_web_b_int : mem_web_b_neg;
+assign mem_mask_b = (cfg_mem_lphase == 0) ? mem_mask_b_int : mem_mask_b_neg;
+assign mem_addr_b = (cfg_mem_lphase == 0) ? mem_addr_b_int : mem_addr_b_neg;
+assign mem_din_b = (cfg_mem_lphase == 0) ? mem_din_b_int : mem_din_b_neg;
+
+//-----------------------------------------
+assign addr_a = (bist_en) ? bist_addr : func_addr_a;
+assign addr_b = (bist_en) ? bist_addr : func_addr_b;
+
+assign mem_cen_a_int = (bist_en) ? !bist_rd : func_cen_a;
+assign mem_cen_b_int = (bist_en) ? !bist_wr : func_cen_b;
+
+assign mem_web_b_int = (bist_en) ? !bist_wr : func_web_b;
+assign mem_mask_b_int = (bist_en) ? {{BIST_MASK_WD}{1'b1}} : func_mask_b;
+
+//assign mem_clk_a = (bist_en) ? bist_clk : func_clk_a;
+//assign mem_clk_b = (bist_en) ? bist_clk : func_clk_b;
+
+ctech_mux2x1 u_mem_clk_a_sel (.A0 (func_clk_a),.A1 (bist_clk),.S (bist_en), .X (mem_clk_a));
+ctech_mux2x1 u_mem_clk_b_sel (.A0 (func_clk_b),.A1 (bist_clk),.S (bist_en), .X (mem_clk_b));
+
+ctech_clk_buf u_cts_mem_clk_a (.A (mem_clk_a), . X(mem_clk_a_cts));
+ctech_clk_buf u_cts_mem_clk_b (.A (mem_clk_b), . X(mem_clk_b_cts));
+
+assign mem_din_b_int = (bist_en) ? bist_wdata : func_din_b;
+
+
+// During scan, SRAM data is unknown, feed data in back to avoid unknow
+// propagation
+assign func_dout_a = (scan_mode) ? mem_din_b : mem_dout_a;
+
+mbist_repair_addr
+ #(.BIST_ADDR_WD (BIST_ADDR_WD),
+ .BIST_DATA_WD (BIST_DATA_WD),
+ .BIST_ADDR_START (BIST_ADDR_START),
+ .BIST_ADDR_END (BIST_ADDR_END),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O))
+ u_repair_A(
+ .AddressOut (mem_addr_a_int ),
+ .Correct (bist_correct ),
+ .sdo (bist_sdo ),
+
+ .AddressIn (addr_a ),
+ .clk (mem_clk_a_cts ),
+ .rst_n (rst_n ),
+ .Error (bist_error ),
+ .ErrorAddr (bist_error_addr ),
+ .scan_shift (bist_shift ),
+ .sdi (bist_sdi )
+);
+
+mbist_repair_addr
+ #(.BIST_ADDR_WD (BIST_ADDR_WD),
+ .BIST_DATA_WD (BIST_DATA_WD),
+ .BIST_ADDR_START (BIST_ADDR_START),
+ .BIST_ADDR_END (BIST_ADDR_END),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O))
+ u_repair_B(
+ .AddressOut (mem_addr_b_int ),
+ .Correct ( ), // Both Bist Correct are same
+ .sdo ( ),
+
+ .AddressIn (addr_b ),
+ .clk (mem_clk_b_cts ),
+ .rst_n (rst_n ),
+ .Error (bist_error ),
+ .ErrorAddr (bist_error_addr ),
+ .scan_shift (1'b0 ), // Both Repair hold same address
+ .sdi (1'b0 )
+);
+
+
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
diff --git a/verilog/rtl/mbist/src/core/mbist_op_sel.sv b/verilog/rtl/mbist/src/core/mbist_op_sel.sv
new file mode 100644
index 0000000..a995b8e
--- /dev/null
+++ b/verilog/rtl/mbist/src/core/mbist_op_sel.sv
@@ -0,0 +1,132 @@
+///////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MBIST Operation Selection ////
+//// ////
+//// This file is part of the mbist_ctrl cores project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block integrate Operation Selection ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 11th Oct 2021, Dinesh A ////
+//// Initial integration ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+
+`include "mbist_def.svh"
+// bist stimulus selection
+
+module mbist_op_sel
+ #( parameter BIST_ADDR_WD = 9,
+ parameter BIST_DATA_WD = 32,
+ parameter BIST_ADDR_START = 9'h000,
+ parameter BIST_ADDR_END = 9'h1F8,
+ parameter BIST_REPAIR_ADDR_START = 9'h1FC,
+ parameter BIST_RAD_WD_I = BIST_ADDR_WD,
+ parameter BIST_RAD_WD_O = BIST_ADDR_WD) (
+
+ output logic op_read , // Opertion Read
+ output logic op_write , // Operation Write
+ output logic op_invert , // Opertaion Data Invert
+ output logic op_updown , // Operation Address Up Down
+ output logic op_reverse , // Operation Reverse
+ output logic op_repeatflag , // Operation Repeat flag
+ output logic sdo , // Scan Data Out
+ output logic last_op , // last operation
+
+ input logic clk , // Clock
+ input logic rst_n , // Reset
+ input logic scan_shift , // Scan Shift
+ input logic sdi , // Scan data in
+ input logic re_init , // Re-init when there is error correction
+ input logic run , // Run
+ input logic [BIST_STI_WD-1:0] stimulus
+
+);
+
+
+logic [BIST_OP_SIZE-1:0] op_sel ;// Actual Operation
+logic [7:0] tmp_op ;// Warning : Assming Max opertion is 8
+logic [7:0] tmpinvert ;// read control
+logic [7:0] tmpread ;// write control
+logic [7:0] tmpwrite ;// invertor control
+integer index ;// output index */
+integer loop ;// bit count
+
+
+/* Operation Selection Selection */
+
+always @(posedge clk or negedge rst_n) begin
+ if(!rst_n) op_sel <= {1'b1,{(BIST_OP_SIZE-1){1'b0}}};
+ else if(scan_shift) op_sel <= {sdi, op_sel[BIST_OP_SIZE-1:1]};
+ else if(re_init) op_sel <= {1'b1,{(BIST_OP_SIZE-1){1'b0}}}; // need fix for pmbist moode
+ else if(run) op_sel <= {op_sel[0],op_sel[BIST_OP_SIZE-1:1]};
+end
+
+assign op_updown = stimulus[BIST_STI_WD-1];
+assign op_reverse = stimulus[BIST_STI_WD-2];
+assign op_repeatflag = stimulus[BIST_STI_WD-3];
+// Re-wind the operation, when the is error correct
+assign last_op = (re_init) ? 1'b0 : op_sel[0];
+
+
+
+always_comb
+begin
+ loop=0;
+ tmpinvert = 8'h0;
+ tmpread = 8'h0;
+ tmpwrite = 8'h0;
+ for(index = 0 ; index < BIST_OP_SIZE ; index = index+1)begin
+ tmpinvert[index] = stimulus[loop];
+ tmpread[index] = stimulus[loop+1];
+ tmpwrite[index] = stimulus[loop+2];
+ loop = loop + 3;
+ end
+end
+
+
+always_comb
+begin
+ tmp_op = 8'b00000000;
+ tmp_op[BIST_OP_SIZE-1:0] = op_sel;
+ case(tmp_op)
+ 8'b10000000: {op_read,op_write,op_invert} = {tmpread[7],tmpwrite[7],tmpinvert[7]};
+ 8'b01000000: {op_read,op_write,op_invert} = {tmpread[6],tmpwrite[6],tmpinvert[6]};
+ 8'b00100000: {op_read,op_write,op_invert} = {tmpread[5],tmpwrite[5],tmpinvert[5]};
+ 8'b00010000: {op_read,op_write,op_invert} = {tmpread[4],tmpwrite[4],tmpinvert[4]};
+ 8'b00001000: {op_read,op_write,op_invert} = {tmpread[3],tmpwrite[3],tmpinvert[3]};
+ 8'b00000100: {op_read,op_write,op_invert} = {tmpread[2],tmpwrite[2],tmpinvert[2]};
+ 8'b00000010: {op_read,op_write,op_invert} = {tmpread[1],tmpwrite[1],tmpinvert[1]};
+ 8'b00000001: {op_read,op_write,op_invert} = {tmpread[0],tmpwrite[0],tmpinvert[0]};
+ default: {op_read,op_write,op_invert} = {tmpread[0],tmpwrite[0],tmpinvert[0]};
+ endcase
+end
+
+
+endmodule
diff --git a/verilog/rtl/mbist/src/core/mbist_pat_sel.sv b/verilog/rtl/mbist/src/core/mbist_pat_sel.sv
new file mode 100644
index 0000000..47a5c98
--- /dev/null
+++ b/verilog/rtl/mbist/src/core/mbist_pat_sel.sv
@@ -0,0 +1,116 @@
+///////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MBIST Pattern Selection ////
+//// ////
+//// This file is part of the mbist_ctrl cores project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block integrate mbist pattern selection ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 11th Oct 2021, Dinesh A ////
+//// Initial integration ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+`include "mbist_def.svh"
+//-----------------------------------
+// MBIST Data Pattern Selection Logic
+//-----------------------------------
+module mbist_pat_sel
+ #( parameter BIST_ADDR_WD = 9,
+ parameter BIST_DATA_WD = 32,
+ parameter BIST_ADDR_START = 9'h000,
+ parameter BIST_ADDR_END = 9'h1F8,
+ parameter BIST_REPAIR_ADDR_START = 9'h1FC,
+ parameter BIST_RAD_WD_I = BIST_ADDR_WD,
+ parameter BIST_RAD_WD_O = BIST_ADDR_WD) (
+
+ output logic pat_last, // Last pattern
+ output logic [BIST_DATA_WD-1:0] pat_data, // pattern data
+ output logic sdo, // scan data output
+ input logic clk, // clock
+ input logic rst_n, // reset
+ input logic run, // stop or start state machine
+ input logic scan_shift, // scan shift
+ input logic sdi // scan input
+
+);
+
+
+logic [BIST_DATA_PAT_SIZE-1:0] pat_sel ;/* Pattern Select */
+logic [63:0] pattern;
+
+integer index ;/* output index */
+
+
+
+// last pattern
+assign pat_last = pat_sel[0];
+
+
+/* Pattern Selection */
+
+always @(posedge clk or negedge rst_n) begin
+ if(!rst_n) pat_sel <= {1'b1,{(BIST_DATA_PAT_SIZE-1){1'b0}}};
+ else if(scan_shift) pat_sel <= {sdi, pat_sel[BIST_DATA_PAT_SIZE-1:1]};
+ else if(run) pat_sel <= {pat_sel[0],pat_sel[BIST_DATA_PAT_SIZE-1:1]};
+end
+
+
+/* Pattern Selection */
+logic [7:0] tmp_pat;
+always_comb
+begin
+ tmp_pat = 8'b00000000;
+ tmp_pat[7:8-BIST_DATA_PAT_SIZE] = pat_sel;
+ case(tmp_pat)
+ 8'b10000000: pattern = BIST_DATA_PAT_TYPE1;
+ 8'b01000000: pattern = BIST_DATA_PAT_TYPE2;
+ 8'b00100000: pattern = BIST_DATA_PAT_TYPE3;
+ 8'b00010000: pattern = BIST_DATA_PAT_TYPE4;
+ 8'b00001000: pattern = BIST_DATA_PAT_TYPE5;
+ 8'b00000100: pattern = BIST_DATA_PAT_TYPE6;
+ 8'b00000010: pattern = BIST_DATA_PAT_TYPE7;
+ 8'b00000001: pattern = BIST_DATA_PAT_TYPE8;
+ default: pattern = BIST_DATA_PAT_TYPE1;
+ endcase
+end
+
+/* Data distributor */
+
+always_comb
+begin
+ for(index = 0 ; index < BIST_DATA_WD ; index = index + 1) begin
+ pat_data[index] = pattern[index%64];
+ end
+end
+
+assign sdo = pat_sel[0];
+
+endmodule
+
+
diff --git a/verilog/rtl/mbist/src/core/mbist_repair_addr.sv b/verilog/rtl/mbist/src/core/mbist_repair_addr.sv
new file mode 100644
index 0000000..dbeddcd
--- /dev/null
+++ b/verilog/rtl/mbist/src/core/mbist_repair_addr.sv
@@ -0,0 +1,157 @@
+///////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MBIST Address Repair ////
+//// ////
+//// This file is part of the mbist_ctrl cores project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block integrate mbist address repair ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 11th Oct 2021, Dinesh A ////
+//// Initial integration ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+
+// BIST address Repair Logic
+
+`include "mbist_def.svh"
+
+module mbist_repair_addr
+ #( parameter BIST_ADDR_WD = 9,
+ parameter BIST_DATA_WD = 32,
+ parameter BIST_ADDR_START = 9'h000,
+ parameter BIST_ADDR_END = 9'h1F8,
+ parameter BIST_REPAIR_ADDR_START = 9'h1FC,
+ parameter BIST_RAD_WD_I = BIST_ADDR_WD,
+ parameter BIST_RAD_WD_O = BIST_ADDR_WD) (
+
+ output logic [BIST_RAD_WD_O-1:0] AddressOut,
+ output logic Correct,
+ output logic sdo, // scan data output
+
+ input logic [BIST_RAD_WD_I-1:0] AddressIn,
+ input logic clk,
+ input logic rst_n,
+ input logic Error,
+ input logic [BIST_RAD_WD_I-1:0] ErrorAddr,
+ input logic scan_shift, // shift scan input
+ input logic sdi // scan data input
+
+
+);
+
+logic [3:0] ErrorCnt; // Assumed Maximum Error correction is less than 16
+logic [15:0] shift_reg;
+logic [15:0] shift_load;
+logic [7:0] shift_cnt;
+logic scan_shift_d;
+logic shift_pos_edge;
+
+logic [BIST_RAD_WD_I-1:0] RepairMem [0:BIST_ERR_LIMIT-1];
+integer i;
+
+
+always@(posedge clk or negedge rst_n)
+begin
+ if(!rst_n) begin
+ ErrorCnt <= '0;
+ Correct <= '0;
+ // Initialize the Repair RAM for SCAN purpose
+ for(i =0; i < BIST_ERR_LIMIT; i = i+1) begin
+ RepairMem[i] = 'h0;
+ end
+ end else if(Error) begin
+ if(ErrorCnt <= BIST_ERR_LIMIT) begin
+ ErrorCnt <= ErrorCnt+1;
+ RepairMem[ErrorCnt] <= ErrorAddr;
+ Correct <= 1'b1;
+ end else begin
+ Correct <= 1'b0;
+ end
+ end
+end
+
+integer index;
+logic eFlag; // Indicate error fix
+
+always_comb
+begin
+ AddressOut = AddressIn;
+ eFlag = 0;
+ for(index=0; index < BIST_ERR_LIMIT; index=index+1) begin
+ if(ErrorCnt > index && AddressIn == RepairMem[index]) begin
+ AddressOut = BIST_REPAIR_ADDR_START+index;
+ eFlag = 1;
+ end
+ end
+end
+
+/********************************************
+* Serial shifting the Repair address
+* *******************************************/
+
+always@(posedge clk or negedge rst_n)
+begin
+ if(!rst_n) begin
+ shift_reg <= '0;
+ shift_cnt <= '0;
+ scan_shift_d <= 1'b0;
+ end else begin
+ if(scan_shift && (shift_cnt[7:4] < BIST_ERR_LIMIT)) begin
+ shift_cnt <= shift_cnt+1;
+ end
+ scan_shift_d <= scan_shift;
+ shift_reg <= shift_load;
+ end
+end
+
+// Detect scan_shift pos edge
+assign shift_pos_edge = (scan_shift_d ==0) && (scan_shift);
+
+always_comb
+begin
+ shift_load = shift_reg;
+ // Block the data reloading every pos edge of shift
+ if(scan_shift && ((shift_cnt[7:4]+1) < BIST_ERR_LIMIT) && (shift_cnt[3:0] == 4'b1111))
+ shift_load = {RepairMem[shift_cnt[7:4]+1]};
+ else if(scan_shift)
+ shift_load = {sdi,shift_reg[15:1]};
+ else
+ shift_load = {RepairMem[shift_cnt[7:4]]};
+
+end
+
+assign sdo = shift_reg[0];
+endmodule
+
+
+
+
+
+
diff --git a/verilog/rtl/mbist/src/core/mbist_sti_sel.sv b/verilog/rtl/mbist/src/core/mbist_sti_sel.sv
new file mode 100644
index 0000000..459dc9f
--- /dev/null
+++ b/verilog/rtl/mbist/src/core/mbist_sti_sel.sv
@@ -0,0 +1,105 @@
+///////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MBIST Stimulus Selection ////
+//// ////
+//// This file is part of the mbist_ctrl cores project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block integrate stimulus slectiion ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 11th Oct 2021, Dinesh A ////
+//// Initial integration ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+
+`include "mbist_def.svh"
+// bist stimulus selection
+
+module mbist_sti_sel
+ #( parameter BIST_ADDR_WD = 9,
+ parameter BIST_DATA_WD = 32,
+ parameter BIST_ADDR_START = 9'h000,
+ parameter BIST_ADDR_END = 9'h1F8,
+ parameter BIST_REPAIR_ADDR_START = 9'h1FC,
+ parameter BIST_RAD_WD_I = BIST_ADDR_WD,
+ parameter BIST_RAD_WD_O = BIST_ADDR_WD) (
+
+ output logic sdo , // Scan Data Out
+ output logic last_stimulus , // last stimulus
+ output logic [BIST_STI_WD-1:0] stimulus ,
+
+ input logic clk , // Clock
+ input logic rst_n , // Reset
+ input logic scan_shift , // Scan Shift
+ input logic sdi , // Scan data in
+ input logic run // Run
+
+);
+
+logic [BIST_STI_SIZE-1:0] sti_sel ; // Stimulation Selection
+logic [7:0] tmp_sti ; // Warning: Max Stimulus assmed is 8
+
+
+
+/* Pattern Selection */
+
+always @(posedge clk or negedge rst_n) begin
+ if(!rst_n) sti_sel <= {1'b1,{(BIST_STI_SIZE-1){1'b0}}};
+ else if(scan_shift) sti_sel <= {sdi, sti_sel[BIST_STI_SIZE-1:1]};
+ else if(run) sti_sel <= {sti_sel[0],sti_sel[BIST_STI_SIZE-1:1]};
+end
+
+
+/* Pattern Selection */
+always_comb
+begin
+ tmp_sti = 8'b00000000;
+ tmp_sti[7:8-BIST_STI_SIZE] = sti_sel;
+ case(tmp_sti)
+ 8'b10000000: stimulus = BIST_STIMULUS_TYPE1;
+ 8'b01000000: stimulus = BIST_STIMULUS_TYPE2;
+ 8'b00100000: stimulus = BIST_STIMULUS_TYPE3;
+ 8'b00010000: stimulus = BIST_STIMULUS_TYPE4;
+ 8'b00001000: stimulus = BIST_STIMULUS_TYPE5;
+ 8'b00000100: stimulus = BIST_STIMULUS_TYPE6;
+ 8'b00000010: stimulus = BIST_STIMULUS_TYPE7;
+ 8'b00000001: stimulus = BIST_STIMULUS_TYPE8;
+ default: stimulus = BIST_STIMULUS_TYPE1;
+ endcase
+end
+
+
+/* Assign output */
+
+assign sdo = sti_sel[0];
+assign last_stimulus = sti_sel[0];
+
+
+
+endmodule
diff --git a/verilog/rtl/mbist/src/top/mbist_top.sv b/verilog/rtl/mbist/src/top/mbist_top.sv
new file mode 100644
index 0000000..806ce13
--- /dev/null
+++ b/verilog/rtl/mbist/src/top/mbist_top.sv
@@ -0,0 +1,566 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MBIST TOP ////
+//// ////
+//// This file is part of the mbist_ctrl cores project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block integrate mbist controller with row ////
+//// redendency feature ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 11th Oct 2021, Dinesh A ////
+//// Initial integration ////
+//// 0.1 - 26th Oct 2021, Dinesh A ////
+//// Fixed Error Address are serial shifted through ////
+//// sdi/sdo ////
+//// 0.2 - 15 Dec 2021, Dinesh A ////
+//// Added support for common MBIST for 4 SRAM ////
+//// 0.3 - 29th Dec 2021, Dinesh A ////
+//// yosys synthesis issue for two dimension variable ////
+//// changed the variable defination from logic to wire ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`include "mbist_def.svh"
+module mbist_top
+ #(
+ parameter BIST_NO_SRAM = 4,
+ parameter BIST_ADDR_WD = 9,
+ parameter BIST_DATA_WD = 32,
+ parameter BIST_ADDR_START = 9'h000,
+ parameter BIST_ADDR_END = 9'h1FB,
+ parameter BIST_REPAIR_ADDR_START = 9'h1FC,
+ parameter BIST_RAD_WD_I = BIST_ADDR_WD,
+ parameter BIST_RAD_WD_O = BIST_ADDR_WD) (
+
+`ifdef USE_POWER_PINS
+ inout vccd1, // User area 1 1.8V supply
+ inout vssd1, // User area 1 digital ground
+`endif
+
+ // Clock Skew Adjust
+ input wire wbd_clk_int,
+ output wire wbd_clk_mbist,
+ input wire [3:0] cfg_cska_mbist, // clock skew adjust for web host
+
+ input logic rst_n,
+
+ // MBIST I/F
+ input wire bist_en,
+ input wire bist_run,
+ input wire bist_shift,
+ input wire bist_load,
+ input wire bist_sdi,
+
+ output wire [3:0] bist_error_cnt0,
+ output wire [3:0] bist_error_cnt1,
+ output wire [3:0] bist_error_cnt2,
+ output wire [3:0] bist_error_cnt3,
+ output wire [BIST_NO_SRAM-1:0] bist_correct ,
+ output wire [BIST_NO_SRAM-1:0] bist_error ,
+ output wire bist_done,
+ output wire bist_sdo,
+
+
+ // WB I/F
+ input wire wb_clk_i, // System clock
+ input wire wb_clk2_i, // System clock2 is no cts
+ input wire mem_req, // strobe/request
+ input wire [(BIST_NO_SRAM+1)/2-1:0] mem_cs,
+ input wire [BIST_ADDR_WD-1:0] mem_addr, // address
+ input wire mem_we , // write
+ input wire [BIST_DATA_WD-1:0] mem_wdata, // data output
+ input wire [BIST_DATA_WD/8-1:0] mem_wmask, // byte enable
+ output wire [BIST_DATA_WD-1:0] mem_rdata, // data input
+
+ // towards memory
+ // PORT-A
+ output wire [BIST_NO_SRAM-1:0] mem_clk_a,
+ output wire [BIST_ADDR_WD-1:0] mem_addr_a0,
+ output wire [BIST_ADDR_WD-1:0] mem_addr_a1,
+ output wire [BIST_ADDR_WD-1:0] mem_addr_a2,
+ output wire [BIST_ADDR_WD-1:0] mem_addr_a3,
+ output wire [BIST_NO_SRAM-1:0] mem_cen_a,
+ output wire [BIST_NO_SRAM-1:0] mem_web_a,
+ output wire [BIST_DATA_WD/8-1:0] mem_mask_a0,
+ output wire [BIST_DATA_WD/8-1:0] mem_mask_a1,
+ output wire [BIST_DATA_WD/8-1:0] mem_mask_a2,
+ output wire [BIST_DATA_WD/8-1:0] mem_mask_a3,
+ output wire [BIST_DATA_WD-1:0] mem_din_a0,
+ output wire [BIST_DATA_WD-1:0] mem_din_a1,
+ output wire [BIST_DATA_WD-1:0] mem_din_a2,
+ output wire [BIST_DATA_WD-1:0] mem_din_a3,
+
+ input wire [BIST_DATA_WD-1:0] mem_dout_a0,
+ input wire [BIST_DATA_WD-1:0] mem_dout_a1,
+ input wire [BIST_DATA_WD-1:0] mem_dout_a2,
+ input wire [BIST_DATA_WD-1:0] mem_dout_a3,
+
+
+ // PORT-B
+ output wire [BIST_NO_SRAM-1:0] mem_clk_b,
+ output wire [BIST_NO_SRAM-1:0] mem_cen_b,
+ output wire [BIST_ADDR_WD-1:0] mem_addr_b0,
+ output wire [BIST_ADDR_WD-1:0] mem_addr_b1,
+ output wire [BIST_ADDR_WD-1:0] mem_addr_b2,
+ output wire [BIST_ADDR_WD-1:0] mem_addr_b3
+
+
+
+
+);
+
+parameter NO_SRAM_WD = (BIST_NO_SRAM+1)/2;
+
+// FUNCTIONAL PORT
+wire func_clk[0:BIST_NO_SRAM-1];
+wire func_cen[0:BIST_NO_SRAM-1];
+wire func_web[0:BIST_NO_SRAM-1];
+wire [BIST_DATA_WD/8-1:0]func_mask[0:BIST_NO_SRAM-1];
+wire [BIST_ADDR_WD-1:0]func_addr[0:BIST_NO_SRAM-1];
+wire [BIST_DATA_WD-1:0]func_dout[0:BIST_NO_SRAM-1];
+wire [BIST_DATA_WD-1:0]func_din[0:BIST_NO_SRAM-1];
+
+//----------------------------------------------------
+// Local variable defination
+// ---------------------------------------------------
+//
+wire srst_n ; // sync reset w.r.t bist_clk
+wire cmd_phase ; // Command Phase
+wire cmp_phase ; // Compare Phase
+wire run_op ; // Run next Operation
+wire run_addr ; // Run Next Address
+wire run_sti ; // Run Next Stimulus
+wire run_pat ; // Run Next Pattern
+wire op_updown ; // Adress updown direction
+wire last_addr ; // last address indication
+wire last_sti ; // last stimulus
+wire last_op ; // last operation
+wire last_pat ; // last pattern
+wire [BIST_DATA_WD-1:0] pat_data ; // Selected Data Pattern
+wire [BIST_STI_WD-1:0] stimulus ; // current stimulus
+wire compare ; // compare data
+wire op_repeatflag;
+wire op_reverse;
+wire op_read ;
+wire op_write ;
+wire op_invert ;
+
+
+wire bist_error_correct[0:BIST_NO_SRAM-1] ;
+wire [BIST_ADDR_WD-1:0]bist_error_addr[0:BIST_NO_SRAM-1] ; // bist address
+
+wire [BIST_ADDR_WD-1:0]bist_addr ; // bist address
+wire [BIST_DATA_WD-1:0] bist_wdata ; // bist write data
+wire bist_wr ;
+wire bist_rd ;
+wire [BIST_DATA_WD-1:0] wb_dat[0:BIST_NO_SRAM-1]; // data input
+
+//--------------------------------------------------------
+// As yosys does not support two dimensional var,
+// converting it single dimension
+// -------------------------------------------------------
+wire [3:0] bist_error_cnt_i [0:BIST_NO_SRAM-1];
+
+assign bist_error_cnt0 = bist_error_cnt_i[0];
+assign bist_error_cnt1 = bist_error_cnt_i[1];
+assign bist_error_cnt2 = bist_error_cnt_i[2];
+assign bist_error_cnt3 = bist_error_cnt_i[3];
+
+
+// Towards MEMORY PORT - A
+wire [BIST_ADDR_WD-1:0] mem_addr_a_i[0:BIST_NO_SRAM-1];
+wire [BIST_DATA_WD/8-1:0] mem_mask_a_i[0:BIST_NO_SRAM-1];
+wire [BIST_DATA_WD-1:0] mem_dout_a_i[0:BIST_NO_SRAM-1];
+wire [BIST_DATA_WD-1:0] mem_din_a_i[0:BIST_NO_SRAM-1];
+
+assign mem_addr_a0 = mem_addr_a_i[0];
+assign mem_addr_a1 = mem_addr_a_i[1];
+assign mem_addr_a2 = mem_addr_a_i[2];
+assign mem_addr_a3 = mem_addr_a_i[3];
+
+assign mem_din_a0 = mem_din_a_i[0];
+assign mem_din_a1 = mem_din_a_i[1];
+assign mem_din_a2 = mem_din_a_i[2];
+assign mem_din_a3 = mem_din_a_i[3];
+
+assign mem_mask_a0= mem_mask_a_i[0];
+assign mem_mask_a1= mem_mask_a_i[1];
+assign mem_mask_a2= mem_mask_a_i[2];
+assign mem_mask_a3= mem_mask_a_i[3];
+
+// FROM MEMORY
+assign mem_dout_a_i[0] = mem_dout_a0;
+assign mem_dout_a_i[1] = mem_dout_a1;
+assign mem_dout_a_i[2] = mem_dout_a2;
+assign mem_dout_a_i[3] = mem_dout_a3;
+
+// Towards MEMORY PORT - A
+assign mem_clk_b = 'b0;
+assign mem_cen_b = 'b0;
+assign mem_addr_b0 = 'b0;
+assign mem_addr_b1 = 'b0;
+assign mem_addr_b2 = 'b0;
+assign mem_addr_b3 = 'b0;
+
+//---------------------------------------------------
+// Manage the SDI => SDO Diasy chain
+// --------------------------------------------------
+//---------------------------------
+// SDI => SDO diasy chain
+// bist_sdi => bist_addr_sdo => bist_sti_sdo => bist_op_sdo => bist_pat_sdo => bist_sdo
+// ---------------------------------
+wire bist_addr_sdo ;
+wire bist_sti_sdo ;
+wire bist_op_sdo ;
+wire bist_pat_sdo ;
+
+wire bist_ms_sdi[0:BIST_NO_SRAM-1];
+wire bist_ms_sdo[0:BIST_NO_SRAM-1];
+
+// Adjust the SDI => SDO Daisy chain
+assign bist_ms_sdi[0] = bist_pat_sdo;
+assign bist_ms_sdi[1] = bist_ms_sdo[0];
+assign bist_ms_sdi[2] = bist_ms_sdo[1];
+assign bist_ms_sdi[3] = bist_ms_sdo[2];
+assign bist_sdo = bist_ms_sdo[3];
+
+// Pick the correct read path
+assign mem_rdata = wb_dat[mem_cs];
+
+assign bist_wr = (cmd_phase && op_write);
+assign bist_rd = (cmd_phase && op_read);
+
+assign compare = (cmp_phase && op_read);
+assign bist_wdata = (op_invert) ? ~pat_data : pat_data;
+
+// Clock Tree branching to avoid clock latency towards SRAM path
+wire wb_clk_b1,wb_clk_b2;
+//ctech_clk_buf u_cts_wb_clk_b1 (.A (wb_clk_i), . X(wb_clk_b1));
+//ctech_clk_buf u_cts_wb_clk_b2 (.A (wb_clk_i), . X(wb_clk_b2));
+
+// wb_host clock skew control
+clk_skew_adjust u_skew_mbist
+ (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ .clk_in (wbd_clk_int ),
+ .sel (cfg_cska_mbist ),
+ .clk_out (wbd_clk_mbist )
+ );
+
+reset_sync u_reset_sync (
+ .scan_mode (1'b0 ),
+ .dclk (wb_clk_i ), // Destination clock domain
+ .arst_n (rst_n ), // active low async reset
+ .srst_n (srst_n )
+ );
+
+
+integer i;
+reg bist_error_and;
+reg bist_error_correct_or;
+
+always_comb begin
+ bist_error_and =0;
+ bist_error_correct_or = 0;
+ for(i=0; i <BIST_NO_SRAM; i = i+1) begin
+ bist_error_and = bist_error_and & bist_error[i];
+ bist_error_correct_or = bist_error_correct_or | bist_error_correct[i];
+ end
+end
+
+
+// bist main control FSM
+
+mbist_fsm
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_fsm (
+
+ .cmd_phase (cmd_phase ),
+ .cmp_phase (cmp_phase ),
+ .run_op (run_op ),
+ .run_addr (run_addr ),
+ .run_sti (run_sti ),
+ .run_pat (run_pat ),
+ .bist_done (bist_done ),
+
+
+ .clk (wb_clk_i ),
+ .rst_n (srst_n ),
+ .bist_run (bist_run ),
+ .last_op (last_op ),
+ .last_addr (last_addr ),
+ .last_sti (last_sti ),
+ .last_pat (last_pat ),
+ .op_reverse (op_reverse ),
+ .bist_error (bist_error_and )
+);
+
+
+// bist address generation
+mbist_addr_gen
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_addr_gen(
+ .last_addr (last_addr ),
+ .bist_addr (bist_addr ),
+ .sdo (bist_addr_sdo ),
+
+ .clk (wb_clk_i ),
+ .rst_n (srst_n ),
+ .run (run_addr ),
+ .updown (op_updown ),
+ .bist_shift (bist_shift ),
+ .bist_load (bist_load ),
+ .sdi (bist_sdi )
+
+);
+
+
+// BIST current stimulus selection
+mbist_sti_sel
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_sti_sel(
+
+ .sdo (bist_sti_sdo ),
+ .last_stimulus (last_sti ),
+ .stimulus (stimulus ),
+
+ .clk (wb_clk_i ),
+ .rst_n (srst_n ),
+ .scan_shift (bist_shift ),
+ .sdi (bist_addr_sdo ),
+ .run (run_sti )
+
+);
+
+
+// Bist Operation selection
+mbist_op_sel
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_op_sel (
+
+ .op_read (op_read ),
+ .op_write (op_write ),
+ .op_invert (op_invert ),
+ .op_updown (op_updown ),
+ .op_reverse (op_reverse ),
+ .op_repeatflag (op_repeatflag ),
+ .sdo (bist_op_sdo ),
+ .last_op (last_op ),
+
+ .clk (wb_clk_i ),
+ .rst_n (srst_n ),
+ .scan_shift (bist_shift ),
+ .sdi (bist_sti_sdo ),
+ .re_init (bist_error_correct_or ),
+ .run (run_op ),
+ .stimulus (stimulus )
+
+ );
+
+
+
+mbist_pat_sel
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_pat_sel (
+ .pat_last (last_pat ),
+ .pat_data (pat_data ),
+ .sdo (bist_pat_sdo ),
+ .clk (wb_clk_i ),
+ .rst_n (srst_n ),
+ .run (run_pat ),
+ .scan_shift (bist_shift ),
+ .sdi (bist_op_sdo )
+
+ );
+
+
+
+
+
+genvar sram_no;
+generate
+for (sram_no = 0; $unsigned(sram_no) < BIST_NO_SRAM; sram_no=sram_no+1) begin : mem_no
+
+
+mbist_data_cmp
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+
+
+ u_cmp (
+ .error (bist_error[sram_no] ),
+ .error_correct (bist_error_correct[sram_no] ),
+ .correct ( ), // same signal available at bist mux
+ .error_addr (bist_error_addr[sram_no] ),
+ .error_cnt (bist_error_cnt_i[sram_no] ),
+ .clk (wb_clk_i ),
+ .rst_n (srst_n ),
+ .addr_inc_phase (run_addr ),
+ .compare (compare ),
+ .read_invert (op_invert ),
+ .comp_data (pat_data ),
+ .rxd_data (func_dout[sram_no] ),
+ .addr (bist_addr )
+
+ );
+
+ // WB To Memory Signal Mapping
+ mbist_mem_wrapper #(
+ .BIST_NO_SRAM (BIST_NO_SRAM ),
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD )
+ ) u_mem_wrapper_(
+ .rst_n (srst_n ),
+ // WB I/F
+ .sram_id (NO_SRAM_WD'(sram_no) ),
+ .wb_clk_i (wb_clk2_i ), // System clock
+ .mem_cs (mem_cs ), // Chip Select
+ .mem_req (mem_req ), // strobe/request
+ .mem_addr (mem_addr ), // address
+ .mem_we (mem_we ), // write
+ .mem_wdata (mem_wdata ), // data output
+ .mem_wmask (mem_wmask ), // byte enable
+ .mem_rdata (wb_dat[sram_no] ), // data input
+ // MEM A PORT
+ .func_clk (func_clk[sram_no] ),
+ .func_cen (func_cen[sram_no] ),
+ .func_web (func_web[sram_no] ),
+ .func_mask (func_mask[sram_no] ),
+ .func_addr (func_addr[sram_no] ),
+ .func_din (func_din[sram_no] ),
+ .func_dout (func_dout[sram_no] )
+ );
+
+
+mbist_mux
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_mem_sel (
+
+ .scan_mode (1'b0 ),
+
+ .rst_n (srst_n ),
+ // MBIST CTRL SIGNAL
+ .bist_en (bist_en ),
+ .bist_addr (bist_addr ),
+ .bist_wdata (bist_wdata ),
+ .bist_clk (wb_clk2_i ),
+ .bist_wr (bist_wr ),
+ .bist_rd (bist_rd ),
+ .bist_error (bist_error_correct[sram_no]),
+ .bist_error_addr (bist_error_addr[sram_no] ),
+ .bist_correct (bist_correct[sram_no] ),
+ .bist_sdi (bist_ms_sdi[sram_no] ),
+ .bist_load (bist_load ),
+ .bist_shift (bist_shift ),
+ .bist_sdo (bist_ms_sdo[sram_no] ),
+
+ // FUNCTIONAL CTRL SIGNAL
+ .func_clk (func_clk[sram_no] ),
+ .func_cen (func_cen[sram_no] ),
+ .func_web (func_web[sram_no] ),
+ .func_mask (func_mask[sram_no] ),
+ .func_addr (func_addr[sram_no] ),
+ .func_din (func_din[sram_no] ),
+ .func_dout (func_dout[sram_no] ),
+
+
+ // towards memory
+ // Memory Out Port
+ .mem_clk (mem_clk_a[sram_no] ),
+ .mem_cen (mem_cen_a[sram_no] ),
+ .mem_web (mem_web_a[sram_no] ),
+ .mem_mask (mem_mask_a_i[sram_no] ),
+ .mem_addr (mem_addr_a_i[sram_no] ),
+ .mem_din (mem_din_a_i[sram_no] ),
+ .mem_dout (mem_dout_a_i[sram_no] )
+
+ );
+end
+endgenerate
+
+endmodule
+
diff --git a/verilog/rtl/mbist/src/top/mbist_top1.sv b/verilog/rtl/mbist/src/top/mbist_top1.sv
new file mode 100644
index 0000000..11b7614
--- /dev/null
+++ b/verilog/rtl/mbist/src/top/mbist_top1.sv
@@ -0,0 +1,484 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MBIST TOP ////
+//// ////
+//// This file is part of the mbist_ctrl cores project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block integrate mbist controller with row ////
+//// redendency feature ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 11th Oct 2021, Dinesh A ////
+//// Initial integration ////
+//// 0.1 - 26th Oct 2021, Dinesh A ////
+//// Fixed Error Address are serial shifted through ////
+//// sdi/sdo ////
+//// 0.2 - Feb 18, 2022, Dinesh A ////
+//// Addition SRAM data launch phase selection option ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`include "mbist_def.svh"
+module mbist_top1
+ #( parameter SCW = 8, // SCAN CHAIN WIDTH
+ parameter BIST_ADDR_WD = 9,
+ parameter BIST_DATA_WD = 32,
+ parameter BIST_ADDR_START = 9'h000,
+ parameter BIST_ADDR_END = 9'h1FB,
+ parameter BIST_REPAIR_ADDR_START = 9'h1FC,
+ parameter BIST_RAD_WD_I = BIST_ADDR_WD,
+ parameter BIST_RAD_WD_O = BIST_ADDR_WD) (
+
+`ifdef USE_POWER_PINS
+ inout vccd1, // User area 1 1.8V supply
+ inout vssd1, // User area 1 digital ground
+`endif
+
+ // Scan I/F
+ input logic scan_en,
+ input logic scan_mode,
+ input logic [SCW-1:0] scan_si,
+ output logic [SCW-1:0] scan_so,
+ output logic scan_en_o,
+ output logic scan_mode_o,
+
+ input logic cfg_mem_lphase, // Data Towards SRAM data lanuch phase , 0 -> posedge, 1 -> negedge
+
+ // Clock Skew Adjust
+ input logic wbd_clk_int,
+ output logic wbd_clk_mbist,
+ input logic [3:0] cfg_cska_mbist, // clock skew adjust for web host
+
+ input logic rst_n,
+
+ // MBIST I/F
+ input logic bist_en,
+ input logic bist_run,
+ input logic bist_shift,
+ input logic bist_load,
+ input logic bist_sdi,
+
+ output logic [3:0] bist_error_cnt,
+ output logic bist_correct,
+ output logic bist_error,
+ output logic bist_done,
+ output logic bist_sdo,
+
+
+ // WB I/F
+ input logic wb_clk_i, // System clock
+ input logic wb_cyc_i, // strobe/request
+ input logic wb_stb_i, // strobe/request
+ input logic [BIST_ADDR_WD-1:0] wb_adr_i, // address
+ input logic wb_we_i , // write
+ input logic [BIST_DATA_WD-1:0] wb_dat_i, // data output
+ input logic [BIST_DATA_WD/8-1:0] wb_sel_i, // byte enable
+ output logic [BIST_DATA_WD-1:0] wb_dat_o, // data input
+ output logic wb_ack_o, // acknowlegement
+ output logic wb_err_o, // error
+
+ // towards memory
+ // PORT-A
+ output logic mem_clk_a,
+ output logic [BIST_ADDR_WD-1:0]mem_addr_a,
+ output logic mem_cen_a,
+ output logic [BIST_DATA_WD-1:0]mem_din_b,
+ // PORT-B
+ output logic mem_clk_b,
+ output logic mem_cen_b,
+ output logic mem_web_b,
+ output logic [BIST_DATA_WD/8-1:0]mem_mask_b,
+ output logic [BIST_ADDR_WD-1:0]mem_addr_b,
+ input logic [BIST_DATA_WD-1:0]mem_dout_a
+
+
+
+
+);
+
+// FUNCTIONAL A PORT
+logic func_clk_a;
+logic func_cen_a;
+logic [BIST_ADDR_WD-1:0]func_addr_a;
+logic [BIST_DATA_WD-1:0]func_dout_a;
+
+// Functional B Port
+logic func_clk_b;
+logic func_cen_b;
+logic func_web_b;
+logic [BIST_DATA_WD/8-1:0]func_mask_b;
+logic [BIST_ADDR_WD-1:0]func_addr_b;
+logic [BIST_DATA_WD-1:0]func_din_b;
+//----------------------------------------------------
+// Local variable defination
+// ---------------------------------------------------
+//
+logic srst_n ; // sync reset w.r.t bist_clk
+logic cmd_phase ; // Command Phase
+logic cmp_phase ; // Compare Phase
+logic run_op ; // Run next Operation
+logic run_addr ; // Run Next Address
+logic run_sti ; // Run Next Stimulus
+logic run_pat ; // Run Next Pattern
+logic op_updown ; // Adress updown direction
+logic last_addr ; // last address indication
+logic last_sti ; // last stimulus
+logic last_op ; // last operation
+logic last_pat ; // last pattern
+logic [BIST_DATA_WD-1:0] pat_data ; // Selected Data Pattern
+logic [BIST_STI_WD-1:0] stimulus ; // current stimulus
+logic compare ; // compare data
+logic op_repeatflag;
+logic op_reverse;
+logic op_read ;
+logic op_write ;
+logic op_invert ;
+
+//---------------------------------
+// SDI => SDO diasy chain
+// bist_sdi => bist_addr_sdo => bist_sti_sdo => bist_op_sdo => bist_pat_sdo => bist_sdo
+// ---------------------------------
+logic bist_addr_sdo ;
+logic bist_sti_sdo ;
+logic bist_op_sdo ;
+logic bist_pat_sdo ;
+
+logic bist_error_correct ;
+logic [BIST_ADDR_WD-1:0]bist_error_addr ; // bist address
+
+logic [BIST_ADDR_WD-1:0]bist_addr ; // bist address
+logic [BIST_DATA_WD-1:0] bist_wdata ; // bist write data
+logic bist_wr ;
+logic bist_rd ;
+
+assign scan_en_o = scan_en;
+assign scan_mode_o = scan_mode;
+
+assign bist_wr = (cmd_phase && op_write);
+assign bist_rd = (cmd_phase && op_read);
+
+assign compare = (cmp_phase && op_read);
+assign bist_wdata = (op_invert) ? ~pat_data : pat_data;
+
+// Clock Tree branching to avoid clock latency towards SRAM path
+wire wb_clk_b1,wb_clk_b2;
+ctech_clk_buf u_cts_wb_clk_b1 (.A (wb_clk_i), . X(wb_clk_b1));
+ctech_clk_buf u_cts_wb_clk_b2 (.A (wb_clk_i), . X(wb_clk_b2));
+
+// wb_host clock skew control
+clk_skew_adjust u_skew_mbist
+ (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ .clk_in (wbd_clk_int ),
+ .sel (cfg_cska_mbist ),
+ .clk_out (wbd_clk_mbist )
+ );
+
+reset_sync u_reset_sync (
+ .scan_mode (scan_mode ),
+ .dclk (wb_clk_b1 ), // Destination clock domain
+ .arst_n (rst_n ), // active low async reset
+ .srst_n (srst_n )
+ );
+
+
+
+// bist main control FSM
+
+mbist_fsm
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_fsm (
+
+ .cmd_phase (cmd_phase ),
+ .cmp_phase (cmp_phase ),
+ .run_op (run_op ),
+ .run_addr (run_addr ),
+ .run_sti (run_sti ),
+ .run_pat (run_pat ),
+ .bist_done (bist_done ),
+
+
+ .clk (wb_clk_b1 ),
+ .rst_n (srst_n ),
+ .bist_run (bist_run ),
+ .last_op (last_op ),
+ .last_addr (last_addr ),
+ .last_sti (last_sti ),
+ .last_pat (last_pat ),
+ .op_reverse (op_reverse ),
+ .bist_error (bist_error )
+);
+
+
+// bist address generation
+mbist_addr_gen
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_addr_gen(
+ .last_addr (last_addr ),
+ .bist_addr (bist_addr ),
+ .sdo (bist_addr_sdo ),
+
+ .clk (wb_clk_b1 ),
+ .rst_n (srst_n ),
+ .run (run_addr ),
+ .updown (op_updown ),
+ .scan_shift (bist_shift ),
+ .scan_load (bist_load ),
+ .sdi (bist_sdi )
+
+);
+
+
+// BIST current stimulus selection
+mbist_sti_sel
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_sti_sel(
+
+ .sdo (bist_sti_sdo ),
+ .last_stimulus (last_sti ),
+ .stimulus (stimulus ),
+
+ .clk (wb_clk_b1 ),
+ .rst_n (srst_n ),
+ .scan_shift (bist_shift ),
+ .sdi (bist_addr_sdo ),
+ .run (run_sti )
+
+);
+
+
+// Bist Operation selection
+mbist_op_sel
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_op_sel (
+
+ .op_read (op_read ),
+ .op_write (op_write ),
+ .op_invert (op_invert ),
+ .op_updown (op_updown ),
+ .op_reverse (op_reverse ),
+ .op_repeatflag (op_repeatflag ),
+ .sdo (bist_op_sdo ),
+ .last_op (last_op ),
+
+ .clk (wb_clk_b1 ),
+ .rst_n (srst_n ),
+ .scan_shift (bist_shift ),
+ .sdi (bist_sti_sdo ),
+ .re_init (bist_error_correct ),
+ .run (run_op ),
+ .stimulus (stimulus )
+
+ );
+
+
+
+mbist_pat_sel
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_pat_sel (
+ .pat_last (last_pat ),
+ .pat_data (pat_data ),
+ .sdo (bist_pat_sdo ),
+ .clk (wb_clk_b1 ),
+ .rst_n (srst_n ),
+ .run (run_pat ),
+ .scan_shift (bist_shift ),
+ .sdi (bist_op_sdo )
+
+ );
+
+
+mbist_data_cmp
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+
+
+ u_cmp (
+ .error (bist_error ),
+ .error_correct (bist_error_correct ),
+ .correct ( ), // same signal available at bist mux
+ .error_addr (bist_error_addr ),
+ .error_cnt (bist_error_cnt ),
+ .clk (wb_clk_b1 ),
+ .rst_n (srst_n ),
+ .addr_inc_phase (run_addr ),
+ .compare (compare ),
+ .read_invert (op_invert ),
+ .comp_data (pat_data ),
+ .rxd_data (func_dout_a ),
+ .addr (bist_addr )
+
+ );
+
+
+mbist_mem_wrapper #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD )
+ ) u_mem_wrapper(
+ .rst_n (srst_n ),
+ // WB I/F
+ .wb_clk_i (wb_clk_b2 ), // System clock
+ .wb_cyc_i (wb_cyc_i ), // strobe/request
+ .wb_stb_i (wb_stb_i ), // strobe/request
+ .wb_adr_i (wb_adr_i ), // address
+ .wb_we_i (wb_we_i ), // write
+ .wb_dat_i (wb_dat_i ), // data output
+ .wb_sel_i (wb_sel_i ), // byte enable
+ .wb_dat_o (wb_dat_o ), // data input
+ .wb_ack_o (wb_ack_o ), // acknowlegement
+ .wb_err_o (wb_err_o ), // error
+ // MEM A PORT
+ .func_clk_a (func_clk_a ),
+ .func_cen_a (func_cen_a ),
+ .func_addr_a (func_addr_a ),
+ .func_dout_a (func_dout_a ),
+
+ // Functional B Port
+ .func_clk_b (func_clk_b ),
+ .func_cen_b (func_cen_b ),
+ .func_web_b (func_web_b ),
+ .func_mask_b (func_mask_b ),
+ .func_addr_b (func_addr_b ),
+ .func_din_b (func_din_b )
+ );
+
+
+mbist_mux
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_mem_sel (
+
+ .scan_mode (scan_mode ),
+ .cfg_mem_lphase (cfg_mem_lphase),
+
+ .rst_n (srst_n ),
+ // MBIST CTRL SIGNAL
+ .bist_en (bist_en ),
+ .bist_addr (bist_addr ),
+ .bist_wdata (bist_wdata ),
+ .bist_clk (wb_clk_b2 ),
+ .bist_wr (bist_wr ),
+ .bist_rd (bist_rd ),
+ .bist_error (bist_error_correct),
+ .bist_error_addr (bist_error_addr),
+ .bist_correct (bist_correct ),
+ .bist_sdi (bist_pat_sdo),
+ .bist_shift (bist_shift),
+ .bist_sdo (bist_sdo),
+
+ // FUNCTIONAL CTRL SIGNAL
+ .func_clk_a (func_clk_a ),
+ .func_cen_a (func_cen_a ),
+ .func_addr_a (func_addr_a ),
+ // Common for func and Mbist i/f
+ .func_dout_a (func_dout_a ),
+
+ .func_clk_b (func_clk_b ),
+ .func_cen_b (func_cen_b ),
+ .func_web_b (func_web_b ),
+ .func_mask_b (func_mask_b ),
+ .func_addr_b (func_addr_b ),
+ .func_din_b (func_din_b ),
+
+
+ // towards memory
+ // Memory Out Port
+ .mem_clk_a (mem_clk_a ),
+ .mem_cen_a (mem_cen_a ),
+ .mem_addr_a (mem_addr_a ),
+ .mem_dout_a (mem_dout_a ),
+
+ // Memory Input Port
+ .mem_clk_b (mem_clk_b ),
+ .mem_cen_b (mem_cen_b ),
+ .mem_web_b (mem_web_b ),
+ .mem_mask_b (mem_mask_b ),
+ .mem_addr_b (mem_addr_b ),
+ .mem_din_b (mem_din_b )
+ );
+
+
+endmodule
+
diff --git a/verilog/rtl/mbist/src/top/mbist_top2.sv b/verilog/rtl/mbist/src/top/mbist_top2.sv
new file mode 100644
index 0000000..db832ac
--- /dev/null
+++ b/verilog/rtl/mbist/src/top/mbist_top2.sv
@@ -0,0 +1,484 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MBIST TOP ////
+//// ////
+//// This file is part of the mbist_ctrl cores project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block integrate mbist controller with row ////
+//// redendency feature ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 11th Oct 2021, Dinesh A ////
+//// Initial integration ////
+//// 0.1 - 26th Oct 2021, Dinesh A ////
+//// Fixed Error Address are serial shifted through ////
+//// sdi/sdo ////
+//// 0.2 - Feb 18, 2022, Dinesh A ////
+//// Addition SRAM data launch phase selection option ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`include "mbist_def.svh"
+module mbist_top2
+ #( parameter SCW = 8, // SCAN CHAIN WIDTH
+ parameter BIST_ADDR_WD = 8,
+ parameter BIST_DATA_WD = 32,
+ parameter BIST_ADDR_START = 8'h00,
+ parameter BIST_ADDR_END = 8'hFB,
+ parameter BIST_REPAIR_ADDR_START = 8'hFC,
+ parameter BIST_RAD_WD_I = BIST_ADDR_WD,
+ parameter BIST_RAD_WD_O = BIST_ADDR_WD) (
+
+`ifdef USE_POWER_PINS
+ inout vccd1, // User area 1 1.8V supply
+ inout vssd1, // User area 1 digital ground
+`endif
+
+ // Scan I/F
+ input logic scan_en,
+ input logic scan_mode,
+ input logic [SCW-1:0] scan_si,
+ output logic [SCW-1:0] scan_so,
+ output logic scan_en_o,
+ output logic scan_mode_o,
+
+ input logic cfg_mem_lphase, // Data Towards SRAM data lanuch phase , 0 -> posedge, 1 -> negedge
+
+ // Clock Skew Adjust
+ input logic wbd_clk_int,
+ output logic wbd_clk_mbist,
+ input logic [3:0] cfg_cska_mbist, // clock skew adjust for web host
+
+ input logic rst_n,
+
+ // MBIST I/F
+ input logic bist_en,
+ input logic bist_run,
+ input logic bist_shift,
+ input logic bist_load,
+ input logic bist_sdi,
+
+ output logic [3:0] bist_error_cnt,
+ output logic bist_correct,
+ output logic bist_error,
+ output logic bist_done,
+ output logic bist_sdo,
+
+
+ // WB I/F
+ input logic wb_clk_i, // System clock
+ input logic wb_cyc_i, // strobe/request
+ input logic wb_stb_i, // strobe/request
+ input logic [BIST_ADDR_WD-1:0] wb_adr_i, // address
+ input logic wb_we_i , // write
+ input logic [BIST_DATA_WD-1:0] wb_dat_i, // data output
+ input logic [BIST_DATA_WD/8-1:0] wb_sel_i, // byte enable
+ output logic [BIST_DATA_WD-1:0] wb_dat_o, // data input
+ output logic wb_ack_o, // acknowlegement
+ output logic wb_err_o, // error
+
+ // towards memory
+ // PORT-A
+ output logic mem_clk_a,
+ output logic [BIST_ADDR_WD-1:0]mem_addr_a,
+ output logic mem_cen_a,
+ output logic [BIST_DATA_WD-1:0]mem_din_b,
+ // PORT-B
+ output logic mem_clk_b,
+ output logic mem_cen_b,
+ output logic mem_web_b,
+ output logic [BIST_DATA_WD/8-1:0]mem_mask_b,
+ output logic [BIST_ADDR_WD-1:0]mem_addr_b,
+ input logic [BIST_DATA_WD-1:0]mem_dout_a
+
+
+
+
+);
+
+// FUNCTIONAL A PORT
+logic func_clk_a;
+logic func_cen_a;
+logic [BIST_ADDR_WD-1:0]func_addr_a;
+logic [BIST_DATA_WD-1:0]func_dout_a;
+
+// Functional B Port
+logic func_clk_b;
+logic func_cen_b;
+logic func_web_b;
+logic [BIST_DATA_WD/8-1:0]func_mask_b;
+logic [BIST_ADDR_WD-1:0]func_addr_b;
+logic [BIST_DATA_WD-1:0]func_din_b;
+//----------------------------------------------------
+// Local variable defination
+// ---------------------------------------------------
+//
+logic srst_n ; // sync reset w.r.t bist_clk
+logic cmd_phase ; // Command Phase
+logic cmp_phase ; // Compare Phase
+logic run_op ; // Run next Operation
+logic run_addr ; // Run Next Address
+logic run_sti ; // Run Next Stimulus
+logic run_pat ; // Run Next Pattern
+logic op_updown ; // Adress updown direction
+logic last_addr ; // last address indication
+logic last_sti ; // last stimulus
+logic last_op ; // last operation
+logic last_pat ; // last pattern
+logic [BIST_DATA_WD-1:0] pat_data ; // Selected Data Pattern
+logic [BIST_STI_WD-1:0] stimulus ; // current stimulus
+logic compare ; // compare data
+logic op_repeatflag;
+logic op_reverse;
+logic op_read ;
+logic op_write ;
+logic op_invert ;
+
+//---------------------------------
+// SDI => SDO diasy chain
+// bist_sdi => bist_addr_sdo => bist_sti_sdo => bist_op_sdo => bist_pat_sdo => bist_sdo
+// ---------------------------------
+logic bist_addr_sdo ;
+logic bist_sti_sdo ;
+logic bist_op_sdo ;
+logic bist_pat_sdo ;
+
+logic bist_error_correct ;
+logic [BIST_ADDR_WD-1:0]bist_error_addr ; // bist address
+
+logic [BIST_ADDR_WD-1:0]bist_addr ; // bist address
+logic [BIST_DATA_WD-1:0] bist_wdata ; // bist write data
+logic bist_wr ;
+logic bist_rd ;
+
+assign scan_en_o = scan_en;
+assign scan_mode_o = scan_mode;
+
+assign bist_wr = (cmd_phase && op_write);
+assign bist_rd = (cmd_phase && op_read);
+
+assign compare = (cmp_phase && op_read);
+assign bist_wdata = (op_invert) ? ~pat_data : pat_data;
+
+// Clock Tree branching to avoid clock latency towards SRAM path
+wire wb_clk_b1,wb_clk_b2;
+ctech_clk_buf u_cts_wb_clk_b1 (.A (wb_clk_i), . X(wb_clk_b1));
+ctech_clk_buf u_cts_wb_clk_b2 (.A (wb_clk_i), . X(wb_clk_b2));
+
+// wb_host clock skew control
+clk_skew_adjust u_skew_mbist
+ (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ .clk_in (wbd_clk_int ),
+ .sel (cfg_cska_mbist ),
+ .clk_out (wbd_clk_mbist )
+ );
+
+reset_sync u_reset_sync (
+ .scan_mode (scan_mode ),
+ .dclk (wb_clk_b1 ), // Destination clock domain
+ .arst_n (rst_n ), // active low async reset
+ .srst_n (srst_n )
+ );
+
+
+
+// bist main control FSM
+
+mbist_fsm
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_fsm (
+
+ .cmd_phase (cmd_phase ),
+ .cmp_phase (cmp_phase ),
+ .run_op (run_op ),
+ .run_addr (run_addr ),
+ .run_sti (run_sti ),
+ .run_pat (run_pat ),
+ .bist_done (bist_done ),
+
+
+ .clk (wb_clk_b1 ),
+ .rst_n (srst_n ),
+ .bist_run (bist_run ),
+ .last_op (last_op ),
+ .last_addr (last_addr ),
+ .last_sti (last_sti ),
+ .last_pat (last_pat ),
+ .op_reverse (op_reverse ),
+ .bist_error (bist_error )
+);
+
+
+// bist address generation
+mbist_addr_gen
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_addr_gen(
+ .last_addr (last_addr ),
+ .bist_addr (bist_addr ),
+ .sdo (bist_addr_sdo ),
+
+ .clk (wb_clk_b1 ),
+ .rst_n (srst_n ),
+ .run (run_addr ),
+ .updown (op_updown ),
+ .scan_shift (bist_shift ),
+ .scan_load (bist_load ),
+ .sdi (bist_sdi )
+
+);
+
+
+// BIST current stimulus selection
+mbist_sti_sel
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_sti_sel(
+
+ .sdo (bist_sti_sdo ),
+ .last_stimulus (last_sti ),
+ .stimulus (stimulus ),
+
+ .clk (wb_clk_b1 ),
+ .rst_n (srst_n ),
+ .scan_shift (bist_shift ),
+ .sdi (bist_addr_sdo ),
+ .run (run_sti )
+
+);
+
+
+// Bist Operation selection
+mbist_op_sel
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_op_sel (
+
+ .op_read (op_read ),
+ .op_write (op_write ),
+ .op_invert (op_invert ),
+ .op_updown (op_updown ),
+ .op_reverse (op_reverse ),
+ .op_repeatflag (op_repeatflag ),
+ .sdo (bist_op_sdo ),
+ .last_op (last_op ),
+
+ .clk (wb_clk_b1 ),
+ .rst_n (srst_n ),
+ .scan_shift (bist_shift ),
+ .sdi (bist_sti_sdo ),
+ .re_init (bist_error_correct ),
+ .run (run_op ),
+ .stimulus (stimulus )
+
+ );
+
+
+
+mbist_pat_sel
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_pat_sel (
+ .pat_last (last_pat ),
+ .pat_data (pat_data ),
+ .sdo (bist_pat_sdo ),
+ .clk (wb_clk_b1 ),
+ .rst_n (srst_n ),
+ .run (run_pat ),
+ .scan_shift (bist_shift ),
+ .sdi (bist_op_sdo )
+
+ );
+
+
+mbist_data_cmp
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+
+
+ u_cmp (
+ .error (bist_error ),
+ .error_correct (bist_error_correct ),
+ .correct ( ), // same signal available at bist mux
+ .error_addr (bist_error_addr ),
+ .error_cnt (bist_error_cnt ),
+ .clk (wb_clk_b1 ),
+ .rst_n (srst_n ),
+ .addr_inc_phase (run_addr ),
+ .compare (compare ),
+ .read_invert (op_invert ),
+ .comp_data (pat_data ),
+ .rxd_data (func_dout_a ),
+ .addr (bist_addr )
+
+ );
+
+
+mbist_mem_wrapper #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD )
+ ) u_mem_wrapper(
+ .rst_n (srst_n ),
+ // WB I/F
+ .wb_clk_i (wb_clk_b2 ), // System clock
+ .wb_cyc_i (wb_cyc_i ), // strobe/request
+ .wb_stb_i (wb_stb_i ), // strobe/request
+ .wb_adr_i (wb_adr_i ), // address
+ .wb_we_i (wb_we_i ), // write
+ .wb_dat_i (wb_dat_i ), // data output
+ .wb_sel_i (wb_sel_i ), // byte enable
+ .wb_dat_o (wb_dat_o ), // data input
+ .wb_ack_o (wb_ack_o ), // acknowlegement
+ .wb_err_o (wb_err_o ), // error
+ // MEM A PORT
+ .func_clk_a (func_clk_a ),
+ .func_cen_a (func_cen_a ),
+ .func_addr_a (func_addr_a ),
+ .func_dout_a (func_dout_a ),
+
+ // Functional B Port
+ .func_clk_b (func_clk_b ),
+ .func_cen_b (func_cen_b ),
+ .func_web_b (func_web_b ),
+ .func_mask_b (func_mask_b ),
+ .func_addr_b (func_addr_b ),
+ .func_din_b (func_din_b )
+ );
+
+
+mbist_mux
+ #(
+ .BIST_ADDR_WD (BIST_ADDR_WD ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (BIST_ADDR_START ),
+ .BIST_ADDR_END (BIST_ADDR_END ),
+ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ),
+ .BIST_RAD_WD_I (BIST_RAD_WD_I ),
+ .BIST_RAD_WD_O (BIST_RAD_WD_O )
+ )
+ u_mem_sel (
+
+ .scan_mode (scan_mode ),
+ .cfg_mem_lphase (cfg_mem_lphase),
+
+ .rst_n (srst_n ),
+ // MBIST CTRL SIGNAL
+ .bist_en (bist_en ),
+ .bist_addr (bist_addr ),
+ .bist_wdata (bist_wdata ),
+ .bist_clk (wb_clk_b2 ),
+ .bist_wr (bist_wr ),
+ .bist_rd (bist_rd ),
+ .bist_error (bist_error_correct),
+ .bist_error_addr (bist_error_addr),
+ .bist_correct (bist_correct ),
+ .bist_sdi (bist_pat_sdo),
+ .bist_shift (bist_shift),
+ .bist_sdo (bist_sdo),
+
+ // FUNCTIONAL CTRL SIGNAL
+ .func_clk_a (func_clk_a ),
+ .func_cen_a (func_cen_a ),
+ .func_addr_a (func_addr_a ),
+ // Common for func and Mbist i/f
+ .func_dout_a (func_dout_a ),
+
+ .func_clk_b (func_clk_b ),
+ .func_cen_b (func_cen_b ),
+ .func_web_b (func_web_b ),
+ .func_mask_b (func_mask_b ),
+ .func_addr_b (func_addr_b ),
+ .func_din_b (func_din_b ),
+
+
+ // towards memory
+ // Memory Out Port
+ .mem_clk_a (mem_clk_a ),
+ .mem_cen_a (mem_cen_a ),
+ .mem_addr_a (mem_addr_a ),
+ .mem_dout_a (mem_dout_a ),
+
+ // Memory Input Port
+ .mem_clk_b (mem_clk_b ),
+ .mem_cen_b (mem_cen_b ),
+ .mem_web_b (mem_web_b ),
+ .mem_mask_b (mem_mask_b ),
+ .mem_addr_b (mem_addr_b ),
+ .mem_din_b (mem_din_b )
+ );
+
+
+endmodule
+
diff --git a/verilog/rtl/mbist_wrapper/src/mbist_wb.sv b/verilog/rtl/mbist_wrapper/src/mbist_wb.sv
new file mode 100644
index 0000000..ef989dd
--- /dev/null
+++ b/verilog/rtl/mbist_wrapper/src/mbist_wb.sv
@@ -0,0 +1,179 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//
+// MBIST wishbone Burst access to SRAM Write and Read access
+// Note: BUSRT crossing the SRAM boundary is not supported due to sram
+// 2 cycle pipe line delay
+//////////////////////////////////////////////////////////////////////
+
+module mbist_wb
+ #(
+ parameter BIST_NO_SRAM = 4,
+ parameter BIST_ADDR_WD = 9,
+ parameter BIST_DATA_WD = 32) (
+
+`ifdef USE_POWER_PINS
+ inout vccd1, // User area 1 1.8V supply
+ inout vssd1, // User area 1 digital ground
+`endif
+
+
+ input logic rst_n,
+
+
+ // WB I/F
+ input logic wb_clk_i, // System clock
+ input logic wb_stb_i, // strobe/request
+ input logic [BIST_ADDR_WD-1:0] wb_adr_i, // address
+ input logic [(BIST_NO_SRAM+1)/2-1:0] wb_cs_i, // address
+ input logic wb_we_i , // write
+ input logic [BIST_DATA_WD-1:0] wb_dat_i, // data output
+ input logic [BIST_DATA_WD/8-1:0] wb_sel_i, // byte enable
+ input logic [9:0] wb_bl_i, // Burst Length
+ input logic wb_bry_i, // Burst Ready
+ output logic [BIST_DATA_WD-1:0] wb_dat_o, // data input
+ output logic wb_ack_o, // acknowlegement
+ output logic wb_lack_o, // acknowlegement
+ output logic wb_err_o, // error
+
+ output logic mem_req,
+ output logic [(BIST_NO_SRAM+1)/2-1:0] mem_cs,
+ output logic [BIST_ADDR_WD-1:0] mem_addr,
+ output logic [31:0] mem_wdata,
+ output logic mem_we,
+ output logic [3:0] mem_wmask,
+ input logic [31:0] mem_rdata
+
+
+
+
+);
+
+parameter IDLE = 2'b00;
+parameter WRITE_ACTION = 2'b01;
+parameter READ_ACTION1 = 2'b10;
+parameter READ_ACTION2 = 2'b11;
+
+
+logic [9:0] mem_bl_cnt ;
+logic wb_ack_l ;
+logic [BIST_ADDR_WD-1:0] mem_next_addr;
+logic [1:0] state;
+logic mem_hval; // Mem Hold Data valid
+logic [31:0] mem_hdata; // Mem Hold Data
+
+
+assign mem_wdata = wb_dat_i;
+
+always @(negedge rst_n, posedge wb_clk_i) begin
+ if (~rst_n) begin
+ mem_bl_cnt <= 'h0;
+ mem_addr <= 'h0;
+ mem_next_addr <= 'h0;
+ wb_ack_l <= 'b0;
+ wb_dat_o <= 'h0;
+ mem_req <= 'b0;
+ mem_cs <= 'b0;
+ mem_wmask <= 'h0;
+ mem_we <= 'h0;
+ mem_hval <= 'b0;
+ mem_hdata <= 'h0;
+ state <= IDLE;
+ end else begin
+ case(state)
+ IDLE: begin
+ mem_bl_cnt <= 'h1;
+ wb_ack_o <= 'b0;
+ wb_lack_o <= 'b0;
+ if(wb_stb_i && wb_bry_i && ~wb_we_i && !wb_lack_o) begin
+ mem_cs <= wb_cs_i;
+ mem_addr <= wb_adr_i;
+ mem_req <= 'b1;
+ mem_we <= 'b0;
+ state <= READ_ACTION1;
+ end else if(wb_stb_i && wb_bry_i && wb_we_i && !wb_lack_o) begin
+ mem_cs <= wb_cs_i;
+ mem_next_addr<= wb_adr_i;
+ mem_we <= 'b1;
+ mem_wmask <= wb_sel_i;
+ state <= WRITE_ACTION;
+ end else begin
+ mem_req <= 1'b0;
+ end
+ end
+
+ WRITE_ACTION: begin
+ if (wb_stb_i && wb_bry_i ) begin
+ wb_ack_o <= 'b1;
+ mem_req <= 1'b1;
+ mem_addr <= mem_next_addr;
+ if((wb_stb_i && wb_bry_i ) && (wb_bl_i == mem_bl_cnt)) begin
+ wb_lack_o <= 'b1;
+ state <= IDLE;
+ end else begin
+ mem_bl_cnt <= mem_bl_cnt+1;
+ mem_next_addr<= mem_next_addr+1;
+ end
+ end else begin
+ wb_ack_o <= 'b0;
+ mem_req <= 1'b0;
+ end
+ end
+ READ_ACTION1: begin
+ mem_addr <= mem_addr +1;
+ mem_hval <= 1'b0;
+ wb_ack_l <= 'b1;
+ mem_bl_cnt <= 'h1;
+ state <= READ_ACTION2;
+ end
+
+ // Wait for Ack from application layer
+ READ_ACTION2: begin
+ // If the not the last ack, update memory pointer
+ // accordingly
+ wb_ack_l <= wb_ack_o;
+ if (wb_stb_i && wb_bry_i ) begin
+ wb_ack_o <= 1'b1;
+ mem_bl_cnt <= mem_bl_cnt+1;
+ mem_addr <= mem_addr +1;
+ if(wb_ack_l || wb_ack_o ) begin // If back to back ack
+ wb_dat_o <= mem_rdata;
+ mem_hval <= 1'b0;
+ end else begin // Pick from previous holding data
+ mem_hval <= 1'b1;
+ wb_dat_o <= mem_hdata;
+ mem_hdata <= mem_rdata;
+ end
+ if((wb_stb_i && wb_bry_i ) && (wb_bl_i == mem_bl_cnt)) begin
+ wb_lack_o <= 1'b1;
+ state <= IDLE;
+ end
+ end else begin
+ wb_ack_o <= 1'b0;
+ if(!mem_hval) begin
+ mem_hdata <= mem_rdata;
+ mem_hval <= 1'b1;
+ end
+ end
+ end
+ endcase
+ end
+end
+
+endmodule
diff --git a/verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv b/verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv
new file mode 100644
index 0000000..07c5ce3
--- /dev/null
+++ b/verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv
@@ -0,0 +1,369 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MBIST TOP ////
+//// ////
+//// This file is part of the mbist_ctrl cores project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block integrate mbist controller with row ////
+//// redendency feature ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.0 - 11th Oct 2021, Dinesh A ////
+//// Initial integration ////
+//// 0.1 - 26th Oct 2021, Dinesh A ////
+//// Fixed Error Address are serial shifted through ////
+//// sdi/sdo ////
+//// 0.2 - 15 Dec 2021, Dinesh A ////
+//// Added support for common MBIST for 4 SRAM ////
+//// 0.3 - 29th Dec 2021, Dinesh A ////
+//// yosys synthesis issue for two dimension variable ////
+//// changed the variable defination from logic to wire ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`include "mbist_def.svh"
+module mbist_wrapper
+ #(
+ parameter BIST_NO_SRAM = 4,
+ parameter BIST_ADDR_WD = 9,
+ parameter BIST_DATA_WD = 32,
+ parameter BIST_ADDR_START = 9'h000,
+ parameter BIST_ADDR_END = 9'h1FB,
+ parameter BIST_REPAIR_ADDR_START = 9'h1FC,
+ parameter BIST_RAD_WD_I = BIST_ADDR_WD,
+ parameter BIST_RAD_WD_O = BIST_ADDR_WD) (
+
+`ifdef USE_POWER_PINS
+ inout vccd1, // User area 1 1.8V supply
+ inout vssd1, // User area 1 digital ground
+`endif
+
+ // Clock Skew Adjust
+ input wire wbd_clk_int,
+ output wire wbd_clk_mbist,
+ input wire [3:0] cfg_cska_mbist, // clock skew adjust for web host
+
+ input logic rst_n,
+
+ // MBIST I/F
+ input wire bist_en,
+ input wire bist_run,
+ input wire bist_shift,
+ input wire bist_load,
+ input wire bist_sdi,
+
+ output wire [3:0] bist_error_cnt0,
+ output wire [3:0] bist_error_cnt1,
+ output wire [3:0] bist_error_cnt2,
+ output wire [3:0] bist_error_cnt3,
+ output wire [BIST_NO_SRAM-1:0] bist_correct ,
+ output wire [BIST_NO_SRAM-1:0] bist_error ,
+ output wire bist_done,
+ output wire bist_sdo,
+
+
+ // WB I/F
+ input wire wb_clk_i, // System clock
+ input wire wb_clk2_i, // System clock2 is no cts
+ input wire wb_stb_i, // strobe/request
+ input wire [(BIST_NO_SRAM+1)/2-1:0] wb_cs_i,
+ input wire [BIST_ADDR_WD-1:0] wb_adr_i, // address
+ input wire wb_we_i , // write
+ input wire [BIST_DATA_WD-1:0] wb_dat_i, // data output
+ input wire [BIST_DATA_WD/8-1:0] wb_sel_i, // byte enable
+ input wire [9:0] wb_bl_i, // burst
+ input wire wb_bry_i, // burst ready
+ output wire [BIST_DATA_WD-1:0] wb_dat_o, // data input
+ output wire wb_ack_o, // acknowlegement
+ output wire wb_lack_o, // acknowlegement
+ output wire wb_err_o, // error
+
+
+ // towards memory
+ // PORT-A
+ output wire [BIST_NO_SRAM-1:0] mem_clk_a,
+ output wire [BIST_ADDR_WD-1:0] mem_addr_a0,
+ output wire [BIST_ADDR_WD-1:0] mem_addr_a1,
+ output wire [BIST_ADDR_WD-1:0] mem_addr_a2,
+ output wire [BIST_ADDR_WD-1:0] mem_addr_a3,
+ output wire [BIST_NO_SRAM-1:0] mem_cen_a,
+ output wire [BIST_NO_SRAM-1:0] mem_web_a,
+ output wire [BIST_DATA_WD/8-1:0] mem_mask_a0,
+ output wire [BIST_DATA_WD/8-1:0] mem_mask_a1,
+ output wire [BIST_DATA_WD/8-1:0] mem_mask_a2,
+ output wire [BIST_DATA_WD/8-1:0] mem_mask_a3,
+ output wire [BIST_DATA_WD-1:0] mem_din_a0,
+ output wire [BIST_DATA_WD-1:0] mem_din_a1,
+ output wire [BIST_DATA_WD-1:0] mem_din_a2,
+ output wire [BIST_DATA_WD-1:0] mem_din_a3,
+
+ input wire [BIST_DATA_WD-1:0] mem_dout_a0,
+ input wire [BIST_DATA_WD-1:0] mem_dout_a1,
+ input wire [BIST_DATA_WD-1:0] mem_dout_a2,
+ input wire [BIST_DATA_WD-1:0] mem_dout_a3,
+
+
+ // PORT-B
+ output wire [BIST_NO_SRAM-1:0] mem_clk_b,
+ output wire [BIST_NO_SRAM-1:0] mem_cen_b,
+ output wire [BIST_ADDR_WD-1:0] mem_addr_b0,
+ output wire [BIST_ADDR_WD-1:0] mem_addr_b1,
+ output wire [BIST_ADDR_WD-1:0] mem_addr_b2,
+ output wire [BIST_ADDR_WD-1:0] mem_addr_b3
+
+
+
+);
+
+parameter NO_SRAM_WD = (BIST_NO_SRAM+1)/2;
+parameter BIST1_ADDR_WD = 11; // 512x32 SRAM
+
+logic mem_req; // strobe/request
+logic [(BIST_NO_SRAM+1)/2-1:0] mem_cs;
+logic [BIST_ADDR_WD-1:0] mem_addr; // address
+logic mem_we ; // write
+logic [BIST_DATA_WD-1:0] mem_wdata; // data output
+logic [BIST_DATA_WD/8-1:0] mem_wmask; // byte enable
+logic [BIST_DATA_WD-1:0] mem_rdata; // data input
+
+
+mbist_wb #(
+ .BIST_NO_SRAM (4 ),
+ .BIST_ADDR_WD (BIST1_ADDR_WD-2 ),
+ .BIST_DATA_WD (BIST_DATA_WD )
+ )
+ u_wb (
+
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+
+ .rst_n (rst_n ),
+ // WB I/F
+ .wb_clk_i (wb_clk_i ),
+ .wb_stb_i (wb_stb_i ),
+ .wb_cs_i (wb_cs_i ),
+ .wb_adr_i (wb_adr_i ),
+ .wb_we_i (wb_we_i ),
+ .wb_dat_i (wb_dat_i ),
+ .wb_sel_i (wb_sel_i ),
+ .wb_bl_i (wb_bl_i ),
+ .wb_bry_i (wb_bry_i ),
+ .wb_dat_o (wb_dat_o ),
+ .wb_ack_o (wb_ack_o ),
+ .wb_lack_o (wb_lack_o ),
+ .wb_err_o ( ),
+
+ .mem_req (mem_req ),
+ .mem_cs (mem_cs ),
+ .mem_addr (mem_addr ),
+ .mem_we (mem_we ),
+ .mem_wdata (mem_wdata ),
+ .mem_wmask (mem_wmask ),
+ .mem_rdata (mem_rdata )
+
+
+
+
+);
+
+
+mbist_top #(
+ `ifndef SYNTHESIS
+ .BIST_NO_SRAM (4 ),
+ .BIST_ADDR_WD (BIST1_ADDR_WD-2 ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (9'h000 ),
+ .BIST_ADDR_END (9'h1FB ),
+ .BIST_REPAIR_ADDR_START (9'h1FC ),
+ .BIST_RAD_WD_I (BIST1_ADDR_WD-2 ),
+ .BIST_RAD_WD_O (BIST1_ADDR_WD-2 )
+ `endif
+ )
+ u_mbist (
+
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+
+ // Clock Skew adjust
+ .wbd_clk_int (wbd_clk_int ),
+ .cfg_cska_mbist (cfg_cska_mbist ),
+ .wbd_clk_mbist (wbd_clk_mbist ),
+
+ // WB I/F
+ .wb_clk2_i (wb_clk2_i ),
+ .wb_clk_i (wb_clk_i ),
+ .mem_req (mem_req ),
+ .mem_cs (mem_cs ),
+ .mem_addr (mem_addr ),
+ .mem_we (mem_we ),
+ .mem_wdata (mem_wdata ),
+ .mem_wmask (mem_wmask ),
+ .mem_rdata (mem_rdata ),
+
+ .rst_n (rst_n ),
+
+
+ .bist_en (bist_en ),
+ .bist_run (bist_run ),
+ .bist_shift (bist_shift ),
+ .bist_load (bist_load ),
+ .bist_sdi (bist_sdi ),
+
+ .bist_error_cnt3 (bist_error_cnt3 ),
+ .bist_error_cnt2 (bist_error_cnt2 ),
+ .bist_error_cnt1 (bist_error_cnt1 ),
+ .bist_error_cnt0 (bist_error_cnt0 ),
+ .bist_correct (bist_correct ),
+ .bist_error (bist_error ),
+ .bist_done (bist_done ),
+ .bist_sdo (bist_sdo ),
+
+ // towards memory
+ // PORT-A
+ .mem_clk_a (mem_clk_a ),
+ .mem_addr_a0 (mem_addr_a0 ),
+ .mem_addr_a1 (mem_addr_a1 ),
+ .mem_addr_a2 (mem_addr_a2 ),
+ .mem_addr_a3 (mem_addr_a3 ),
+ .mem_cen_a (mem_cen_a ),
+ .mem_web_a (mem_web_a ),
+ .mem_mask_a0 (mem_mask_a0 ),
+ .mem_mask_a1 (mem_mask_a1 ),
+ .mem_mask_a2 (mem_mask_a2 ),
+ .mem_mask_a3 (mem_mask_a3 ),
+ .mem_din_a0 (mem_din_a0 ),
+ .mem_din_a1 (mem_din_a1 ),
+ .mem_din_a2 (mem_din_a2 ),
+ .mem_din_a3 (mem_din_a3 ),
+ .mem_dout_a0 (mem_dout_a0 ),
+ .mem_dout_a1 (mem_dout_a1 ),
+ .mem_dout_a2 (mem_dout_a2 ),
+ .mem_dout_a3 (mem_dout_a3 ),
+ // PORT-B
+ .mem_clk_b (mem_clk_b ),
+ .mem_cen_b (mem_cen_b ),
+ .mem_addr_b0 (mem_addr_b0 ),
+ .mem_addr_b1 (mem_addr_b1 ),
+ .mem_addr_b2 (mem_addr_b2 ),
+ .mem_addr_b3 (mem_addr_b3 )
+
+
+);
+
+
+/**
+sky130_sram_2kbyte_1rw1r_32x512_8 u_sram0_2kb(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1),// User area 1 1.8V supply
+ .vssd1 (vssd1),// User area 1 digital ground
+`endif
+// Port 0: RW
+ .clk0 (mem_clk_a[0]),
+ .csb0 (mem_cen_a[0]),
+ .web0 (mem_web_a[0]),
+ .wmask0 (mem0_mask_a),
+ .addr0 (mem0_addr_a),
+ .din0 (mem0_din_a),
+ .dout0 (mem0_dout_a),
+// Port 1: R
+ .clk1 (mem_clk_b[0]),
+ .csb1 (mem_cen_b[0]),
+ .addr1 (mem0_addr_b),
+ .dout1 ()
+ );
+
+sky130_sram_2kbyte_1rw1r_32x512_8 u_sram1_2kb(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1),// User area 1 1.8V supply
+ .vssd1 (vssd1),// User area 1 digital ground
+`endif
+// Port 0: RW
+ .clk0 (mem_clk_a[1]),
+ .csb0 (mem_cen_a[1]),
+ .web0 (mem_web_a[1]),
+ .wmask0 (mem1_mask_a),
+ .addr0 (mem1_addr_a),
+ .din0 (mem1_din_a),
+ .dout0 (mem1_dout_a),
+// Port 1: R
+ .clk1 (mem_clk_b[1]),
+ .csb1 (mem_cen_b[1]),
+ .addr1 (mem1_addr_b),
+ .dout1 ()
+ );
+
+sky130_sram_2kbyte_1rw1r_32x512_8 u_sram2_2kb(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1),// User area 1 1.8V supply
+ .vssd1 (vssd1),// User area 1 digital ground
+`endif
+// Port 0: RW
+ .clk0 (mem_clk_a[2]),
+ .csb0 (mem_cen_a[2]),
+ .web0 (mem_web_a[2]),
+ .wmask0 (mem2_mask_a),
+ .addr0 (mem2_addr_a),
+ .din0 (mem2_din_a),
+ .dout0 (mem2_dout_a),
+// Port 1: R
+ .clk1 (mem_clk_b[2]),
+ .csb1 (mem_cen_b[2]),
+ .addr1 (mem2_addr_b),
+ .dout1 ()
+ );
+
+
+sky130_sram_2kbyte_1rw1r_32x512_8 u_sram3_2kb(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1),// User area 1 1.8V supply
+ .vssd1 (vssd1),// User area 1 digital ground
+`endif
+// Port 0: RW
+ .clk0 (mem_clk_a[3]),
+ .csb0 (mem_cen_a[3]),
+ .web0 (mem_web_a[3]),
+ .wmask0 (mem3_mask_a),
+ .addr0 (mem3_addr_a),
+ .din0 (mem3_din_a),
+ .dout0 (mem3_dout_a),
+// Port 1: R
+ .clk1 (mem_clk_b[3]),
+ .csb1 (mem_cen_b[3]),
+ .addr1 (mem3_addr_b),
+ .dout1 ()
+ );
+
+
+***/
+
+endmodule
+
diff --git a/verilog/rtl/uart/src/uart_cfg.sv b/verilog/rtl/uart/src/uart_cfg.sv
new file mode 100644
index 0000000..ca4dea6
--- /dev/null
+++ b/verilog/rtl/uart/src/uart_cfg.sv
@@ -0,0 +1,405 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// UART Configuration ////
+//// ////
+//// This file is part of the YIFive cores project ////
+//// https://github.com/dineshannayya/yifive_r0.git ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 20th June 2021, Dinesh A ////
+//// 1. initial version picked from ////
+//// http://www.opencores.org/cores/oms8051mini ////
+//// 0.2 - 20th June 2021, Dinesh A ////
+//// tx and rx buffer status added into reg7 and reg8 ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module uart_cfg (
+
+ mclk,
+ reset_n,
+
+ // Reg Bus Interface Signal
+ reg_cs,
+ reg_wr,
+ reg_addr,
+ reg_wdata,
+ reg_be,
+
+ // Outputs
+ reg_rdata,
+ reg_ack,
+
+ // Uart Tx fifo interface
+ tx_fifo_full,
+ tx_fifo_fspace,
+ tx_fifo_wr_en,
+ tx_fifo_data,
+
+ // Uart Rx fifo interface
+ rx_fifo_empty,
+ rx_fifo_dval ,
+ rx_fifo_rd_en,
+ rx_fifo_data ,
+
+ // configuration
+ cfg_tx_enable,
+ cfg_rx_enable,
+ cfg_stop_bit ,
+ cfg_pri_mod ,
+ cfg_baud_16x ,
+
+ frm_error_o,
+ par_error_o,
+ rx_fifo_full_err_o
+
+ );
+
+
+
+input mclk;
+input reset_n;
+
+//--------------------------------
+// Uart Tx fifo interface
+//--------------------------------
+input tx_fifo_full;
+input [4:0] tx_fifo_fspace ; // Total Tx fifo Free Space
+output tx_fifo_wr_en;
+output [7:0] tx_fifo_data;
+
+//--------------------------------
+// Uart Rx fifo interface
+//--------------------------------
+input rx_fifo_empty;
+input [4:0] rx_fifo_dval ; // Total Rx fifo Data Available
+output rx_fifo_rd_en;
+input [7:0] rx_fifo_data;
+
+//----------------------------------
+// configuration
+//----------------------------------
+output cfg_tx_enable ; // Tx Enable
+output cfg_rx_enable ; // Rx Enable
+output cfg_stop_bit ; // 0 -> 1 Stop, 1 -> 2 Stop
+output [1:0] cfg_pri_mod ; // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd
+output [11:0] cfg_baud_16x ; // 16x Baud clock config
+
+input frm_error_o ; // framing error
+input par_error_o ; // par error
+input rx_fifo_full_err_o ; // rx fifo full error
+
+//---------------------------------
+// Reg Bus Interface Signal
+//---------------------------------
+input reg_cs ;
+input reg_wr ;
+input [3:0] reg_addr ;
+input [7:0] reg_wdata ;
+input reg_be ;
+
+// Outputs
+output [7:0] reg_rdata ;
+output reg_ack ;
+
+
+
+//-----------------------------------------------------------------------
+// Internal Wire Declarations
+//-----------------------------------------------------------------------
+
+wire sw_rd_en;
+wire sw_wr_en;
+wire [3:0] sw_addr ; // addressing 16 registers
+wire wr_be ;
+
+reg [7:0] reg_rdata ;
+reg reg_ack ;
+
+wire [7:0] reg_0; // Software_Reg_0
+wire [7:0] reg_1; // Software-Reg_1
+wire [7:0] reg_2; // Software-Reg_2
+wire [7:0] reg_3; // Software-Reg_3
+wire [7:0] reg_4; // Software-Reg_4
+wire [7:0] reg_5; // Software-Reg_5
+wire [7:0] reg_6; // Software-Reg_6
+wire [7:0] reg_7; // Software-Reg_7
+wire [7:0] reg_8; // Software-Reg_8
+wire [7:0] reg_9; // Software-Reg_9
+wire [7:0] reg_10; // Software-Reg_10
+wire [7:0] reg_11; // Software-Reg_11
+wire [7:0] reg_12; // Software-Reg_12
+wire [7:0] reg_13; // Software-Reg_13
+wire [7:0] reg_14; // Software-Reg_14
+wire [7:0] reg_15; // Software-Reg_15
+reg [7:0] reg_out;
+
+//-----------------------------------------------------------------------
+// Main code starts here
+//-----------------------------------------------------------------------
+
+//-----------------------------------------------------------------------
+// Internal Logic Starts here
+//-----------------------------------------------------------------------
+ assign sw_addr = reg_addr [3:0];
+ assign sw_rd_en = reg_cs & !reg_wr;
+ assign sw_wr_en = reg_cs & reg_wr;
+ assign wr_be = reg_be;
+
+
+//-----------------------------------------------------------------------
+// Read path mux
+//-----------------------------------------------------------------------
+
+always @ (posedge mclk or negedge reset_n)
+begin : preg_out_Seq
+ if (reset_n == 1'b0)
+ begin
+ reg_rdata [7:0] <= 8'h00;
+ reg_ack <= 1'b0;
+ end
+ else if (sw_rd_en && !reg_ack)
+ begin
+ reg_rdata [7:0] <= reg_out [7:0];
+ reg_ack <= 1'b1;
+ end
+ else if (sw_wr_en && !reg_ack)
+ reg_ack <= 1'b1;
+ else
+ begin
+ reg_ack <= 1'b0;
+ end
+end
+
+
+//-----------------------------------------------------------------------
+// register read enable and write enable decoding logic
+//-----------------------------------------------------------------------
+wire sw_wr_en_0 = sw_wr_en & (sw_addr == 4'h0);
+wire sw_rd_en_0 = sw_rd_en & (sw_addr == 4'h0);
+wire sw_wr_en_1 = sw_wr_en & (sw_addr == 4'h1);
+wire sw_rd_en_1 = sw_rd_en & (sw_addr == 4'h1);
+wire sw_wr_en_2 = sw_wr_en & (sw_addr == 4'h2);
+wire sw_rd_en_2 = sw_rd_en & (sw_addr == 4'h2);
+wire sw_wr_en_3 = sw_wr_en & (sw_addr == 4'h3);
+wire sw_rd_en_3 = sw_rd_en & (sw_addr == 4'h3);
+wire sw_wr_en_4 = sw_wr_en & (sw_addr == 4'h4);
+wire sw_rd_en_4 = sw_rd_en & (sw_addr == 4'h4);
+wire sw_wr_en_5 = sw_wr_en & (sw_addr == 4'h5);
+wire sw_rd_en_5 = sw_rd_en & (sw_addr == 4'h5);
+wire sw_wr_en_6 = sw_wr_en & (sw_addr == 4'h6);
+wire sw_rd_en_6 = sw_rd_en & (sw_addr == 4'h6);
+wire sw_wr_en_7 = sw_wr_en & (sw_addr == 4'h7);
+wire sw_rd_en_7 = sw_rd_en & (sw_addr == 4'h7);
+wire sw_wr_en_8 = sw_wr_en & (sw_addr == 4'h8);
+wire sw_rd_en_8 = sw_rd_en & (sw_addr == 4'h8);
+wire sw_wr_en_9 = sw_wr_en & (sw_addr == 4'h9);
+wire sw_rd_en_9 = sw_rd_en & (sw_addr == 4'h9);
+wire sw_wr_en_10 = sw_wr_en & (sw_addr == 4'hA);
+wire sw_rd_en_10 = sw_rd_en & (sw_addr == 4'hA);
+wire sw_wr_en_11 = sw_wr_en & (sw_addr == 4'hB);
+wire sw_rd_en_11 = sw_rd_en & (sw_addr == 4'hB);
+wire sw_wr_en_12 = sw_wr_en & (sw_addr == 4'hC);
+wire sw_rd_en_12 = sw_rd_en & (sw_addr == 4'hC);
+wire sw_wr_en_13 = sw_wr_en & (sw_addr == 4'hD);
+wire sw_rd_en_13 = sw_rd_en & (sw_addr == 4'hD);
+wire sw_wr_en_14 = sw_wr_en & (sw_addr == 4'hE);
+wire sw_rd_en_14 = sw_rd_en & (sw_addr == 4'hE);
+wire sw_wr_en_15 = sw_wr_en & (sw_addr == 4'hF);
+wire sw_rd_en_15 = sw_rd_en & (sw_addr == 4'hF);
+
+
+always @( *)
+begin : preg_sel_Com
+
+ reg_out [7:0] = 8'd0;
+
+ case (sw_addr [3:0])
+ 4'b0000 : reg_out [7:0] = reg_0 [7:0];
+ 4'b0001 : reg_out [7:0] = reg_1 [7:0];
+ 4'b0010 : reg_out [7:0] = reg_2 [7:0];
+ 4'b0011 : reg_out [7:0] = reg_3 [7:0];
+ 4'b0100 : reg_out [7:0] = reg_4 [7:0];
+ 4'b0101 : reg_out [7:0] = reg_5 [7:0];
+ 4'b0110 : reg_out [7:0] = reg_6 [7:0];
+ 4'b0111 : reg_out [7:0] = reg_7 [7:0];
+ 4'b1000 : reg_out [7:0] = reg_8 [7:0];
+ 4'b1001 : reg_out [7:0] = reg_9 [7:0];
+ 4'b1010 : reg_out [7:0] = reg_10 [7:0];
+ 4'b1011 : reg_out [7:0] = reg_11 [7:0];
+ 4'b1100 : reg_out [7:0] = reg_12 [7:0];
+ 4'b1101 : reg_out [7:0] = reg_13 [7:0];
+ 4'b1110 : reg_out [7:0] = reg_14 [7:0];
+ 4'b1111 : reg_out [7:0] = reg_15 [7:0];
+ endcase
+end
+
+
+
+//-----------------------------------------------------------------------
+// Individual register assignments
+//-----------------------------------------------------------------------
+// Logic for Register 0 : uart Control Register
+//-----------------------------------------------------------------------
+wire [1:0] cfg_pri_mod = reg_0[4:3]; // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd
+wire cfg_stop_bit = reg_0[2]; // 0 -> 1 Stop, 1 -> 2 Stop
+wire cfg_rx_enable = reg_0[1]; // Rx Enable
+wire cfg_tx_enable = reg_0[0]; // Tx Enable
+
+generic_register #(5,0 ) u_uart_ctrl_be0 (
+ .we ({5{sw_wr_en_0 &
+ wr_be }} ),
+ .data_in (reg_wdata[4:0] ),
+ .reset_n (reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (reg_0[4:0] )
+ );
+
+
+assign reg_0[7:5] = 3'h0;
+
+//-----------------------------------------------------------------------
+// Logic for Register 1 : uart interrupt status
+//-----------------------------------------------------------------------
+stat_register u_intr_bit0 (
+ //inputs
+ . clk (mclk ),
+ . reset_n (reset_n ),
+ . cpu_we (sw_wr_en_1 &
+ wr_be ),
+ . cpu_ack (reg_wdata[0] ),
+ . hware_req (frm_error_o ),
+
+ //outputs
+ . data_out (reg_1[0] )
+ );
+
+stat_register u_intr_bit1 (
+ //inputs
+ . clk (mclk ),
+ . reset_n (reset_n ),
+ . cpu_we (sw_wr_en_1 &
+ wr_be ),
+ . cpu_ack (reg_wdata[1] ),
+ . hware_req (par_error_o ),
+
+ //outputs
+ . data_out (reg_1[1] )
+ );
+
+stat_register u_intr_bit2 (
+ //inputs
+ . clk (mclk ),
+ . reset_n (reset_n ),
+ . cpu_we (sw_wr_en_1 &
+ wr_be ),
+ . cpu_ack (reg_wdata[2] ),
+ . hware_req (rx_fifo_full_err_o ),
+
+ //outputs
+ . data_out (reg_1[2] )
+ );
+
+assign reg_1[7:3] = 5'h0;
+
+
+//-----------------------------------------------------------------------
+// Logic for Register 2 : Baud Rate Control
+//-----------------------------------------------------------------------
+wire [11:0] cfg_baud_16x = {reg_3[3:0],reg_2[7:0]};
+
+generic_register #(8,0 ) u_uart_ctrl_reg2 (
+ .we ({8{sw_wr_en_2 &
+ wr_be }} ),
+ .data_in (reg_wdata[7:0] ),
+ .reset_n (reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (reg_2[7:0] )
+ );
+
+generic_register #(4,0 ) u_uart_ctrl_reg3 (
+ .we ({4{sw_wr_en_3 &
+ wr_be }} ),
+ .data_in (reg_wdata[3:0] ),
+ .reset_n (reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (reg_3[3:0] )
+ );
+
+assign reg_3[7:4] = 4'h0;
+
+
+// reg-4 status
+//
+assign reg_4[7:0] = {6'h0,rx_fifo_empty,tx_fifo_full};
+
+// reg_5 is tx_fifo wr
+assign tx_fifo_wr_en = sw_wr_en_5 & reg_ack & !tx_fifo_full;
+assign tx_fifo_data = reg_wdata[7:0];
+
+// reg_6 is rx_fifo read
+// rx_fifo read data
+assign reg_6[7:0] = {rx_fifo_data};
+assign rx_fifo_rd_en = sw_rd_en_6 & reg_ack & !rx_fifo_empty;
+
+assign reg_7[7:0] = {3'h0,tx_fifo_fspace}; // tx fifo free space
+assign reg_8[7:0] = {3'h0,rx_fifo_dval}; // rx fifo data available
+
+endmodule
diff --git a/verilog/rtl/uart/src/uart_core.sv b/verilog/rtl/uart/src/uart_core.sv
new file mode 100644
index 0000000..948cd35
--- /dev/null
+++ b/verilog/rtl/uart/src/uart_core.sv
@@ -0,0 +1,334 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// UART CORE with TX/RX 16 Byte Buffer ////
+//// ////
+//// This file is part of the YIFive cores project ////
+//// https://github.com/dineshannayya/yifive_r0.git ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 20th June 2021, Dinesh A ////
+//// 1. initial version picked from ////
+//// http://www.opencores.org/cores/oms8051mini ////
+//// 0.2 - 25th June 2021, Dinesh A ////
+//// Pad logic moved inside core to avoid combo logic at ////
+//// soc digital core level ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module uart_core
+
+ (
+
+ input logic arst_n , // async reset
+ input logic app_clk ,
+
+ // Reg Bus Interface Signal
+ input logic reg_cs,
+ input logic reg_wr,
+ input logic [3:0] reg_addr,
+ input logic [7:0] reg_wdata,
+ input logic reg_be,
+
+ // Outputs
+ output logic [7:0] reg_rdata,
+ output logic reg_ack,
+
+ // Pad Control
+ input logic rxd,
+ output logic txd
+
+ );
+
+
+
+
+parameter W = 8'd8;
+parameter DP = 8'd16;
+parameter AW = (DP == 2) ? 1 :
+ (DP == 4) ? 2 :
+ (DP == 8) ? 3 :
+ (DP == 16) ? 4 :
+ (DP == 32) ? 5 :
+ (DP == 64) ? 6 :
+ (DP == 128) ? 7 :
+ (DP == 256) ? 8 : 0;
+
+
+
+// Wire Declaration
+wire app_reset_n ;
+wire line_reset_n ;
+
+wire [W-1: 0] tx_fifo_rd_data;
+wire [W-1: 0] rx_fifo_wr_data;
+wire [W-1: 0] app_rxfifo_data;
+wire [W-1: 0] app_txfifo_data;
+wire [1 : 0] error_ind;
+
+// Wire
+wire cfg_tx_enable ; // Tx Enable
+wire cfg_rx_enable ; // Rx Enable
+wire cfg_stop_bit ; // 0 -> 1 Stop, 1 -> 2 Stop
+wire [1:0] cfg_pri_mod ; // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd
+
+wire frm_error_o ; // framing error
+wire par_error_o ; // par error
+wire rx_fifo_full_err_o ; // rx fifo full error
+
+wire [11:0] cfg_baud_16x ; // 16x Baud clock generation
+wire rx_fifo_wr_full ;
+wire tx_fifo_rd_empty ;
+wire tx_fifo_rd ;
+wire app_rxfifo_empty ;
+wire app_rxfifo_rd_en ;
+wire app_tx_fifo_full ;
+wire rx_fifo_wr ;
+wire tx_fifo_wr_en ;
+wire [AW:0] tx_fifo_fspace ; // Total Tx fifo Free Space
+wire [AW:0] rx_fifo_dval ; // Total Rx fifo Data Available
+wire si_ss ;
+
+
+
+uart_cfg u_cfg (
+
+ . mclk (app_clk),
+ . reset_n (app_reset_n),
+
+ // Reg Bus Interface Signal
+ . reg_cs (reg_cs),
+ . reg_wr (reg_wr),
+ . reg_addr (reg_addr),
+ . reg_wdata (reg_wdata),
+ . reg_be (reg_be),
+
+ // Outputs
+ . reg_rdata (reg_rdata),
+ . reg_ack (reg_ack),
+
+
+ // configuration
+ . cfg_tx_enable (cfg_tx_enable),
+ . cfg_rx_enable (cfg_rx_enable),
+ . cfg_stop_bit (cfg_stop_bit),
+ . cfg_pri_mod (cfg_pri_mod),
+
+ . cfg_baud_16x (cfg_baud_16x),
+
+ . tx_fifo_full (app_tx_fifo_full),
+ .tx_fifo_fspace (tx_fifo_fspace ),
+ . tx_fifo_wr_en (tx_fifo_wr_en),
+ . tx_fifo_data (app_txfifo_data),
+
+ . rx_fifo_empty (app_rxfifo_empty),
+ .rx_fifo_dval (rx_fifo_dval ),
+ . rx_fifo_rd_en (app_rxfifo_rd_en),
+ . rx_fifo_data (app_rxfifo_data) ,
+
+ . frm_error_o (frm_error_o),
+ . par_error_o (par_error_o),
+ . rx_fifo_full_err_o (rx_fifo_full_err_o)
+
+ );
+
+
+//##############################################################
+// 16x Baud clock generation
+// Example: to generate 19200 Baud clock from 50Mhz Link clock
+// 50 * 1000 * 1000 / (2 + cfg_baud_16x) = 19200 * 16
+// cfg_baud_16x = 0xA0 (160)
+//###############################################################
+
+wire line_clk_16x_in;
+
+// OpenSource CTS tool does not work with buffer as source point
+// changed buf to max with select tied=0
+//ctech_clk_buf u_lineclk_buf (.A(line_clk_16x_in), .X(line_clk_16x));
+ctech_mux2x1 u_lineclk_buf (.A0(line_clk_16x_in), .A1(1'b0), .S(1'b0), .X(line_clk_16x));
+
+clk_ctl #(11) u_clk_ctl (
+ // Outputs
+ .clk_o (line_clk_16x_in),
+
+ // Inputs
+ .mclk (app_clk),
+ .reset_n (app_reset_n),
+ .clk_div_ratio (cfg_baud_16x)
+ );
+
+//###################################
+// Application Reset Synchronization
+//###################################
+reset_sync u_app_rst (
+ .scan_mode (1'b0 ),
+ .dclk (app_clk ), // Destination clock domain
+ .arst_n (arst_n ), // active low async reset
+ .srst_n (app_reset_n )
+ );
+
+//###################################
+// Line Reset Synchronization
+//###################################
+reset_sync u_line_rst (
+ .scan_mode (1'b0 ),
+ .dclk (line_clk_16x ), // Destination clock domain
+ .arst_n (arst_n ), // active low async reset
+ .srst_n (line_reset_n )
+ );
+
+
+uart_txfsm u_txfsm (
+ .reset_n ( line_reset_n ),
+ .baud_clk_16x ( line_clk_16x ),
+
+ .cfg_tx_enable ( cfg_tx_enable ),
+ .cfg_stop_bit ( cfg_stop_bit ),
+ .cfg_pri_mod ( cfg_pri_mod ),
+
+ // FIFO control signal
+ .fifo_empty ( tx_fifo_rd_empty ),
+ .fifo_rd ( tx_fifo_rd ),
+ .fifo_data ( tx_fifo_rd_data ),
+
+ // Line Interface
+ .so ( txd )
+ );
+
+
+uart_rxfsm u_rxfsm (
+ .reset_n ( line_reset_n ),
+ .baud_clk_16x ( line_clk_16x ) ,
+
+ .cfg_rx_enable ( cfg_rx_enable ),
+ .cfg_stop_bit ( cfg_stop_bit ),
+ .cfg_pri_mod ( cfg_pri_mod ),
+
+ .error_ind ( error_ind ),
+
+ // FIFO control signal
+ .fifo_aval ( !rx_fifo_wr_full ),
+ .fifo_wr ( rx_fifo_wr ),
+ .fifo_data ( rx_fifo_wr_data ),
+
+ // Line Interface
+ .si (si_ss )
+ );
+
+async_fifo_th #(W,DP,0,0) u_rxfifo (
+ .wr_clk (line_clk_16x ),
+ .wr_reset_n (line_reset_n ),
+ .wr_en (rx_fifo_wr ),
+ .wr_data (rx_fifo_wr_data ),
+ .full (rx_fifo_wr_full ), // sync'ed to wr_clk
+ .wr_total_free_space( ),
+
+ .rd_clk (app_clk ),
+ .rd_reset_n (app_reset_n ),
+ .rd_en (app_rxfifo_rd_en ),
+ .empty (app_rxfifo_empty ), // sync'ed to rd_clk
+ .rd_total_aval (rx_fifo_dval ),
+ .rd_data (app_rxfifo_data )
+ );
+
+async_fifo_th #(W,DP,0,0) u_txfifo (
+ .wr_clk (app_clk ),
+ .wr_reset_n (app_reset_n ),
+ .wr_en (tx_fifo_wr_en ),
+ .wr_data (app_txfifo_data ),
+ .full (app_tx_fifo_full ), // sync'ed to wr_clk
+ .wr_total_free_space(tx_fifo_fspace ),
+
+ .rd_clk (line_clk_16x ),
+ .rd_reset_n (line_reset_n ),
+ .rd_en (tx_fifo_rd ),
+ .empty (tx_fifo_rd_empty ), // sync'ed to rd_clk
+ .rd_total_aval ( ),
+ .rd_data (tx_fifo_rd_data )
+ );
+
+
+double_sync_low u_si_sync (
+ .in_data (rxd ),
+ .out_clk (line_clk_16x ),
+ .out_rst_n (line_reset_n ),
+ .out_data (si_ss )
+ );
+
+wire frm_error = (error_ind == 2'b01);
+wire par_error = (error_ind == 2'b10);
+wire rx_fifo_full_err = (error_ind == 2'b11);
+
+double_sync_low u_frm_err (
+ .in_data ( frm_error ),
+ .out_clk ( app_clk ),
+ .out_rst_n ( app_reset_n ),
+ .out_data ( frm_error_o )
+ );
+
+double_sync_low u_par_err (
+ .in_data ( par_error ),
+ .out_clk ( app_clk ),
+ .out_rst_n ( app_reset_n ),
+ .out_data ( par_error_o )
+ );
+
+double_sync_low u_rxfifo_err (
+ .in_data ( rx_fifo_full_err ),
+ .out_clk ( app_clk ),
+ .out_rst_n ( app_reset_n ),
+ .out_data ( rx_fifo_full_err_o )
+ );
+
+
+endmodule
diff --git a/verilog/rtl/uart/src/uart_rxfsm.sv b/verilog/rtl/uart/src/uart_rxfsm.sv
new file mode 100644
index 0000000..58916e6
--- /dev/null
+++ b/verilog/rtl/uart/src/uart_rxfsm.sv
@@ -0,0 +1,221 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// UART RX FSM ////
+//// ////
+//// This file is part of the YIFive cores project ////
+//// https://github.com/dineshannayya/yifive_r0.git ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 20th June 2021, Dinesh A ////
+//// 1. initial version picked from ////
+//// http://www.opencores.org/cores/oms8051mini ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module uart_rxfsm (
+ reset_n ,
+ baud_clk_16x ,
+
+ cfg_rx_enable ,
+ cfg_stop_bit ,
+ cfg_pri_mod ,
+
+ error_ind ,
+
+ // FIFO control signal
+ fifo_aval ,
+ fifo_wr ,
+ fifo_data ,
+
+ // Line Interface
+ si
+ );
+
+
+input reset_n ; // active low reset signal
+input baud_clk_16x ; // baud clock-16x
+
+input cfg_rx_enable ; // transmit interface enable
+input cfg_stop_bit ; // stop bit
+ // 0 --> 1 stop, 1 --> 2 Stop
+input [1:0] cfg_pri_mod ;// Priority Mode
+ // 2'b00 --> None
+ // 2'b10 --> Even priority
+ // 2'b11 --> Odd priority
+
+output [1:0] error_ind ; // 2'b00 --> Normal
+ // 2'b01 --> framing error
+ // 2'b10 --> parity error
+ // 2'b11 --> fifo full
+//--------------------------------------
+// FIFO control signal
+//--------------------------------------
+input fifo_aval ; // fifo empty
+output fifo_wr ; // fifo write, assumed no back to back write
+output [7:0] fifo_data ; // fifo write data
+
+// Line Interface
+input si ; // rxd pin
+
+
+
+reg [7:0] fifo_data ; // fifo write data
+reg fifo_wr ; // fifo write
+reg [1:0] error_ind ;
+reg [2:0] cnt ;
+reg [3:0] offset ; // free-running counter from 0 - 15
+reg [3:0] rxpos ; // stable rx position
+reg [2:0] rxstate ;
+
+parameter idle_st = 3'b000;
+parameter xfr_start = 3'b001;
+parameter xfr_data_st = 3'b010;
+parameter xfr_pri_st = 3'b011;
+parameter xfr_stop_st1 = 3'b100;
+parameter xfr_stop_st2 = 3'b101;
+
+
+always @(negedge reset_n or posedge baud_clk_16x) begin
+ if(reset_n == 0) begin
+ rxstate <= 3'b0;
+ offset <= 4'b0;
+ rxpos <= 4'b0;
+ cnt <= 3'b0;
+ error_ind <= 2'b0;
+ fifo_wr <= 1'b0;
+ fifo_data <= 8'h0;
+ end
+ else begin
+ offset <= offset + 1;
+ case(rxstate)
+ idle_st : begin
+ if(!si) begin // Start indication
+ if(fifo_aval && cfg_rx_enable) begin
+ rxstate <= xfr_start;
+ cnt <= 0;
+ rxpos <= offset + 8; // Assign center rxoffset
+ error_ind <= 2'b00;
+ end
+ else begin
+ error_ind <= 2'b11; // fifo full error indication
+ end
+ end else begin
+ error_ind <= 2'b00; // Reset Error
+ end
+ end
+ xfr_start : begin
+ // Make Sure that minimum 8 cycle low is detected
+ if(cnt < 7 && si) begin // Start indication
+ rxstate <= idle_st;
+ end
+ else if(cnt == 7 && !si) begin // Start indication
+ rxstate <= xfr_data_st;
+ cnt <= 0;
+ end else begin
+ cnt <= cnt +1;
+ end
+ end
+ xfr_data_st : begin
+ if(rxpos == offset) begin
+ fifo_data[cnt] <= si;
+ cnt <= cnt+1;
+ if(cnt == 7) begin
+ fifo_wr <= 1;
+ if(cfg_pri_mod == 2'b00) // No Priority
+ rxstate <= xfr_stop_st1;
+ else rxstate <= xfr_pri_st;
+ end
+ end
+ end
+ xfr_pri_st : begin
+ fifo_wr <= 0;
+ if(rxpos == offset) begin
+ if(cfg_pri_mod == 2'b10) // even priority
+ if( si != ^fifo_data) error_ind <= 2'b10;
+ else // Odd Priority
+ if( si != ~(^fifo_data)) error_ind <= 2'b10;
+ rxstate <= xfr_stop_st1;
+ end
+ end
+ xfr_stop_st1 : begin
+ fifo_wr <= 0;
+ if(rxpos == offset) begin
+ if(si) begin
+ if(cfg_stop_bit) // Two Stop bit
+ rxstate <= xfr_stop_st2;
+ else
+ rxstate <= idle_st;
+ end else begin // Framing error
+ error_ind <= 2'b01;
+ rxstate <= idle_st;
+ end
+ end
+ end
+ xfr_stop_st2 : begin
+ if(rxpos == offset) begin
+ if(si) begin
+ rxstate <= idle_st;
+ end else begin // Framing error
+ error_ind <= 2'b01;
+ rxstate <= idle_st;
+ end
+ end
+ end
+ default: rxstate <= idle_st;
+ endcase
+ end
+end
+
+
+endmodule
diff --git a/verilog/rtl/uart/src/uart_txfsm.sv b/verilog/rtl/uart/src/uart_txfsm.sv
new file mode 100644
index 0000000..ad6507e
--- /dev/null
+++ b/verilog/rtl/uart/src/uart_txfsm.sv
@@ -0,0 +1,190 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// UART TX FSM ////
+//// ////
+//// This file is part of the YIFive cores project ////
+//// https://github.com/dineshannayya/yifive_r0.git ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 20th June 2021, Dinesh A ////
+//// 1. initial version picked from ////
+//// http://www.opencores.org/cores/oms8051mini ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+
+module uart_txfsm (
+ reset_n ,
+ baud_clk_16x ,
+
+ cfg_tx_enable ,
+ cfg_stop_bit ,
+ cfg_pri_mod ,
+
+ // FIFO control signal
+ fifo_empty ,
+ fifo_rd ,
+ fifo_data ,
+
+ // Line Interface
+ so
+ );
+
+
+input reset_n ; // active low reset signal
+input baud_clk_16x ; // baud clock-16x
+
+input cfg_tx_enable ; // transmit interface enable
+input cfg_stop_bit ; // stop bit
+ // 0 --> 1 stop, 1 --> 2 Stop
+input [1:0] cfg_pri_mod ;// Priority Mode
+ // 2'b00 --> None
+ // 2'b10 --> Even priority
+ // 2'b11 --> Odd priority
+
+//--------------------------------------
+// FIFO control signal
+//--------------------------------------
+input fifo_empty ; // fifo empty
+output fifo_rd ; // fifo read, assumed no back to back read
+input [7:0] fifo_data ; // fifo read data
+
+// Line Interface
+output so ; // txd pin
+
+
+reg [2:0] txstate ; // tx state
+reg so ; // txd pin
+reg [7:0] txdata ; // local txdata
+reg fifo_rd ; // Fifo read enable
+reg [2:0] cnt ; // local data cont
+reg [3:0] divcnt ; // clock div count
+
+parameter idle_st = 3'b000;
+parameter xfr_data_st = 3'b001;
+parameter xfr_pri_st = 3'b010;
+parameter xfr_stop_st1 = 3'b011;
+parameter xfr_stop_st2 = 3'b100;
+
+
+always @(negedge reset_n or posedge baud_clk_16x)
+begin
+ if(reset_n == 1'b0) begin
+ txstate <= idle_st;
+ so <= 1'b1;
+ cnt <= 3'b0;
+ txdata <= 8'h0;
+ fifo_rd <= 1'b0;
+ divcnt <= 4'b0;
+ end
+ else begin
+ divcnt <= divcnt+1;
+ if(divcnt == 4'b0000) begin // Do at once in 16 clock
+ case(txstate)
+ idle_st : begin
+ if(!fifo_empty && cfg_tx_enable) begin
+ so <= 1'b0 ; // Start bit
+ cnt <= 3'b0;
+ fifo_rd <= 1'b1;
+ txdata <= fifo_data;
+ txstate <= xfr_data_st;
+ end
+ end
+
+ xfr_data_st : begin
+ fifo_rd <= 1'b0;
+ so <= txdata[cnt];
+ cnt <= cnt+1;
+ if(cnt == 7) begin
+ if(cfg_pri_mod == 2'b00) begin // No Priority
+ txstate <= xfr_stop_st1;
+ end
+ else begin
+ txstate <= xfr_pri_st;
+ end
+ end
+ end
+
+ xfr_pri_st : begin
+ if(cfg_pri_mod == 2'b10) // even priority
+ so <= ^txdata;
+ else begin // Odd Priority
+ so <= ~(^txdata);
+ end
+ txstate <= xfr_stop_st1;
+ end
+
+ xfr_stop_st1 : begin // First Stop Bit
+ so <= 1;
+ if(cfg_stop_bit == 0) // 1 Stop Bit
+ txstate <= idle_st;
+ else // 2 Stop Bit
+ txstate <= xfr_stop_st2;
+ end
+
+ xfr_stop_st2 : begin // Second Stop Bit
+ so <= 1;
+ txstate <= idle_st;
+ end
+ default: txstate <= idle_st;
+ endcase
+ end
+ else begin
+ fifo_rd <= 1'b0;
+ end
+ end
+end
+
+
+endmodule
diff --git a/verilog/rtl/uart2wb/src/run_verilog b/verilog/rtl/uart2wb/src/run_verilog
new file mode 100644
index 0000000..c689827
--- /dev/null
+++ b/verilog/rtl/uart2wb/src/run_verilog
@@ -0,0 +1 @@
+iverilog uart2wb.sv uart2_core.sv uart_msg_handler.v ../../uart/src/uart_rxfsm.sv ../../uart/src/uart_txfsm.sv ../../lib/double_sync_low.v ../../lib/clk_ctl.v ../../lib/reset_sync.sv
diff --git a/verilog/rtl/uart2wb/src/uart2_core.sv b/verilog/rtl/uart2wb/src/uart2_core.sv
new file mode 100755
index 0000000..78daa1a
--- /dev/null
+++ b/verilog/rtl/uart2wb/src/uart2_core.sv
@@ -0,0 +1,192 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores UART Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+module uart2_core (
+ input wire arst_n , // Async reset
+ input wire app_clk , // Application clock
+
+
+ // configuration control
+ input wire cfg_tx_enable , // Enable Transmit Path
+ input wire cfg_rx_enable , // Enable Received Path
+ input wire cfg_stop_bit , // 0 -> 1 Start , 1 -> 2 Stop Bits
+ input wire [1:0] cfg_pri_mod , // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd
+ input wire [11:0]cfg_baud_16x , // 16x baud rate control
+
+ // TX PATH Information
+ input wire tx_data_avail , // Indicate valid TXD Data
+ output wire tx_rd , // Indicate TXD Data Been Read
+ input wire [7:0]tx_data , // Indicate TXD Data Been
+
+
+ // RXD Information
+ input wire rx_ready , // Indicate Ready to accept the Read Data
+ output wire rx_wr , // Valid RXD Data
+ output wire [7:0]rx_data , // RXD Data
+
+ // Status information
+ output wire frm_error , // framing error
+ output wire par_error , // par error
+
+ output wire baud_clk_16x , // 16x Baud clock
+ output wire line_reset_n , // Reset sync to 16x Baud clock
+
+ // Line Interface
+ input wire rxd , // uart rxd
+ output wire txd // uart txd
+
+ );
+
+
+
+//---------------------------------
+// Global Dec
+// ---------------------------------
+
+// Wire Declaration
+
+wire [1 : 0] error_ind ;
+wire si_ss ;
+
+// OpenSource CTS tool does not work with buffer as source point
+// changed buf to max with select tied=0
+//ctech_clk_buf u_lineclk_buf (.A(line_clk_16x_in), .X(line_clk_16x));
+wire line_clk_16x;
+ctech_mux2x1 u_uart_clk (.A0(line_clk_16x), .A1(1'b0), .S(1'b0), .X(baud_clk_16x));
+
+// 16x Baud clock generation
+// Example: to generate 19200 Baud clock from 50Mhz Link clock
+// 50 * 1000 * 1000 / (2 + cfg_baud_16x) = 19200 * 16
+// cfg_baud_16x = 0xA0 (160)
+
+clk_ctl #(11) u_clk_ctl (
+ // Outputs
+ .clk_o (line_clk_16x),
+
+ // Inputs
+ .mclk (app_clk),
+ .reset_n (arst_n),
+ .clk_div_ratio (cfg_baud_16x)
+ );
+
+
+//###################################
+// Line Reset Synchronization
+//###################################
+reset_sync u_line_rst (
+ .scan_mode (1'b0 ),
+ .dclk (baud_clk_16x ), // Destination clock domain
+ .arst_n (arst_n ), // active low async reset
+ .srst_n (line_reset_n )
+ );
+
+
+
+uart_txfsm u_txfsm (
+ . reset_n ( line_reset_n ),
+ . baud_clk_16x ( baud_clk_16x ),
+
+ . cfg_tx_enable ( cfg_tx_enable ),
+ . cfg_stop_bit ( cfg_stop_bit ),
+ . cfg_pri_mod ( cfg_pri_mod ),
+
+ // FIFO control signal
+ . fifo_empty ( !tx_data_avail ),
+ . fifo_rd ( tx_rd ),
+ . fifo_data ( tx_data ),
+
+ // Line Interface
+ . so ( txd )
+ );
+
+
+uart_rxfsm u_rxfsm (
+ . reset_n ( line_reset_n ),
+ . baud_clk_16x ( baud_clk_16x ) ,
+
+ . cfg_rx_enable ( cfg_rx_enable ),
+ . cfg_stop_bit ( cfg_stop_bit ),
+ . cfg_pri_mod ( cfg_pri_mod ),
+
+ . error_ind ( error_ind ),
+
+ // FIFO control signal
+ . fifo_aval ( rx_ready ),
+ . fifo_wr ( rx_wr ),
+ . fifo_data ( rx_data ),
+
+ // Line Interface
+ . si (si_ss )
+ );
+
+// Double Sync RXD
+double_sync_low u_rxd_sync (
+ .in_data (rxd ),
+ .out_clk (baud_clk_16x ),
+ .out_rst_n (line_reset_n ),
+ .out_data (si_ss )
+ );
+
+
+assign frm_error = (error_ind == 2'b01);
+assign par_error = (error_ind == 2'b10);
+
+
+
+endmodule
diff --git a/verilog/rtl/uart2wb/src/uart2wb.sv b/verilog/rtl/uart2wb/src/uart2wb.sv
new file mode 100755
index 0000000..0bf50b3
--- /dev/null
+++ b/verilog/rtl/uart2wb/src/uart2wb.sv
@@ -0,0 +1,229 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// UART2WB Top Module ////
+//// ////
+//// Description ////
+//// 1. uart_core ////
+//// 2. uart_msg_handler ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module uart2wb (
+ input wire arst_n , // sync reset
+ input wire app_clk , // sys clock
+
+ // configuration control
+ input wire cfg_tx_enable , // Enable Transmit Path
+ input wire cfg_rx_enable , // Enable Received Path
+ input wire cfg_stop_bit , // 0 -> 1 Start , 1 -> 2 Stop Bits
+ input wire [1:0] cfg_pri_mod , // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd
+ input wire [11:0] cfg_baud_16x , // 16x Baud clock generation
+
+ // Master Port
+ output wire wbm_cyc_o , // strobe/request
+ output wire wbm_stb_o , // strobe/request
+ output wire [31:0] wbm_adr_o , // address
+ output wire wbm_we_o , // write
+ output wire [31:0] wbm_dat_o , // data output
+ output wire [3:0] wbm_sel_o , // byte enable
+ input wire [31:0] wbm_dat_i , // data input
+ input wire wbm_ack_i , // acknowlegement
+ input wire wbm_err_i , // error
+
+ // Status information
+ output wire frm_error , // framing error
+ output wire par_error , // par error
+
+ output wire baud_clk_16x , // 16x Baud clock
+
+ // Line Interface
+ input wire rxd , // uart rxd
+ output wire txd // uart txd
+
+ );
+
+
+
+
+
+
+//-------------------------------------
+//---------------------------------------
+// Control Unit interface
+// --------------------------------------
+
+wire [31:0] reg_addr ; // Register Address
+wire [31:0] reg_wdata ; // Register Wdata
+wire reg_req ; // Register Request
+wire reg_wr ; // 1 -> write; 0 -> read
+wire reg_ack ; // Register Ack
+wire [31:0] reg_rdata ;
+//--------------------------------------
+// TXD Path
+// -------------------------------------
+wire tx_data_avail ; // Indicate valid TXD Data
+wire [7:0] tx_data ; // TXD Data to be transmited
+wire tx_rd ; // Indicate TXD Data Been Read
+
+
+//--------------------------------------
+// RXD Path
+// -------------------------------------
+wire rx_ready ; // Indicate Ready to accept the Read Data
+wire [7:0] rx_data ; // RXD Data
+wire rx_wr ; // Valid RXD Data
+
+wire line_reset_n ;
+
+assign wbm_cyc_o = wbm_stb_o;
+
+
+// Async App clock to Uart clock handling
+
+async_reg_bus #(.AW(32), .DW(32),.BEW(4))
+ u_async_reg_bus (
+ // Initiator declartion
+ .in_clk (baud_clk_16x),
+ .in_reset_n (line_reset_n),
+ // Reg Bus Master
+ // outputs
+ .in_reg_rdata (reg_rdata),
+ .in_reg_ack (reg_ack),
+ .in_reg_timeout (),
+
+ // Inputs
+ .in_reg_cs (reg_req),
+ .in_reg_addr (reg_addr),
+ .in_reg_wdata (reg_wdata),
+ .in_reg_wr (reg_wr),
+ .in_reg_be (4'hF), // No byte enable based support
+
+ // Target Declaration
+ .out_clk (app_clk),
+ .out_reset_n (arst_n),
+ // Reg Bus Slave
+ // output
+ .out_reg_cs (wbm_stb_o),
+ .out_reg_addr (wbm_adr_o),
+ .out_reg_wdata (wbm_dat_o),
+ .out_reg_wr (wbm_we_o),
+ .out_reg_be (wbm_sel_o),
+
+ // Inputs
+ .out_reg_rdata (wbm_dat_i),
+ .out_reg_ack (wbm_ack_i)
+ );
+
+
+uart2_core u_core (
+ .arst_n (arst_n) ,
+ .app_clk (app_clk) ,
+
+ // configuration control
+ .cfg_tx_enable (cfg_tx_enable) ,
+ .cfg_rx_enable (cfg_rx_enable) ,
+ .cfg_stop_bit (cfg_stop_bit) ,
+ .cfg_pri_mod (cfg_pri_mod) ,
+ .cfg_baud_16x (cfg_baud_16x) ,
+
+ // TXD Information
+ .tx_data_avail (tx_data_avail) ,
+ .tx_rd (tx_rd) ,
+ .tx_data (tx_data) ,
+
+
+ // RXD Information
+ .rx_ready (rx_ready) ,
+ .rx_wr (rx_wr) ,
+ .rx_data (rx_data) ,
+
+ // Status information
+ .frm_error (frm_error) ,
+ .par_error (par_error) ,
+
+ .baud_clk_16x (baud_clk_16x) ,
+ .line_reset_n (line_reset_n),
+
+ // Line Interface
+ .rxd (rxd) ,
+ .txd (txd)
+
+ );
+
+
+
+uart_msg_handler u_msg (
+ .reset_n (arst_n ) ,
+ .sys_clk (baud_clk_16x ) ,
+
+
+ // UART-TX Information
+ .tx_data_avail (tx_data_avail) ,
+ .tx_rd (tx_rd) ,
+ .tx_data (tx_data) ,
+
+
+ // UART-RX Information
+ .rx_ready (rx_ready) ,
+ .rx_wr (rx_wr) ,
+ .rx_data (rx_data) ,
+
+ // Towards Control Unit
+ .reg_addr (reg_addr),
+ .reg_wr (reg_wr),
+ .reg_wdata (reg_wdata),
+ .reg_req (reg_req),
+ .reg_ack (reg_ack),
+ .reg_rdata (reg_rdata)
+
+ );
+
+endmodule
diff --git a/verilog/rtl/uart2wb/src/uart_msg_handler.v b/verilog/rtl/uart2wb/src/uart_msg_handler.v
new file mode 100755
index 0000000..471ff88
--- /dev/null
+++ b/verilog/rtl/uart2wb/src/uart_msg_handler.v
@@ -0,0 +1,376 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// UART Message Handler Module ////
+//// ////
+//// This file is part of the uart2spi cores project ////
+//// http://www.opencores.org/cores/uart2spi/ ////
+//// ////
+//// Description ////
+//// Uart Message Handler definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module uart_msg_handler (
+ reset_n ,
+ sys_clk ,
+
+
+ // UART-TX Information
+ tx_data_avail,
+ tx_rd,
+ tx_data,
+
+
+ // UART-RX Information
+ rx_ready,
+ rx_wr,
+ rx_data,
+
+ // Towards Register Interface
+ reg_addr,
+ reg_wr,
+ reg_wdata,
+ reg_req,
+ reg_ack,
+ reg_rdata
+
+ );
+
+
+// Define the Message Hanlde States
+`define IDLE 4'h0
+`define IDLE_TX_MSG1 4'h1
+`define IDLE_TX_MSG2 4'h2
+`define RX_CMD_PHASE 4'h3
+`define ADR_PHASE 4'h4
+`define WR_DATA_PHASE 4'h5
+`define SEND_WR_REQ 4'h6
+`define SEND_RD_REQ 4'h7
+`define SEND_RD_DATA 4'h8
+`define TX_MSG 4'h9
+
+`define BREAK_CHAR 8'h0A
+
+//---------------------------------
+// Global Dec
+// ---------------------------------
+
+input reset_n ; // line reset
+input sys_clk ; // line clock
+
+
+//--------------------------------------
+// UART TXD Path
+// -------------------------------------
+output tx_data_avail ; // Indicate valid TXD Data available
+output [7:0] tx_data ; // TXD Data to be transmited
+input tx_rd ; // Indicate TXD Data Been Read
+
+
+//--------------------------------------
+// UART RXD Path
+// -------------------------------------
+output rx_ready ; // Indicate Ready to accept the Read Data
+input [7:0] rx_data ; // RXD Data
+input rx_wr ; // Valid RXD Data
+
+//---------------------------------------
+// Control Unit interface
+// --------------------------------------
+
+output [31:0] reg_addr ; // Operend-1
+output [31:0] reg_wdata ; // Operend-2
+output reg_req ; // Register Request
+output reg_wr ; // 1 -> write; 0 -> read
+input reg_ack ; // Register Ack
+input [31:0] reg_rdata ;
+
+// Local Wire/Register Decleration
+//
+//
+reg tx_data_avail ;
+reg [7:0] tx_data ;
+reg [16*8-1:0] TxMsgBuf ; // 16 Byte Tx Message Buffer
+reg [4:0] TxMsgSize ;
+reg [4:0] RxMsgCnt ; // Count the Receive Message Count
+reg [3:0] State ;
+reg [3:0] NextState ;
+reg [15:0] cmd ; // command
+reg [31:0] reg_addr ; // reg_addr
+reg [31:0] reg_wdata ; // reg_addr
+reg reg_wr ; // 1 -> Reg Write request, 0 -> Read Requestion
+reg reg_req ; // 1 -> Register request
+
+
+wire rx_ready = 1;
+/****************************************************************
+* UART Message Hanlding Steps
+*
+* 1. On Reset Or Unknown command, Send the Default Message
+* Select Option:
+* wr <addr> <data>
+* rd <addr>
+* 2. Wait for User command <wr/rd>
+* 3. On <wr> command move to write address phase;
+* phase
+* A. After write address phase move to write data phase
+* B. After write data phase, once user press \r command ; send register req
+* and write request and address + data
+* C. On receiving register ack response; send <success> message back and move
+* to state-2
+* 3. On <rd> command move to read address phase;
+* A. After read address phase , once user press '\r' command; send
+* register req , read request
+* C. On receiving register ack response; send <response + read_data> message and move
+* to state-2
+* *****************************************************************/
+
+always @(negedge reset_n or posedge sys_clk)
+begin
+ if(reset_n == 1'b0) begin
+ tx_data_avail <= 0;
+ reg_req <= 0;
+ reg_addr <= 0;
+ reg_wr <= 1'b0; // Read request
+ reg_wdata <= 0;
+ State <= `IDLE;
+ NextState <= `IDLE;
+ end else begin
+ case(State)
+ // Send Default Message
+ `IDLE: begin
+ TxMsgBuf <= "Command Format:\n"; // Align to 16 character format by appending space character
+ TxMsgSize <= 16;
+ tx_data_avail <= 0;
+ State <= `TX_MSG;
+ NextState <= `IDLE_TX_MSG1;
+ end
+
+ // Send Default Message (Contd..)
+ `IDLE_TX_MSG1: begin
+ TxMsgBuf <= "wm <ad> <data>\n "; // Align to 16 character format by appending space character
+ TxMsgSize <= 15;
+ tx_data_avail <= 0;
+ State <= `TX_MSG;
+ NextState <= `IDLE_TX_MSG2;
+ end
+
+ // Send Default Message (Contd..)
+ `IDLE_TX_MSG2: begin
+ TxMsgBuf <= "rm <ad>\n>> "; // Align to 16 character format by appending space character
+ TxMsgSize <= 10;
+ tx_data_avail <= 0;
+ RxMsgCnt <= 0;
+ State <= `TX_MSG;
+ NextState <= `RX_CMD_PHASE;
+ end
+
+ // Wait for Response
+ `RX_CMD_PHASE: begin
+ if(rx_wr == 1) begin
+ //if(RxMsgCnt == 0 && rx_data == " ") begin // Ignore the same
+ if(RxMsgCnt == 0 && rx_data == 8'h20) begin // Ignore the same
+ //end else if(RxMsgCnt > 0 && rx_data == " ") begin // Check the command
+ end else if(RxMsgCnt > 0 && rx_data == 8'h20) begin // Check the command
+ reg_addr <= 0;
+ RxMsgCnt <= 0;
+ //if(cmd == "wm") begin
+ if(cmd == 16'h776D) begin
+ State <= `ADR_PHASE;
+ //end else if(cmd == "rm") begin
+ end else if(cmd == 16'h726D) begin
+
+ State <= `ADR_PHASE;
+ end else begin // Unknow command
+ State <= `IDLE;
+ end
+ //end else if(rx_data == "\n") begin // Error State
+ end else if(rx_data == `BREAK_CHAR) begin // Error State
+ State <= `IDLE;
+ end
+ else begin
+ cmd <= (cmd << 8) | rx_data ;
+ RxMsgCnt <= RxMsgCnt+1;
+ end
+ end
+ end
+ // Write Address Phase
+ `ADR_PHASE: begin
+ if(rx_wr == 1) begin
+ //if(RxMsgCnt == 0 && rx_data == " ") begin // Ignore the Space character
+ if(RxMsgCnt == 0 && rx_data == 8'h20) begin // Ignore the Space character
+ end else if(RxMsgCnt > 0 && (rx_data == 8'h20 || rx_data == `BREAK_CHAR)) begin // Move to write data phase
+ //if(RxMsgCnt > 0 && "wm" && rx_data == " ") begin // Move to write data phase
+ if(cmd == 16'h776D && rx_data == 8'h20) begin // Move to write data phase
+ reg_wdata <= 0;
+ State <= `WR_DATA_PHASE;
+ // end else if(RxMsgCnt > 0 && "rm" && rx_data == "\n") begin // Move to read data phase
+ end else if(cmd == 16'h726D && rx_data == `BREAK_CHAR) begin // Move to read data phase
+ reg_wr <= 1'b0; // Read request
+ reg_req <= 1'b1; // Reg Request
+ State <= `SEND_RD_REQ;
+ end else begin // Unknow command
+ State <= `IDLE;
+ end
+ //end else if(rx_data == "\n") begin // Error State
+ end else if(rx_data == `BREAK_CHAR) begin // Error State
+ State <= `IDLE;
+ end else begin
+ reg_addr <= (reg_addr << 4) | char2hex(rx_data);
+ RxMsgCnt <= RxMsgCnt+1;
+ end
+ end
+ end
+ // Write Data Phase
+ `WR_DATA_PHASE: begin
+ if(rx_wr == 1) begin
+ //if(rx_data == " ") begin // Ignore the Space character
+ if(rx_data == 8'h20) begin // Ignore the Space character
+ //end else if(rx_data == "\n") begin // Error State
+ end else if(rx_data == `BREAK_CHAR) begin // Error State
+ State <= `SEND_WR_REQ;
+ reg_wr <= 1'b1; // Write request
+ reg_req <= 1'b1;
+ end else begin // A to F
+ reg_wdata <= (reg_wdata << 4) | char2hex(rx_data);
+ end
+ end
+ end
+ `SEND_WR_REQ: begin
+ if(reg_ack) begin
+ reg_req <= 1'b0;
+ TxMsgBuf <= "cmd success\n>> "; // Align to 16 character format by appending space character
+ TxMsgSize <= 14;
+ tx_data_avail <= 0;
+ State <= `TX_MSG;
+ NextState <= `RX_CMD_PHASE;
+ end
+ end
+
+ `SEND_RD_REQ: begin
+ if(reg_ack) begin
+ reg_req <= 1'b0;
+ TxMsgBuf <= "Response: "; // Align to 16 character format by appending space character
+ TxMsgSize <= 10;
+ tx_data_avail <= 0;
+ State <= `TX_MSG;
+ NextState <= `SEND_RD_DATA;
+ end
+ end
+ `SEND_RD_DATA: begin // Wait for Operation Completion
+ TxMsgBuf[16*8-1:15*8] <= hex2char(reg_rdata[31:28]);
+ TxMsgBuf[15*8-1:14*8] <= hex2char(reg_rdata[27:24]);
+ TxMsgBuf[14*8-1:13*8] <= hex2char(reg_rdata[23:20]);
+ TxMsgBuf[13*8-1:12*8] <= hex2char(reg_rdata[19:16]);
+ TxMsgBuf[12*8-1:11*8] <= hex2char(reg_rdata[15:12]);
+ TxMsgBuf[11*8-1:10*8] <= hex2char(reg_rdata[11:8]);
+ TxMsgBuf[10*8-1:9*8] <= hex2char(reg_rdata[7:4]);
+ TxMsgBuf[9*8-1:8*8] <= hex2char(reg_rdata[3:0]);
+ TxMsgBuf[8*8-1:7*8] <= "\n";
+ TxMsgSize <= 9;
+ tx_data_avail <= 0;
+ State <= `TX_MSG;
+ NextState <= `RX_CMD_PHASE;
+ end
+
+ // Send Default Message (Contd..)
+ `TX_MSG: begin
+ tx_data_avail <= 1;
+ tx_data <= TxMsgBuf[16*8-1:15*8];
+ if(TxMsgSize == 0) begin
+ tx_data_avail <= 0;
+ State <= NextState;
+ end else if(tx_rd) begin
+ TxMsgBuf <= TxMsgBuf << 8;
+ TxMsgSize <= TxMsgSize -1;
+ end
+ end
+ endcase
+ end
+end
+
+
+// Character to hex number
+function [3:0] char2hex;
+input [7:0] data_in;
+case (data_in)
+ 8'h30: char2hex = 4'h0; // character '0'
+ 8'h31: char2hex = 4'h1; // character '1'
+ 8'h32: char2hex = 4'h2; // character '2'
+ 8'h33: char2hex = 4'h3; // character '3'
+ 8'h34: char2hex = 4'h4; // character '4'
+ 8'h35: char2hex = 4'h5; // character '5'
+ 8'h36: char2hex = 4'h6; // character '6'
+ 8'h37: char2hex = 4'h7; // character '7'
+ 8'h38: char2hex = 4'h8; // character '8'
+ 8'h39: char2hex = 4'h9; // character '9'
+ 8'h41: char2hex = 4'hA; // character 'A'
+ 8'h42: char2hex = 4'hB; // character 'B'
+ 8'h43: char2hex = 4'hC; // character 'C'
+ 8'h44: char2hex = 4'hD; // character 'D'
+ 8'h45: char2hex = 4'hE; // character 'E'
+ 8'h46: char2hex = 4'hF; // character 'F'
+ 8'h61: char2hex = 4'hA; // character 'a'
+ 8'h62: char2hex = 4'hB; // character 'b'
+ 8'h63: char2hex = 4'hC; // character 'c'
+ 8'h64: char2hex = 4'hD; // character 'd'
+ 8'h65: char2hex = 4'hE; // character 'e'
+ 8'h66: char2hex = 4'hF; // character 'f'
+ default : char2hex = 4'hF;
+ endcase
+endfunction
+
+// Hex to Asci Character
+function [7:0] hex2char;
+input [3:0] data_in;
+case (data_in)
+ 4'h0: hex2char = 8'h30; // character '0'
+ 4'h1: hex2char = 8'h31; // character '1'
+ 4'h2: hex2char = 8'h32; // character '2'
+ 4'h3: hex2char = 8'h33; // character '3'
+ 4'h4: hex2char = 8'h34; // character '4'
+ 4'h5: hex2char = 8'h35; // character '5'
+ 4'h6: hex2char = 8'h36; // character '6'
+ 4'h7: hex2char = 8'h37; // character '7'
+ 4'h8: hex2char = 8'h38; // character '8'
+ 4'h9: hex2char = 8'h39; // character '9'
+ 4'hA: hex2char = 8'h41; // character 'A'
+ 4'hB: hex2char = 8'h42; // character 'B'
+ 4'hC: hex2char = 8'h43; // character 'C'
+ 4'hD: hex2char = 8'h44; // character 'D'
+ 4'hE: hex2char = 8'h45; // character 'E'
+ 4'hF: hex2char = 8'h46; // character 'F'
+ endcase
+endfunction
+endmodule
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
new file mode 100644
index 0000000..96c4399
--- /dev/null
+++ b/verilog/rtl/uprj_netlists.v
@@ -0,0 +1,95 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+// Include caravel global defines for the number of the user project IO pads
+`include "defines.v"
+`define USE_POWER_PINS
+`define UNIT_DELAY #0.1
+
+`ifdef GL
+ // Assume default net type to be wire because GL netlists don't have the wire definitions
+ `default_nettype wire
+ `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+ `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+ `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
+ `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+ `include "gl/user_project_wrapper.v"
+ `include "gl/glbl_cfg.v"
+ `include "gl/mbist1.v"
+ `include "gl/mbist2.v"
+ `include "gl/wb_host.v"
+ `include "gl/wb_interconnect.v"
+ `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+ `include "sram_macros/sky130_sram_1kbyte_1rw1r_32x256_8.v"
+
+`else
+ `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+ `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+ `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
+ `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+
+ `include "user_project_wrapper.v"
+
+
+ `include "mbist/src/core/mbist_addr_gen.sv"
+ `include "mbist/src/core/mbist_fsm.sv"
+ `include "mbist/src/core/mbist_op_sel.sv"
+ `include "mbist/src/core/mbist_repair_addr.sv"
+ `include "mbist/src/core/mbist_sti_sel.sv"
+ `include "mbist/src/core/mbist_pat_sel.sv"
+ `include "mbist/src/core/mbist_mux.sv"
+ `include "mbist/src/core/mbist_data_cmp.sv"
+ `include "mbist/src/core/mbist_mem_wrapper.sv"
+
+ `include "mbist/src/top/mbist_top1.sv"
+ `include "mbist/src/top/mbist_top2.sv"
+
+ `include "wb_host/src/wb_host.sv"
+ `include "lib/async_fifo.sv"
+ `include "lib/async_wb.sv"
+ `include "lib/registers.v"
+ `include "lib/clk_ctl.v"
+ `include "lib/reset_sync.sv"
+ `include "lib/ser_inf_32b.sv"
+ `include "lib/ctech_cells.sv"
+ `include "lib/async_reg_bus.sv"
+ `include "lib/clk_gate.sv"
+ `include "lib/crc_32.sv"
+
+ `include "lib/wb_stagging.sv"
+ `include "wb_interconnect/src/wb_interconnect.sv"
+ `include "glbl/src/glbl_cfg.sv"
+ `include "lbist/src/lbist_top.sv"
+ `include "lbist/src/lbist_core.sv"
+ `include "lbist/src/lbist_reg.sv"
+
+ `include "uart/src/uart_core.sv"
+ `include "uart/src/uart_cfg.sv"
+ `include "uart/src/uart_rxfsm.sv"
+ `include "uart/src/uart_txfsm.sv"
+ `include "lib/async_fifo_th.sv"
+ `include "lib/double_sync_low.v"
+ `include "lib/clk_buf.v"
+ `include "lib/wb_arb.sv"
+
+ `include "uart2wb/src/uart2wb.sv"
+ `include "uart2wb/src/uart2_core.sv"
+ `include "uart2wb/src/uart_msg_handler.v"
+
+ `include "clk_skew_adjust/src/clk_skew_adjust.v"
+ `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+ `include "sram_macros/sky130_sram_1kbyte_1rw1r_32x256_8.v"
+
+`endif
diff --git a/verilog/rtl/user_defines.v b/verilog/rtl/user_defines.v
new file mode 100644
index 0000000..1e2cb90
--- /dev/null
+++ b/verilog/rtl/user_defines.v
@@ -0,0 +1,87 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`ifndef __USER_DEFINES_H
+// User GPIO initial configuration parameters
+`define __USER_DEFINES_H
+
+// Useful GPIO mode values. These match the names used in defs.h.
+`define GPIO_MODE_MGMT_STD_INPUT_NOPULL 13'h0403
+`define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 13'h0803
+`define GPIO_MODE_MGMT_STD_INPUT_PULLUP 13'h0c03
+`define GPIO_MODE_MGMT_STD_OUTPUT 13'h1809
+`define GPIO_MODE_MGMT_STD_BIDIRECTIONAL 13'h1801
+`define GPIO_MODE_MGMT_STD_ANALOG 13'h000b
+
+`define GPIO_MODE_USER_STD_INPUT_NOPULL 13'h0402
+`define GPIO_MODE_USER_STD_INPUT_PULLDOWN 13'h0802
+`define GPIO_MODE_USER_STD_INPUT_PULLUP 13'h0c02
+`define GPIO_MODE_USER_STD_OUTPUT 13'h1808
+`define GPIO_MODE_USER_STD_BIDIRECTIONAL 13'h1800
+`define GPIO_MODE_USER_STD_OUT_MONITORED 13'h1802
+`define GPIO_MODE_USER_STD_ANALOG 13'h000a
+
+// The power-on configuration for GPIO 0 to 4 is fixed and cannot be
+// modified (allowing the SPI and debug to always be accessible unless
+// overridden by a flash program).
+
+// The values below can be any of the standard types defined above,
+// or they can be any 13-bit value if the user wants a non-standard
+// startup state for the GPIO. By default, every GPIO from 5 to 37
+// is set to power up as an input controlled by the management SoC.
+// Users may want to redefine these so that the user project powers
+// up in a state that can be used immediately without depending on
+// the management SoC to run a startup program to configure the GPIOs.
+
+`define USER_CONFIG_GPIO_5_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL // UART_TXD[1]
+`define USER_CONFIG_GPIO_6_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL // UART_RXD[1]
+`define USER_CONFIG_GPIO_7_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_8_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_9_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_12_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_13_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_14_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+
+// Configurations of GPIO 15 to 25 are used on caravel but not caravan.
+`define USER_CONFIG_GPIO_15_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_16_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_17_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_18_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_19_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_20_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_21_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_22_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_23_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_24_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_25_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+
+`define USER_CONFIG_GPIO_26_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_27_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_28_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_29_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_30_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_31_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_32_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_33_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_34_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_35_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_36_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_37_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+
+`endif // __USER_DEFINES_H
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
new file mode 100644
index 0000000..62c35bf
--- /dev/null
+++ b/verilog/rtl/user_project_wrapper.v
@@ -0,0 +1,1805 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Digital core ////
+//// ////
+//// This file is part of the mbist_ctrl project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This is digital core and integrate all the main block ////
+//// here. ////
+//// 1. Wishbone Host ////
+//// 2. 4x MBIST Controller ////
+//// 3. 2x SRAM 2KB ////
+//// 4. 2x SRAM 1KB ////
+//// 5. Wishbone Interconnect ////
+//// 6. Global Register ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 13th Oct 2021, Dinesh A ////
+//// Initial Version ////
+//// 0.2 - 19, Nov 2021, Dinesh A ////
+//// Following things are integrated ////
+//// 2x SRAM 2KB, 2x SRAM 1KB, 4 MBIST , ////
+//// 1 Wishbone Interconnect, 1 Global register ////
+//// 0.3 - 20, Nov 2021, Dinesh A ////
+//// Following are integrated ////
+//// 4x SRAM 2KB, 4x SRAM 1KB, 8 MBIST , ////
+//// 1 Wishbone Interconnect, 1 Global register ////
+//// 0.4 - 23 Nov 2021, Dinesh A ////
+//// Three Software Register added for signature at glbl ////
+//// 1.0 - 01 Dec 2021, Dinesh A -MPW-4 ////
+//// A. Logic Bist Integrated inside the Wb_host ////
+//// B. Below Scan chain created ////
+//// WB_HOST(LBIST) => GLBL => MBIST5 => MBIST6 => MBIST7 ////
+//// => MBIST8 => WB_INTERCONNECT => MBIST4 => MBIST3 => ////
+//// MBIST2 => MBIST1 => WB_HOST(LBIST) ////
+//// 1.1 - 03 Dec 2021, Dinesh A ////
+//// Timing closure clean-up ////
+//// 1.2 - 10 Dec 2021, Dinesh A ////
+//// Full Chip Timing closure wth caravel ////
+//// 1.3 - 21 Dec 2021, Dinesh A ////
+//// A. LBIST bypass added, SCAN can be controlled through ////
+//// LA ports ////
+//// B. LBIST reset chain check compare bypass added ////
+//// 1.4 Jan 02, 2022, Dinesh A ////
+//// 1. LA[0] is added as soft reset option at wb_port ////
+//// 2. Uart Master is added at wb_port ////
+//// 1.5 Feb 18, 2022, Dinesh A ////
+//// As SRAM timing model are not accurate, added additionl ////
+//// drive data towards SRAM in negedge phase(cfg_mem_lphase)///
+//// 1.6 Mar 16, 2022, Dinesh A ////
+//// RTL changes in wb_host to fix caraval wb address ////
+//// reduction to 0x3000_0000 to 0x300F_FFFF ////
+//////////////////////////////////////////////////////////////////////
+`default_nettype none
+
+module user_project_wrapper(
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ // IOs
+ input [37:0] io_in,
+ output [37:0] io_out,
+ output [37:0] io_oeb,
+
+ // Analog (direct connection to GPIO pad---use with caution)
+ // Note that analog I/O is not available on the 7 lowest-numbered
+ // GPIO pads, and so the analog_io indexing is offset from the
+ // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
+ inout [28:0] analog_io,
+
+ // Independent clock (on independent integer divider)
+ input user_clock2,
+
+ // User maskable interrupt signals
+ output [2:0] user_irq
+);
+
+parameter BIST1_ADDR_WD = 11; // 512x32 SRAM
+parameter BIST2_ADDR_WD = 10; // 256x32 SRAM
+parameter BIST_DATA_WD = 32;
+parameter WB_WIDTH = 32; // WB ADDRESS/DARA WIDTH
+
+parameter SCW = 8; // SCAN CHAIN WIDTH
+//---------------------------------------------------------------------
+// WB HOST Interface
+//---------------------------------------------------------------------
+wire wbd_int_cyc_i; // strobe/request
+wire wbd_int_stb_i; // strobe/request
+wire [WB_WIDTH-1:0] wbd_int_adr_i; // address
+wire wbd_int_we_i; // write
+wire [WB_WIDTH-1:0] wbd_int_dat_i; // data output
+wire [3:0] wbd_int_sel_i; // byte enable
+wire [WB_WIDTH-1:0] wbd_int_dat_o; // data input
+wire wbd_int_ack_o; // acknowlegement
+wire wbd_int_err_o; // error
+
+//---------------------------------------------------------------------
+// Global Register Wishbone Interface
+//---------------------------------------------------------------------
+wire wbd_glbl_stb_o; // strobe/request
+wire [7:0] wbd_glbl_adr_o; // address
+wire wbd_glbl_we_o; // write
+wire [WB_WIDTH-1:0] wbd_glbl_dat_o; // data output
+wire [3:0] wbd_glbl_sel_o; // byte enable
+wire wbd_glbl_cyc_o ;
+wire [WB_WIDTH-1:0] wbd_glbl_dat_i; // data input
+wire wbd_glbl_ack_i; // acknowlegement
+wire wbd_glbl_err_i; // error
+
+//---------------------------------------------------------------------
+// MBIST1
+//---------------------------------------------------------------------
+wire wbd_mbist1_stb_o; // strobe/request
+wire [BIST1_ADDR_WD-1:0] wbd_mbist1_adr_o; // address
+wire wbd_mbist1_we_o; // write
+wire [WB_WIDTH-1:0] wbd_mbist1_dat_o; // data output
+wire [3:0] wbd_mbist1_sel_o; // byte enable
+wire wbd_mbist1_cyc_o ;
+wire [WB_WIDTH-1:0] wbd_mbist1_dat_i; // data input
+wire wbd_mbist1_ack_i; // acknowlegement
+wire wbd_mbist1_err_i; // error
+
+//---------------------------------------------------------------------
+// MBIST2
+//---------------------------------------------------------------------
+wire wbd_mbist2_stb_o; // strobe/request
+wire [BIST1_ADDR_WD-1:0] wbd_mbist2_adr_o; // address
+wire wbd_mbist2_we_o; // write
+wire [WB_WIDTH-1:0] wbd_mbist2_dat_o; // data output
+wire [3:0] wbd_mbist2_sel_o; // byte enable
+wire wbd_mbist2_cyc_o ;
+wire [WB_WIDTH-1:0] wbd_mbist2_dat_i; // data input
+wire wbd_mbist2_ack_i; // acknowlegement
+wire wbd_mbist2_err_i; // error
+
+//---------------------------------------------------------------------
+// MBIST3
+//---------------------------------------------------------------------
+wire wbd_mbist3_stb_o; // strobe/request
+wire [BIST1_ADDR_WD-1:0] wbd_mbist3_adr_o; // address
+wire wbd_mbist3_we_o; // write
+wire [WB_WIDTH-1:0] wbd_mbist3_dat_o; // data output
+wire [3:0] wbd_mbist3_sel_o; // byte enable
+wire wbd_mbist3_cyc_o ;
+wire [WB_WIDTH-1:0] wbd_mbist3_dat_i; // data input
+wire wbd_mbist3_ack_i; // acknowlegement
+wire wbd_mbist3_err_i; // error
+
+//---------------------------------------------------------------------
+// MBIST4
+//---------------------------------------------------------------------
+wire wbd_mbist4_stb_o; // strobe/request
+wire [BIST1_ADDR_WD-1:0] wbd_mbist4_adr_o; // address
+wire wbd_mbist4_we_o; // write
+wire [WB_WIDTH-1:0] wbd_mbist4_dat_o; // data output
+wire [3:0] wbd_mbist4_sel_o; // byte enable
+wire wbd_mbist4_cyc_o ;
+wire [WB_WIDTH-1:0] wbd_mbist4_dat_i; // data input
+wire wbd_mbist4_ack_i; // acknowlegement
+wire wbd_mbist4_err_i; // error
+
+//---------------------------------------------------------------------
+// MBIST5
+//---------------------------------------------------------------------
+wire wbd_mbist5_stb_o; // strobe/request
+wire [BIST2_ADDR_WD-1:0] wbd_mbist5_adr_o; // address
+wire wbd_mbist5_we_o; // write
+wire [WB_WIDTH-1:0] wbd_mbist5_dat_o; // data output
+wire [3:0] wbd_mbist5_sel_o; // byte enable
+wire wbd_mbist5_cyc_o ;
+wire [WB_WIDTH-1:0] wbd_mbist5_dat_i; // data input
+wire wbd_mbist5_ack_i; // acknowlegement
+wire wbd_mbist5_err_i; // error
+
+//---------------------------------------------------------------------
+// MBIST6
+//---------------------------------------------------------------------
+wire wbd_mbist6_stb_o; // strobe/request
+wire [BIST2_ADDR_WD-1:0] wbd_mbist6_adr_o; // address
+wire wbd_mbist6_we_o; // write
+wire [WB_WIDTH-1:0] wbd_mbist6_dat_o; // data output
+wire [3:0] wbd_mbist6_sel_o; // byte enable
+wire wbd_mbist6_cyc_o ;
+wire [WB_WIDTH-1:0] wbd_mbist6_dat_i; // data input
+wire wbd_mbist6_ack_i; // acknowlegement
+wire wbd_mbist6_err_i; // error
+
+//---------------------------------------------------------------------
+// MBIST7
+//---------------------------------------------------------------------
+wire wbd_mbist7_stb_o; // strobe/request
+wire [BIST2_ADDR_WD-1:0] wbd_mbist7_adr_o; // address
+wire wbd_mbist7_we_o; // write
+wire [WB_WIDTH-1:0] wbd_mbist7_dat_o; // data output
+wire [3:0] wbd_mbist7_sel_o; // byte enable
+wire wbd_mbist7_cyc_o ;
+wire [WB_WIDTH-1:0] wbd_mbist7_dat_i; // data input
+wire wbd_mbist7_ack_i; // acknowlegement
+wire wbd_mbist7_err_i; // error
+
+//---------------------------------------------------------------------
+// MBIST8
+//---------------------------------------------------------------------
+wire wbd_mbist8_stb_o; // strobe/request
+wire [BIST2_ADDR_WD-1:0] wbd_mbist8_adr_o; // address
+wire wbd_mbist8_we_o; // write
+wire [WB_WIDTH-1:0] wbd_mbist8_dat_o; // data output
+wire [3:0] wbd_mbist8_sel_o; // byte enable
+wire wbd_mbist8_cyc_o ;
+wire [WB_WIDTH-1:0] wbd_mbist8_dat_i; // data input
+wire wbd_mbist8_ack_i; // acknowlegement
+wire wbd_mbist8_err_i; // error
+
+
+wire wbd_int_rst_n;
+wire bist_rst_n;
+
+// MBIST I/F
+wire [7:0] bist_en;
+wire [7:0] bist_run;
+wire [7:0] bist_shift;
+wire [7:0] bist_load;
+wire [7:0] bist_sdi;
+
+wire [7:0] bist_correct;
+wire [7:0] bist_error;
+wire [7:0] bist_done;
+wire [7:0] bist_sdo;
+
+wire [3:0] bist_error_cnt0;
+wire [3:0] bist_error_cnt1;
+wire [3:0] bist_error_cnt2;
+wire [3:0] bist_error_cnt3;
+wire [3:0] bist_error_cnt4;
+wire [3:0] bist_error_cnt5;
+wire [3:0] bist_error_cnt6;
+wire [3:0] bist_error_cnt7;
+
+// MBIST I/F Buffered
+wire [7:0] bist_en_int;
+wire [7:0] bist_run_int;
+wire [7:0] bist_shift_int;
+wire [7:0] bist_load_int;
+wire [7:0] bist_sdi_int;
+
+wire [7:0] bist_correct_int;
+wire [7:0] bist_error_int;
+wire [7:0] bist_done_int;
+wire [7:0] bist_sdo_int;
+
+wire [3:0] bist_error_cnt0_int;
+wire [3:0] bist_error_cnt1_int;
+wire [3:0] bist_error_cnt2_int;
+wire [3:0] bist_error_cnt3_int;
+wire [3:0] bist_error_cnt4_int;
+wire [3:0] bist_error_cnt5_int;
+wire [3:0] bist_error_cnt6_int;
+wire [3:0] bist_error_cnt7_int;
+
+// towards memory MBIST1
+// PORT-A
+wire mem1_clk_a;
+wire [BIST1_ADDR_WD-1:2] mem1_addr_a;
+wire mem1_cen_a;
+wire [BIST_DATA_WD-1:0] mem1_din_b;
+
+// PORT-B
+wire mem1_clk_b;
+wire mem1_cen_b;
+wire mem1_web_b;
+wire [BIST_DATA_WD/8-1:0] mem1_mask_b;
+wire [BIST1_ADDR_WD-1:2] mem1_addr_b;
+wire [BIST_DATA_WD-1:0] mem1_dout_a;
+
+// towards memory MBIST2
+// PORT-A
+wire mem2_clk_a;
+wire [BIST1_ADDR_WD-1:2] mem2_addr_a;
+wire mem2_cen_a;
+wire [BIST_DATA_WD-1:0] mem2_din_b;
+
+// PORT-B
+wire mem2_clk_b;
+wire mem2_cen_b;
+wire mem2_web_b;
+wire [BIST_DATA_WD/8-1:0] mem2_mask_b;
+wire [BIST1_ADDR_WD-1:2] mem2_addr_b;
+wire [BIST_DATA_WD-1:0] mem2_dout_a;
+
+// towards memory MBIST3
+// PORT-A
+wire mem3_clk_a;
+wire [BIST1_ADDR_WD-1:2] mem3_addr_a;
+wire mem3_cen_a;
+wire [BIST_DATA_WD-1:0] mem3_din_b;
+
+// PORT-B
+wire mem3_clk_b;
+wire mem3_cen_b;
+wire mem3_web_b;
+wire [BIST_DATA_WD/8-1:0] mem3_mask_b;
+wire [BIST1_ADDR_WD-1:2] mem3_addr_b;
+wire [BIST_DATA_WD-1:0] mem3_dout_a;
+
+// towards memory MBIST4
+// PORT-A
+wire mem4_clk_a;
+wire [BIST1_ADDR_WD-1:2] mem4_addr_a;
+wire mem4_cen_a;
+wire [BIST_DATA_WD-1:0] mem4_din_b;
+
+// PORT-B
+wire mem4_clk_b;
+wire mem4_cen_b;
+wire mem4_web_b;
+wire [BIST_DATA_WD/8-1:0] mem4_mask_b;
+wire [BIST1_ADDR_WD-1:2] mem4_addr_b;
+wire [BIST_DATA_WD-1:0] mem4_dout_a;
+
+// towards memory MBIST5
+// PORT-A
+wire mem5_clk_a;
+wire [BIST2_ADDR_WD-1:2] mem5_addr_a;
+wire mem5_cen_a;
+wire [BIST_DATA_WD-1:0] mem5_din_b;
+
+// PORT-B
+wire mem5_clk_b;
+wire mem5_cen_b;
+wire mem5_web_b;
+wire [BIST_DATA_WD/8-1:0] mem5_mask_b;
+wire [BIST2_ADDR_WD-1:2] mem5_addr_b;
+wire [BIST_DATA_WD-1:0] mem5_dout_a;
+
+// towards memory MBIST6
+// PORT-A
+wire mem6_clk_a;
+wire [BIST2_ADDR_WD-1:2] mem6_addr_a;
+wire mem6_cen_a;
+wire [BIST_DATA_WD-1:0] mem6_din_b;
+
+// PORT-B
+wire mem6_clk_b;
+wire mem6_cen_b;
+wire mem6_web_b;
+wire [BIST_DATA_WD/8-1:0] mem6_mask_b;
+wire [BIST2_ADDR_WD-1:2] mem6_addr_b;
+wire [BIST_DATA_WD-1:0] mem6_dout_a;
+
+// towards memory MBIST7
+// PORT-A
+wire mem7_clk_a;
+wire [BIST2_ADDR_WD-1:2] mem7_addr_a;
+wire mem7_cen_a;
+wire [BIST_DATA_WD-1:0] mem7_din_b;
+
+// PORT-B
+wire mem7_clk_b;
+wire mem7_cen_b;
+wire mem7_web_b;
+wire [BIST_DATA_WD/8-1:0] mem7_mask_b;
+wire [BIST2_ADDR_WD-1:2] mem7_addr_b;
+wire [BIST_DATA_WD-1:0] mem7_dout_a;
+
+// towards memory MBIST8
+// PORT-A
+wire mem8_clk_a;
+wire [BIST2_ADDR_WD-1:2] mem8_addr_a;
+wire mem8_cen_a;
+wire [BIST_DATA_WD-1:0] mem8_din_b;
+
+// PORT-B
+wire mem8_clk_b;
+wire mem8_cen_b;
+wire mem8_web_b;
+wire [BIST_DATA_WD/8-1:0] mem8_mask_b;
+wire [BIST2_ADDR_WD-1:2] mem8_addr_b;
+wire [BIST_DATA_WD-1:0] mem8_dout_a;
+
+wire lbist_clk ;
+wire wbd_clk_wh ;
+wire wbd_clk_int ;
+wire wbd_clk_glbl_int ;
+wire wbd_clk_mbist1_int ;
+wire wbd_clk_mbist2_int ;
+wire wbd_clk_mbist3_int ;
+wire wbd_clk_mbist4_int ;
+wire wbd_clk_mbist5_int ;
+wire wbd_clk_mbist6_int ;
+wire wbd_clk_mbist7_int ;
+wire wbd_clk_mbist8_int ;
+wire wbd_clk_wi ;
+wire wbd_clk_glbl ; // clock for global reg
+wire wbd_clk_mbist1 ; // clock for global reg
+wire wbd_clk_mbist2 ; // clock for global reg
+wire wbd_clk_mbist3 ; // clock for global reg
+wire wbd_clk_mbist4 ; // clock for global reg
+wire wbd_clk_mbist5 ; // clock for global reg
+wire wbd_clk_mbist6 ; // clock for global reg
+wire wbd_clk_mbist7 ; // clock for global reg
+wire wbd_clk_mbist8 ; // clock for global reg
+
+wire [31:0] cfg_clk_ctrl1 ;
+wire [31:0] cfg_clk_ctrl2 ;
+
+// Scan Control Signal
+wire scan_clk ;
+wire scan_rst_n ;
+
+wire scan_mode ;
+wire scan_en ;
+wire [SCW-1:0] scan_in ;
+wire [SCW-1:0] scan_out ;
+
+wire scan_mode_glbl ;
+wire scan_en_glbl ;
+wire [SCW-1:0] scan_out_glbl ;
+
+wire scan_mode_wbi ;
+wire scan_en_wbi ;
+wire [SCW-1:0] scan_out_wbi ;
+
+wire scan_mode_mbist1 ;
+wire scan_en_mbist1 ;
+wire [SCW-1:0] scan_out_mbist1 ;
+
+wire scan_mode_mbist2 ;
+wire scan_en_mbist2 ;
+wire [SCW-1:0] scan_out_mbist2 ;
+
+wire scan_mode_mbist3 ;
+wire scan_en_mbist3 ;
+wire [SCW-1:0] scan_out_mbist3 ;
+
+wire scan_mode_mbist4 ;
+wire scan_en_mbist4 ;
+wire [SCW-1:0] scan_out_mbist4 ;
+
+wire scan_mode_mbist5 ;
+wire scan_en_mbist5 ;
+wire [SCW-1:0] scan_out_mbist5 ;
+
+wire scan_mode_mbist6 ;
+wire scan_en_mbist6 ;
+wire [SCW-1:0] scan_out_mbist6 ;
+
+wire scan_mode_mbist7 ;
+wire scan_en_mbist7 ;
+wire [SCW-1:0] scan_out_mbist7 ;
+
+wire scan_mode_mbist8 ;
+wire scan_en_mbist8 ;
+wire [SCW-1:0] scan_out_mbist8 ;
+
+////////////////////////////////////////////////////////////
+// Scan Tree Map
+///////////////////////////////////////////////////////////
+
+// WB_HOST(LBIST) => GLBL => MBIST5 => MBIST6 => MBIST7
+// => MBIST8 => WB_INTERCONNECT => MBIST4 => MBIST3
+// => MBIST2 => MBIST1 => WB_HOST(LBIST)
+
+/////////////////////////////////////////////////////////
+// Clock Skew Ctrl
+////////////////////////////////////////////////////////
+
+wire [3:0] cfg_cska_wh = cfg_clk_ctrl1[3:0];
+wire [3:0] cfg_cska_wi = cfg_clk_ctrl1[7:4];
+wire [3:0] cfg_cska_glbl = cfg_clk_ctrl1[11:8];
+wire [3:0] cfg_cska_lbist = cfg_clk_ctrl1[15:12];
+
+wire cfg_mem_lphase = cfg_clk_ctrl1[31]; // SRAM data lanuch phase selection
+
+wire [3:0] cfg_cska_mbist1 = cfg_clk_ctrl2[3:0];
+wire [3:0] cfg_cska_mbist2 = cfg_clk_ctrl2[7:4];
+wire [3:0] cfg_cska_mbist3 = cfg_clk_ctrl2[11:8];
+wire [3:0] cfg_cska_mbist4 = cfg_clk_ctrl2[15:12];
+wire [3:0] cfg_cska_mbist5 = cfg_clk_ctrl2[19:16];
+wire [3:0] cfg_cska_mbist6 = cfg_clk_ctrl2[23:20];
+wire [3:0] cfg_cska_mbist7 = cfg_clk_ctrl2[27:24];
+wire [3:0] cfg_cska_mbist8 = cfg_clk_ctrl2[31:28];
+
+wb_host
+ #(
+ `ifndef SYNTHESIS
+ .SCW(SCW) // SCAN CHAIN WIDTH
+ `endif
+ )
+ u_wb_host(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ .user_clock1 (wb_clk_i ),
+ .user_clock2 (user_clock2 ),
+ .user_irq (user_irq ),
+
+ // Master Port
+ .wbm_rst_i (wb_rst_i ),
+ .wbm_clk_i (wb_clk_i ),
+ .wbm_cyc_i (wbs_cyc_i ),
+ .wbm_stb_i (wbs_stb_i ),
+ .wbm_adr_i (wbs_adr_i ),
+ .wbm_we_i (wbs_we_i ),
+ .wbm_dat_i (wbs_dat_i ),
+ .wbm_sel_i (wbs_sel_i ),
+ .wbm_dat_o (wbs_dat_o ),
+ .wbm_ack_o (wbs_ack_o ),
+ .wbm_err_o ( ),
+
+ // Clock Skeq Adjust
+ .wbd_clk_int (wbd_clk_int ),
+ .wbd_clk_wh (wbd_clk_wh ),
+ .cfg_cska_wh (cfg_cska_wh ),
+
+ // Clock Skeq Adjust
+ .lbist_clk_int (lbist_clk ),
+ .lbist_clk_out (lbist_clk ),
+ .cfg_cska_lbist (cfg_cska_lbist ),
+
+ // Slave Port
+ .wbs_clk_out (wbd_clk_int ),
+ .wbs_clk_i (wbd_clk_wh ),
+ .wbs_cyc_o (wbd_int_cyc_i ),
+ .wbs_stb_o (wbd_int_stb_i ),
+ .wbs_adr_o (wbd_int_adr_i ),
+ .wbs_we_o (wbd_int_we_i ),
+ .wbs_dat_o (wbd_int_dat_i ),
+ .wbs_sel_o (wbd_int_sel_i ),
+ .wbs_dat_i (wbd_int_dat_o ),
+ .wbs_ack_i (wbd_int_ack_o ),
+ .wbs_err_i (wbd_int_err_o ),
+
+ .cfg_clk_ctrl1 (cfg_clk_ctrl1 ),
+ .cfg_clk_ctrl2 (cfg_clk_ctrl2 ),
+
+ .bist_rst_n (bist_rst_n ),
+ .wbd_int_rst_n (wbd_int_rst_n ),
+
+ .io_in (io_in[0] ),
+ .io_out (io_out ),
+ .io_oeb (io_oeb ),
+ .la_data_in (la_data_in[35:0] ),
+ .la_data_out (la_data_out ),
+
+
+ // Scan Control Signal
+ .scan_clk (scan_clk ),
+ .scan_rst_n (scan_rst_n ),
+ .scan_mode (scan_mode ),
+ .scan_en (scan_en ),
+ .scan_in (scan_in ),
+ .scan_out (scan_out_mbist1 )
+
+ );
+
+wb_interconnect #(
+ `ifndef SYNTHESIS
+ .SCW(SCW), // SCAN CHAIN WIDTH
+ .CH_CLK_WD(9),
+ .CH_DATA_WD(104)
+ `endif
+ )
+ u_intercon (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ // SCAN I/F
+ .scan_en (scan_en_mbist8 ),
+ .scan_mode (scan_mode_mbist8 ),
+ .scan_si (scan_out_mbist8 ),
+
+ .scan_en_o (scan_en_wbi ),
+ .scan_mode_o (scan_mode_wbi ),
+ .scan_so (scan_out_wbi ),
+ // Clock Skew adjust
+ .wbd_clk_int (wbd_clk_int ),
+ .cfg_cska_wi (cfg_cska_wi ),
+ .wbd_clk_wi (wbd_clk_wi ),
+
+ .ch_clk_in ({
+ wbd_clk_int,
+ wbd_clk_int,
+ wbd_clk_int,
+ wbd_clk_int,
+ wbd_clk_int,
+ wbd_clk_int,
+ wbd_clk_int,
+ wbd_clk_int,
+ wbd_clk_int}),
+ .ch_clk_out ({
+ wbd_clk_mbist8_int,
+ wbd_clk_mbist7_int,
+ wbd_clk_mbist6_int,
+ wbd_clk_mbist5_int,
+ wbd_clk_mbist4_int,
+ wbd_clk_mbist3_int,
+ wbd_clk_mbist2_int,
+ wbd_clk_mbist1_int,
+ wbd_clk_glbl_int
+ }),
+ .ch_data_in ({
+ bist_error_cnt7,
+ bist_correct[7],
+ bist_error[7],
+ bist_done[7],
+ bist_sdo[7],
+ bist_sdi[7],
+ bist_load[7],
+ bist_shift[7],
+ bist_run[7],
+ bist_en[7],
+
+ bist_error_cnt6,
+ bist_correct[6],
+ bist_error[6],
+ bist_done[6],
+ bist_sdo[6],
+ bist_sdi[6],
+ bist_load[6],
+ bist_shift[6],
+ bist_run[6],
+ bist_en[6],
+
+ bist_error_cnt5,
+ bist_correct[5],
+ bist_error[5],
+ bist_done[5],
+ bist_sdo[5],
+ bist_sdi[5],
+ bist_load[5],
+ bist_shift[5],
+ bist_run[5],
+ bist_en[5],
+
+ bist_error_cnt4,
+ bist_correct[4],
+ bist_error[4],
+ bist_done[4],
+ bist_sdo[4],
+ bist_sdi[4],
+ bist_load[4],
+ bist_shift[4],
+ bist_run[4],
+ bist_en[4],
+
+ bist_error_cnt3,
+ bist_correct[3],
+ bist_error[3],
+ bist_done[3],
+ bist_sdo[3],
+ bist_sdi[3],
+ bist_load[3],
+ bist_shift[3],
+ bist_run[3],
+ bist_en[3],
+
+ bist_error_cnt2,
+ bist_correct[2],
+ bist_error[2],
+ bist_done[2],
+ bist_sdo[2],
+ bist_sdi[2],
+ bist_load[2],
+ bist_shift[2],
+ bist_run[2],
+ bist_en[2],
+
+ bist_error_cnt1,
+ bist_correct[1],
+ bist_error[1],
+ bist_done[1],
+ bist_sdo[1],
+ bist_sdi[1],
+ bist_load[1],
+ bist_shift[1],
+ bist_run[1],
+ bist_en[1],
+
+ bist_error_cnt0,
+ bist_correct[0],
+ bist_error[0],
+ bist_done[0],
+ bist_sdo[0],
+ bist_sdi[0],
+ bist_load[0],
+ bist_shift[0],
+ bist_run[0],
+ bist_en[0]
+ } ),
+ .ch_data_out ({
+ bist_error_cnt7_int,
+ bist_correct_int[7],
+ bist_error_int[7],
+ bist_done_int[7],
+ bist_sdo_int[7],
+ bist_sdi_int[7],
+ bist_load_int[7],
+ bist_shift_int[7],
+ bist_run_int[7],
+ bist_en_int[7],
+
+ bist_error_cnt6_int,
+ bist_correct_int[6],
+ bist_error_int[6],
+ bist_done_int[6],
+ bist_sdo_int[6],
+ bist_sdi_int[6],
+ bist_load_int[6],
+ bist_shift_int[6],
+ bist_run_int[6],
+ bist_en_int[6],
+
+ bist_error_cnt5_int,
+ bist_correct_int[5],
+ bist_error_int[5],
+ bist_done_int[5],
+ bist_sdo_int[5],
+ bist_sdi_int[5],
+ bist_load_int[5],
+ bist_shift_int[5],
+ bist_run_int[5],
+ bist_en_int[5],
+
+ bist_error_cnt4_int,
+ bist_correct_int[4],
+ bist_error_int[4],
+ bist_done_int[4],
+ bist_sdo_int[4],
+ bist_sdi_int[4],
+ bist_load_int[4],
+ bist_shift_int[4],
+ bist_run_int[4],
+ bist_en_int[4],
+
+ bist_error_cnt3_int,
+ bist_correct_int[3],
+ bist_error_int[3],
+ bist_done_int[3],
+ bist_sdo_int[3],
+ bist_sdi_int[3],
+ bist_load_int[3],
+ bist_shift_int[3],
+ bist_run_int[3],
+ bist_en_int[3],
+
+ bist_error_cnt2_int,
+ bist_correct_int[2],
+ bist_error_int[2],
+ bist_done_int[2],
+ bist_sdo_int[2],
+ bist_sdi_int[2],
+ bist_load_int[2],
+ bist_shift_int[2],
+ bist_run_int[2],
+ bist_en_int[2],
+
+ bist_error_cnt1_int,
+ bist_correct_int[1],
+ bist_error_int[1],
+ bist_done_int[1],
+ bist_sdo_int[1],
+ bist_sdi_int[1],
+ bist_load_int[1],
+ bist_shift_int[1],
+ bist_run_int[1],
+ bist_en_int[1],
+
+ bist_error_cnt0_int,
+ bist_correct_int[0],
+ bist_error_int[0],
+ bist_done_int[0],
+ bist_sdo_int[0],
+ bist_sdi_int[0],
+ bist_load_int[0],
+ bist_shift_int[0],
+ bist_run_int[0],
+ bist_en_int[0]
+ }),
+
+ .clk_i (wbd_clk_wi ),
+ .rst_n (wbd_int_rst_n ),
+
+ // Master 0 Interface
+ .m0_wbd_dat_i (wbd_int_dat_i ),
+ .m0_wbd_adr_i (wbd_int_adr_i ),
+ .m0_wbd_sel_i (wbd_int_sel_i ),
+ .m0_wbd_we_i (wbd_int_we_i ),
+ .m0_wbd_cyc_i (wbd_int_cyc_i ),
+ .m0_wbd_stb_i (wbd_int_stb_i ),
+ .m0_wbd_dat_o (wbd_int_dat_o ),
+ .m0_wbd_ack_o (wbd_int_ack_o ),
+ .m0_wbd_err_o (wbd_int_err_o ),
+
+ // Slave 0 Interface
+ // .s0_wbd_err_i (1'b0 ), - Moved inside IP
+ .s0_wbd_dat_i (wbd_glbl_dat_i ),
+ .s0_wbd_ack_i (wbd_glbl_ack_i ),
+ .s0_wbd_dat_o (wbd_glbl_dat_o ),
+ .s0_wbd_adr_o (wbd_glbl_adr_o ),
+ .s0_wbd_sel_o (wbd_glbl_sel_o ),
+ .s0_wbd_we_o (wbd_glbl_we_o ),
+ .s0_wbd_cyc_o (wbd_glbl_cyc_o ),
+ .s0_wbd_stb_o (wbd_glbl_stb_o ),
+
+ // Slave 0 Interface
+ // .s0_wbd_err_i (1'b0 ), - Moved inside IP
+ .s1_wbd_dat_i (wbd_mbist1_dat_i ),
+ .s1_wbd_ack_i (wbd_mbist1_ack_i ),
+ .s1_wbd_dat_o (wbd_mbist1_dat_o ),
+ .s1_wbd_adr_o (wbd_mbist1_adr_o ),
+ .s1_wbd_sel_o (wbd_mbist1_sel_o ),
+ .s1_wbd_we_o (wbd_mbist1_we_o ),
+ .s1_wbd_cyc_o (wbd_mbist1_cyc_o ),
+ .s1_wbd_stb_o (wbd_mbist1_stb_o ),
+
+ // Slave 1 Interface
+ // .s1_wbd_err_i (1'b0 ), - Moved inside IP
+ .s2_wbd_dat_i (wbd_mbist2_dat_i ),
+ .s2_wbd_ack_i (wbd_mbist2_ack_i ),
+ .s2_wbd_dat_o (wbd_mbist2_dat_o ),
+ .s2_wbd_adr_o (wbd_mbist2_adr_o ),
+ .s2_wbd_sel_o (wbd_mbist2_sel_o ),
+ .s2_wbd_we_o (wbd_mbist2_we_o ),
+ .s2_wbd_cyc_o (wbd_mbist2_cyc_o ),
+ .s2_wbd_stb_o (wbd_mbist2_stb_o ),
+
+ // Slave 2 Interface
+ // .s2_wbd_err_i (1'b0 ), - Moved inside IP
+ .s3_wbd_dat_i (wbd_mbist3_dat_i ),
+ .s3_wbd_ack_i (wbd_mbist3_ack_i ),
+ .s3_wbd_dat_o (wbd_mbist3_dat_o ),
+ .s3_wbd_adr_o (wbd_mbist3_adr_o ),
+ .s3_wbd_sel_o (wbd_mbist3_sel_o ),
+ .s3_wbd_we_o (wbd_mbist3_we_o ),
+ .s3_wbd_cyc_o (wbd_mbist3_cyc_o ),
+ .s3_wbd_stb_o (wbd_mbist3_stb_o ),
+
+ // Slave 3 Interface
+ // .s3_wbd_err_i (1'b0 ), - Moved inside IP
+ .s4_wbd_dat_i (wbd_mbist4_dat_i ),
+ .s4_wbd_ack_i (wbd_mbist4_ack_i ),
+ .s4_wbd_dat_o (wbd_mbist4_dat_o ),
+ .s4_wbd_adr_o (wbd_mbist4_adr_o ),
+ .s4_wbd_sel_o (wbd_mbist4_sel_o ),
+ .s4_wbd_we_o (wbd_mbist4_we_o ),
+ .s4_wbd_cyc_o (wbd_mbist4_cyc_o ),
+ .s4_wbd_stb_o (wbd_mbist4_stb_o ),
+
+ // Slave 4 Interface
+ // .s0_wbd_err_i (1'b0 ), - Moved inside IP
+ .s5_wbd_dat_i (wbd_mbist5_dat_i ),
+ .s5_wbd_ack_i (wbd_mbist5_ack_i ),
+ .s5_wbd_dat_o (wbd_mbist5_dat_o ),
+ .s5_wbd_adr_o (wbd_mbist5_adr_o ),
+ .s5_wbd_sel_o (wbd_mbist5_sel_o ),
+ .s5_wbd_we_o (wbd_mbist5_we_o ),
+ .s5_wbd_cyc_o (wbd_mbist5_cyc_o ),
+ .s5_wbd_stb_o (wbd_mbist5_stb_o ),
+
+ // Slave 5 Interface
+ // .s6_wbd_err_i (1'b0 ), - Moved inside IP
+ .s6_wbd_dat_i (wbd_mbist6_dat_i ),
+ .s6_wbd_ack_i (wbd_mbist6_ack_i ),
+ .s6_wbd_dat_o (wbd_mbist6_dat_o ),
+ .s6_wbd_adr_o (wbd_mbist6_adr_o ),
+ .s6_wbd_sel_o (wbd_mbist6_sel_o ),
+ .s6_wbd_we_o (wbd_mbist6_we_o ),
+ .s6_wbd_cyc_o (wbd_mbist6_cyc_o ),
+ .s6_wbd_stb_o (wbd_mbist6_stb_o ),
+
+ // Slave 6 Interface
+ // .s7_wbd_err_i (1'b0 ), - Moved inside IP
+ .s7_wbd_dat_i (wbd_mbist7_dat_i ),
+ .s7_wbd_ack_i (wbd_mbist7_ack_i ),
+ .s7_wbd_dat_o (wbd_mbist7_dat_o ),
+ .s7_wbd_adr_o (wbd_mbist7_adr_o ),
+ .s7_wbd_sel_o (wbd_mbist7_sel_o ),
+ .s7_wbd_we_o (wbd_mbist7_we_o ),
+ .s7_wbd_cyc_o (wbd_mbist7_cyc_o ),
+ .s7_wbd_stb_o (wbd_mbist7_stb_o ),
+
+ // Slave 7 Interface
+ // .s8_wbd_err_i (1'b0 ), - Moved inside IP
+ .s8_wbd_dat_i (wbd_mbist8_dat_i ),
+ .s8_wbd_ack_i (wbd_mbist8_ack_i ),
+ .s8_wbd_dat_o (wbd_mbist8_dat_o ),
+ .s8_wbd_adr_o (wbd_mbist8_adr_o ),
+ .s8_wbd_sel_o (wbd_mbist8_sel_o ),
+ .s8_wbd_we_o (wbd_mbist8_we_o ),
+ .s8_wbd_cyc_o (wbd_mbist8_cyc_o ),
+ .s8_wbd_stb_o (wbd_mbist8_stb_o )
+ );
+
+
+glbl_cfg #(
+ `ifndef SYNTHESIS
+ .SCW(SCW) // SCAN CHAIN WIDTH
+ `endif
+ ) u_glbl(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ // SCAN I/F
+ .scan_en (scan_en ),
+ .scan_mode (scan_mode ),
+ .scan_si (scan_in ),
+
+ .scan_en_o (scan_en_glbl ),
+ .scan_mode_o (scan_mode_glbl ),
+ .scan_so (scan_out_glbl ),
+
+
+ .wbd_clk_int (wbd_clk_glbl_int ),
+ .cfg_cska_glbl (cfg_cska_glbl ),
+ .wbd_clk_glbl (wbd_clk_glbl ),
+
+ .mclk (wbd_clk_glbl ),
+ .reset_n (wbd_int_rst_n ),
+
+ // Reg Bus Interface Signal
+ .reg_cs (wbd_glbl_stb_o ),
+ .reg_wr (wbd_glbl_we_o ),
+ .reg_addr (wbd_glbl_adr_o ),
+ .reg_wdata (wbd_glbl_dat_o ),
+ .reg_be (wbd_glbl_sel_o ),
+
+ // Outputs
+ .reg_rdata (wbd_glbl_dat_i ),
+ .reg_ack (wbd_glbl_ack_i ),
+
+
+ // BIST I/F Outputs
+ .bist_en (bist_en),
+ .bist_run (bist_run),
+ .bist_load (bist_load),
+
+ .bist_sdi (bist_sdi),
+ .bist_shift (bist_shift),
+
+ // BIST Inputs
+ .bist_sdo (bist_sdo_int),
+ .bist_done (bist_done_int),
+ .bist_error (bist_error_int),
+ .bist_correct (bist_correct_int),
+ .bist_error_cnt0 (bist_error_cnt0_int),
+ .bist_error_cnt1 (bist_error_cnt1_int),
+ .bist_error_cnt2 (bist_error_cnt2_int),
+ .bist_error_cnt3 (bist_error_cnt3_int),
+ .bist_error_cnt4 (bist_error_cnt4_int),
+ .bist_error_cnt5 (bist_error_cnt5_int),
+ .bist_error_cnt6 (bist_error_cnt6_int),
+ .bist_error_cnt7 (bist_error_cnt7_int)
+
+ );
+
+
+//------------- MBIST1 - 512x32 ----
+
+mbist_top1 #(
+ `ifndef SYNTHESIS
+ .SCW (SCW), // SCAN CHAIN WIDTH
+ .BIST_ADDR_WD (BIST1_ADDR_WD-2 ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (9'h000 ),
+ .BIST_ADDR_END (9'h1FB ),
+ .BIST_REPAIR_ADDR_START (9'h1FC ),
+ .BIST_RAD_WD_I (BIST1_ADDR_WD-2 ),
+ .BIST_RAD_WD_O (BIST1_ADDR_WD-2 )
+ `endif
+ )
+ u_mbist1 (
+
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ // SCAN I/F
+ .scan_en (scan_en_mbist2 ),
+ .scan_mode (scan_mode_mbist2 ),
+ .scan_si (scan_out_mbist2 ),
+
+ .scan_en_o (scan_en_mbist1 ),
+ .scan_mode_o (scan_mode_mbist1 ),
+ .scan_so (scan_out_mbist1 ),
+
+ .cfg_mem_lphase (cfg_mem_lphase ),
+
+ // Clock Skew adjust
+ .wbd_clk_int (wbd_clk_mbist1_int),
+ .cfg_cska_mbist (cfg_cska_mbist1 ),
+ .wbd_clk_mbist (wbd_clk_mbist1 ),
+
+ // WB I/F
+ .wb_clk_i (wbd_clk_mbist1 ),
+ .wb_cyc_i (wbd_mbist1_cyc_o),
+ .wb_stb_i (wbd_mbist1_stb_o),
+ .wb_adr_i (wbd_mbist1_adr_o[BIST1_ADDR_WD-1:2]),
+ .wb_we_i (wbd_mbist1_we_o ),
+ .wb_dat_i (wbd_mbist1_dat_o),
+ .wb_sel_i (wbd_mbist1_sel_o),
+ .wb_dat_o (wbd_mbist1_dat_i),
+ .wb_ack_o (wbd_mbist1_ack_i),
+ .wb_err_o ( ),
+
+ .rst_n (bist_rst_n ),
+
+
+ .bist_en (bist_en_int[0] ),
+ .bist_run (bist_run_int[0] ),
+ .bist_shift (bist_shift_int[0] ),
+ .bist_load (bist_load_int[0] ),
+ .bist_sdi (bist_sdi_int[0] ),
+
+ .bist_error_cnt (bist_error_cnt0 ),
+ .bist_correct (bist_correct[0] ),
+ .bist_error (bist_error[0] ),
+ .bist_done (bist_done[0] ),
+ .bist_sdo (bist_sdo[0] ),
+
+ // towards memory
+ // PORT-A
+ .mem_clk_a (mem1_clk_a ),
+ .mem_addr_a (mem1_addr_a ),
+ .mem_cen_a (mem1_cen_a ),
+ .mem_dout_a (mem1_dout_a ),
+ // PORT-B
+ .mem_clk_b (mem1_clk_b ),
+ .mem_cen_b (mem1_cen_b ),
+ .mem_web_b (mem1_web_b ),
+ .mem_mask_b (mem1_mask_b ),
+ .mem_addr_b (mem1_addr_b ),
+ .mem_din_b (mem1_din_b )
+
+
+);
+
+sky130_sram_2kbyte_1rw1r_32x512_8 u_sram1_2kb(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1),// User area 1 1.8V supply
+ .vssd1 (vssd1),// User area 1 digital ground
+`endif
+// Port 0: RW
+ .clk0 (mem1_clk_b),
+ .csb0 (mem1_cen_b),
+ .web0 (mem1_web_b),
+ .wmask0 (mem1_mask_b),
+ .addr0 (mem1_addr_b),
+ .din0 (mem1_din_b),
+ .dout0 (),
+// Port 1: R
+ .clk1 (mem1_clk_a),
+ .csb1 (mem1_cen_a),
+ .addr1 (mem1_addr_a),
+ .dout1 (mem1_dout_a)
+ );
+
+//------------- MBIST2 - 512x32 ----
+
+mbist_top1 #(
+ `ifndef SYNTHESIS
+ .SCW (SCW), // SCAN CHAIN WIDTH
+ .BIST_ADDR_WD (BIST1_ADDR_WD-2 ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (9'h000 ),
+ .BIST_ADDR_END (9'h1FB ),
+ .BIST_REPAIR_ADDR_START (9'h1FC ),
+ .BIST_RAD_WD_I (BIST1_ADDR_WD-2 ),
+ .BIST_RAD_WD_O (BIST1_ADDR_WD-2 )
+ `endif
+ )
+ u_mbist2 (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ // SCAN I/F
+ .scan_en (scan_en_mbist3 ),
+ .scan_mode (scan_mode_mbist3 ),
+ .scan_si (scan_out_mbist3 ),
+
+ .scan_en_o (scan_en_mbist2 ),
+ .scan_mode_o (scan_mode_mbist2 ),
+ .scan_so (scan_out_mbist2 ),
+
+ .cfg_mem_lphase (cfg_mem_lphase ),
+
+ // Clock Skew adjust
+ .wbd_clk_int (wbd_clk_mbist2_int),
+ .cfg_cska_mbist (cfg_cska_mbist2 ),
+ .wbd_clk_mbist (wbd_clk_mbist2 ),
+
+ // WB I/F
+ .wb_clk_i (wbd_clk_mbist2 ),
+ .wb_cyc_i (wbd_mbist2_cyc_o),
+ .wb_stb_i (wbd_mbist2_stb_o),
+ .wb_adr_i (wbd_mbist2_adr_o[BIST1_ADDR_WD-1:2]),
+ .wb_we_i (wbd_mbist2_we_o ),
+ .wb_dat_i (wbd_mbist2_dat_o),
+ .wb_sel_i (wbd_mbist2_sel_o),
+ .wb_dat_o (wbd_mbist2_dat_i),
+ .wb_ack_o (wbd_mbist2_ack_i),
+ .wb_err_o ( ),
+
+ .rst_n (bist_rst_n ),
+
+
+ .bist_en (bist_en_int[1] ),
+ .bist_run (bist_run_int[1] ),
+ .bist_shift (bist_shift_int[1] ),
+ .bist_load (bist_load_int[1] ),
+ .bist_sdi (bist_sdi_int[1] ),
+
+ .bist_error_cnt (bist_error_cnt1 ),
+ .bist_correct (bist_correct[1] ),
+ .bist_error (bist_error[1] ),
+ .bist_done (bist_done[1] ),
+ .bist_sdo (bist_sdo[1] ),
+
+ // towards memory
+ // PORT-A
+ .mem_clk_a (mem2_clk_a ),
+ .mem_addr_a (mem2_addr_a ),
+ .mem_cen_a (mem2_cen_a ),
+ .mem_dout_a (mem2_dout_a ),
+ // PORT-B
+ .mem_clk_b (mem2_clk_b ),
+ .mem_cen_b (mem2_cen_b ),
+ .mem_web_b (mem2_web_b ),
+ .mem_mask_b (mem2_mask_b ),
+ .mem_addr_b (mem2_addr_b ),
+ .mem_din_b (mem2_din_b )
+
+
+);
+
+sky130_sram_2kbyte_1rw1r_32x512_8 u_sram2_2kb(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1),// User area 1 1.8V supply
+ .vssd1 (vssd1),// User area 1 digital ground
+`endif
+// Port 0: RW
+ .clk0 (mem2_clk_b),
+ .csb0 (mem2_cen_b),
+ .web0 (mem2_web_b),
+ .wmask0 (mem2_mask_b),
+ .addr0 (mem2_addr_b),
+ .din0 (mem2_din_b),
+ .dout0 (),
+// Port 1: R
+ .clk1 (mem2_clk_a),
+ .csb1 (mem2_cen_a),
+ .addr1 (mem2_addr_a),
+ .dout1 (mem2_dout_a)
+ );
+
+//------------- MBIST3 - 512x32 ----
+
+mbist_top1 #(
+ `ifndef SYNTHESIS
+ .SCW (SCW), // SCAN CHAIN WIDTH
+ .BIST_ADDR_WD (BIST1_ADDR_WD-2 ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (9'h000 ),
+ .BIST_ADDR_END (9'h1FB ),
+ .BIST_REPAIR_ADDR_START (9'h1FC ),
+ .BIST_RAD_WD_I (BIST1_ADDR_WD-2 ),
+ .BIST_RAD_WD_O (BIST1_ADDR_WD-2 )
+ `endif
+ )
+ u_mbist3 (
+
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ // SCAN I/F
+ .scan_en (scan_en_mbist4 ),
+ .scan_mode (scan_mode_mbist4 ),
+ .scan_si (scan_out_mbist4 ),
+
+ .scan_en_o (scan_en_mbist3 ),
+ .scan_mode_o (scan_mode_mbist3 ),
+ .scan_so (scan_out_mbist3 ),
+
+ .cfg_mem_lphase (cfg_mem_lphase ),
+
+ // Clock Skew adjust
+ .wbd_clk_int (wbd_clk_mbist3_int ),
+ .cfg_cska_mbist (cfg_cska_mbist3 ),
+ .wbd_clk_mbist (wbd_clk_mbist3 ),
+
+ // WB I/F
+ .wb_clk_i (wbd_clk_mbist3 ),
+ .wb_cyc_i (wbd_mbist3_cyc_o),
+ .wb_stb_i (wbd_mbist3_stb_o),
+ .wb_adr_i (wbd_mbist3_adr_o[BIST1_ADDR_WD-1:2]),
+ .wb_we_i (wbd_mbist3_we_o ),
+ .wb_dat_i (wbd_mbist3_dat_o),
+ .wb_sel_i (wbd_mbist3_sel_o),
+ .wb_dat_o (wbd_mbist3_dat_i),
+ .wb_ack_o (wbd_mbist3_ack_i),
+ .wb_err_o ( ),
+
+ .rst_n (bist_rst_n ),
+
+
+ .bist_en (bist_en_int[2] ),
+ .bist_run (bist_run_int[2] ),
+ .bist_shift (bist_shift_int[2]),
+ .bist_load (bist_load_int[2] ),
+ .bist_sdi (bist_sdi_int[2] ),
+
+ .bist_error_cnt (bist_error_cnt2 ),
+ .bist_correct (bist_correct[2] ),
+ .bist_error (bist_error[2] ),
+ .bist_done (bist_done[2] ),
+ .bist_sdo (bist_sdo[2] ),
+
+ // towards memory
+ // PORT-A
+ .mem_clk_a (mem3_clk_a ),
+ .mem_addr_a (mem3_addr_a ),
+ .mem_cen_a (mem3_cen_a ),
+ .mem_dout_a (mem3_dout_a ),
+ // PORT-B
+ .mem_clk_b (mem3_clk_b ),
+ .mem_cen_b (mem3_cen_b ),
+ .mem_web_b (mem3_web_b ),
+ .mem_mask_b (mem3_mask_b ),
+ .mem_addr_b (mem3_addr_b ),
+ .mem_din_b (mem3_din_b )
+
+
+);
+
+sky130_sram_2kbyte_1rw1r_32x512_8 u_sram3_2kb(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1),// User area 1 1.8V supply
+ .vssd1 (vssd1),// User area 1 digital ground
+`endif
+// Port 0: RW
+ .clk0 (mem3_clk_b),
+ .csb0 (mem3_cen_b),
+ .web0 (mem3_web_b),
+ .wmask0 (mem3_mask_b),
+ .addr0 (mem3_addr_b),
+ .din0 (mem3_din_b),
+ .dout0 (),
+// Port 1: R
+ .clk1 (mem3_clk_a),
+ .csb1 (mem3_cen_a),
+ .addr1 (mem3_addr_a),
+ .dout1 (mem3_dout_a)
+ );
+
+//------------- MBIST4 - 512x32 ----
+
+mbist_top1 #(
+ `ifndef SYNTHESIS
+ .SCW (SCW), // SCAN CHAIN WIDTH
+ .BIST_ADDR_WD (BIST1_ADDR_WD-2 ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (9'h000 ),
+ .BIST_ADDR_END (9'h1FB ),
+ .BIST_REPAIR_ADDR_START (9'h1FC ),
+ .BIST_RAD_WD_I (BIST1_ADDR_WD-2 ),
+ .BIST_RAD_WD_O (BIST1_ADDR_WD-2 )
+ `endif
+ )
+ u_mbist4 (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ // SCAN I/F
+ .scan_en (scan_en_wbi ),
+ .scan_mode (scan_mode_wbi ),
+ .scan_si (scan_out_wbi ),
+
+ .scan_en_o (scan_en_mbist4 ),
+ .scan_mode_o (scan_mode_mbist4 ),
+ .scan_so (scan_out_mbist4 ),
+
+ .cfg_mem_lphase (cfg_mem_lphase ),
+
+ // Clock Skew adjust
+ .wbd_clk_int (wbd_clk_mbist4_int ),
+ .cfg_cska_mbist (cfg_cska_mbist4 ),
+ .wbd_clk_mbist (wbd_clk_mbist4 ),
+
+ // WB I/F
+ .wb_clk_i (wbd_clk_mbist4 ),
+ .wb_cyc_i (wbd_mbist4_cyc_o),
+ .wb_stb_i (wbd_mbist4_stb_o),
+ .wb_adr_i (wbd_mbist4_adr_o[BIST1_ADDR_WD-1:2]),
+ .wb_we_i (wbd_mbist4_we_o ),
+ .wb_dat_i (wbd_mbist4_dat_o),
+ .wb_sel_i (wbd_mbist4_sel_o),
+ .wb_dat_o (wbd_mbist4_dat_i),
+ .wb_ack_o (wbd_mbist4_ack_i),
+ .wb_err_o ( ),
+
+ .rst_n (bist_rst_n ),
+
+
+ .bist_en (bist_en_int[3] ),
+ .bist_run (bist_run_int[3] ),
+ .bist_shift (bist_shift_int[3] ),
+ .bist_load (bist_load_int[3] ),
+ .bist_sdi (bist_sdi_int[3] ),
+
+ .bist_error_cnt (bist_error_cnt3 ),
+ .bist_correct (bist_correct[3] ),
+ .bist_error (bist_error[3] ),
+ .bist_done (bist_done[3] ),
+ .bist_sdo (bist_sdo[3] ),
+
+ // towards memory
+ // PORT-A
+ .mem_clk_a (mem4_clk_a ),
+ .mem_addr_a (mem4_addr_a ),
+ .mem_cen_a (mem4_cen_a ),
+ .mem_dout_a (mem4_dout_a ),
+ // PORT-B
+ .mem_clk_b (mem4_clk_b ),
+ .mem_cen_b (mem4_cen_b ),
+ .mem_web_b (mem4_web_b ),
+ .mem_mask_b (mem4_mask_b ),
+ .mem_addr_b (mem4_addr_b ),
+ .mem_din_b (mem4_din_b )
+
+
+);
+
+sky130_sram_2kbyte_1rw1r_32x512_8 u_sram4_2kb(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1),// User area 1 1.8V supply
+ .vssd1 (vssd1),// User area 1 digital ground
+`endif
+// Port 0: RW
+ .clk0 (mem4_clk_b),
+ .csb0 (mem4_cen_b),
+ .web0 (mem4_web_b),
+ .wmask0 (mem4_mask_b),
+ .addr0 (mem4_addr_b),
+ .din0 (mem4_din_b),
+ .dout0 (),
+// Port 1: R
+ .clk1 (mem4_clk_a),
+ .csb1 (mem4_cen_a),
+ .addr1 (mem4_addr_a),
+ .dout1 (mem4_dout_a)
+ );
+
+//------------- MBIST5 - 256x32 ----
+
+mbist_top2 #(
+ `ifndef SYNTHESIS
+ .SCW (SCW), // SCAN CHAIN WIDTH
+ .BIST_ADDR_WD (BIST2_ADDR_WD-2 ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (8'h00 ),
+ .BIST_ADDR_END (8'hFB ),
+ .BIST_REPAIR_ADDR_START (8'hFC ),
+ .BIST_RAD_WD_I (BIST2_ADDR_WD-2 ),
+ .BIST_RAD_WD_O (BIST2_ADDR_WD-2 )
+ `endif
+ )
+ u_mbist5 (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ // SCAN I/F
+ .scan_en (scan_en_glbl ),
+ .scan_mode (scan_mode_glbl ),
+ .scan_si (scan_out_glbl ),
+
+ .scan_en_o (scan_en_mbist5 ),
+ .scan_mode_o (scan_mode_mbist5 ),
+ .scan_so (scan_out_mbist5 ),
+
+ .cfg_mem_lphase (cfg_mem_lphase ),
+
+ // Clock Skew adjust
+ .wbd_clk_int (wbd_clk_mbist5_int ),
+ .cfg_cska_mbist (cfg_cska_mbist5 ),
+ .wbd_clk_mbist (wbd_clk_mbist5 ),
+
+ // WB I/F
+ .wb_clk_i (wbd_clk_mbist5 ),
+ .wb_cyc_i (wbd_mbist5_cyc_o),
+ .wb_stb_i (wbd_mbist5_stb_o),
+ .wb_adr_i (wbd_mbist5_adr_o[BIST2_ADDR_WD-1:2]),
+ .wb_we_i (wbd_mbist5_we_o ),
+ .wb_dat_i (wbd_mbist5_dat_o),
+ .wb_sel_i (wbd_mbist5_sel_o),
+ .wb_dat_o (wbd_mbist5_dat_i),
+ .wb_ack_o (wbd_mbist5_ack_i),
+ .wb_err_o ( ),
+
+ .rst_n (bist_rst_n ),
+
+
+ .bist_en (bist_en_int[4] ),
+ .bist_run (bist_run_int[4] ),
+ .bist_shift (bist_shift_int[4]),
+ .bist_load (bist_load_int[4] ),
+ .bist_sdi (bist_sdi_int[4] ),
+
+ .bist_error_cnt (bist_error_cnt4 ),
+ .bist_correct (bist_correct[4] ),
+ .bist_error (bist_error[4] ),
+ .bist_done (bist_done[4] ),
+ .bist_sdo (bist_sdo[4] ),
+
+
+ // towards memory
+ // PORT-A
+ .mem_clk_a (mem5_clk_a ),
+ .mem_addr_a (mem5_addr_a ),
+ .mem_cen_a (mem5_cen_a ),
+ .mem_dout_a (mem5_dout_a ),
+ // PORT-B
+ .mem_clk_b (mem5_clk_b ),
+ .mem_cen_b (mem5_cen_b ),
+ .mem_web_b (mem5_web_b ),
+ .mem_mask_b (mem5_mask_b ),
+ .mem_addr_b (mem5_addr_b ),
+ .mem_din_b (mem5_din_b )
+
+
+);
+
+sky130_sram_1kbyte_1rw1r_32x256_8 u_sram5_1kb(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1),// User area 1 1.8V supply
+ .vssd1 (vssd1),// User area 1 digital ground
+`endif
+// Port 0: RW
+ .clk0 (mem5_clk_b),
+ .csb0 (mem5_cen_b),
+ .web0 (mem5_web_b),
+ .wmask0 (mem5_mask_b),
+ .addr0 (mem5_addr_b),
+ .din0 (mem5_din_b),
+ .dout0 (),
+// Port 1: R
+ .clk1 (mem5_clk_a),
+ .csb1 (mem5_cen_a),
+ .addr1 (mem5_addr_a),
+ .dout1 (mem5_dout_a)
+ );
+
+//------------- MBIST6 - 256x32 ----
+
+mbist_top2 #(
+ `ifndef SYNTHESIS
+ .SCW (SCW), // SCAN CHAIN WIDTH
+ .BIST_ADDR_WD (BIST2_ADDR_WD-2 ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (8'h00 ),
+ .BIST_ADDR_END (8'hFB ),
+ .BIST_REPAIR_ADDR_START (8'hFC ),
+ .BIST_RAD_WD_I (BIST2_ADDR_WD-2 ),
+ .BIST_RAD_WD_O (BIST2_ADDR_WD-2 )
+ `endif
+ )
+ u_mbist6 (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ // SCAN I/F
+ .scan_en (scan_en_mbist5 ),
+ .scan_mode (scan_mode_mbist5 ),
+ .scan_si (scan_out_mbist5 ),
+
+ .scan_en_o (scan_en_mbist6 ),
+ .scan_mode_o (scan_mode_mbist6 ),
+ .scan_so (scan_out_mbist6 ),
+
+ .cfg_mem_lphase (cfg_mem_lphase ),
+
+ // Clock Skew adjust
+ .wbd_clk_int (wbd_clk_mbist6_int ),
+ .cfg_cska_mbist (cfg_cska_mbist6 ),
+ .wbd_clk_mbist (wbd_clk_mbist6 ),
+
+ // WB I/F
+ .wb_clk_i (wbd_clk_mbist6 ),
+ .wb_cyc_i (wbd_mbist6_cyc_o),
+ .wb_stb_i (wbd_mbist6_stb_o),
+ .wb_adr_i (wbd_mbist6_adr_o[BIST2_ADDR_WD-1:2]),
+ .wb_we_i (wbd_mbist6_we_o ),
+ .wb_dat_i (wbd_mbist6_dat_o),
+ .wb_sel_i (wbd_mbist6_sel_o),
+ .wb_dat_o (wbd_mbist6_dat_i),
+ .wb_ack_o (wbd_mbist6_ack_i),
+ .wb_err_o ( ),
+
+ .rst_n (bist_rst_n ),
+
+
+ .bist_en (bist_en_int[5] ),
+ .bist_run (bist_run_int[5] ),
+ .bist_shift (bist_shift_int[5]),
+ .bist_load (bist_load_int[5] ),
+ .bist_sdi (bist_sdi_int[5] ),
+
+ .bist_error_cnt (bist_error_cnt5 ),
+ .bist_correct (bist_correct[5] ),
+ .bist_error (bist_error[5] ),
+ .bist_done (bist_done[5] ),
+ .bist_sdo (bist_sdo[5] ),
+
+ // towards memory
+ // PORT-A
+ .mem_clk_a (mem6_clk_a ),
+ .mem_addr_a (mem6_addr_a ),
+ .mem_cen_a (mem6_cen_a ),
+ .mem_dout_a (mem6_dout_a ),
+ // PORT-B
+ .mem_clk_b (mem6_clk_b ),
+ .mem_cen_b (mem6_cen_b ),
+ .mem_web_b (mem6_web_b ),
+ .mem_mask_b (mem6_mask_b ),
+ .mem_addr_b (mem6_addr_b ),
+ .mem_din_b (mem6_din_b )
+
+
+);
+
+sky130_sram_1kbyte_1rw1r_32x256_8 u_sram6_1kb(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1),// User area 1 1.8V supply
+ .vssd1 (vssd1),// User area 1 digital ground
+`endif
+// Port 0: RW
+ .clk0 (mem6_clk_b),
+ .csb0 (mem6_cen_b),
+ .web0 (mem6_web_b),
+ .wmask0 (mem6_mask_b),
+ .addr0 (mem6_addr_b),
+ .din0 (mem6_din_b),
+ .dout0 (),
+// Port 1: R
+ .clk1 (mem6_clk_a),
+ .csb1 (mem6_cen_a),
+ .addr1 (mem6_addr_a),
+ .dout1 (mem6_dout_a)
+ );
+//------------- MBIST7 - 256x32 ----
+
+mbist_top2 #(
+ `ifndef SYNTHESIS
+ .SCW (SCW), // SCAN CHAIN WIDTH
+ .BIST_ADDR_WD (BIST2_ADDR_WD-2 ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (8'h00 ),
+ .BIST_ADDR_END (8'hFB ),
+ .BIST_REPAIR_ADDR_START (8'hFC ),
+ .BIST_RAD_WD_I (BIST2_ADDR_WD-2 ),
+ .BIST_RAD_WD_O (BIST2_ADDR_WD-2 )
+ `endif
+ )
+ u_mbist7 (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ // SCAN I/F
+ .scan_en (scan_en_mbist6 ),
+ .scan_mode (scan_mode_mbist6 ),
+ .scan_si (scan_out_mbist6 ),
+
+ .scan_en_o (scan_en_mbist7 ),
+ .scan_mode_o (scan_mode_mbist7 ),
+ .scan_so (scan_out_mbist7 ),
+
+ .cfg_mem_lphase (cfg_mem_lphase ),
+ // Clock Skew adjust
+ .wbd_clk_int (wbd_clk_mbist7_int ),
+ .cfg_cska_mbist (cfg_cska_mbist7 ),
+ .wbd_clk_mbist (wbd_clk_mbist7 ),
+
+ // WB I/F
+ .wb_clk_i (wbd_clk_mbist7 ),
+ .wb_cyc_i (wbd_mbist7_cyc_o),
+ .wb_stb_i (wbd_mbist7_stb_o),
+ .wb_adr_i (wbd_mbist7_adr_o[BIST2_ADDR_WD-1:2]),
+ .wb_we_i (wbd_mbist7_we_o ),
+ .wb_dat_i (wbd_mbist7_dat_o),
+ .wb_sel_i (wbd_mbist7_sel_o),
+ .wb_dat_o (wbd_mbist7_dat_i),
+ .wb_ack_o (wbd_mbist7_ack_i),
+ .wb_err_o ( ),
+
+ .rst_n (bist_rst_n ),
+
+
+ .bist_en (bist_en_int[6] ),
+ .bist_run (bist_run_int[6] ),
+ .bist_shift (bist_shift_int[6]),
+ .bist_load (bist_load_int[6] ),
+ .bist_sdi (bist_sdi_int[6] ),
+
+ .bist_error_cnt (bist_error_cnt6 ),
+ .bist_correct (bist_correct[6] ),
+ .bist_error (bist_error[6] ),
+ .bist_done (bist_done[6] ),
+ .bist_sdo (bist_sdo[6] ),
+
+
+ // towards memory
+ // PORT-A
+ .mem_clk_a (mem7_clk_a ),
+ .mem_addr_a (mem7_addr_a ),
+ .mem_cen_a (mem7_cen_a ),
+ .mem_dout_a (mem7_dout_a ),
+ // PORT-B
+ .mem_clk_b (mem7_clk_b ),
+ .mem_cen_b (mem7_cen_b ),
+ .mem_web_b (mem7_web_b ),
+ .mem_mask_b (mem7_mask_b ),
+ .mem_addr_b (mem7_addr_b ),
+ .mem_din_b (mem7_din_b )
+
+
+);
+
+sky130_sram_1kbyte_1rw1r_32x256_8 u_sram7_1kb(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1),// User area 1 1.8V supply
+ .vssd1 (vssd1),// User area 1 digital ground
+`endif
+// Port 0: RW
+ .clk0 (mem7_clk_b),
+ .csb0 (mem7_cen_b),
+ .web0 (mem7_web_b),
+ .wmask0 (mem7_mask_b),
+ .addr0 (mem7_addr_b),
+ .din0 (mem7_din_b),
+ .dout0 (),
+// Port 1: R
+ .clk1 (mem7_clk_a),
+ .csb1 (mem7_cen_a),
+ .addr1 (mem7_addr_a),
+ .dout1 (mem7_dout_a)
+ );
+
+//------------- MBIST6 - 256x32 ----
+
+mbist_top2 #(
+ `ifndef SYNTHESIS
+ .SCW (SCW), // SCAN CHAIN WIDTH
+ .BIST_ADDR_WD (BIST2_ADDR_WD-2 ),
+ .BIST_DATA_WD (BIST_DATA_WD ),
+ .BIST_ADDR_START (8'h00 ),
+ .BIST_ADDR_END (8'hFB ),
+ .BIST_REPAIR_ADDR_START (8'hFC ),
+ .BIST_RAD_WD_I (BIST2_ADDR_WD-2 ),
+ .BIST_RAD_WD_O (BIST2_ADDR_WD-2 )
+ `endif
+ )
+ u_mbist8 (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ // SCAN I/F
+ .scan_en (scan_en_mbist7 ),
+ .scan_mode (scan_mode_mbist7 ),
+ .scan_si (scan_out_mbist7 ),
+
+ .scan_en_o (scan_en_mbist8 ),
+ .scan_mode_o (scan_mode_mbist8 ),
+ .scan_so (scan_out_mbist8 ),
+
+ .cfg_mem_lphase (cfg_mem_lphase ),
+
+ // Clock Skew adjust
+ .wbd_clk_int (wbd_clk_mbist8_int),
+ .cfg_cska_mbist (cfg_cska_mbist8 ),
+ .wbd_clk_mbist (wbd_clk_mbist8 ),
+
+ // WB I/F
+ .wb_clk_i (wbd_clk_mbist8 ),
+ .wb_cyc_i (wbd_mbist8_cyc_o),
+ .wb_stb_i (wbd_mbist8_stb_o),
+ .wb_adr_i (wbd_mbist8_adr_o[BIST2_ADDR_WD-1:2]),
+ .wb_we_i (wbd_mbist8_we_o ),
+ .wb_dat_i (wbd_mbist8_dat_o),
+ .wb_sel_i (wbd_mbist8_sel_o),
+ .wb_dat_o (wbd_mbist8_dat_i),
+ .wb_ack_o (wbd_mbist8_ack_i),
+ .wb_err_o ( ),
+
+ .rst_n (bist_rst_n ),
+
+
+ .bist_en (bist_en_int[7] ),
+ .bist_run (bist_run_int[7] ),
+ .bist_shift (bist_shift_int[7]),
+ .bist_load (bist_load_int[7] ),
+ .bist_sdi (bist_sdi_int[7] ),
+
+ .bist_error_cnt (bist_error_cnt7 ),
+ .bist_correct (bist_correct[7] ),
+ .bist_error (bist_error[7] ),
+ .bist_done (bist_done[7] ),
+ .bist_sdo (bist_sdo[7] ),
+
+ // towards memory
+ // PORT-A
+ .mem_clk_a (mem8_clk_a ),
+ .mem_addr_a (mem8_addr_a ),
+ .mem_cen_a (mem8_cen_a ),
+ .mem_dout_a (mem8_dout_a ),
+ // PORT-B
+ .mem_clk_b (mem8_clk_b ),
+ .mem_cen_b (mem8_cen_b ),
+ .mem_web_b (mem8_web_b ),
+ .mem_mask_b (mem8_mask_b ),
+ .mem_addr_b (mem8_addr_b ),
+ .mem_din_b (mem8_din_b )
+
+
+);
+
+sky130_sram_1kbyte_1rw1r_32x256_8 u_sram8_1kb(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1),// User area 1 1.8V supply
+ .vssd1 (vssd1),// User area 1 digital ground
+`endif
+// Port 0: RW
+ .clk0 (mem8_clk_b),
+ .csb0 (mem8_cen_b),
+ .web0 (mem8_web_b),
+ .wmask0 (mem8_mask_b),
+ .addr0 (mem8_addr_b),
+ .din0 (mem8_din_b),
+ .dout0 (),
+// Port 1: R
+ .clk1 (mem8_clk_a),
+ .csb1 (mem8_cen_a),
+ .addr1 (mem8_addr_a),
+ .dout1 (mem8_dout_a)
+ );
+
+endmodule // user_project_wrapper
+
+`default_nettype wire
diff --git a/verilog/rtl/user_reg_map.v b/verilog/rtl/user_reg_map.v
new file mode 100644
index 0000000..0868a11
--- /dev/null
+++ b/verilog/rtl/user_reg_map.v
@@ -0,0 +1,47 @@
+
+// Note in caravel, 0x300X_XXXX only come to user interface
+// So, using wb_host bank select we have changing MSB address [31:16] = 0x1000
+//
+`define ADDR_SPACE_WBHOST 32'h3008_0000
+`define ADDR_SPACE_LBIST 32'h300C_0000
+`define ADDR_SPACE_GLBL 32'h3000_0000
+`define ADDR_SPACE_MBIST1 32'h3000_1000
+`define ADDR_SPACE_MBIST2 32'h3000_2000
+`define ADDR_SPACE_MBIST3 32'h3000_3000
+`define ADDR_SPACE_MBIST4 32'h3000_4000
+`define ADDR_SPACE_MBIST5 32'h3000_5000
+`define ADDR_SPACE_MBIST6 32'h3000_6000
+`define ADDR_SPACE_MBIST7 32'h3000_7000
+`define ADDR_SPACE_MBIST8 32'h3000_8000
+
+//--------------------------------------------------
+// WB Host Register
+//--------------------------------------------------
+`define WBHOST_GLBL_CFG 8'h00 // reg_0 - Global Config
+`define WBHOST_BANK_SEL 8'h04 // reg_1 - Bank Select
+`define WBHOST_CLK_CTRL1 8'h08 // reg_2 - Clock Control-1
+`define WBHOST_CLK_CTRL2 8'h0C // reg_3 - Clock Control-2
+
+//--------------------------------------------------
+// LBIST Register
+//--------------------------------------------------
+`define LBIST_CTRL1 8'h00
+`define LBIST_CTRL2 8'h04
+`define LBIST_SIG 8'h08
+
+//-------------------------------------------------
+// GLBL Register
+//-------------------------------------------------
+
+`define GLBL_BIST_CTRL1 'h08
+`define GLBL_BIST_CTRL2 'h0C
+`define GLBL_BIST_STAT1 'h10
+`define GLBL_BIST_STAT2 'h14
+`define GLBL_BIST_SWDATA 'h18
+`define GLBL_BIST_SRDATA 'h1C
+`define GLBL_BIST_SPDATA 'h20
+`define GLBL_BIST_SOFT1 'h24
+`define GLBL_BIST_SOFT2 'h28
+`define GLBL_BIST_SOFT3 'h2C
+
+
diff --git a/verilog/rtl/wb_host/src/run_iverilog b/verilog/rtl/wb_host/src/run_iverilog
new file mode 100755
index 0000000..f3b96e3
--- /dev/null
+++ b/verilog/rtl/wb_host/src/run_iverilog
@@ -0,0 +1,10 @@
+iverilog -g2005-sv \
+wb_host.sv \
+../../lib/async_wb.sv \
+../../lib/async_fifo.sv \
+../../lib/clk_ctl.v \
+../../lib/ctech_cells.sv \
+../../lib/registers.v \
+../../clk_skew_adjust/src/clk_skew_adjust.gv \
+$PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v \
+$PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
diff --git a/verilog/rtl/wb_host/src/run_verilator b/verilog/rtl/wb_host/src/run_verilator
new file mode 100755
index 0000000..89514ed
--- /dev/null
+++ b/verilog/rtl/wb_host/src/run_verilator
@@ -0,0 +1,12 @@
+verilator -cc \
+wb_host.sv \
+../../lib/async_wb.sv \
+../../lib/async_fifo.sv \
+../../lib/clk_ctl.v \
+../../lib/ctech_cells.sv \
+../../lib/registers.v \
+../../clk_skew_adjust/src/clk_skew_adjust.gv \
+$PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v \
+$PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v \
+--timescale 1ns/100ps --bbox-unsup \
+--top-module wb_host
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
new file mode 100644
index 0000000..b9a8749
--- /dev/null
+++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -0,0 +1,649 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Wishbone host Interface ////
+//// ////
+//// This file is part of the mbist_ctrl project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block does async Wishbone from one clock to other ////
+//// clock domain ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 25th Feb 2021, Dinesh A ////
+//// initial version ////
+//// 0.2 - 14th Nov 2021, Dinesh A ////
+//// reset_n connectivity fix for bist and memclock ////
+//// 0.1 - Nov 16 2021, Dinesh A ////
+//// Wishbone out are register for better timing ////
+//// 0.2 - Mar 15 2021, Dinesh A ////
+//// 1. To fix the bug in caravel mgmt soc address range ////
+//// reduction to 0x3000_0000 to 0x300F_FFFF ////
+//// Address Map has changes as follows ////
+//// 0x3008_0000 to 0x3008_00FF - Local Wishbone Reg ////
+//// 0x3000_0000 to 0x3007_FFFF - SOC access with ////
+//// indirect Map {Bank_Sel[15:3], wbm_adr_i[18:0]} ////
+//// 2.wbm_cyc_i need to qualified with wbm_stb_i ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module wb_host
+ #(parameter SCW = 8 // SCAN CHAIN WIDTH
+ ) (
+
+`ifdef USE_POWER_PINS
+ inout vccd1, // User area 1 1.8V supply
+ inout vssd1, // User area 1 digital ground
+`endif
+ input logic user_clock1 ,
+ input logic user_clock2 ,
+ output logic [2:0] user_irq ,
+
+ output logic wbd_int_rst_n ,
+ output logic bist_rst_n ,
+
+ // Master Port
+ input logic wbm_rst_i , // Regular Reset signal
+ input logic wbm_clk_i , // System clock
+ input logic wbm_cyc_i , // strobe/request
+ input logic wbm_stb_i , // strobe/request
+ input logic [31:0] wbm_adr_i , // address
+ input logic wbm_we_i , // write
+ input logic [31:0] wbm_dat_i , // data output
+ input logic [3:0] wbm_sel_i , // byte enable
+ output logic [31:0] wbm_dat_o , // data input
+ output logic wbm_ack_o , // acknowlegement
+ output logic wbm_err_o , // error
+
+ // Clock Skew Adjust
+ input logic wbd_clk_int ,
+ output logic wbd_clk_wh ,
+ input logic [3:0] cfg_cska_wh , // clock skew adjust for web host
+
+ // lbist Clock Skew Adjust
+ input logic lbist_clk_int ,
+ output logic lbist_clk_out ,
+ input logic [3:0] cfg_cska_lbist , // clock skew adjust for web host
+
+ // Slave Port
+ output logic wbs_clk_out , // System clock
+ input logic wbs_clk_i , // System clock
+ output logic wbs_cyc_o , // strobe/request
+ output logic wbs_stb_o , // strobe/request
+ output logic [31:0] wbs_adr_o , // address
+ output logic wbs_we_o , // write
+ output logic [31:0] wbs_dat_o , // data output
+ output logic [3:0] wbs_sel_o , // byte enable
+ input logic [31:0] wbs_dat_i , // data input
+ input logic wbs_ack_i , // acknowlegement
+ input logic wbs_err_i , // error
+
+ output logic [31:0] cfg_clk_ctrl1 ,
+ output logic [31:0] cfg_clk_ctrl2 ,
+ // MBIST I/F
+
+
+ input logic io_in,
+ output logic [37:0] io_out,
+ output logic [37:0] io_oeb,
+ input logic [35:0] la_data_in,
+ output logic [127:0] la_data_out,
+
+ // Scan Control Signal
+ output logic scan_clk,
+ output logic scan_rst_n,
+ output logic scan_mode,
+ output logic scan_en,
+ output logic [SCW-1:0] scan_in,
+ input logic [SCW-1:0] scan_out
+
+ );
+
+
+//--------------------------------
+// local dec
+//
+//--------------------------------
+logic wbm_rst_n;
+logic wbs_rst_n;
+logic [31:0] wbm_dat_int; // data input
+logic wbm_ack_int; // acknowlegement
+logic wbm_err_int; // error
+
+logic wb_reg_sel ; // Local Register Select
+logic [31:0] wb_reg_rdata ;
+logic [31:0] wb_reg_out ;
+logic wb_reg_ack ;
+
+logic lbist_reg_sel ; // LBIST Register Select
+logic [31:0] lbist_reg_rdata ;
+logic lbist_reg_ack ;
+logic lbist_reg_err ;
+
+logic [1:0] sw_addr ;
+logic sw_rd_en ;
+logic sw_wr_en ;
+logic sw_wr_en_0;
+logic sw_wr_en_1;
+logic sw_wr_en_2;
+logic sw_wr_en_3;
+logic sw_wr_en_4;
+logic sw_rd_en_5;
+logic [15:0] cfg_bank_sel;
+logic [31:0] wbm_adr_int;
+logic wbm_stb_int;
+logic [31:0] reg_0; // Software_Reg_0
+logic [31:0] reg_1; // Software_Reg_0
+
+logic [3:0] cfg_wb_clk_ctrl;
+logic [3:0] cfg_lbist_clk_ctrl;
+logic [7:0] cfg_glb_ctrl;
+logic cfg_la_lbist;
+
+// uart Master Port
+logic wbm_uart_cyc_i ; // strobe/request
+logic wbm_uart_stb_i ; // strobe/request
+logic [31:0] wbm_uart_adr_i ; // address
+logic wbm_uart_we_i ; // write
+logic [31:0] wbm_uart_dat_i ; // data output
+logic [3:0] wbm_uart_sel_i ; // byte enable
+logic [31:0] wbm_uart_dat_o ; // data input
+logic wbm_uart_ack_o ; // acknowlegement
+logic wbm_uart_err_o ; // error
+
+// Selected Master Port
+logic wb_cyc_i ; // strobe/request
+logic wb_stb_i ; // strobe/request
+logic [31:0] wb_adr_i ; // address
+logic wb_we_i ; // write
+logic [31:0] wb_dat_i ; // data output
+logic [3:0] wb_sel_i ; // byte enable
+logic [31:0] wb_dat_o ; // data input
+logic wb_ack_o ; // acknowlegement
+logic wb_err_o ; // error
+logic [31:0] wb_adr_int ;
+logic wb_stb_int ;
+logic [31:0] wb_dat_int ; // data input
+logic wb_ack_int ; // acknowlegement
+logic wb_err_int ; // error
+
+logic lbist_clk_skew ; // LBIST clock
+logic scan_mode_int ;
+// LBIST Control Signal
+logic lbist_scan_clk;
+logic lbist_scan_rst_n;
+logic lbist_scan_mode;
+logic lbist_scan_en;
+logic [SCW-1:0] lbist_scan_in;
+
+logic uartm_rxd ;
+logic uartm_txd ;
+
+// Drive UART TXD/RXD
+assign uartm_rxd = io_in;
+assign io_oeb[0] = 1'b1;
+assign io_out[0] = 1'b0;
+
+assign io_out[1] = uartm_txd;
+assign io_oeb[1] = 1'b0;
+
+assign io_out[37:2] = 'h0;
+assign io_oeb[37:2] = 'h0;
+
+//---------------------------------------------------
+// Local OR LA based Logic BIST Selection
+// --------------------------------------------------
+
+assign scan_clk = (cfg_la_lbist) ? la_data_in[35] : lbist_scan_clk;
+assign scan_rst_n = (cfg_la_lbist) ? la_data_in[34] : lbist_scan_rst_n;
+assign scan_mode_int = (cfg_la_lbist) ? la_data_in[33] : lbist_scan_mode;
+assign scan_en = (cfg_la_lbist) ? la_data_in[32] : lbist_scan_en;
+assign scan_in = (cfg_la_lbist) ? la_data_in[31:24]: lbist_scan_in;
+assign la_data_out = {120'h0,scan_out};
+
+
+//-------------------
+assign user_irq = 'h0;
+
+//--------------------------------------------------------------------------------
+// Look like wishbone reset removed early than user Power up sequence
+// To control the reset phase, we have added additional control through la[0]
+// ------------------------------------------------------------------------------
+wire arst_n = !wbm_rst_i & la_data_in[0];
+reset_sync u_wbm_rst (
+ .scan_mode (1'b0 ),
+ .dclk (wbm_clk_i ), // Destination clock domain
+ .arst_n (arst_n ), // active low async reset
+ .srst_n (wbm_rst_n )
+ );
+
+reset_sync u_wbs_rst (
+ .scan_mode (1'b0 ),
+ .dclk (wbs_clk_i ), // Destination clock domain
+ .arst_n (arst_n ), // active low async reset
+ .srst_n (wbs_rst_n )
+ );
+
+// UART Master
+uart2wb u_uart2wb (
+ .arst_n (wbm_rst_n ), // sync reset
+ .app_clk (wbm_clk_i ), // sys clock
+
+ // configuration control
+ .cfg_tx_enable (la_data_in[1] ), // Enable Transmit Path
+ .cfg_rx_enable (la_data_in[2] ), // Enable Received Path
+ .cfg_stop_bit (la_data_in[3] ), // 0 -> 1 Start , 1 -> 2 Stop Bits
+ .cfg_baud_16x (la_data_in[15:4] ), // 16x Baud clock generation
+ .cfg_pri_mod (la_data_in[17:16] ), // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd
+
+ // Master Port
+ .wbm_cyc_o (wbm_uart_cyc_i ), // strobe/request
+ .wbm_stb_o (wbm_uart_stb_i ), // strobe/request
+ .wbm_adr_o (wbm_uart_adr_i ), // address
+ .wbm_we_o (wbm_uart_we_i ), // write
+ .wbm_dat_o (wbm_uart_dat_i ), // data output
+ .wbm_sel_o (wbm_uart_sel_i ), // byte enable
+ .wbm_dat_i (wbm_uart_dat_o ), // data input
+ .wbm_ack_i (wbm_uart_ack_o ), // acknowlegement
+ .wbm_err_i (wbm_uart_err_o ), // error
+
+ // Status information
+ .frm_error (), // framing error
+ .par_error (), // par error
+
+ .baud_clk_16x (), // 16x Baud clock
+
+ // Line Interface
+ .rxd (uartm_rxd) , // uart rxd
+ .txd (uartm_txd) // uart txd
+
+ );
+
+
+// Arbitor to select between external wb vs uart wb
+wire [1:0] grnt;
+wb_arb u_arb(
+ .clk (wbm_clk_i),
+ .rstn (wbm_rst_n),
+ .req ({1'b0,wbm_uart_stb_i,(wbm_stb_i & wbm_cyc_i)}),
+ .gnt (grnt)
+ );
+
+// Select the master based on the grant
+assign wb_cyc_i = (grnt == 2'b00) ? wbm_cyc_i : wbm_uart_cyc_i;
+assign wb_stb_i = (grnt == 2'b00) ? (wbm_cyc_i & wbm_stb_i) : wbm_uart_stb_i;
+assign wb_adr_i = (grnt == 2'b00) ? wbm_adr_i : wbm_uart_adr_i;
+assign wb_we_i = (grnt == 2'b00) ? wbm_we_i : wbm_uart_we_i;
+assign wb_dat_i = (grnt == 2'b00) ? wbm_dat_i : wbm_uart_dat_i;
+assign wb_sel_i = (grnt == 2'b00) ? wbm_sel_i : wbm_uart_sel_i;
+
+assign wbm_dat_o = (grnt == 2'b00) ? wb_dat_o : 'h0;
+assign wbm_ack_o = (grnt == 2'b00) ? wb_ack_o : 'h0;
+assign wbm_err_o = (grnt == 2'b00) ? wb_err_o : 'h0;
+
+
+assign wbm_uart_dat_o = (grnt == 2'b01) ? wb_dat_o : 'h0;
+assign wbm_uart_ack_o = (grnt == 2'b01) ? wb_ack_o : 'h0;
+assign wbm_uart_err_o = (grnt == 2'b01) ? wb_err_o : 'h0;
+
+
+
+
+
+ctech_buf u_scan_buf (.A(scan_mode_int), .X(scan_mode));
+// Reset bypass for scan mode
+ctech_mux2x1 u_wb_rst_scan_sel (.A0 (cfg_glb_ctrl[0]), .A1 (scan_rst_n), .S (scan_mode), .X (wbd_int_rst_n));
+ctech_mux2x1 u_bist_rst_scan_sel (.A0 (cfg_glb_ctrl[1]), .A1 (scan_rst_n), .S (scan_mode), .X (bist_rst_n));
+
+// wb_host clock skew control
+clk_skew_adjust u_skew_wh
+ (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ .clk_in (wbd_clk_int ),
+ .sel (cfg_cska_wh ),
+ .clk_out (wbd_clk_wh )
+ );
+
+// To reduce the load/Timing Wishbone I/F, Strobe is register to create
+// multi-cycle
+wire [31:0] wb_dat_o1 = (wb_reg_sel) ? wb_reg_rdata : (lbist_reg_sel) ? lbist_reg_rdata : wb_dat_int; // data input
+wire wb_ack_o1 = (wb_reg_sel) ? wb_reg_ack : (lbist_reg_sel) ? lbist_reg_ack : wb_ack_int; // acknowlegement
+wire wb_err_o1 = (wb_reg_sel) ? 1'b0 : (lbist_reg_sel) ? lbist_reg_err : wb_err_int; // error
+
+logic wb_req;
+// Hold fix for STROBE
+wire wb_stb_d1,wb_stb_d2,wb_stb_d3;
+ctech_delay_buf u_delay1_stb0 (.X(wb_stb_d1),.A(wb_stb_i));
+ctech_delay_buf u_delay2_stb1 (.X(wb_stb_d2),.A(wb_stb_d1));
+ctech_delay_buf u_delay2_stb2 (.X(wb_stb_d3),.A(wb_stb_d2));
+always_ff @(negedge wbm_rst_n or posedge wbm_clk_i) begin
+ if ( wbm_rst_n == 1'b0 ) begin
+ wb_req <= '0;
+ wb_dat_o <= '0;
+ wb_ack_o <= '0;
+ wb_err_o <= '0;
+ end else begin
+ wb_req <= wb_stb_d3 && ((wb_ack_o == 0) && (wb_ack_o1 == 0)) ;
+ wb_ack_o <= wb_ack_o1;
+ wb_err_o <= wb_err_o1;
+ if(wb_ack_o1) // Keep last data in the bus
+ wb_dat_o <= wb_dat_o1;
+ end
+end
+
+
+//-----------------------------------------------------------------------
+// Local register decide based on address[19] == 1
+//
+// Locally there register are define to control the reset and clock for user
+// area
+//-----------------------------------------------------------------------
+// caravel user space is 0x3000_0000 to 0x3007_FFFF
+// So we have allocated
+// 0x3008_0000 - 0x3008_00FF - Assigned to WB Host Address Space
+// Since We need more than 16MB Address space to access SDRAM/SPI we have
+// added indirect MSB 8 bit address select option
+// So Address will be {Bank_Sel[15:2], wbm_adr_i[17:0]}
+// ---------------------------------------------------------------------
+assign wb_reg_sel = wb_req & (wb_adr_i[19:18] == 2'b10);
+assign lbist_reg_sel = wb_req & (wb_adr_i[19:18] == 2'b11);
+
+assign sw_addr = wb_adr_i [3:2];
+assign sw_rd_en = wb_reg_sel & !wb_we_i;
+assign sw_wr_en = wb_reg_sel & wb_we_i;
+
+assign sw_wr_en_0 = sw_wr_en && (sw_addr==0);
+assign sw_wr_en_1 = sw_wr_en && (sw_addr==1);
+assign sw_wr_en_2 = sw_wr_en && (sw_addr==2);
+assign sw_wr_en_3 = sw_wr_en && (sw_addr==3);
+
+always @ (posedge wbm_clk_i or negedge wbm_rst_n)
+begin : preg_out_Seq
+ if (wbm_rst_n == 1'b0)
+ begin
+ wb_reg_rdata <= 'h0;
+ wb_reg_ack <= 1'b0;
+ end
+ else if (sw_rd_en && !wb_reg_ack)
+ begin
+ wb_reg_rdata <= wb_reg_out ;
+ wb_reg_ack <= 1'b1;
+ end
+ else if (sw_wr_en && !wb_reg_ack)
+ wb_reg_ack <= 1'b1;
+ else
+ begin
+ wb_reg_ack <= 1'b0;
+ end
+end
+
+
+//-------------------------------------
+// Global + Clock Control
+// -------------------------------------
+assign cfg_glb_ctrl = reg_0[7:0];
+assign cfg_wb_clk_ctrl = reg_0[11:8];
+assign cfg_lbist_clk_ctrl = reg_0[15:12];
+assign cfg_la_lbist = reg_0[31]; // Use LA as Logic BIST
+
+
+always @( *)
+begin
+ wb_reg_out [31:0] = 32'h0;
+
+ case (sw_addr [1:0])
+ 2'b00 : wb_reg_out [31:0] = reg_0;
+ 2'b01 : wb_reg_out [31:0] = {16'h0,cfg_bank_sel [15:0]};
+ 2'b10 : wb_reg_out [31:0] = cfg_clk_ctrl1 [31:0];
+ 2'b11 : wb_reg_out [31:0] = cfg_clk_ctrl2 [31:0];
+ default : wb_reg_out [31:0] = 'h0;
+ endcase
+end
+
+
+gen_32b_reg #(32'h00) u_glb_ctrl (
+ //List of Inputs
+ .reset_n (wbm_rst_n ),
+ .clk (wbm_clk_i ),
+ .cs (sw_wr_en_0 ),
+ .we (wb_sel_i ),
+ .data_in (wb_dat_i ),
+
+ //List of Outs
+ .data_out (reg_0 )
+ );
+
+
+generic_register #(16,16'h1000 ) u_bank_sel (
+ .we ({16{sw_wr_en_1}} ),
+ .data_in (wb_dat_i[15:0] ),
+ .reset_n (wbm_rst_n ),
+ .clk (wbm_clk_i ),
+
+ //List of Outs
+ .data_out (cfg_bank_sel[15:0] )
+ );
+
+
+generic_register #(32,0 ) u_clk_ctrl1 (
+ .we ({32{sw_wr_en_2}} ),
+ .data_in (wb_dat_i[31:0] ),
+ .reset_n (wbm_rst_n ),
+ .clk (wbm_clk_i ),
+
+ //List of Outs
+ .data_out (cfg_clk_ctrl1[31:0])
+ );
+
+generic_register #(32,0 ) u_clk_ctrl2 (
+ .we ({32{sw_wr_en_3}} ),
+ .data_in (wb_dat_i[31:0] ),
+ .reset_n (wbm_rst_n ),
+ .clk (wbm_clk_i ),
+
+ //List of Outs
+ .data_out (cfg_clk_ctrl2[31:0])
+ );
+
+
+assign wb_stb_int = wb_req & (!wb_reg_sel & !lbist_reg_sel);
+
+// Since design need more than 16MB address space, we have implemented
+// indirect access
+assign wb_adr_int = {cfg_bank_sel[15:2],wb_adr_i[17:0]};
+
+// During scan mode, feedback the input back for better scan coverage
+logic wbs_cyc_o1 ; // strobe/request
+logic wbs_stb_o1 ; // strobe/request
+logic [31:0] wbs_adr_o1 ; // address
+logic wbs_we_o1 ; // write
+logic [31:0] wbs_dat_o1 ; // data output
+logic [3:0] wbs_sel_o1 ; // byte enable
+
+
+assign wbs_cyc_o = (scan_mode) ? wbs_ack_i : wbs_cyc_o1;
+assign wbs_stb_o = (scan_mode) ? wbs_ack_i : wbs_stb_o1;
+assign wbs_adr_o = (scan_mode) ? wbs_dat_i : wbs_adr_o1;
+assign wbs_we_o = (scan_mode) ? wbs_ack_i : wbs_we_o1;
+assign wbs_dat_o = (scan_mode) ? wbs_dat_i : wbs_dat_o1;
+assign wbs_sel_o = (scan_mode) ? wbs_dat_i[3:0] : wbs_sel_o1;
+
+async_wb u_async_wb(
+// Master Port
+ .wbm_rst_n (wbm_rst_n ),
+ .wbm_clk_i (wbm_clk_i ),
+ .wbm_cyc_i (wb_cyc_i ),
+ .wbm_stb_i (wb_stb_int ),
+ .wbm_adr_i (wb_adr_int ),
+ .wbm_we_i (wb_we_i ),
+ .wbm_dat_i (wb_dat_i ),
+ .wbm_sel_i (wb_sel_i ),
+ .wbm_dat_o (wb_dat_int ),
+ .wbm_ack_o (wb_ack_int ),
+ .wbm_err_o (wb_err_int ),
+
+// Slave Port
+ .wbs_rst_n (wbs_rst_n ),
+ .wbs_clk_i (wbs_clk_i ),
+ .wbs_cyc_o (wbs_cyc_o1 ),
+ .wbs_stb_o (wbs_stb_o1 ),
+ .wbs_adr_o (wbs_adr_o1 ),
+ .wbs_we_o (wbs_we_o1 ),
+ .wbs_dat_o (wbs_dat_o1 ),
+ .wbs_sel_o (wbs_sel_o1 ),
+ .wbs_dat_i (wbs_dat_i ),
+ .wbs_ack_i (wbs_ack_i ),
+ .wbs_err_i (wbs_err_i )
+
+ );
+
+
+//--------------------------------
+// LBIST TOP
+// -------------------------------
+
+lbist_top
+ #(.SCW(SCW) // SCAN CHAIN WIDTH
+ ) u_lbist (
+ // Wishbone Reg I/F
+ .wb_clk (wbm_clk_i),
+ .wb_rst_n (wbm_rst_n),
+ .wb_cs (lbist_reg_sel),
+ .wb_addr (sw_addr),
+ .wb_wr (wb_we_i),
+ .wb_wdata (wb_dat_i),
+ .wb_be (wb_sel_i),
+
+ .wb_rdata (lbist_reg_rdata),
+ .wb_ack (lbist_reg_ack),
+ .wb_err (lbist_reg_err),
+
+ // LBIST I/F
+ .lbist_clk (lbist_clk),
+ .lbist_clk_skew (lbist_clk_int),
+
+
+ // Scan Control Signal
+ .scan_clk (lbist_scan_clk),
+ .scan_rst_n (lbist_scan_rst_n),
+ .scan_mode (lbist_scan_mode),
+ .scan_en (lbist_scan_en),
+ .scan_in (lbist_scan_in),
+ .scan_out (scan_out)
+);
+
+
+//----------------------------------
+// Generate Internal WishBone Clock
+//----------------------------------
+logic wb_clk_div;
+logic wbs_clk;
+logic cfg_wb_clk_div;
+logic [2:0] cfg_wb_clk_ratio;
+
+assign cfg_wb_clk_ratio = cfg_wb_clk_ctrl[2:0];
+assign cfg_wb_clk_div = cfg_wb_clk_ctrl[3];
+
+
+//assign wbs_clk_out = (cfg_wb_clk_div) ? wb_clk_div : wbm_clk_i;
+
+ctech_mux2x1 u_wbs_clk_sel (.A0 (wbm_clk_i), .A1 (wb_clk_div), .S (cfg_wb_clk_div), .X (wbs_clk));
+ctech_mux2x1 u_wbs_clk_scan_sel (.A0 (wbs_clk), .A1 (scan_clk), .S (scan_mode), .X (wbs_clk_out));
+
+
+clk_ctl #(2) u_wbclk (
+ // Outputs
+ .clk_o (wb_clk_div ),
+ // Inputs
+ .mclk (wbm_clk_i ),
+ .reset_n (wbm_rst_n ),
+ .clk_div_ratio (cfg_wb_clk_ratio )
+ );
+
+//----------------------------------
+// Generate Internal WishBone Clock
+//----------------------------------
+logic lbist_clk_div;
+logic cfg_lbist_clk_div;
+logic [2:0] cfg_lbist_clk_ratio;
+
+assign cfg_lbist_clk_ratio = cfg_lbist_clk_ctrl[2:0];
+assign cfg_lbist_clk_div = cfg_lbist_clk_ctrl[3];
+
+
+//assign wbs_clk_out = (cfg_wb_clk_div) ? wb_clk_div : wbm_clk_i;
+ctech_mux2x1 u_lbist_clk_sel (.A0 (wbm_clk_i), .A1 (lbist_clk_div), .S (cfg_lbist_clk_div), .X (lbist_clk));
+
+
+clk_ctl #(2) u_lbist_clk (
+ // Outputs
+ .clk_o (lbist_clk_div ),
+ // Inputs
+ .mclk (wbm_clk_i ),
+ .reset_n (wbm_rst_n ),
+ .clk_div_ratio (cfg_lbist_clk_ratio )
+ );
+
+// wb_host clock skew control
+clk_skew_adjust u_skew_lbist
+ (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ .clk_in (lbist_clk ),
+ .sel (cfg_cska_lbist ),
+ .clk_out (lbist_clk_out )
+ );
+
+endmodule
diff --git a/verilog/rtl/wb_host/src/wb_host.sv.1 b/verilog/rtl/wb_host/src/wb_host.sv.1
new file mode 100644
index 0000000..185226f
--- /dev/null
+++ b/verilog/rtl/wb_host/src/wb_host.sv.1
@@ -0,0 +1,641 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Wishbone host Interface ////
+//// ////
+//// This file is part of the mbist_ctrl project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// This block does async Wishbone from one clock to other ////
+//// clock domain ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 25th Feb 2021, Dinesh A ////
+//// initial version ////
+//// 0.2 - 14th Nov 2021, Dinesh A ////
+//// reset_n connectivity fix for bist and memclock ////
+//// 0.1 - Nov 16 2021, Dinesh A ////
+//// Wishbone out are register for better timing ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module wb_host
+ #(parameter SCW = 8 // SCAN CHAIN WIDTH
+ ) (
+
+`ifdef USE_POWER_PINS
+ inout vccd1, // User area 1 1.8V supply
+ inout vssd1, // User area 1 digital ground
+`endif
+ input logic user_clock1 ,
+ input logic user_clock2 ,
+ output logic [2:0] user_irq ,
+
+ output logic wbd_int_rst_n ,
+ output logic bist_rst_n ,
+
+ // Master Port
+ input logic wbm_rst_i , // Regular Reset signal
+ input logic wbm_clk_i , // System clock
+ input logic wbm_cyc_i , // strobe/request
+ input logic wbm_stb_i , // strobe/request
+ input logic [31:0] wbm_adr_i , // address
+ input logic wbm_we_i , // write
+ input logic [31:0] wbm_dat_i , // data output
+ input logic [3:0] wbm_sel_i , // byte enable
+ output logic [31:0] wbm_dat_o , // data input
+ output logic wbm_ack_o , // acknowlegement
+ output logic wbm_err_o , // error
+
+ // Clock Skew Adjust
+ input logic wbd_clk_int ,
+ output logic wbd_clk_wh ,
+ input logic [3:0] cfg_cska_wh , // clock skew adjust for web host
+
+ // lbist Clock Skew Adjust
+ input logic lbist_clk_int ,
+ output logic lbist_clk_out ,
+ input logic [3:0] cfg_cska_lbist , // clock skew adjust for web host
+
+ // Slave Port
+ output logic wbs_clk_out , // System clock
+ input logic wbs_clk_i , // System clock
+ output logic wbs_cyc_o , // strobe/request
+ output logic wbs_stb_o , // strobe/request
+ output logic [31:0] wbs_adr_o , // address
+ output logic wbs_we_o , // write
+ output logic [31:0] wbs_dat_o , // data output
+ output logic [3:0] wbs_sel_o , // byte enable
+ input logic [31:0] wbs_dat_i , // data input
+ input logic wbs_ack_i , // acknowlegement
+ input logic wbs_err_i , // error
+
+ output logic [31:0] cfg_clk_ctrl1 ,
+ output logic [31:0] cfg_clk_ctrl2 ,
+ // MBIST I/F
+
+
+ input logic io_in,
+ output logic [37:0] io_out,
+ output logic [37:0] io_oeb,
+ input logic [35:0] la_data_in,
+ output logic [127:0] la_data_out,
+
+ // Scan Control Signal
+ output logic scan_clk,
+ output logic scan_rst_n,
+ output logic scan_mode,
+ output logic scan_en,
+ output logic [SCW-1:0] scan_in,
+ input logic [SCW-1:0] scan_out
+
+ );
+
+
+//--------------------------------
+// local dec
+//
+//--------------------------------
+logic wbm_rst_n;
+logic wbs_rst_n;
+logic [31:0] wbm_dat_int; // data input
+logic wbm_ack_int; // acknowlegement
+logic wbm_err_int; // error
+
+logic wb_reg_sel ; // Local Register Select
+logic [31:0] wb_reg_rdata ;
+logic [31:0] wb_reg_out ;
+logic wb_reg_ack ;
+
+logic lbist_reg_sel ; // LBIST Register Select
+logic [31:0] lbist_reg_rdata ;
+logic lbist_reg_ack ;
+logic lbist_reg_err ;
+
+logic [1:0] sw_addr ;
+logic sw_rd_en ;
+logic sw_wr_en ;
+logic sw_wr_en_0;
+logic sw_wr_en_1;
+logic sw_wr_en_2;
+logic sw_wr_en_3;
+logic sw_wr_en_4;
+logic sw_rd_en_5;
+logic [7:0] cfg_bank_sel;
+logic [31:0] wbm_adr_int;
+logic wbm_stb_int;
+logic [31:0] reg_0; // Software_Reg_0
+logic [31:0] reg_1; // Software_Reg_0
+
+logic [3:0] cfg_wb_clk_ctrl;
+logic [3:0] cfg_lbist_clk_ctrl;
+logic [7:0] cfg_glb_ctrl;
+logic cfg_la_lbist;
+
+// uart Master Port
+logic wbm_uart_cyc_i ; // strobe/request
+logic wbm_uart_stb_i ; // strobe/request
+logic [31:0] wbm_uart_adr_i ; // address
+logic wbm_uart_we_i ; // write
+logic [31:0] wbm_uart_dat_i ; // data output
+logic [3:0] wbm_uart_sel_i ; // byte enable
+logic [31:0] wbm_uart_dat_o ; // data input
+logic wbm_uart_ack_o ; // acknowlegement
+logic wbm_uart_err_o ; // error
+
+// Selected Master Port
+logic wb_cyc_i ; // strobe/request
+logic wb_stb_i ; // strobe/request
+logic [31:0] wb_adr_i ; // address
+logic wb_we_i ; // write
+logic [31:0] wb_dat_i ; // data output
+logic [3:0] wb_sel_i ; // byte enable
+logic [31:0] wb_dat_o ; // data input
+logic wb_ack_o ; // acknowlegement
+logic wb_err_o ; // error
+logic [31:0] wb_adr_int ;
+logic wb_stb_int ;
+logic [31:0] wb_dat_int ; // data input
+logic wb_ack_int ; // acknowlegement
+logic wb_err_int ; // error
+
+logic lbist_clk_skew ; // LBIST clock
+logic scan_mode_int ;
+// LBIST Control Signal
+logic lbist_scan_clk;
+logic lbist_scan_rst_n;
+logic lbist_scan_mode;
+logic lbist_scan_en;
+logic [SCW-1:0] lbist_scan_in;
+
+logic uartm_rxd ;
+logic uartm_txd ;
+
+// Drive UART TXD/RXD
+assign uartm_rxd = io_in;
+assign io_oeb[0] = 1'b1;
+assign io_out[0] = 1'b0;
+
+assign io_out[1] = uartm_txd;
+assign io_oeb[1] = 1'b0;
+
+assign io_out[37:2] = 'h0;
+assign io_oeb[37:2] = 'h0;
+
+//---------------------------------------------------
+// Local OR LA based Logic BIST Selection
+// --------------------------------------------------
+
+assign scan_clk = (cfg_la_lbist) ? la_data_in[35] : lbist_scan_clk;
+assign scan_rst_n = (cfg_la_lbist) ? la_data_in[34] : lbist_scan_rst_n;
+assign scan_mode_int = (cfg_la_lbist) ? la_data_in[33] : lbist_scan_mode;
+assign scan_en = (cfg_la_lbist) ? la_data_in[32] : lbist_scan_en;
+assign scan_in = (cfg_la_lbist) ? la_data_in[31:24]: lbist_scan_in;
+assign la_data_out = {120'h0,scan_out};
+
+
+//-------------------
+assign user_irq = 'h0;
+
+//--------------------------------------------------------------------------------
+// Look like wishbone reset removed early than user Power up sequence
+// To control the reset phase, we have added additional control through la[0]
+// ------------------------------------------------------------------------------
+wire arst_n = !wbm_rst_i & la_data_in[0];
+reset_sync u_wbm_rst (
+ .scan_mode (1'b0 ),
+ .dclk (wbm_clk_i ), // Destination clock domain
+ .arst_n (arst_n ), // active low async reset
+ .srst_n (wbm_rst_n )
+ );
+
+reset_sync u_wbs_rst (
+ .scan_mode (1'b0 ),
+ .dclk (wbs_clk_i ), // Destination clock domain
+ .arst_n (arst_n ), // active low async reset
+ .srst_n (wbs_rst_n )
+ );
+
+// UART Master
+uart2wb u_uart2wb (
+ .arst_n (wbm_rst_n ), // sync reset
+ .app_clk (wbm_clk_i ), // sys clock
+
+ // configuration control
+ .cfg_tx_enable (la_data_in[1] ), // Enable Transmit Path
+ .cfg_rx_enable (la_data_in[2] ), // Enable Received Path
+ .cfg_stop_bit (la_data_in[3] ), // 0 -> 1 Start , 1 -> 2 Stop Bits
+ .cfg_baud_16x (la_data_in[15:4] ), // 16x Baud clock generation
+ .cfg_pri_mod (la_data_in[17:16] ), // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd
+
+ // Master Port
+ .wbm_cyc_o (wbm_uart_cyc_i ), // strobe/request
+ .wbm_stb_o (wbm_uart_stb_i ), // strobe/request
+ .wbm_adr_o (wbm_uart_adr_i ), // address
+ .wbm_we_o (wbm_uart_we_i ), // write
+ .wbm_dat_o (wbm_uart_dat_i ), // data output
+ .wbm_sel_o (wbm_uart_sel_i ), // byte enable
+ .wbm_dat_i (wbm_uart_dat_o ), // data input
+ .wbm_ack_i (wbm_uart_ack_o ), // acknowlegement
+ .wbm_err_i (wbm_uart_err_o ), // error
+
+ // Status information
+ .frm_error (), // framing error
+ .par_error (), // par error
+
+ .baud_clk_16x (), // 16x Baud clock
+
+ // Line Interface
+ .rxd (uartm_rxd) , // uart rxd
+ .txd (uartm_txd) // uart txd
+
+ );
+
+
+// Arbitor to select between external wb vs uart wb
+wire [1:0] grnt;
+wb_arb u_arb(
+ .clk (wbm_clk_i),
+ .rstn (wbm_rst_n),
+ .req ({1'b0,wbm_uart_stb_i,wbm_stb_i}),
+ .gnt (grnt)
+ );
+
+// Select the master based on the grant
+assign wb_cyc_i = (grnt == 2'b00) ? wbm_cyc_i : wbm_uart_cyc_i;
+assign wb_stb_i = (grnt == 2'b00) ? wbm_stb_i : wbm_uart_stb_i;
+assign wb_adr_i = (grnt == 2'b00) ? wbm_adr_i : wbm_uart_adr_i;
+assign wb_we_i = (grnt == 2'b00) ? wbm_we_i : wbm_uart_we_i;
+assign wb_dat_i = (grnt == 2'b00) ? wbm_dat_i : wbm_uart_dat_i;
+assign wb_sel_i = (grnt == 2'b00) ? wbm_sel_i : wbm_uart_sel_i;
+
+assign wbm_dat_o = (grnt == 2'b00) ? wb_dat_o : 'h0;
+assign wbm_ack_o = (grnt == 2'b00) ? wb_ack_o : 'h0;
+assign wbm_err_o = (grnt == 2'b00) ? wb_err_o : 'h0;
+
+
+assign wbm_uart_dat_o = (grnt == 2'b01) ? wb_dat_o : 'h0;
+assign wbm_uart_ack_o = (grnt == 2'b01) ? wb_ack_o : 'h0;
+assign wbm_uart_err_o = (grnt == 2'b01) ? wb_err_o : 'h0;
+
+
+
+
+
+ctech_buf u_scan_buf (.A(scan_mode_int), .X(scan_mode));
+// Reset bypass for scan mode
+ctech_mux2x1 u_wb_rst_scan_sel (.A0 (cfg_glb_ctrl[0]), .A1 (scan_rst_n), .S (scan_mode), .X (wbd_int_rst_n));
+ctech_mux2x1 u_bist_rst_scan_sel (.A0 (cfg_glb_ctrl[1]), .A1 (scan_rst_n), .S (scan_mode), .X (bist_rst_n));
+
+// wb_host clock skew control
+clk_skew_adjust u_skew_wh
+ (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ .clk_in (wbd_clk_int ),
+ .sel (cfg_cska_wh ),
+ .clk_out (wbd_clk_wh )
+ );
+
+
+// To reduce the load/Timing Wishbone I/F, Strobe is register to create
+// multi-cycle
+wire [31:0] wb_dat_o1 = (reg_sel) ? reg_rdata : wb_dat_int; // data input
+wire wb_ack_o1 = (reg_sel) ? reg_ack : wb_ack_int; // acknowlegement
+wire wb_err_o1 = (reg_sel) ? 1'b0 : wb_err_int; // error
+
+logic wb_req;
+// Hold fix for STROBE
+wire wb_stb_d1,wb_stb_d2,wb_stb_d3;
+ctech_delay_buf u_delay1_stb0 (.X(wb_stb_d1),.A(wb_stb_i));
+ctech_delay_buf u_delay2_stb1 (.X(wb_stb_d2),.A(wb_stb_d1));
+ctech_delay_buf u_delay2_stb2 (.X(wb_stb_d3),.A(wb_stb_d2));
+always_ff @(negedge wbm_rst_n or posedge wbm_clk_i) begin
+ if ( wbm_rst_n == 1'b0 ) begin
+ wb_req <= '0;
+ wb_dat_o <= '0;
+ wb_ack_o <= '0;
+ wb_err_o <= '0;
+ end else begin
+ wb_req <= wb_stb_d3 && ((wb_ack_o == 0) && (wb_ack_o1 == 0)) ;
+ wb_ack_o <= wb_ack_o1;
+ wb_err_o <= wb_err_o1;
+ if(wb_ack_o1) // Keep last data in the bus
+ wb_dat_o <= wb_dat_o1;
+ end
+end
+
+
+//-----------------------------------------------------------------------
+// Local register decide based on address[31] == 1
+//
+// Locally there register are define to control the reset and clock for user
+// area
+//-----------------------------------------------------------------------
+// caravel user space is 0x3000_0000 to 0x30FF_FFFF
+// So we have allocated
+// 0x3000_0000 - 0x307F_7FFF - To SRAM Address Space
+// 0x3080_0000 - 0x30B0_00FF - Assigned to WB Host Address Space
+// 0x30C0_0000 - 0x30FF_00FF - Assigned to Logic Bist Address Space
+// ---------------------------------------------------------------------
+assign wb_reg_sel = wb_req & (wb_adr_i[23:22] == 2'b10);
+assign lbist_reg_sel = wb_req & (wb_adr_i[23:22] == 2'b11);
+
+assign sw_addr = wb_adr_i [3:2];
+assign sw_rd_en = wb_reg_sel & !wb_we_i;
+assign sw_wr_en = wb_reg_sel & wb_we_i;
+
+assign sw_wr_en_0 = sw_wr_en && (sw_addr==0);
+assign sw_wr_en_1 = sw_wr_en && (sw_addr==1);
+assign sw_wr_en_2 = sw_wr_en && (sw_addr==2);
+assign sw_wr_en_3 = sw_wr_en && (sw_addr==3);
+
+always @ (posedge wbm_clk_i or negedge wbm_rst_n)
+begin : preg_out_Seq
+ if (wbm_rst_n == 1'b0)
+ begin
+ wb_reg_rdata <= 'h0;
+ wb_reg_ack <= 1'b0;
+ end
+ else if (sw_rd_en && !wb_reg_ack)
+ begin
+ wb_reg_rdata <= wb_reg_out ;
+ wb_reg_ack <= 1'b1;
+ end
+ else if (sw_wr_en && !wb_reg_ack)
+ wb_reg_ack <= 1'b1;
+ else
+ begin
+ wb_reg_ack <= 1'b0;
+ end
+end
+
+
+//-------------------------------------
+// Global + Clock Control
+// -------------------------------------
+assign cfg_glb_ctrl = reg_0[7:0];
+assign cfg_wb_clk_ctrl = reg_0[11:8];
+assign cfg_lbist_clk_ctrl = reg_0[15:12];
+assign cfg_la_lbist = reg_0[31]; // Use LA as Logic BIST
+
+
+always @( *)
+begin
+ wb_reg_out [31:0] = 32'h0;
+
+ case (sw_addr [1:0])
+ 2'b00 : wb_reg_out [31:0] = reg_0;
+ 2'b01 : wb_reg_out [31:0] = {24'h0,cfg_bank_sel [7:0]};
+ 2'b10 : wb_reg_out [31:0] = cfg_clk_ctrl1 [31:0];
+ 2'b11 : wb_reg_out [31:0] = cfg_clk_ctrl2 [31:0];
+ default : wb_reg_out [31:0] = 'h0;
+ endcase
+end
+
+
+gen_32b_reg #(32'h00) u_glb_ctrl (
+ //List of Inputs
+ .reset_n (wbm_rst_n ),
+ .clk (wbm_clk_i ),
+ .cs (sw_wr_en_0 ),
+ .we (wb_sel_i ),
+ .data_in (wb_dat_i ),
+
+ //List of Outs
+ .data_out (reg_0 )
+ );
+
+
+generic_register #(8,8'h00 ) u_bank_sel (
+ .we ({8{sw_wr_en_1}} ),
+ .data_in (wb_dat_i[7:0] ),
+ .reset_n (wbm_rst_n ),
+ .clk (wbm_clk_i ),
+
+ //List of Outs
+ .data_out (cfg_bank_sel[7:0] )
+ );
+
+
+generic_register #(32,0 ) u_clk_ctrl1 (
+ .we ({32{sw_wr_en_2}} ),
+ .data_in (wb_dat_i[31:0] ),
+ .reset_n (wbm_rst_n ),
+ .clk (wbm_clk_i ),
+
+ //List of Outs
+ .data_out (cfg_clk_ctrl1[31:0])
+ );
+
+generic_register #(32,0 ) u_clk_ctrl2 (
+ .we ({32{sw_wr_en_3}} ),
+ .data_in (wb_dat_i[31:0] ),
+ .reset_n (wbm_rst_n ),
+ .clk (wbm_clk_i ),
+
+ //List of Outs
+ .data_out (cfg_clk_ctrl2[31:0])
+ );
+
+
+assign wbm_stb_int = wb_req & (!wb_reg_sel & !lbist_reg_sel);
+
+// Since design need more than 16MB address space, we have implemented
+// indirect access
+assign wbm_adr_int = {4'b0000,cfg_bank_sel[7:0],wbm_adr_i[19:0]};
+
+// During scan mode, feedback the input back for better scan coverage
+logic wbs_cyc_o1 ; // strobe/request
+logic wbs_stb_o1 ; // strobe/request
+logic [31:0] wbs_adr_o1 ; // address
+logic wbs_we_o1 ; // write
+logic [31:0] wbs_dat_o1 ; // data output
+logic [3:0] wbs_sel_o1 ; // byte enable
+
+
+assign wbs_cyc_o = (scan_mode) ? wbs_ack_i : wbs_cyc_o1;
+assign wbs_stb_o = (scan_mode) ? wbs_ack_i : wbs_stb_o1;
+assign wbs_adr_o = (scan_mode) ? wbs_dat_i : wbs_adr_o1;
+assign wbs_we_o = (scan_mode) ? wbs_ack_i : wbs_we_o1;
+assign wbs_dat_o = (scan_mode) ? wbs_dat_i : wbs_dat_o1;
+assign wbs_sel_o = (scan_mode) ? wbs_dat_i[3:0] : wbs_sel_o1;
+
+async_wb u_async_wb(
+// Master Port
+ .wbm_rst_n (wbm_rst_n ),
+ .wbm_clk_i (wbm_clk_i ),
+ .wbm_cyc_i (wb_cyc_i ),
+ .wbm_stb_i (wb_stb_int ),
+ .wbm_adr_i (wb_adr_int ),
+ .wbm_we_i (wb_we_i ),
+ .wbm_dat_i (wb_dat_i ),
+ .wbm_sel_i (wb_sel_i ),
+ .wbm_dat_o (wb_dat_int ),
+ .wbm_ack_o (wb_ack_int ),
+ .wbm_err_o (wb_err_int ),
+
+// Slave Port
+ .wbs_rst_n (wbs_rst_n ),
+ .wbs_clk_i (wbs_clk_i ),
+ .wbs_cyc_o (wbs_cyc_o1 ),
+ .wbs_stb_o (wbs_stb_o1 ),
+ .wbs_adr_o (wbs_adr_o1 ),
+ .wbs_we_o (wbs_we_o1 ),
+ .wbs_dat_o (wbs_dat_o1 ),
+ .wbs_sel_o (wbs_sel_o1 ),
+ .wbs_dat_i (wbs_dat_i ),
+ .wbs_ack_i (wbs_ack_i ),
+ .wbs_err_i (wbs_err_i )
+
+ );
+
+
+//--------------------------------
+// LBIST TOP
+// -------------------------------
+
+lbist_top
+ #(.SCW(SCW) // SCAN CHAIN WIDTH
+ ) u_lbist (
+ // Wishbone Reg I/F
+ .wb_clk (wbm_clk_i),
+ .wb_rst_n (wbm_rst_n),
+ .wb_cs (lbist_reg_sel),
+ .wb_addr (sw_addr),
+ .wb_wr (wbm_we_i),
+ .wb_wdata (wbm_dat_i),
+ .wb_be (wbm_sel_i),
+
+ .wb_rdata (lbist_reg_rdata),
+ .wb_ack (lbist_reg_ack),
+ .wb_err (lbist_reg_err),
+
+ // LBIST I/F
+ .lbist_clk (lbist_clk),
+ .lbist_clk_skew (lbist_clk_int),
+
+
+ // Scan Control Signal
+ .scan_clk (lbist_scan_clk),
+ .scan_rst_n (lbist_scan_rst_n),
+ .scan_mode (lbist_scan_mode),
+ .scan_en (lbist_scan_en),
+ .scan_in (lbist_scan_in),
+ .scan_out (scan_out)
+);
+
+
+//----------------------------------
+// Generate Internal WishBone Clock
+//----------------------------------
+logic wb_clk_div;
+logic wbs_clk;
+logic cfg_wb_clk_div;
+logic [2:0] cfg_wb_clk_ratio;
+
+assign cfg_wb_clk_ratio = cfg_wb_clk_ctrl[2:0];
+assign cfg_wb_clk_div = cfg_wb_clk_ctrl[3];
+
+
+//assign wbs_clk_out = (cfg_wb_clk_div) ? wb_clk_div : wbm_clk_i;
+
+ctech_mux2x1 u_wbs_clk_sel (.A0 (wbm_clk_i), .A1 (wb_clk_div), .S (cfg_wb_clk_div), .X (wbs_clk));
+ctech_mux2x1 u_wbs_clk_scan_sel (.A0 (wbs_clk), .A1 (scan_clk), .S (scan_mode), .X (wbs_clk_out));
+
+
+clk_ctl #(2) u_wbclk (
+ // Outputs
+ .clk_o (wb_clk_div ),
+ // Inputs
+ .mclk (wbm_clk_i ),
+ .reset_n (wbm_rst_n ),
+ .clk_div_ratio (cfg_wb_clk_ratio )
+ );
+
+//----------------------------------
+// Generate Internal WishBone Clock
+//----------------------------------
+logic lbist_clk_div;
+logic cfg_lbist_clk_div;
+logic [2:0] cfg_lbist_clk_ratio;
+
+assign cfg_lbist_clk_ratio = cfg_lbist_clk_ctrl[2:0];
+assign cfg_lbist_clk_div = cfg_lbist_clk_ctrl[3];
+
+
+//assign wbs_clk_out = (cfg_wb_clk_div) ? wb_clk_div : wbm_clk_i;
+ctech_mux2x1 u_lbist_clk_sel (.A0 (wbm_clk_i), .A1 (lbist_clk_div), .S (cfg_lbist_clk_div), .X (lbist_clk));
+
+
+clk_ctl #(2) u_lbist_clk (
+ // Outputs
+ .clk_o (lbist_clk_div ),
+ // Inputs
+ .mclk (wbm_clk_i ),
+ .reset_n (wbm_rst_n ),
+ .clk_div_ratio (cfg_lbist_clk_ratio )
+ );
+
+// wb_host clock skew control
+clk_skew_adjust u_skew_lbist
+ (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ .clk_in (lbist_clk ),
+ .sel (cfg_cska_lbist ),
+ .clk_out (lbist_clk_out )
+ );
+
+endmodule
diff --git a/verilog/rtl/wb_interconnect/src/run_iverilog b/verilog/rtl/wb_interconnect/src/run_iverilog
new file mode 100755
index 0000000..97426bc
--- /dev/null
+++ b/verilog/rtl/wb_interconnect/src/run_iverilog
@@ -0,0 +1,6 @@
+iverilog -g2005-sv \
+wb_interconnect.sv \
+../../lib/wb_stagging.sv \
+../../clk_skew_adjust/src/clk_skew_adjust.gv \
+$PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v \
+$PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
diff --git a/verilog/rtl/wb_interconnect/src/run_verilator b/verilog/rtl/wb_interconnect/src/run_verilator
new file mode 100755
index 0000000..c5110a9
--- /dev/null
+++ b/verilog/rtl/wb_interconnect/src/run_verilator
@@ -0,0 +1,7 @@
+verilator -cc \
+wb_interconnect.sv \
+../../lib/wb_stagging.sv \
+../../clk_skew_adjust/src/clk_skew_adjust.gv \
+$PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v \
+$PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v \
+--timescale 1ns/100ps --bbox-unsup
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
new file mode 100644
index 0000000..18fc86d
--- /dev/null
+++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -0,0 +1,518 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Wishbone Interconnect ////
+//// ////
+//// This file is part of the mbist_ctrl cores project ////
+//// https://github.com/dineshannayya/mbist_ctrl.git ////
+//// ////
+//// Description ////
+//// 1. 1 masters and 5 slaves share bus Wishbone connection ////
+//// M0 - WB_PORT ////
+//// S0 - Glbl_Reg ////
+//// S1 - MBIST1 ////
+//// S2 - MBIST2 ////
+//// S3 - MBIST3 ////
+//// S4 - MBIST4 ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+
+
+module wb_interconnect #(
+ parameter SCW = 8, // SCAN CHAIN WIDTH
+ parameter CH_CLK_WD = 9,
+ parameter CH_DATA_WD = 95
+ ) (
+`ifdef USE_POWER_PINS
+ input logic vccd1, // User area 1 1.8V supply
+ input logic vssd1, // User area 1 digital ground
+`endif
+ input logic scan_en,
+ input logic scan_mode,
+ input logic [SCW-1:0] scan_si,
+ output logic [SCW-1:0] scan_so,
+ output logic scan_en_o,
+ output logic scan_mode_o,
+
+ // Clock Skew Adjust
+ input logic [3:0] cfg_cska_wi,
+ input logic wbd_clk_int,
+ output logic wbd_clk_wi,
+
+ // Bus repeaters
+ input [CH_CLK_WD-1:0] ch_clk_in,
+ output [CH_CLK_WD-1:0] ch_clk_out,
+ input [CH_DATA_WD-1:0] ch_data_in,
+ output [CH_DATA_WD-1:0]ch_data_out,
+
+ input logic clk_i,
+ input logic rst_n,
+
+ // Master 0 Interface
+ input logic [31:0] m0_wbd_dat_i,
+ input logic [31:0] m0_wbd_adr_i,
+ input logic [3:0] m0_wbd_sel_i,
+ input logic m0_wbd_we_i,
+ input logic m0_wbd_cyc_i,
+ input logic m0_wbd_stb_i,
+ output logic [31:0] m0_wbd_dat_o,
+ output logic m0_wbd_ack_o,
+ output logic m0_wbd_err_o,
+
+
+ // Slave 0 Interface
+ input logic [31:0] s0_wbd_dat_i,
+ input logic s0_wbd_ack_i,
+ //input logic s0_wbd_err_i, - unused
+ output logic [31:0] s0_wbd_dat_o,
+ output logic [7:0] s0_wbd_adr_o,
+ output logic [3:0] s0_wbd_sel_o,
+ output logic s0_wbd_we_o,
+ output logic s0_wbd_cyc_o,
+ output logic s0_wbd_stb_o,
+
+ // Slave 1 Interface
+ input logic [31:0] s1_wbd_dat_i,
+ input logic s1_wbd_ack_i,
+ // input logic s1_wbd_err_i, - unused
+ output logic [31:0] s1_wbd_dat_o,
+ output logic [10:0] s1_wbd_adr_o,
+ output logic [3:0] s1_wbd_sel_o,
+ output logic s1_wbd_we_o,
+ output logic s1_wbd_cyc_o,
+ output logic s1_wbd_stb_o,
+
+ // Slave 2 Interface
+ input logic [31:0] s2_wbd_dat_i,
+ input logic s2_wbd_ack_i,
+ // input logic s2_wbd_err_i, - unused
+ output logic [31:0] s2_wbd_dat_o,
+ output logic [10:0] s2_wbd_adr_o, // glbl reg need only 8 bits
+ output logic [3:0] s2_wbd_sel_o,
+ output logic s2_wbd_we_o,
+ output logic s2_wbd_cyc_o,
+ output logic s2_wbd_stb_o,
+
+ // Slave 3 Interface
+ // Uart is 8bit interface
+ input logic [31:0] s3_wbd_dat_i,
+ input logic s3_wbd_ack_i,
+ // input logic s3_wbd_err_i,
+ output logic [31:0] s3_wbd_dat_o,
+ output logic [10:0] s3_wbd_adr_o,
+ output logic [3:0] s3_wbd_sel_o,
+ output logic s3_wbd_we_o,
+ output logic s3_wbd_cyc_o,
+ output logic s3_wbd_stb_o,
+
+ // Slave 4 Interface
+ input logic [31:0] s4_wbd_dat_i,
+ input logic s4_wbd_ack_i,
+ // input logic s4_wbd_err_i,
+ output logic [31:0] s4_wbd_dat_o,
+ output logic [10:0] s4_wbd_adr_o,
+ output logic [3:0] s4_wbd_sel_o,
+ output logic s4_wbd_we_o,
+ output logic s4_wbd_cyc_o,
+ output logic s4_wbd_stb_o,
+
+ // Slave 5 Interface
+ input logic [31:0] s5_wbd_dat_i,
+ input logic s5_wbd_ack_i,
+ // input logic s5_wbd_err_i, - unused
+ output logic [31:0] s5_wbd_dat_o,
+ output logic [9:0] s5_wbd_adr_o,
+ output logic [3:0] s5_wbd_sel_o,
+ output logic s5_wbd_we_o,
+ output logic s5_wbd_cyc_o,
+ output logic s5_wbd_stb_o,
+
+ // Slave 6 Interface
+ input logic [31:0] s6_wbd_dat_i,
+ input logic s6_wbd_ack_i,
+ // input logic s6_wbd_err_i, - unused
+ output logic [31:0] s6_wbd_dat_o,
+ output logic [9:0] s6_wbd_adr_o, // glbl reg need only 8 bits
+ output logic [3:0] s6_wbd_sel_o,
+ output logic s6_wbd_we_o,
+ output logic s6_wbd_cyc_o,
+ output logic s6_wbd_stb_o,
+
+ // Slave 7 Interface
+ // Uart is 8bit interface
+ input logic [31:0] s7_wbd_dat_i,
+ input logic s7_wbd_ack_i,
+ // input logic s7_wbd_err_i,
+ output logic [31:0] s7_wbd_dat_o,
+ output logic [9:0] s7_wbd_adr_o,
+ output logic [3:0] s7_wbd_sel_o,
+ output logic s7_wbd_we_o,
+ output logic s7_wbd_cyc_o,
+ output logic s7_wbd_stb_o,
+
+ // Slave 8 Interface
+ input logic [31:0] s8_wbd_dat_i,
+ input logic s8_wbd_ack_i,
+ // input logic s8_wbd_err_i,
+ output logic [31:0] s8_wbd_dat_o,
+ output logic [9:0] s8_wbd_adr_o,
+ output logic [3:0] s8_wbd_sel_o,
+ output logic s8_wbd_we_o,
+ output logic s8_wbd_cyc_o,
+ output logic s8_wbd_stb_o
+ );
+
+////////////////////////////////////////////////////////////////////
+//
+// Type define
+//
+
+
+// WishBone Wr Interface
+typedef struct packed {
+ logic [31:0] wbd_dat;
+ logic [31:0] wbd_adr;
+ logic [3:0] wbd_sel;
+ logic wbd_we;
+ logic wbd_cyc;
+ logic wbd_stb;
+ logic [3:0] wbd_tid; // target id
+} type_wb_wr_intf;
+
+// WishBone Rd Interface
+typedef struct packed {
+ logic [31:0] wbd_dat;
+ logic wbd_ack;
+ logic wbd_err;
+} type_wb_rd_intf;
+
+
+// Master Write Interface
+type_wb_wr_intf m0_wb_wr;
+
+// Master Read Interface
+type_wb_rd_intf m0_wb_rd;
+
+// Slave Write Interface
+type_wb_wr_intf s0_wb_wr;
+type_wb_wr_intf s1_wb_wr;
+type_wb_wr_intf s2_wb_wr;
+type_wb_wr_intf s3_wb_wr;
+type_wb_wr_intf s4_wb_wr;
+type_wb_wr_intf s5_wb_wr;
+type_wb_wr_intf s6_wb_wr;
+type_wb_wr_intf s7_wb_wr;
+type_wb_wr_intf s8_wb_wr;
+
+// Slave Read Interface
+type_wb_rd_intf s0_wb_rd;
+type_wb_rd_intf s1_wb_rd;
+type_wb_rd_intf s2_wb_rd;
+type_wb_rd_intf s3_wb_rd;
+type_wb_rd_intf s4_wb_rd;
+type_wb_rd_intf s5_wb_rd;
+type_wb_rd_intf s6_wb_rd;
+type_wb_rd_intf s7_wb_rd;
+type_wb_rd_intf s8_wb_rd;
+
+
+type_wb_wr_intf m_bus_wr; // Multiplexed Master I/F
+type_wb_rd_intf m_bus_rd; // Multiplexed Slave I/F
+
+type_wb_wr_intf s_bus_wr; // Multiplexed Master I/F
+type_wb_rd_intf s_bus_rd; // Multiplexed Slave I/F
+
+// channel repeater
+assign ch_clk_out = ch_clk_in;
+assign ch_data_out = ch_data_in;
+
+assign scan_en_o = scan_en;
+assign scan_mode_o = scan_mode;
+
+// Wishbone interconnect clock skew control
+clk_skew_adjust u_skew_wi
+ (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ .clk_in (wbd_clk_int ),
+ .sel (cfg_cska_wi ),
+ .clk_out (wbd_clk_wi )
+ );
+
+//-------------------------------------------------------------------
+// EXTERNAL MEMORY MAP
+// 0x0000_0000 to 0x0000_0FFF - GLBL
+// 0x0000_1000 to 0x0000_1FFF - MBIST1
+// 0x0000_2000 to 0x0000_2FFF - MBIST2
+// 0x0000_3000 to 0x0000_3FFF - MBIST3
+// 0x0000_4000 to 0x0000_4FFF - MBIST4
+// 0x0000_5000 to 0x0000_5FFF - MBIST5
+// 0x0000_6000 to 0x0000_6FFF - MBIST6
+// 0x0000_7000 to 0x0000_7FFF - MBIST7
+// 0x0000_8000 to 0x0000_8FFF - MBIST8
+// ---------------------------------------------------------------------------
+//
+wire [3:0] m0_wbd_tid_i = (m0_wbd_adr_i[15:12] == 4'b0000 ) ? 4'b0000 : // GLBL
+ (m0_wbd_adr_i[15:12] == 4'b0001 ) ? 4'b0001 : // MBIST1
+ (m0_wbd_adr_i[15:12] == 4'b0010 ) ? 4'b0010 : // MBIST2
+ (m0_wbd_adr_i[15:12] == 4'b0011 ) ? 4'b0011 : // MBIST3
+ (m0_wbd_adr_i[15:12] == 4'b0100 ) ? 4'b0100 : // MBIST4
+ (m0_wbd_adr_i[15:12] == 4'b0101 ) ? 4'b0101 : // MBIST5
+ (m0_wbd_adr_i[15:12] == 4'b0110 ) ? 4'b0110 : // MBIST6
+ (m0_wbd_adr_i[15:12] == 4'b0111 ) ? 4'b0111 : // MBIST7
+ (m0_wbd_adr_i[15:12] == 4'b1000 ) ? 4'b1000 : // MBIST8
+ 4'b0000;
+
+//----------------------------------------
+// Master Mapping
+// -------------------------------------
+assign m0_wb_wr.wbd_dat = m0_wbd_dat_i;
+assign m0_wb_wr.wbd_adr = {m0_wbd_adr_i[31:2],2'b00};
+assign m0_wb_wr.wbd_sel = m0_wbd_sel_i;
+assign m0_wb_wr.wbd_we = m0_wbd_we_i;
+assign m0_wb_wr.wbd_cyc = m0_wbd_cyc_i;
+assign m0_wb_wr.wbd_stb = m0_wbd_stb_i;
+assign m0_wb_wr.wbd_tid = m0_wbd_tid_i;
+
+assign m0_wbd_dat_o = m0_wb_rd.wbd_dat;
+assign m0_wbd_ack_o = m0_wb_rd.wbd_ack;
+assign m0_wbd_err_o = m0_wb_rd.wbd_err;
+
+
+//----------------------------------------
+// Slave Mapping
+// -------------------------------------
+// Masked Now and added stagging FF now
+ assign s0_wbd_dat_o = s0_wb_wr.wbd_dat ;
+ assign s0_wbd_adr_o = s0_wb_wr.wbd_adr[7:0] ;
+ assign s0_wbd_sel_o = s0_wb_wr.wbd_sel ;
+ assign s0_wbd_we_o = s0_wb_wr.wbd_we ;
+ assign s0_wbd_cyc_o = s0_wb_wr.wbd_cyc ;
+ assign s0_wbd_stb_o = s0_wb_wr.wbd_stb ;
+
+// 2KB SRAM
+ assign s1_wbd_dat_o = s1_wb_wr.wbd_dat ;
+ assign s1_wbd_adr_o = s1_wb_wr.wbd_adr[10:0] ;
+ assign s1_wbd_sel_o = s1_wb_wr.wbd_sel ;
+ assign s1_wbd_we_o = s1_wb_wr.wbd_we ;
+ assign s1_wbd_cyc_o = s1_wb_wr.wbd_cyc ;
+ assign s1_wbd_stb_o = s1_wb_wr.wbd_stb ;
+
+ assign s2_wbd_dat_o = s2_wb_wr.wbd_dat ;
+ assign s2_wbd_adr_o = s2_wb_wr.wbd_adr[10:0] ; // Global Reg Need 8 bit
+ assign s2_wbd_sel_o = s2_wb_wr.wbd_sel ;
+ assign s2_wbd_we_o = s2_wb_wr.wbd_we ;
+ assign s2_wbd_cyc_o = s2_wb_wr.wbd_cyc ;
+ assign s2_wbd_stb_o = s2_wb_wr.wbd_stb ;
+
+ assign s3_wbd_dat_o = s3_wb_wr.wbd_dat;
+ assign s3_wbd_adr_o = s3_wb_wr.wbd_adr[10:0] ; // Global Reg Need 8 bit
+ assign s3_wbd_sel_o = s3_wb_wr.wbd_sel;
+ assign s3_wbd_we_o = s3_wb_wr.wbd_we ;
+ assign s3_wbd_cyc_o = s3_wb_wr.wbd_cyc ;
+ assign s3_wbd_stb_o = s3_wb_wr.wbd_stb ;
+
+ assign s4_wbd_dat_o = s4_wb_wr.wbd_dat ;
+ assign s4_wbd_adr_o = s4_wb_wr.wbd_adr[10:0] ; // Global Reg Need 8 bit
+ assign s4_wbd_sel_o = s4_wb_wr.wbd_sel ;
+ assign s4_wbd_we_o = s4_wb_wr.wbd_we ;
+ assign s4_wbd_cyc_o = s4_wb_wr.wbd_cyc ;
+ assign s4_wbd_stb_o = s4_wb_wr.wbd_stb ;
+
+// 1KB SRAM
+ assign s5_wbd_dat_o = s5_wb_wr.wbd_dat ;
+ assign s5_wbd_adr_o = s5_wb_wr.wbd_adr[9:0] ;
+ assign s5_wbd_sel_o = s5_wb_wr.wbd_sel ;
+ assign s5_wbd_we_o = s5_wb_wr.wbd_we ;
+ assign s5_wbd_cyc_o = s5_wb_wr.wbd_cyc ;
+ assign s5_wbd_stb_o = s5_wb_wr.wbd_stb ;
+
+ assign s6_wbd_dat_o = s6_wb_wr.wbd_dat ;
+ assign s6_wbd_adr_o = s6_wb_wr.wbd_adr[9:0] ; // Global Reg Need 8 bit
+ assign s6_wbd_sel_o = s6_wb_wr.wbd_sel ;
+ assign s6_wbd_we_o = s6_wb_wr.wbd_we ;
+ assign s6_wbd_cyc_o = s6_wb_wr.wbd_cyc ;
+ assign s6_wbd_stb_o = s6_wb_wr.wbd_stb ;
+
+ assign s7_wbd_dat_o = s7_wb_wr.wbd_dat;
+ assign s7_wbd_adr_o = s7_wb_wr.wbd_adr[9:0] ; // Global Reg Need 8 bit
+ assign s7_wbd_sel_o = s7_wb_wr.wbd_sel;
+ assign s7_wbd_we_o = s7_wb_wr.wbd_we ;
+ assign s7_wbd_cyc_o = s7_wb_wr.wbd_cyc ;
+ assign s7_wbd_stb_o = s7_wb_wr.wbd_stb ;
+
+ assign s8_wbd_dat_o = s8_wb_wr.wbd_dat ;
+ assign s8_wbd_adr_o = s8_wb_wr.wbd_adr[9:0] ; // Global Reg Need 8 bit
+ assign s8_wbd_sel_o = s8_wb_wr.wbd_sel ;
+ assign s8_wbd_we_o = s8_wb_wr.wbd_we ;
+ assign s8_wbd_cyc_o = s8_wb_wr.wbd_cyc ;
+ assign s8_wbd_stb_o = s8_wb_wr.wbd_stb ;
+
+ assign s0_wb_rd.wbd_dat = s0_wbd_dat_i ;
+ assign s0_wb_rd.wbd_ack = s0_wbd_ack_i ;
+ assign s0_wb_rd.wbd_err = 1'b0; // s0_wbd_err_i ; - unused
+
+ assign s1_wb_rd.wbd_dat = s1_wbd_dat_i ;
+ assign s1_wb_rd.wbd_ack = s1_wbd_ack_i ;
+ assign s1_wb_rd.wbd_err = 1'b0; // s1_wbd_err_i ; - unused
+
+ assign s2_wb_rd.wbd_dat = s2_wbd_dat_i ;
+ assign s2_wb_rd.wbd_ack = s2_wbd_ack_i ;
+ assign s2_wb_rd.wbd_err = 1'b0; // s2_wbd_err_i ; - unused
+
+ assign s3_wb_rd.wbd_dat = s3_wbd_dat_i ;
+ assign s3_wb_rd.wbd_ack = s3_wbd_ack_i ;
+ assign s3_wb_rd.wbd_err = 1'b0; // s3_wbd_err_i ; - unused
+
+ assign s4_wb_rd.wbd_dat = s4_wbd_dat_i ;
+ assign s4_wb_rd.wbd_ack = s4_wbd_ack_i ;
+ assign s4_wb_rd.wbd_err = 1'b0; // s4_wbd_err_i ; - unused
+
+ assign s5_wb_rd.wbd_dat = s5_wbd_dat_i ;
+ assign s5_wb_rd.wbd_ack = s5_wbd_ack_i ;
+ assign s5_wb_rd.wbd_err = 1'b0; // s5_wbd_err_i ; - unused
+
+ assign s6_wb_rd.wbd_dat = s6_wbd_dat_i ;
+ assign s6_wb_rd.wbd_ack = s6_wbd_ack_i ;
+ assign s6_wb_rd.wbd_err = 1'b0; // s6_wbd_err_i ; - unused
+
+ assign s7_wb_rd.wbd_dat = s7_wbd_dat_i ;
+ assign s7_wb_rd.wbd_ack = s7_wbd_ack_i ;
+ assign s7_wb_rd.wbd_err = 1'b0; // s7_wbd_err_i ; - unused
+
+ assign s8_wb_rd.wbd_dat = s8_wbd_dat_i ;
+ assign s8_wb_rd.wbd_ack = s8_wbd_ack_i ;
+ assign s8_wb_rd.wbd_err = 1'b0; // s8_wbd_err_i ; - unused
+//
+// arbitor removed as only one master
+//
+wire [1:0] gnt = 2'b0;;
+
+
+// Generate Multiplexed Master Interface based on grant
+always_comb begin
+ case(gnt)
+ 2'h0: m_bus_wr = m0_wb_wr;
+ default: m_bus_wr = m0_wb_wr;
+ endcase
+end
+
+
+// Generate Multiplexed Slave Interface based on target Id
+wire [3:0] s_wbd_tid = s_bus_wr.wbd_tid; // to fix iverilog warning
+always_comb begin
+ case(s_wbd_tid)
+ 4'h0: s_bus_rd = s0_wb_rd;
+ 4'h1: s_bus_rd = s1_wb_rd;
+ 4'h2: s_bus_rd = s2_wb_rd;
+ 4'h3: s_bus_rd = s3_wb_rd;
+ 4'h4: s_bus_rd = s4_wb_rd;
+ 4'h5: s_bus_rd = s5_wb_rd;
+ 4'h6: s_bus_rd = s6_wb_rd;
+ 4'h7: s_bus_rd = s7_wb_rd;
+ 4'h8: s_bus_rd = s8_wb_rd;
+ default: s_bus_rd = s0_wb_rd;
+ endcase
+end
+
+
+// Connect Master => Slave
+assign s0_wb_wr = (s_wbd_tid == 4'b0000) ? s_bus_wr : 'h0;
+assign s1_wb_wr = (s_wbd_tid == 4'b0001) ? s_bus_wr : 'h0;
+assign s2_wb_wr = (s_wbd_tid == 4'b0010) ? s_bus_wr : 'h0;
+assign s3_wb_wr = (s_wbd_tid == 4'b0011) ? s_bus_wr : 'h0;
+assign s4_wb_wr = (s_wbd_tid == 4'b0100) ? s_bus_wr : 'h0;
+assign s5_wb_wr = (s_wbd_tid == 4'b0101) ? s_bus_wr : 'h0;
+assign s6_wb_wr = (s_wbd_tid == 4'b0110) ? s_bus_wr : 'h0;
+assign s7_wb_wr = (s_wbd_tid == 4'b0111) ? s_bus_wr : 'h0;
+assign s8_wb_wr = (s_wbd_tid == 4'b1000) ? s_bus_wr : 'h0;
+
+// Connect Slave to Master
+assign m0_wb_rd = (gnt == 2'b00) ? m_bus_rd : 'h0;
+
+
+// Stagging FF to break write and read timing path
+wb_stagging u_m_wb_stage(
+ .clk_i (clk_i ),
+ .rst_n (rst_n ),
+ // WishBone Input master I/P
+ .m_wbd_dat_i (m_bus_wr.wbd_dat ),
+ .m_wbd_adr_i (m_bus_wr.wbd_adr ),
+ .m_wbd_sel_i (m_bus_wr.wbd_sel ),
+ .m_wbd_we_i (m_bus_wr.wbd_we ),
+ .m_wbd_cyc_i (m_bus_wr.wbd_cyc ),
+ .m_wbd_stb_i (m_bus_wr.wbd_stb ),
+ .m_wbd_tid_i (m_bus_wr.wbd_tid ),
+ .m_wbd_dat_o (m_bus_rd.wbd_dat ),
+ .m_wbd_ack_o (m_bus_rd.wbd_ack ),
+ .m_wbd_err_o (m_bus_rd.wbd_err ),
+
+ // Slave Interface
+ .s_wbd_dat_i (s_bus_rd.wbd_dat ),
+ .s_wbd_ack_i (s_bus_rd.wbd_ack ),
+ .s_wbd_err_i (s_bus_rd.wbd_err ),
+ .s_wbd_dat_o (s_bus_wr.wbd_dat ),
+ .s_wbd_adr_o (s_bus_wr.wbd_adr ),
+ .s_wbd_sel_o (s_bus_wr.wbd_sel ),
+ .s_wbd_we_o (s_bus_wr.wbd_we ),
+ .s_wbd_cyc_o (s_bus_wr.wbd_cyc ),
+ .s_wbd_stb_o (s_bus_wr.wbd_stb ),
+ .s_wbd_tid_o (s_bus_wr.wbd_tid )
+
+);
+
+
+endmodule
+
