commit: e589cf6bdae411c5570d2582b5f72f98398fe592
[log]
author: dineshannayya <dinesh.annayya@gmail.com>
Thu Dec 15 08:15:11 2022 +0530
committer: dineshannayya <dinesh.annayya@gmail.com>
Thu Dec 15 08:15:11 2022 +0530
tree: 3c01dc45e93bdb2e518266f66cdcdafc453f836d
parent: 7ffed8dd9a3db1f2f47f3a9ef0a9413231592463 [diff]

first version

Makefile[Added - diff]
gds/user_project_wrapper.gds.gz[Added - diff]
lef/user_project_wrapper.lef.gz[Added - diff]
openlane/Makefile[Added - diff]
openlane/glbl_cfg/base.sdc[Added - diff]
openlane/glbl_cfg/config.tcl[Added - diff]
openlane/glbl_cfg/pdn.tcl[Added - diff]
openlane/glbl_cfg/pin_order.cfg[Added - diff]
openlane/mbist_top1/base.sdc[Added - diff]
openlane/mbist_top1/config.tcl[Added - diff]
openlane/mbist_top1/pin_order.cfg[Added - diff]
openlane/mbist_top1/sta.tcl[Added - diff]
openlane/mbist_top2/base.sdc[Added - diff]
openlane/mbist_top2/config.tcl[Added - diff]
openlane/mbist_top2/pin_order.cfg[Added - diff]
openlane/mbist_top2/sta.tcl[Added - diff]
openlane/user_project_wrapper/base.sdc[Added - diff]
openlane/user_project_wrapper/config.tcl[Added - diff]
openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl[Added - diff]
openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl[Added - diff]
openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper.def[Added - diff]
openlane/user_project_wrapper/fixed_dont_change/wb_port.txt[Added - diff]
openlane/user_project_wrapper/fixed_dont_change/wb_port_uniq.txt[Added - diff]
openlane/user_project_wrapper/interactive.tcl[Added - diff]
openlane/user_project_wrapper/macro.cfg[Added - diff]
openlane/user_project_wrapper/pdn_cfg.tcl[Added - diff]
openlane/user_project_wrapper/sta.tcl[Added - diff]
openlane/wb_host/base.sdc[Added - diff]
openlane/wb_host/config.tcl[Added - diff]
openlane/wb_host/pin_order.cfg[Added - diff]
openlane/wb_host/sta/Makefile[Added - diff]
openlane/wb_host/sta/func.sdc[Added - diff]
openlane/wb_host/sta/logs/sta_func.log[Added - diff]
openlane/wb_host/sta/logs/wb_host.log[Added - diff]
openlane/wb_host/sta/scripts/or_write_verilog.tcl[Added - diff]
openlane/wb_host/sta/scripts/sta.tcl[Added - diff]
openlane/wb_interconnect/base.sdc[Added - diff]
openlane/wb_interconnect/config.tcl[Added - diff]
openlane/wb_interconnect/pdn.tcl[Added - diff]
openlane/wb_interconnect/pin_order.cfg[Added - diff]
openlane/wb_interconnect/sta.tcl[Added - diff]
verilog/gl/user_project_wrapper.v.gz[Added - diff]
verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv[Added - diff]
verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.v[Added - diff]
verilog/rtl/clk_skew_adjust/synth/Makefile[Added - diff]
verilog/rtl/clk_skew_adjust/synth/synth.tcl[Added - diff]
verilog/rtl/digital_core.v[Added - diff]
verilog/rtl/glbl/src/glbl_cfg.sv[Added - diff]
verilog/rtl/glbl/src/run_iverilog[Added - diff]
verilog/rtl/glbl/src/run_verilator[Added - diff]
verilog/rtl/gmac/crc32/g_rx_crc32.v[Added - diff]
verilog/rtl/gmac/crc32/g_tx_crc32.v[Added - diff]
verilog/rtl/gmac/ctrl/eth_parser.v[Added - diff]
verilog/rtl/gmac/mac/byte_reg.v[Added - diff]
verilog/rtl/gmac/mac/dble_reg.v[Added - diff]
verilog/rtl/gmac/mac/filelist_mac.f[Added - diff]
verilog/rtl/gmac/mac/g_cfg_mgmt.v[Added - diff]
verilog/rtl/gmac/mac/g_deferral.v[Added - diff]
verilog/rtl/gmac/mac/g_deferral_rx.v[Added - diff]
verilog/rtl/gmac/mac/g_mac_core.v[Added - diff]
verilog/rtl/gmac/mac/g_md_intf.v[Added - diff]
verilog/rtl/gmac/mac/g_mii_intf.v[Added - diff]
verilog/rtl/gmac/mac/g_rx_fsm.v[Added - diff]
verilog/rtl/gmac/mac/g_rx_top.v[Added - diff]
verilog/rtl/gmac/mac/g_tx_fsm.v[Added - diff]
verilog/rtl/gmac/mac/g_tx_top.v[Added - diff]
verilog/rtl/gmac/mac/s2f_sync.v[Added - diff]
verilog/rtl/gmac/top/filelist_top.f[Added - diff]
verilog/rtl/gmac/top/g_mac_top.v[Added - diff]
verilog/rtl/lbist/src/lbist_core.sv[Added - diff]
verilog/rtl/lbist/src/lbist_reg.sv[Added - diff]
verilog/rtl/lbist/src/lbist_top.sv[Added - diff]
verilog/rtl/lbist/src/run_compile[Added - diff]
verilog/rtl/lib/async_fifo.sv[Added - diff]
verilog/rtl/lib/async_fifo.v[Added - diff]
verilog/rtl/lib/async_fifo_th.sv[Added - diff]
verilog/rtl/lib/async_reg_bus.sv[Added - diff]
verilog/rtl/lib/async_wb.sv[Added - diff]
verilog/rtl/lib/clk_buf.v[Added - diff]
verilog/rtl/lib/clk_ctl.v[Added - diff]
verilog/rtl/lib/clk_div8.v[Added - diff]
verilog/rtl/lib/clk_gate.sv[Added - diff]
verilog/rtl/lib/clk_skew_adjust.gv[Added - diff]
verilog/rtl/lib/crc_32.sv[Added - diff]
verilog/rtl/lib/ctech_cells.sv[Added - diff]
verilog/rtl/lib/dble_reg.v[Added - diff]
verilog/rtl/lib/double_sync_high.v[Added - diff]
verilog/rtl/lib/double_sync_low.v[Added - diff]
verilog/rtl/lib/g_dpath_ctrl.v[Added - diff]
verilog/rtl/lib/pulse_gen_type1.sv[Added - diff]
verilog/rtl/lib/pulse_gen_type2.sv[Added - diff]
verilog/rtl/lib/registers.v[Added - diff]
verilog/rtl/lib/reset_sync.sv[Added - diff]
verilog/rtl/lib/ser_inf_32b.sv[Added - diff]
verilog/rtl/lib/ser_shift.sv[Added - diff]
verilog/rtl/lib/sfifo.v[Added - diff]
verilog/rtl/lib/stat_counter.v[Added - diff]
verilog/rtl/lib/sync_fifo.sv[Added - diff]
verilog/rtl/lib/sync_fifo2.sv[Added - diff]
verilog/rtl/lib/sync_wbb.sv[Added - diff]
verilog/rtl/lib/toggle_sync.v[Added - diff]
verilog/rtl/lib/wb_arb.sv[Added - diff]
verilog/rtl/lib/wb_crossbar.v[Added - diff]
verilog/rtl/lib/wb_interface.v[Added - diff]
verilog/rtl/lib/wb_rd_mem2mem.v[Added - diff]
verilog/rtl/lib/wb_stagging.sv[Added - diff]
verilog/rtl/lib/wb_wr_mem2mem.v[Added - diff]
verilog/rtl/mbist/include/mbist_def.svh[Added - diff]
verilog/rtl/mbist/run_iverilog[Added - diff]
verilog/rtl/mbist/run_verilator[Added - diff]
verilog/rtl/mbist/src/core/mbist_addr_gen.sv[Added - diff]
verilog/rtl/mbist/src/core/mbist_data_cmp.sv[Added - diff]
verilog/rtl/mbist/src/core/mbist_fsm.sv[Added - diff]
verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv[Added - diff]
verilog/rtl/mbist/src/core/mbist_mux.sv[Added - diff]
verilog/rtl/mbist/src/core/mbist_op_sel.sv[Added - diff]
verilog/rtl/mbist/src/core/mbist_pat_sel.sv[Added - diff]
verilog/rtl/mbist/src/core/mbist_repair_addr.sv[Added - diff]
verilog/rtl/mbist/src/core/mbist_sti_sel.sv[Added - diff]
verilog/rtl/mbist/src/top/mbist_top.sv[Added - diff]
verilog/rtl/mbist/src/top/mbist_top1.sv[Added - diff]
verilog/rtl/mbist/src/top/mbist_top2.sv[Added - diff]
verilog/rtl/mbist_wrapper/src/mbist_wb.sv[Added - diff]
verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv[Added - diff]
verilog/rtl/uart/src/uart_cfg.sv[Added - diff]
verilog/rtl/uart/src/uart_core.sv[Added - diff]
verilog/rtl/uart/src/uart_rxfsm.sv[Added - diff]
verilog/rtl/uart/src/uart_txfsm.sv[Added - diff]
verilog/rtl/uart2wb/src/run_verilog[Added - diff]
verilog/rtl/uart2wb/src/uart2_core.sv[Added - diff]
verilog/rtl/uart2wb/src/uart2wb.sv[Added - diff]
verilog/rtl/uart2wb/src/uart_msg_handler.v[Added - diff]
verilog/rtl/uprj_netlists.v[Added - diff]
verilog/rtl/user_defines.v[Added - diff]
verilog/rtl/user_project_wrapper.v[Added - diff]
verilog/rtl/user_reg_map.v[Added - diff]
verilog/rtl/wb_host/src/run_iverilog[Added - diff]
verilog/rtl/wb_host/src/run_verilator[Added - diff]
verilog/rtl/wb_host/src/wb_host.sv[Added - diff]
verilog/rtl/wb_host/src/wb_host.sv.1[Added - diff]
verilog/rtl/wb_interconnect/src/run_iverilog[Added - diff]
verilog/rtl/wb_interconnect/src/run_verilator[Added - diff]
verilog/rtl/wb_interconnect/src/wb_interconnect.sv[Added - diff]

143 files changed

tree: 3c01dc45e93bdb2e518266f66cdcdafc453f836d

README.md

riscduino_pxt1

Riscduino Peripheral Extension Chip Set-1

Reference

Julien OURY MPW Project https://github.com/JulienOury/ChristmasTreeController.git