| Warning: propagated logic value 0 differs from constraint value of 1 on pin padframe/flash_io1_pad/DM[2]. |
| Warning: propagated logic value 0 differs from constraint value of 1 on pin padframe/flash_io1_pad/DM[1]. |
| Warning: propagated logic value 1 differs from constraint value of 0 on pin padframe/flash_io1_pad/DM[0]. |
| Warning: There are 21 input ports missing set_input_delay. |
| mprj_io[1] |
| mprj_io[4] |
| resetb |
| vccd |
| vccd1 |
| vccd2 |
| vdda |
| vdda1 |
| vdda1_2 |
| vdda2 |
| vddio |
| vddio_2 |
| vssa |
| vssa1 |
| vssa1_2 |
| vssa2 |
| vssd |
| vssd1 |
| vssd2 |
| vssio |
| vssio_2 |
| Warning: There are 51 output ports missing set_output_delay. |
| gpio |
| mprj_io[0] |
| mprj_io[12] |
| mprj_io[13] |
| mprj_io[14] |
| mprj_io[15] |
| mprj_io[16] |
| mprj_io[17] |
| mprj_io[18] |
| mprj_io[19] |
| mprj_io[1] |
| mprj_io[20] |
| mprj_io[21] |
| mprj_io[22] |
| mprj_io[23] |
| mprj_io[24] |
| mprj_io[25] |
| mprj_io[26] |
| mprj_io[27] |
| mprj_io[28] |
| mprj_io[29] |
| mprj_io[2] |
| mprj_io[30] |
| mprj_io[31] |
| mprj_io[32] |
| mprj_io[33] |
| mprj_io[34] |
| mprj_io[35] |
| mprj_io[36] |
| mprj_io[37] |
| mprj_io[3] |
| mprj_io[4] |
| mprj_io[5] |
| vccd |
| vccd1 |
| vccd2 |
| vdda |
| vdda1 |
| vdda1_2 |
| vdda2 |
| vddio |
| vddio_2 |
| vssa |
| vssa1 |
| vssa1_2 |
| vssa2 |
| vssd |
| vssd1 |
| vssd2 |
| vssio |
| vssio_2 |
| Warning: There are 93 unclocked register/latch pins. |
| clock_ctrl/_412_/CLK |
| clock_ctrl/_413_/CLK |
| clock_ctrl/_414_/CLK |
| clock_ctrl/_415_/CLK |
| clock_ctrl/_416_/CLK |
| clock_ctrl/_417_/CLK |
| clock_ctrl/_418_/CLK |
| clock_ctrl/_419_/CLK |
| clock_ctrl/_420_/CLK |
| clock_ctrl/_421_/CLK_N |
| clock_ctrl/_422_/CLK |
| clock_ctrl/_423_/CLK_N |
| clock_ctrl/_424_/CLK |
| clock_ctrl/_425_/CLK_N |
| clock_ctrl/_426_/CLK |
| clock_ctrl/_427_/CLK_N |
| clock_ctrl/_428_/CLK |
| clock_ctrl/_429_/CLK |
| clock_ctrl/_430_/CLK |
| clock_ctrl/_431_/CLK |
| clock_ctrl/_432_/CLK |
| clock_ctrl/_433_/CLK |
| clock_ctrl/_434_/CLK |
| clock_ctrl/_435_/CLK |
| clock_ctrl/_436_/CLK |
| clock_ctrl/_437_/CLK |
| clock_ctrl/_438_/CLK |
| clock_ctrl/_439_/CLK |
| clock_ctrl/_440_/CLK |
| clock_ctrl/_441_/CLK |
| clock_ctrl/_442_/CLK |
| clock_ctrl/_443_/CLK |
| clock_ctrl/_444_/CLK |
| clock_ctrl/_445_/CLK |
| clock_ctrl/_446_/CLK_N |
| clock_ctrl/_447_/CLK |
| clock_ctrl/_448_/CLK_N |
| clock_ctrl/_449_/CLK |
| clock_ctrl/_450_/CLK_N |
| clock_ctrl/_451_/CLK |
| clock_ctrl/_452_/CLK_N |
| clock_ctrl/_453_/CLK |
| clock_ctrl/_454_/CLK |
| clock_ctrl/_455_/CLK |
| clock_ctrl/_456_/CLK |
| clock_ctrl/_457_/CLK |
| clock_ctrl/_458_/CLK |
| clock_ctrl/_459_/CLK |
| clock_ctrl/_460_/CLK |
| clock_ctrl/_461_/CLK |
| clock_ctrl/_462_/CLK |
| clock_ctrl/_463_/CLK |
| clock_ctrl/_464_/CLK |
| clock_ctrl/_465_/CLK |
| mprj/u_sram0_2kb/clk1 |
| mprj/u_sram1_2kb/clk1 |
| mprj/u_sram2_2kb/clk1 |
| mprj/u_sram3_2kb/clk1 |
| mprj/u_sram4_2kb/clk1 |
| mprj/u_sram5_2kb/clk1 |
| mprj/u_sram6_2kb/clk1 |
| mprj/u_sram7_2kb/clk1 |
| pll/_455_/CLK |
| pll/_456_/CLK |
| pll/_457_/CLK |
| pll/_458_/CLK |
| pll/_459_/CLK |
| pll/_460_/CLK |
| pll/_461_/CLK |
| pll/_462_/CLK |
| pll/_463_/CLK |
| pll/_464_/CLK |
| pll/_465_/CLK |
| pll/_466_/CLK |
| pll/_467_/CLK |
| pll/_468_/CLK |
| pll/_469_/CLK |
| pll/_470_/CLK |
| pll/_471_/CLK |
| pll/_472_/CLK |
| pll/_473_/CLK |
| pll/_474_/CLK |
| pll/_475_/CLK |
| pll/_476_/CLK |
| pll/_477_/CLK |
| spare_logic[0]/spare_logic_flop[0]/CLK |
| spare_logic[0]/spare_logic_flop[1]/CLK |
| spare_logic[1]/spare_logic_flop[0]/CLK |
| spare_logic[1]/spare_logic_flop[1]/CLK |
| spare_logic[2]/spare_logic_flop[0]/CLK |
| spare_logic[2]/spare_logic_flop[1]/CLK |
| spare_logic[3]/spare_logic_flop[0]/CLK |
| spare_logic[3]/spare_logic_flop[1]/CLK |
| Warning: There are 357 unconstrained endpoints. |
| flash_io1 |
| gpio |
| mprj_io[0] |
| mprj_io[12] |
| mprj_io[13] |
| mprj_io[14] |
| mprj_io[15] |
| mprj_io[16] |
| mprj_io[17] |
| mprj_io[18] |
| mprj_io[19] |
| mprj_io[1] |
| mprj_io[20] |
| mprj_io[21] |
| mprj_io[22] |
| mprj_io[23] |
| mprj_io[24] |
| mprj_io[25] |
| mprj_io[26] |
| mprj_io[27] |
| mprj_io[28] |
| mprj_io[29] |
| mprj_io[2] |
| mprj_io[30] |
| mprj_io[31] |
| mprj_io[32] |
| mprj_io[33] |
| mprj_io[34] |
| mprj_io[35] |
| mprj_io[36] |
| mprj_io[37] |
| mprj_io[3] |
| mprj_io[4] |
| mprj_io[5] |
| vccd |
| vccd1 |
| vccd2 |
| vdda |
| vdda1 |
| vdda1_2 |
| vdda2 |
| vddio |
| vddio_2 |
| vssa |
| vssa1 |
| vssa1_2 |
| vssa2 |
| vssd |
| vssd1 |
| vssd2 |
| vssio |
| vssio_2 |
| clock_ctrl/_411_/D |
| clock_ctrl/_412_/D |
| clock_ctrl/_413_/D |
| clock_ctrl/_414_/D |
| clock_ctrl/_415_/D |
| clock_ctrl/_416_/D |
| clock_ctrl/_417_/D |
| clock_ctrl/_418_/D |
| clock_ctrl/_419_/D |
| clock_ctrl/_420_/D |
| clock_ctrl/_421_/D |
| clock_ctrl/_422_/D |
| clock_ctrl/_423_/D |
| clock_ctrl/_424_/D |
| clock_ctrl/_425_/D |
| clock_ctrl/_426_/D |
| clock_ctrl/_427_/D |
| clock_ctrl/_428_/D |
| clock_ctrl/_429_/D |
| clock_ctrl/_430_/D |
| clock_ctrl/_431_/D |
| clock_ctrl/_432_/D |
| clock_ctrl/_433_/D |
| clock_ctrl/_434_/D |
| clock_ctrl/_435_/D |
| clock_ctrl/_436_/D |
| clock_ctrl/_437_/D |
| clock_ctrl/_438_/D |
| clock_ctrl/_439_/D |
| clock_ctrl/_440_/D |
| clock_ctrl/_441_/D |
| clock_ctrl/_442_/D |
| clock_ctrl/_443_/D |
| clock_ctrl/_444_/D |
| clock_ctrl/_445_/D |
| clock_ctrl/_446_/D |
| clock_ctrl/_447_/D |
| clock_ctrl/_448_/D |
| clock_ctrl/_449_/D |
| clock_ctrl/_450_/D |
| clock_ctrl/_451_/D |
| clock_ctrl/_452_/D |
| clock_ctrl/_453_/D |
| clock_ctrl/_454_/D |
| clock_ctrl/_455_/D |
| clock_ctrl/_456_/D |
| clock_ctrl/_457_/D |
| clock_ctrl/_458_/D |
| clock_ctrl/_459_/D |
| clock_ctrl/_460_/D |
| clock_ctrl/_461_/D |
| clock_ctrl/_462_/D |
| clock_ctrl/_463_/D |
| clock_ctrl/_464_/D |
| clock_ctrl/_465_/D |
| housekeeping/_7103_/D |
| mprj/u_mbist0/_4497_/D |
| mprj/u_mbist1/_4497_/D |
| mprj/u_sram0_2kb/addr1[0] |
| mprj/u_sram0_2kb/addr1[1] |
| mprj/u_sram0_2kb/addr1[2] |
| mprj/u_sram0_2kb/addr1[3] |
| mprj/u_sram0_2kb/addr1[4] |
| mprj/u_sram0_2kb/addr1[5] |
| mprj/u_sram0_2kb/addr1[6] |
| mprj/u_sram0_2kb/addr1[7] |
| mprj/u_sram0_2kb/addr1[8] |
| mprj/u_sram0_2kb/csb1 |
| mprj/u_sram1_2kb/addr1[0] |
| mprj/u_sram1_2kb/addr1[1] |
| mprj/u_sram1_2kb/addr1[2] |
| mprj/u_sram1_2kb/addr1[3] |
| mprj/u_sram1_2kb/addr1[4] |
| mprj/u_sram1_2kb/addr1[5] |
| mprj/u_sram1_2kb/addr1[6] |
| mprj/u_sram1_2kb/addr1[7] |
| mprj/u_sram1_2kb/addr1[8] |
| mprj/u_sram1_2kb/csb1 |
| mprj/u_sram2_2kb/addr1[0] |
| mprj/u_sram2_2kb/addr1[1] |
| mprj/u_sram2_2kb/addr1[2] |
| mprj/u_sram2_2kb/addr1[3] |
| mprj/u_sram2_2kb/addr1[4] |
| mprj/u_sram2_2kb/addr1[5] |
| mprj/u_sram2_2kb/addr1[6] |
| mprj/u_sram2_2kb/addr1[7] |
| mprj/u_sram2_2kb/addr1[8] |
| mprj/u_sram2_2kb/csb1 |
| mprj/u_sram3_2kb/addr1[0] |
| mprj/u_sram3_2kb/addr1[1] |
| mprj/u_sram3_2kb/addr1[2] |
| mprj/u_sram3_2kb/addr1[3] |
| mprj/u_sram3_2kb/addr1[4] |
| mprj/u_sram3_2kb/addr1[5] |
| mprj/u_sram3_2kb/addr1[6] |
| mprj/u_sram3_2kb/addr1[7] |
| mprj/u_sram3_2kb/addr1[8] |
| mprj/u_sram3_2kb/csb1 |
| mprj/u_sram4_2kb/addr1[0] |
| mprj/u_sram4_2kb/addr1[1] |
| mprj/u_sram4_2kb/addr1[2] |
| mprj/u_sram4_2kb/addr1[3] |
| mprj/u_sram4_2kb/addr1[4] |
| mprj/u_sram4_2kb/addr1[5] |
| mprj/u_sram4_2kb/addr1[6] |
| mprj/u_sram4_2kb/addr1[7] |
| mprj/u_sram4_2kb/addr1[8] |
| mprj/u_sram4_2kb/csb1 |
| mprj/u_sram5_2kb/addr1[0] |
| mprj/u_sram5_2kb/addr1[1] |
| mprj/u_sram5_2kb/addr1[2] |
| mprj/u_sram5_2kb/addr1[3] |
| mprj/u_sram5_2kb/addr1[4] |
| mprj/u_sram5_2kb/addr1[5] |
| mprj/u_sram5_2kb/addr1[6] |
| mprj/u_sram5_2kb/addr1[7] |
| mprj/u_sram5_2kb/addr1[8] |
| mprj/u_sram5_2kb/csb1 |
| mprj/u_sram6_2kb/addr1[0] |
| mprj/u_sram6_2kb/addr1[1] |
| mprj/u_sram6_2kb/addr1[2] |
| mprj/u_sram6_2kb/addr1[3] |
| mprj/u_sram6_2kb/addr1[4] |
| mprj/u_sram6_2kb/addr1[5] |
| mprj/u_sram6_2kb/addr1[6] |
| mprj/u_sram6_2kb/addr1[7] |
| mprj/u_sram6_2kb/addr1[8] |
| mprj/u_sram6_2kb/csb1 |
| mprj/u_sram7_2kb/addr1[0] |
| mprj/u_sram7_2kb/addr1[1] |
| mprj/u_sram7_2kb/addr1[2] |
| mprj/u_sram7_2kb/addr1[3] |
| mprj/u_sram7_2kb/addr1[4] |
| mprj/u_sram7_2kb/addr1[5] |
| mprj/u_sram7_2kb/addr1[6] |
| mprj/u_sram7_2kb/addr1[7] |
| mprj/u_sram7_2kb/addr1[8] |
| mprj/u_sram7_2kb/csb1 |
| mprj/u_wb_host/_5876_/D |
| mprj/u_wb_host/_5950_/D |
| mprj/u_wb_host/_5952_/D |
| mprj/u_wb_host/_6415_/D |
| mprj/u_wb_host/u_lbist.u_lbist_core.u_scan_gate.u_clk_gate/SCE |
| pll/_455_/D |
| pll/_456_/D |
| pll/_457_/D |
| pll/_458_/D |
| pll/_459_/D |
| pll/_460_/D |
| pll/_461_/D |
| pll/_462_/D |
| pll/_463_/D |
| pll/_464_/D |
| pll/_465_/D |
| pll/_466_/D |
| pll/_467_/D |
| pll/_468_/D |
| pll/_469_/D |
| pll/_470_/D |
| pll/_471_/D |
| pll/_472_/D |
| pll/_473_/D |
| pll/_474_/D |
| pll/_475_/D |
| pll/_476_/D |
| pll/_477_/D |
| soc/_30518_/D |
| soc/_30520_/D |
| soc/_30522_/D |
| soc/_30524_/D |
| soc/_30526_/D |
| soc/_30528_/D |
| soc/_30530_/D |
| soc/_30532_/D |
| soc/_30534_/D |
| soc/_30536_/D |
| soc/_30538_/D |
| soc/_30540_/D |
| soc/_30542_/D |
| soc/_30544_/D |
| soc/_30546_/D |
| soc/_30548_/D |
| soc/_30550_/D |
| soc/_30552_/D |
| soc/_30554_/D |
| soc/_30556_/D |
| soc/_30558_/D |
| soc/_30560_/D |
| soc/_30562_/D |
| soc/_30564_/D |
| soc/_30566_/D |
| soc/_30568_/D |
| soc/_30570_/D |
| soc/_30572_/D |
| soc/_30574_/D |
| soc/_30576_/D |
| soc/_30578_/D |
| soc/_30580_/D |
| soc/_30582_/D |
| soc/_30584_/D |
| soc/_30586_/D |
| soc/_30588_/D |
| soc/_30590_/D |
| soc/_30592_/D |
| soc/_30594_/D |
| soc/_30596_/D |
| soc/_30598_/D |
| soc/_30600_/D |
| soc/_30602_/D |
| soc/_30604_/D |
| soc/_30606_/D |
| soc/_30608_/D |
| soc/_30610_/D |
| soc/_30612_/D |
| soc/_30614_/D |
| soc/_30616_/D |
| soc/_30618_/D |
| soc/_30620_/D |
| soc/_30622_/D |
| soc/_30624_/D |
| soc/_30626_/D |
| soc/_30628_/D |
| soc/_30630_/D |
| soc/_30632_/D |
| soc/_30634_/D |
| soc/_30636_/D |
| soc/_30638_/D |
| soc/_30640_/D |
| soc/_30642_/D |
| soc/_30644_/D |
| soc/_30646_/D |
| soc/_30648_/D |
| soc/_30650_/D |
| soc/_30652_/D |
| soc/_30654_/D |
| soc/_30656_/D |
| soc/_30658_/D |
| soc/_30660_/D |
| soc/_30662_/D |
| soc/_30664_/D |
| soc/_30666_/D |
| soc/_30668_/D |
| soc/_30670_/D |
| soc/_30672_/D |
| soc/_30674_/D |
| soc/_30676_/D |
| soc/_30678_/D |
| soc/_30680_/D |
| soc/_30682_/D |
| soc/_30684_/D |
| soc/_30686_/D |
| soc/_30688_/D |
| soc/_30690_/D |
| soc/_30692_/D |
| soc/_30694_/D |
| soc/_30696_/D |
| soc/_30698_/D |
| soc/_30700_/D |
| soc/_30702_/D |
| soc/_30704_/D |
| soc/_30706_/D |
| soc/_30708_/D |
| soc/_30710_/D |
| soc/_30712_/D |
| soc/_30714_/D |
| soc/_30716_/D |
| soc/_30718_/D |
| soc/_30720_/D |
| soc/_30722_/D |
| soc/_30724_/D |
| soc/_30726_/D |
| soc/_30728_/D |
| soc/_30730_/D |
| soc/_30732_/D |
| soc/_30734_/D |
| soc/_30736_/D |
| soc/_30738_/D |
| soc/_30740_/D |
| soc/_30742_/D |
| soc/_30744_/D |
| soc/_30746_/D |
| soc/_30748_/D |
| soc/_30750_/D |
| soc/_30752_/D |
| soc/_30754_/D |
| soc/_30756_/D |
| soc/_32552_/D |
| soc/_32554_/D |
| soc/_32556_/D |
| soc/_32558_/D |
| soc/_32560_/D |
| soc/_32566_/D |
| soc/_32568_/D |
| soc/_32570_/D |
| soc/_32571_/D |
| soc/_32573_/D |
| soc/_32582_/D |
| spare_logic[0]/spare_logic_flop[0]/D |
| spare_logic[0]/spare_logic_flop[1]/D |
| spare_logic[1]/spare_logic_flop[0]/D |
| spare_logic[1]/spare_logic_flop[1]/D |
| spare_logic[2]/spare_logic_flop[0]/D |
| spare_logic[2]/spare_logic_flop[1]/D |
| spare_logic[3]/spare_logic_flop[0]/D |
| spare_logic[3]/spare_logic_flop[1]/D |
| Warning: There are 3 combinational loops in the design. |
| pll/ringosc.dstage[9].id.delayen1/Z |
| pll/ringosc.dstage[9].id.delayint0/A |
| pll/ringosc.dstage[9].id.delayint0/Y |
| pll/ringosc.dstage[9].id.delayen0/A |
| pll/ringosc.dstage[9].id.delayen0/Z |
| pll/ringosc.dstage[10].id.delaybuf0/A |
| pll/ringosc.dstage[10].id.delaybuf0/X |
| pll/ringosc.dstage[10].id.delaybuf1/A |
| pll/ringosc.dstage[10].id.delaybuf1/X |
| pll/ringosc.dstage[10].id.delayen1/A |
| pll/ringosc.dstage[10].id.delayen1/Z |
| pll/ringosc.dstage[10].id.delayint0/A |
| pll/ringosc.dstage[10].id.delayint0/Y |
| pll/ringosc.dstage[10].id.delayen0/A |
| pll/ringosc.dstage[10].id.delayen0/Z |
| pll/ringosc.dstage[11].id.delaybuf0/A |
| pll/ringosc.dstage[11].id.delaybuf0/X |
| pll/ringosc.dstage[11].id.delaybuf1/A |
| pll/ringosc.dstage[11].id.delaybuf1/X |
| pll/ringosc.dstage[11].id.delayen1/A |
| pll/ringosc.dstage[11].id.delayen1/Z |
| pll/ringosc.dstage[11].id.delayint0/A |
| pll/ringosc.dstage[11].id.delayint0/Y |
| pll/ringosc.dstage[11].id.delayen0/A |
| pll/ringosc.dstage[11].id.delayen0/Z |
| pll/ringosc.iss.delaybuf0/A |
| pll/ringosc.iss.delaybuf0/X |
| pll/ringosc.iss.delayen1/A |
| pll/ringosc.iss.delayen1/Z |
| pll/ringosc.iss.delayint0/A |
| pll/ringosc.iss.delayint0/Y |
| pll/ringosc.iss.delayen0/A |
| pll/ringosc.iss.delayen0/Z |
| pll/ringosc.dstage[0].id.delaybuf0/A |
| pll/ringosc.dstage[0].id.delaybuf0/X |
| pll/ringosc.dstage[0].id.delaybuf1/A |
| pll/ringosc.dstage[0].id.delaybuf1/X |
| pll/ringosc.dstage[0].id.delayen1/A |
| pll/ringosc.dstage[0].id.delayen1/Z |
| pll/ringosc.dstage[0].id.delayint0/A |
| pll/ringosc.dstage[0].id.delayint0/Y |
| pll/ringosc.dstage[0].id.delayen0/A |
| pll/ringosc.dstage[0].id.delayen0/Z |
| pll/ringosc.dstage[1].id.delaybuf0/A |
| pll/ringosc.dstage[1].id.delaybuf0/X |
| pll/ringosc.dstage[1].id.delaybuf1/A |
| pll/ringosc.dstage[1].id.delaybuf1/X |
| pll/ringosc.dstage[1].id.delayen1/A |
| pll/ringosc.dstage[1].id.delayen1/Z |
| pll/ringosc.dstage[1].id.delayint0/A |
| pll/ringosc.dstage[1].id.delayint0/Y |
| pll/ringosc.dstage[1].id.delayen0/A |
| pll/ringosc.dstage[1].id.delayen0/Z |
| pll/ringosc.dstage[2].id.delaybuf0/A |
| pll/ringosc.dstage[2].id.delaybuf0/X |
| pll/ringosc.dstage[2].id.delaybuf1/A |
| pll/ringosc.dstage[2].id.delaybuf1/X |
| pll/ringosc.dstage[2].id.delayen1/A |
| pll/ringosc.dstage[2].id.delayen1/Z |
| pll/ringosc.dstage[2].id.delayint0/A |
| pll/ringosc.dstage[2].id.delayint0/Y |
| pll/ringosc.dstage[2].id.delayen0/A |
| pll/ringosc.dstage[2].id.delayen0/Z |
| pll/ringosc.dstage[3].id.delaybuf0/A |
| pll/ringosc.dstage[3].id.delaybuf0/X |
| pll/ringosc.dstage[3].id.delaybuf1/A |
| pll/ringosc.dstage[3].id.delaybuf1/X |
| pll/ringosc.dstage[3].id.delayen1/A |
| pll/ringosc.dstage[3].id.delayen1/Z |
| pll/ringosc.dstage[3].id.delayint0/A |
| pll/ringosc.dstage[3].id.delayint0/Y |
| pll/ringosc.dstage[3].id.delayen0/A |
| pll/ringosc.dstage[3].id.delayen0/Z |
| pll/ringosc.dstage[4].id.delaybuf0/A |
| pll/ringosc.dstage[4].id.delaybuf0/X |
| pll/ringosc.dstage[4].id.delaybuf1/A |
| pll/ringosc.dstage[4].id.delaybuf1/X |
| pll/ringosc.dstage[4].id.delayen1/A |
| pll/ringosc.dstage[4].id.delayen1/Z |
| pll/ringosc.dstage[4].id.delayint0/A |
| pll/ringosc.dstage[4].id.delayint0/Y |
| pll/ringosc.dstage[4].id.delayen0/A |
| pll/ringosc.dstage[4].id.delayen0/Z |
| pll/ringosc.dstage[5].id.delaybuf0/A |
| pll/ringosc.dstage[5].id.delaybuf0/X |
| pll/ringosc.dstage[5].id.delaybuf1/A |
| pll/ringosc.dstage[5].id.delaybuf1/X |
| pll/ringosc.dstage[5].id.delayen1/A |
| pll/ringosc.dstage[5].id.delayen1/Z |
| pll/ringosc.dstage[5].id.delayint0/A |
| pll/ringosc.dstage[5].id.delayint0/Y |
| pll/ringosc.dstage[5].id.delayen0/A |
| pll/ringosc.dstage[5].id.delayen0/Z |
| pll/ringosc.dstage[6].id.delaybuf0/A |
| pll/ringosc.dstage[6].id.delaybuf0/X |
| pll/ringosc.dstage[6].id.delaybuf1/A |
| pll/ringosc.dstage[6].id.delaybuf1/X |
| pll/ringosc.dstage[6].id.delayen1/A |
| pll/ringosc.dstage[6].id.delayen1/Z |
| pll/ringosc.dstage[6].id.delayint0/A |
| pll/ringosc.dstage[6].id.delayint0/Y |
| pll/ringosc.dstage[6].id.delayen0/A |
| pll/ringosc.dstage[6].id.delayen0/Z |
| pll/ringosc.dstage[7].id.delaybuf0/A |
| pll/ringosc.dstage[7].id.delaybuf0/X |
| pll/ringosc.dstage[7].id.delaybuf1/A |
| pll/ringosc.dstage[7].id.delaybuf1/X |
| pll/ringosc.dstage[7].id.delayen1/A |
| pll/ringosc.dstage[7].id.delayen1/Z |
| pll/ringosc.dstage[7].id.delayint0/A |
| pll/ringosc.dstage[7].id.delayint0/Y |
| pll/ringosc.dstage[7].id.delayen0/A |
| pll/ringosc.dstage[7].id.delayen0/Z |
| pll/ringosc.dstage[8].id.delaybuf0/A |
| pll/ringosc.dstage[8].id.delaybuf0/X |
| pll/ringosc.dstage[8].id.delaybuf1/A |
| pll/ringosc.dstage[8].id.delaybuf1/X |
| pll/ringosc.dstage[8].id.delayen1/A |
| pll/ringosc.dstage[8].id.delayen1/Z |
| pll/ringosc.dstage[8].id.delayint0/A |
| pll/ringosc.dstage[8].id.delayint0/Y |
| pll/ringosc.dstage[8].id.delayen0/A |
| pll/ringosc.dstage[8].id.delayen0/Z |
| pll/ringosc.dstage[9].id.delaybuf0/A |
| pll/ringosc.dstage[9].id.delaybuf0/X |
| pll/ringosc.dstage[9].id.delaybuf1/A |
| pll/ringosc.dstage[9].id.delaybuf1/X |
| pll/ringosc.dstage[9].id.delayen1/A |
| | loop cut point |
| pll/ringosc.dstage[9].id.delayen1/Z |
| -------------------------------- |
| pll/ringosc.dstage[10].id.delaybuf0/A |
| pll/ringosc.dstage[10].id.delaybuf0/X |
| pll/ringosc.dstage[10].id.delaybuf1/A |
| pll/ringosc.dstage[10].id.delaybuf1/X |
| pll/ringosc.dstage[10].id.delayen1/A |
| pll/ringosc.dstage[10].id.delayen1/Z |
| pll/ringosc.dstage[10].id.delayint0/A |
| pll/ringosc.dstage[10].id.delayint0/Y |
| pll/ringosc.dstage[10].id.delayen0/A |
| pll/ringosc.dstage[10].id.delayen0/Z |
| pll/ringosc.dstage[11].id.delaybuf0/A |
| pll/ringosc.dstage[11].id.delaybuf0/X |
| pll/ringosc.dstage[11].id.delaybuf1/A |
| pll/ringosc.dstage[11].id.delaybuf1/X |
| pll/ringosc.dstage[11].id.delayen1/A |
| pll/ringosc.dstage[11].id.delayen1/Z |
| pll/ringosc.dstage[11].id.delayint0/A |
| pll/ringosc.dstage[11].id.delayint0/Y |
| pll/ringosc.dstage[11].id.delayen0/A |
| pll/ringosc.dstage[11].id.delayen0/Z |
| pll/ringosc.iss.delaybuf0/A |
| pll/ringosc.iss.delaybuf0/X |
| pll/ringosc.iss.delayen1/A |
| pll/ringosc.iss.delayen1/Z |
| pll/ringosc.iss.delayint0/A |
| pll/ringosc.iss.delayint0/Y |
| pll/ringosc.iss.delayen0/A |
| pll/ringosc.iss.delayen0/Z |
| pll/ringosc.dstage[0].id.delaybuf0/A |
| pll/ringosc.dstage[0].id.delaybuf0/X |
| pll/ringosc.dstage[0].id.delaybuf1/A |
| pll/ringosc.dstage[0].id.delaybuf1/X |
| pll/ringosc.dstage[0].id.delayen1/A |
| pll/ringosc.dstage[0].id.delayen1/Z |
| pll/ringosc.dstage[0].id.delayint0/A |
| pll/ringosc.dstage[0].id.delayint0/Y |
| pll/ringosc.dstage[0].id.delayen0/A |
| pll/ringosc.dstage[0].id.delayen0/Z |
| pll/ringosc.dstage[1].id.delaybuf0/A |
| pll/ringosc.dstage[1].id.delaybuf0/X |
| pll/ringosc.dstage[1].id.delaybuf1/A |
| pll/ringosc.dstage[1].id.delaybuf1/X |
| pll/ringosc.dstage[1].id.delayen1/A |
| pll/ringosc.dstage[1].id.delayen1/Z |
| pll/ringosc.dstage[1].id.delayint0/A |
| pll/ringosc.dstage[1].id.delayint0/Y |
| pll/ringosc.dstage[1].id.delayen0/A |
| pll/ringosc.dstage[1].id.delayen0/Z |
| pll/ringosc.dstage[2].id.delaybuf0/A |
| pll/ringosc.dstage[2].id.delaybuf0/X |
| pll/ringosc.dstage[2].id.delaybuf1/A |
| pll/ringosc.dstage[2].id.delaybuf1/X |
| pll/ringosc.dstage[2].id.delayen1/A |
| pll/ringosc.dstage[2].id.delayen1/Z |
| pll/ringosc.dstage[2].id.delayint0/A |
| pll/ringosc.dstage[2].id.delayint0/Y |
| pll/ringosc.dstage[2].id.delayen0/A |
| pll/ringosc.dstage[2].id.delayen0/Z |
| pll/ringosc.dstage[3].id.delaybuf0/A |
| pll/ringosc.dstage[3].id.delaybuf0/X |
| pll/ringosc.dstage[3].id.delaybuf1/A |
| pll/ringosc.dstage[3].id.delaybuf1/X |
| pll/ringosc.dstage[3].id.delayen1/A |
| pll/ringosc.dstage[3].id.delayen1/Z |
| pll/ringosc.dstage[3].id.delayint0/A |
| pll/ringosc.dstage[3].id.delayint0/Y |
| pll/ringosc.dstage[3].id.delayen0/A |
| pll/ringosc.dstage[3].id.delayen0/Z |
| pll/ringosc.dstage[4].id.delaybuf0/A |
| pll/ringosc.dstage[4].id.delaybuf0/X |
| pll/ringosc.dstage[4].id.delaybuf1/A |
| pll/ringosc.dstage[4].id.delaybuf1/X |
| pll/ringosc.dstage[4].id.delayen1/A |
| pll/ringosc.dstage[4].id.delayen1/Z |
| pll/ringosc.dstage[4].id.delayint0/A |
| pll/ringosc.dstage[4].id.delayint0/Y |
| pll/ringosc.dstage[4].id.delayen0/A |
| pll/ringosc.dstage[4].id.delayen0/Z |
| pll/ringosc.dstage[5].id.delaybuf0/A |
| pll/ringosc.dstage[5].id.delaybuf0/X |
| pll/ringosc.dstage[5].id.delaybuf1/A |
| pll/ringosc.dstage[5].id.delaybuf1/X |
| pll/ringosc.dstage[5].id.delayen1/A |
| pll/ringosc.dstage[5].id.delayen1/Z |
| pll/ringosc.dstage[5].id.delayint0/A |
| pll/ringosc.dstage[5].id.delayint0/Y |
| pll/ringosc.dstage[5].id.delayen0/A |
| pll/ringosc.dstage[5].id.delayen0/Z |
| pll/ringosc.dstage[6].id.delaybuf0/A |
| pll/ringosc.dstage[6].id.delaybuf0/X |
| pll/ringosc.dstage[6].id.delaybuf1/A |
| pll/ringosc.dstage[6].id.delaybuf1/X |
| pll/ringosc.dstage[6].id.delayen1/A |
| pll/ringosc.dstage[6].id.delayen1/Z |
| pll/ringosc.dstage[6].id.delayint0/A |
| pll/ringosc.dstage[6].id.delayint0/Y |
| pll/ringosc.dstage[6].id.delayen0/A |
| pll/ringosc.dstage[6].id.delayen0/Z |
| pll/ringosc.dstage[7].id.delaybuf0/A |
| pll/ringosc.dstage[7].id.delaybuf0/X |
| pll/ringosc.dstage[7].id.delaybuf1/A |
| pll/ringosc.dstage[7].id.delaybuf1/X |
| pll/ringosc.dstage[7].id.delayen1/A |
| pll/ringosc.dstage[7].id.delayen1/Z |
| pll/ringosc.dstage[7].id.delayint0/A |
| pll/ringosc.dstage[7].id.delayint0/Y |
| pll/ringosc.dstage[7].id.delayen0/A |
| pll/ringosc.dstage[7].id.delayen0/Z |
| pll/ringosc.dstage[8].id.delaybuf0/A |
| pll/ringosc.dstage[8].id.delaybuf0/X |
| pll/ringosc.dstage[8].id.delaybuf1/A |
| pll/ringosc.dstage[8].id.delaybuf1/X |
| pll/ringosc.dstage[8].id.delayen1/A |
| pll/ringosc.dstage[8].id.delayen1/Z |
| pll/ringosc.dstage[8].id.delayint0/A |
| pll/ringosc.dstage[8].id.delayint0/Y |
| pll/ringosc.dstage[8].id.delayen0/A |
| pll/ringosc.dstage[8].id.delayen0/Z |
| pll/ringosc.dstage[9].id.delaybuf0/A |
| pll/ringosc.dstage[9].id.delaybuf0/X |
| pll/ringosc.dstage[9].id.delayenb0/A |
| pll/ringosc.dstage[9].id.delayenb0/Z |
| | loop cut point |
| pll/ringosc.dstage[10].id.delaybuf0/A |
| -------------------------------- |
| pll/ringosc.dstage[9].id.delayint0/A |
| pll/ringosc.dstage[9].id.delayint0/Y |
| pll/ringosc.dstage[9].id.delayen0/A |
| pll/ringosc.dstage[9].id.delayen0/Z |
| pll/ringosc.dstage[10].id.delaybuf0/A |
| pll/ringosc.dstage[10].id.delaybuf0/X |
| pll/ringosc.dstage[10].id.delaybuf1/A |
| pll/ringosc.dstage[10].id.delaybuf1/X |
| pll/ringosc.dstage[10].id.delayen1/A |
| pll/ringosc.dstage[10].id.delayen1/Z |
| pll/ringosc.dstage[10].id.delayint0/A |
| pll/ringosc.dstage[10].id.delayint0/Y |
| pll/ringosc.dstage[10].id.delayen0/A |
| pll/ringosc.dstage[10].id.delayen0/Z |
| pll/ringosc.dstage[11].id.delaybuf0/A |
| pll/ringosc.dstage[11].id.delaybuf0/X |
| pll/ringosc.dstage[11].id.delaybuf1/A |
| pll/ringosc.dstage[11].id.delaybuf1/X |
| pll/ringosc.dstage[11].id.delayen1/A |
| pll/ringosc.dstage[11].id.delayen1/Z |
| pll/ringosc.dstage[11].id.delayint0/A |
| pll/ringosc.dstage[11].id.delayint0/Y |
| pll/ringosc.dstage[11].id.delayen0/A |
| pll/ringosc.dstage[11].id.delayen0/Z |
| pll/ringosc.iss.delaybuf0/A |
| pll/ringosc.iss.delaybuf0/X |
| pll/ringosc.iss.delayen1/A |
| pll/ringosc.iss.delayen1/Z |
| pll/ringosc.iss.delayint0/A |
| pll/ringosc.iss.delayint0/Y |
| pll/ringosc.iss.delayen0/A |
| pll/ringosc.iss.delayen0/Z |
| pll/ringosc.dstage[0].id.delaybuf0/A |
| pll/ringosc.dstage[0].id.delaybuf0/X |
| pll/ringosc.dstage[0].id.delaybuf1/A |
| pll/ringosc.dstage[0].id.delaybuf1/X |
| pll/ringosc.dstage[0].id.delayen1/A |
| pll/ringosc.dstage[0].id.delayen1/Z |
| pll/ringosc.dstage[0].id.delayint0/A |
| pll/ringosc.dstage[0].id.delayint0/Y |
| pll/ringosc.dstage[0].id.delayen0/A |
| pll/ringosc.dstage[0].id.delayen0/Z |
| pll/ringosc.dstage[1].id.delaybuf0/A |
| pll/ringosc.dstage[1].id.delaybuf0/X |
| pll/ringosc.dstage[1].id.delaybuf1/A |
| pll/ringosc.dstage[1].id.delaybuf1/X |
| pll/ringosc.dstage[1].id.delayen1/A |
| pll/ringosc.dstage[1].id.delayen1/Z |
| pll/ringosc.dstage[1].id.delayint0/A |
| pll/ringosc.dstage[1].id.delayint0/Y |
| pll/ringosc.dstage[1].id.delayen0/A |
| pll/ringosc.dstage[1].id.delayen0/Z |
| pll/ringosc.dstage[2].id.delaybuf0/A |
| pll/ringosc.dstage[2].id.delaybuf0/X |
| pll/ringosc.dstage[2].id.delaybuf1/A |
| pll/ringosc.dstage[2].id.delaybuf1/X |
| pll/ringosc.dstage[2].id.delayen1/A |
| pll/ringosc.dstage[2].id.delayen1/Z |
| pll/ringosc.dstage[2].id.delayint0/A |
| pll/ringosc.dstage[2].id.delayint0/Y |
| pll/ringosc.dstage[2].id.delayen0/A |
| pll/ringosc.dstage[2].id.delayen0/Z |
| pll/ringosc.dstage[3].id.delaybuf0/A |
| pll/ringosc.dstage[3].id.delaybuf0/X |
| pll/ringosc.dstage[3].id.delaybuf1/A |
| pll/ringosc.dstage[3].id.delaybuf1/X |
| pll/ringosc.dstage[3].id.delayen1/A |
| pll/ringosc.dstage[3].id.delayen1/Z |
| pll/ringosc.dstage[3].id.delayint0/A |
| pll/ringosc.dstage[3].id.delayint0/Y |
| pll/ringosc.dstage[3].id.delayen0/A |
| pll/ringosc.dstage[3].id.delayen0/Z |
| pll/ringosc.dstage[4].id.delaybuf0/A |
| pll/ringosc.dstage[4].id.delaybuf0/X |
| pll/ringosc.dstage[4].id.delaybuf1/A |
| pll/ringosc.dstage[4].id.delaybuf1/X |
| pll/ringosc.dstage[4].id.delayen1/A |
| pll/ringosc.dstage[4].id.delayen1/Z |
| pll/ringosc.dstage[4].id.delayint0/A |
| pll/ringosc.dstage[4].id.delayint0/Y |
| pll/ringosc.dstage[4].id.delayen0/A |
| pll/ringosc.dstage[4].id.delayen0/Z |
| pll/ringosc.dstage[5].id.delaybuf0/A |
| pll/ringosc.dstage[5].id.delaybuf0/X |
| pll/ringosc.dstage[5].id.delaybuf1/A |
| pll/ringosc.dstage[5].id.delaybuf1/X |
| pll/ringosc.dstage[5].id.delayen1/A |
| pll/ringosc.dstage[5].id.delayen1/Z |
| pll/ringosc.dstage[5].id.delayint0/A |
| pll/ringosc.dstage[5].id.delayint0/Y |
| pll/ringosc.dstage[5].id.delayen0/A |
| pll/ringosc.dstage[5].id.delayen0/Z |
| pll/ringosc.dstage[6].id.delaybuf0/A |
| pll/ringosc.dstage[6].id.delaybuf0/X |
| pll/ringosc.dstage[6].id.delaybuf1/A |
| pll/ringosc.dstage[6].id.delaybuf1/X |
| pll/ringosc.dstage[6].id.delayen1/A |
| pll/ringosc.dstage[6].id.delayen1/Z |
| pll/ringosc.dstage[6].id.delayint0/A |
| pll/ringosc.dstage[6].id.delayint0/Y |
| pll/ringosc.dstage[6].id.delayen0/A |
| pll/ringosc.dstage[6].id.delayen0/Z |
| pll/ringosc.dstage[7].id.delaybuf0/A |
| pll/ringosc.dstage[7].id.delaybuf0/X |
| pll/ringosc.dstage[7].id.delaybuf1/A |
| pll/ringosc.dstage[7].id.delaybuf1/X |
| pll/ringosc.dstage[7].id.delayen1/A |
| pll/ringosc.dstage[7].id.delayen1/Z |
| pll/ringosc.dstage[7].id.delayint0/A |
| pll/ringosc.dstage[7].id.delayint0/Y |
| pll/ringosc.dstage[7].id.delayen0/A |
| pll/ringosc.dstage[7].id.delayen0/Z |
| pll/ringosc.dstage[8].id.delaybuf0/A |
| pll/ringosc.dstage[8].id.delaybuf0/X |
| pll/ringosc.dstage[8].id.delaybuf1/A |
| pll/ringosc.dstage[8].id.delaybuf1/X |
| pll/ringosc.dstage[8].id.delayen1/A |
| pll/ringosc.dstage[8].id.delayen1/Z |
| pll/ringosc.dstage[8].id.delayint0/A |
| pll/ringosc.dstage[8].id.delayint0/Y |
| pll/ringosc.dstage[8].id.delayen0/A |
| pll/ringosc.dstage[8].id.delayen0/Z |
| pll/ringosc.dstage[9].id.delaybuf0/A |
| pll/ringosc.dstage[9].id.delaybuf0/X |
| pll/ringosc.dstage[9].id.delayenb1/A |
| pll/ringosc.dstage[9].id.delayenb1/Z |
| | loop cut point |
| pll/ringosc.dstage[9].id.delayint0/A |
| -------------------------------- |
