tapeout check FOM denisty fix
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index 57e93ac..b938dd7 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz
index 675a160..17d0c06 100644
--- a/lef/user_project_wrapper.lef.gz
+++ b/lef/user_project_wrapper.lef.gz
Binary files differ
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a8111ff..5a5aad4 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -11,11 +11,11 @@
u_sram2_2kb 150 1100 N
u_sram3_2kb 975 1100 N
-u_mbist1 150 2100 N
-u_sram4_2kb 150 1600 FS
-u_sram5_2kb 975 1600 FS
-u_sram6_2kb 150 2400 N
-u_sram7_2kb 975 2400 N
+u_mbist1 150 2200 N
+u_sram4_2kb 150 1700 FS
+u_sram5_2kb 975 1700 FS
+u_sram6_2kb 150 2500 N
+u_sram7_2kb 975 2500 N
u_rp_south 100 20 N
u_rp_north 100 3400 N
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index e345bad..f359a61 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -72,7 +72,7 @@
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 200 1500"
+set ::env(DIE_AREA) "0 0 200 1600"
# If you're going to use multiple power domains, then keep this disabled.
@@ -82,8 +82,8 @@
set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.22"
-#set ::env(CELL_PAD) "8"
+set ::env(PL_TARGET_DENSITY) "0.16"
+set ::env(CELL_PAD) "12"
## Routing
set ::env(GRT_ADJUSTMENT) 0.2
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index f085729..f39483f 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg
@@ -226,10 +226,10 @@
s2_wbd_dat_i\[0\]
s2_wbd_ack_i
-ch_clk_out\[2\] 1300 0 2
+ch_clk_out\[2\] 1400 0 2
-s3_wbd_cyc_o 1350 0 2
+s3_wbd_cyc_o 1450 0 2
s3_wbd_stb_o
s3_wbd_we_o
s3_wbd_adr_o\[14\]
diff --git a/sdc/user_project_wrapper.sdc b/sdc/user_project_wrapper.sdc
index a371c21..b36ab7a 100644
--- a/sdc/user_project_wrapper.sdc
+++ b/sdc/user_project_wrapper.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Sat Dec 31 10:51:33 2022
+# Sun Jan 1 05:45:20 2023
###############################################################################
current_design user_project_wrapper
###############################################################################
diff --git a/sdc/wb_interconnect.sdc b/sdc/wb_interconnect.sdc
index 395fc25..53c4ecf 100644
--- a/sdc/wb_interconnect.sdc
+++ b/sdc/wb_interconnect.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Sat Dec 24 06:37:19 2022
+# Sun Jan 1 03:58:42 2023
###############################################################################
current_design wb_interconnect
###############################################################################
diff --git a/verilog/gl/user_project_wrapper.v.gz b/verilog/gl/user_project_wrapper.v.gz
index 20b9f44..8b100d8 100644
--- a/verilog/gl/user_project_wrapper.v.gz
+++ b/verilog/gl/user_project_wrapper.v.gz
Binary files differ
