sdc/mbist_wrapper.sdc

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# Created by write_sdc
# Sat Dec 24 06:38:39 2022
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current_design mbist_wrapper
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# Timing Constraints
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create_clock -name wb_clk_i -period 10.0000 [get_ports {wb_clk_i}]
set_clock_transition 0.1500 [get_clocks {wb_clk_i}]
set_clock_uncertainty 0.2500 wb_clk_i
set_propagated_clock [get_clocks {wb_clk_i}]
create_clock -name wb_clk2_i -period 10.0000 [get_ports {wb_clk2_i}]
set_clock_transition 0.1500 [get_clocks {wb_clk2_i}]
set_clock_uncertainty 0.2500 wb_clk2_i
set_propagated_clock [get_clocks {wb_clk2_i}]
create_generated_clock -name bist_mem_clk_a[0] -add -source [get_ports {wb_clk2_i}] -master_clock [get_clocks {wb_clk2_i}] -divide_by 1 -comment {Mem Clock A0} [get_ports {mem_clk_a[0]}]
set_clock_transition 0.1500 [get_clocks {bist_mem_clk_a[0]}]
set_clock_uncertainty 0.2500 bist_mem_clk_a[0]
set_propagated_clock [get_clocks {bist_mem_clk_a[0]}]
create_generated_clock -name bist_mem_clk_a[1] -add -source [get_ports {wb_clk2_i}] -master_clock [get_clocks {wb_clk2_i}] -divide_by 1 -comment {Mem Clock A1} [get_ports {mem_clk_a[1]}]
set_clock_transition 0.1500 [get_clocks {bist_mem_clk_a[1]}]
set_clock_uncertainty 0.2500 bist_mem_clk_a[1]
set_propagated_clock [get_clocks {bist_mem_clk_a[1]}]
create_generated_clock -name bist_mem_clk_a[2] -add -source [get_ports {wb_clk2_i}] -master_clock [get_clocks {wb_clk2_i}] -divide_by 1 -comment {Mem Clock A2} [get_ports {mem_clk_a[2]}]
set_clock_transition 0.1500 [get_clocks {bist_mem_clk_a[2]}]
set_clock_uncertainty 0.2500 bist_mem_clk_a[2]
set_propagated_clock [get_clocks {bist_mem_clk_a[2]}]
create_generated_clock -name bist_mem_clk_a[3] -add -source [get_ports {wb_clk2_i}] -master_clock [get_clocks {wb_clk2_i}] -divide_by 1 -comment {Mem Clock A3} [get_ports {mem_clk_a[3]}]
set_clock_transition 0.1500 [get_clocks {bist_mem_clk_a[3]}]
set_clock_uncertainty 0.2500 bist_mem_clk_a[3]
set_propagated_clock [get_clocks {bist_mem_clk_a[3]}]
create_generated_clock -name bist_mem_clk_b[0] -add -source [get_ports {wb_clk2_i}] -master_clock [get_clocks {wb_clk2_i}] -divide_by 1 -comment {Mem Clock B0} [get_ports {mem_clk_b[0]}]
set_clock_transition 0.1500 [get_clocks {bist_mem_clk_b[0]}]
set_clock_uncertainty 0.2500 bist_mem_clk_b[0]
set_propagated_clock [get_clocks {bist_mem_clk_b[0]}]
create_generated_clock -name bist_mem_clk_b[1] -add -source [get_ports {wb_clk2_i}] -master_clock [get_clocks {wb_clk2_i}] -divide_by 1 -comment {Mem Clock B1} [get_ports {mem_clk_b[1]}]
set_clock_transition 0.1500 [get_clocks {bist_mem_clk_b[1]}]
set_clock_uncertainty 0.2500 bist_mem_clk_b[1]
set_propagated_clock [get_clocks {bist_mem_clk_b[1]}]
create_generated_clock -name bist_mem_clk_b[2] -add -source [get_ports {wb_clk2_i}] -master_clock [get_clocks {wb_clk2_i}] -divide_by 1 -comment {Mem Clock B2} [get_ports {mem_clk_b[2]}]
set_clock_transition 0.1500 [get_clocks {bist_mem_clk_b[2]}]
set_clock_uncertainty 0.2500 bist_mem_clk_b[2]
set_propagated_clock [get_clocks {bist_mem_clk_b[2]}]
create_generated_clock -name bist_mem_clk_b[3] -add -source [get_ports {wb_clk2_i}] -master_clock [get_clocks {wb_clk2_i}] -divide_by 1 -comment {Mem Clock B3} [get_ports {mem_clk_b[3]}]
set_clock_transition 0.1500 [get_clocks {bist_mem_clk_b[3]}]
set_clock_uncertainty 0.2500 bist_mem_clk_b[3]
set_propagated_clock [get_clocks {bist_mem_clk_b[3]}]
set_clock_groups -name async_clock -asynchronous \
 -group [list [get_clocks {bist_mem_clk_a[0]}]\
           [get_clocks {bist_mem_clk_a[1]}]\
           [get_clocks {bist_mem_clk_a[2]}]\
           [get_clocks {bist_mem_clk_a[3]}]\
           [get_clocks {bist_mem_clk_b[0]}]\
           [get_clocks {bist_mem_clk_b[1]}]\
           [get_clocks {bist_mem_clk_b[2]}]\
           [get_clocks {bist_mem_clk_b[3]}]\
           [get_clocks {wb_clk2_i}]\
           [get_clocks {wb_clk_i}]] -comment {Async Clock group}
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[0]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[0]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[10]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[10]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[11]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[11]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[12]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[12]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[13]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[13]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[14]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[14]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[15]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[15]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[16]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[16]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[17]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[17]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[18]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[18]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[19]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[19]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[1]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[1]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[20]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[20]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[21]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[21]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[22]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[22]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[23]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[23]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[24]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[24]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[25]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[25]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[26]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[26]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[27]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[27]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[28]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[28]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[29]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[29]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[2]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[2]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[30]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[30]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[31]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[31]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[3]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[3]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[4]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[4]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[5]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[5]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[6]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[6]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[7]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[7]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[8]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[8]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -min -add_delay [get_ports {mem_dout_a0[9]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -clock_fall -max -add_delay [get_ports {mem_dout_a0[9]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[0]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[0]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[10]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[10]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[11]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[11]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[12]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[12]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[13]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[13]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[14]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[14]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[15]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[15]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[16]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[16]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[17]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[17]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[18]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[18]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[19]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[19]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[1]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[1]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[20]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[20]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[21]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[21]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[22]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[22]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[23]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[23]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[24]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[24]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[25]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[25]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[26]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[26]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[27]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[27]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[28]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[28]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[29]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[29]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[2]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[2]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[30]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[30]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[31]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[31]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[3]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[3]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[4]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[4]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[5]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[5]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[6]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[6]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[7]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[7]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[8]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[8]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -min -add_delay [get_ports {mem_dout_a1[9]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -clock_fall -max -add_delay [get_ports {mem_dout_a1[9]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[0]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[0]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[10]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[10]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[11]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[11]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[12]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[12]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[13]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[13]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[14]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[14]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[15]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[15]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[16]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[16]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[17]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[17]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[18]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[18]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[19]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[19]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[1]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[1]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[20]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[20]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[21]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[21]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[22]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[22]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[23]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[23]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[24]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[24]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[25]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[25]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[26]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[26]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[27]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[27]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[28]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[28]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[29]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[29]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[2]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[2]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[30]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[30]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[31]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[31]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[3]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[3]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[4]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[4]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[5]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[5]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[6]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[6]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[7]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[7]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[8]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[8]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -min -add_delay [get_ports {mem_dout_a2[9]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -clock_fall -max -add_delay [get_ports {mem_dout_a2[9]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[0]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[0]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[10]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[10]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[11]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[11]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[12]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[12]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[13]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[13]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[14]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[14]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[15]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[15]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[16]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[16]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[17]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[17]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[18]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[18]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[19]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[19]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[1]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[1]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[20]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[20]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[21]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[21]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[22]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[22]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[23]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[23]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[24]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[24]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[25]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[25]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[26]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[26]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[27]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[27]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[28]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[28]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[29]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[29]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[2]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[2]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[30]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[30]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[31]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[31]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[3]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[3]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[4]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[4]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[5]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[5]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[6]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[6]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[7]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[7]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[8]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[8]}]
set_input_delay 1.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -min -add_delay [get_ports {mem_dout_a3[9]}]
set_input_delay 3.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -clock_fall -max -add_delay [get_ports {mem_dout_a3[9]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {rst_n}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {rst_n}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_adr_i[0]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_adr_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_adr_i[10]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_adr_i[10]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_adr_i[11]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_adr_i[11]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_adr_i[12]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_adr_i[12]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_adr_i[13]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_adr_i[13]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_adr_i[14]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_adr_i[14]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_adr_i[1]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_adr_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_adr_i[2]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_adr_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_adr_i[3]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_adr_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_adr_i[4]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_adr_i[4]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_adr_i[5]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_adr_i[5]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_adr_i[6]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_adr_i[6]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_adr_i[7]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_adr_i[7]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_adr_i[8]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_adr_i[8]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_adr_i[9]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_adr_i[9]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_cyc_i}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_cyc_i}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_sel_i[0]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_sel_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_sel_i[1]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_sel_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_sel_i[2]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_sel_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_sel_i[3]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_sel_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_stb_i}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_stb_i}]
set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_we_i}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_we_i}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_addr_a0[0]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_addr_a0[0]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_addr_a0[1]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_addr_a0[1]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_addr_a0[2]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_addr_a0[2]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_addr_a0[3]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_addr_a0[3]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_addr_a0[4]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_addr_a0[4]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_addr_a0[5]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_addr_a0[5]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_addr_a0[6]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_addr_a0[6]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_addr_a0[7]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_addr_a0[7]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_addr_a0[8]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_addr_a0[8]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_addr_a1[0]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_addr_a1[0]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_addr_a1[1]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_addr_a1[1]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_addr_a1[2]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_addr_a1[2]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_addr_a1[3]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_addr_a1[3]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_addr_a1[4]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_addr_a1[4]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_addr_a1[5]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_addr_a1[5]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_addr_a1[6]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_addr_a1[6]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_addr_a1[7]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_addr_a1[7]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_addr_a1[8]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_addr_a1[8]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_addr_a2[0]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_addr_a2[0]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_addr_a2[1]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_addr_a2[1]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_addr_a2[2]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_addr_a2[2]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_addr_a2[3]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_addr_a2[3]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_addr_a2[4]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_addr_a2[4]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_addr_a2[5]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_addr_a2[5]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_addr_a2[6]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_addr_a2[6]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_addr_a2[7]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_addr_a2[7]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_addr_a2[8]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_addr_a2[8]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_addr_a3[0]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_addr_a3[0]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_addr_a3[1]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_addr_a3[1]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_addr_a3[2]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_addr_a3[2]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_addr_a3[3]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_addr_a3[3]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_addr_a3[4]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_addr_a3[4]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_addr_a3[5]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_addr_a3[5]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_addr_a3[6]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_addr_a3[6]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_addr_a3[7]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_addr_a3[7]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_addr_a3[8]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_addr_a3[8]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[0]}] -min -add_delay [get_ports {mem_addr_b0[0]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[0]}] -max -add_delay [get_ports {mem_addr_b0[0]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[0]}] -min -add_delay [get_ports {mem_addr_b0[1]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[0]}] -max -add_delay [get_ports {mem_addr_b0[1]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[0]}] -min -add_delay [get_ports {mem_addr_b0[2]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[0]}] -max -add_delay [get_ports {mem_addr_b0[2]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[0]}] -min -add_delay [get_ports {mem_addr_b0[3]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[0]}] -max -add_delay [get_ports {mem_addr_b0[3]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[0]}] -min -add_delay [get_ports {mem_addr_b0[4]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[0]}] -max -add_delay [get_ports {mem_addr_b0[4]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[0]}] -min -add_delay [get_ports {mem_addr_b0[5]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[0]}] -max -add_delay [get_ports {mem_addr_b0[5]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[0]}] -min -add_delay [get_ports {mem_addr_b0[6]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[0]}] -max -add_delay [get_ports {mem_addr_b0[6]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[0]}] -min -add_delay [get_ports {mem_addr_b0[7]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[0]}] -max -add_delay [get_ports {mem_addr_b0[7]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[0]}] -min -add_delay [get_ports {mem_addr_b0[8]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[0]}] -max -add_delay [get_ports {mem_addr_b0[8]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[1]}] -min -add_delay [get_ports {mem_addr_b1[0]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[1]}] -max -add_delay [get_ports {mem_addr_b1[0]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[1]}] -min -add_delay [get_ports {mem_addr_b1[1]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[1]}] -max -add_delay [get_ports {mem_addr_b1[1]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[1]}] -min -add_delay [get_ports {mem_addr_b1[2]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[1]}] -max -add_delay [get_ports {mem_addr_b1[2]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[1]}] -min -add_delay [get_ports {mem_addr_b1[3]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[1]}] -max -add_delay [get_ports {mem_addr_b1[3]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[1]}] -min -add_delay [get_ports {mem_addr_b1[4]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[1]}] -max -add_delay [get_ports {mem_addr_b1[4]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[1]}] -min -add_delay [get_ports {mem_addr_b1[5]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[1]}] -max -add_delay [get_ports {mem_addr_b1[5]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[1]}] -min -add_delay [get_ports {mem_addr_b1[6]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[1]}] -max -add_delay [get_ports {mem_addr_b1[6]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[1]}] -min -add_delay [get_ports {mem_addr_b1[7]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[1]}] -max -add_delay [get_ports {mem_addr_b1[7]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[1]}] -min -add_delay [get_ports {mem_addr_b1[8]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[1]}] -max -add_delay [get_ports {mem_addr_b1[8]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[2]}] -min -add_delay [get_ports {mem_addr_b2[0]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[2]}] -max -add_delay [get_ports {mem_addr_b2[0]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[2]}] -min -add_delay [get_ports {mem_addr_b2[1]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[2]}] -max -add_delay [get_ports {mem_addr_b2[1]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[2]}] -min -add_delay [get_ports {mem_addr_b2[2]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[2]}] -max -add_delay [get_ports {mem_addr_b2[2]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[2]}] -min -add_delay [get_ports {mem_addr_b2[3]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[2]}] -max -add_delay [get_ports {mem_addr_b2[3]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[2]}] -min -add_delay [get_ports {mem_addr_b2[4]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[2]}] -max -add_delay [get_ports {mem_addr_b2[4]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[2]}] -min -add_delay [get_ports {mem_addr_b2[5]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[2]}] -max -add_delay [get_ports {mem_addr_b2[5]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[2]}] -min -add_delay [get_ports {mem_addr_b2[6]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[2]}] -max -add_delay [get_ports {mem_addr_b2[6]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[2]}] -min -add_delay [get_ports {mem_addr_b2[7]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[2]}] -max -add_delay [get_ports {mem_addr_b2[7]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[2]}] -min -add_delay [get_ports {mem_addr_b2[8]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[2]}] -max -add_delay [get_ports {mem_addr_b2[8]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[3]}] -min -add_delay [get_ports {mem_addr_b3[0]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[3]}] -max -add_delay [get_ports {mem_addr_b3[0]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[3]}] -min -add_delay [get_ports {mem_addr_b3[1]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[3]}] -max -add_delay [get_ports {mem_addr_b3[1]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[3]}] -min -add_delay [get_ports {mem_addr_b3[2]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[3]}] -max -add_delay [get_ports {mem_addr_b3[2]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[3]}] -min -add_delay [get_ports {mem_addr_b3[3]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[3]}] -max -add_delay [get_ports {mem_addr_b3[3]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[3]}] -min -add_delay [get_ports {mem_addr_b3[4]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[3]}] -max -add_delay [get_ports {mem_addr_b3[4]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[3]}] -min -add_delay [get_ports {mem_addr_b3[5]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[3]}] -max -add_delay [get_ports {mem_addr_b3[5]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[3]}] -min -add_delay [get_ports {mem_addr_b3[6]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[3]}] -max -add_delay [get_ports {mem_addr_b3[6]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[3]}] -min -add_delay [get_ports {mem_addr_b3[7]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[3]}] -max -add_delay [get_ports {mem_addr_b3[7]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[3]}] -min -add_delay [get_ports {mem_addr_b3[8]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[3]}] -max -add_delay [get_ports {mem_addr_b3[8]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_cen_a[0]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_cen_a[0]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_cen_a[1]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_cen_a[1]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_cen_a[2]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_cen_a[2]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_cen_a[3]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_cen_a[3]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[0]}] -min -add_delay [get_ports {mem_cen_b[0]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[0]}] -max -add_delay [get_ports {mem_cen_b[0]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[1]}] -min -add_delay [get_ports {mem_cen_b[1]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[1]}] -max -add_delay [get_ports {mem_cen_b[1]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[2]}] -min -add_delay [get_ports {mem_cen_b[2]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[2]}] -max -add_delay [get_ports {mem_cen_b[2]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_b[3]}] -min -add_delay [get_ports {mem_cen_b[3]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_b[3]}] -max -add_delay [get_ports {mem_cen_b[3]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[0]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[0]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[10]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[10]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[11]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[11]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[12]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[12]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[13]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[13]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[14]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[14]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[15]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[15]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[16]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[16]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[17]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[17]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[18]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[18]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[19]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[19]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[1]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[1]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[20]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[20]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[21]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[21]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[22]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[22]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[23]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[23]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[24]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[24]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[25]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[25]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[26]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[26]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[27]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[27]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[28]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[28]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[29]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[29]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[2]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[2]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[30]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[30]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[31]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[31]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[3]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[3]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[4]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[4]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[5]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[5]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[6]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[6]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[7]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[7]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[8]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[8]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_din_a0[9]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_din_a0[9]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[0]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[0]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[10]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[10]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[11]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[11]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[12]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[12]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[13]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[13]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[14]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[14]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[15]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[15]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[16]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[16]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[17]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[17]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[18]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[18]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[19]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[19]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[1]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[1]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[20]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[20]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[21]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[21]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[22]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[22]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[23]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[23]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[24]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[24]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[25]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[25]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[26]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[26]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[27]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[27]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[28]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[28]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[29]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[29]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[2]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[2]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[30]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[30]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[31]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[31]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[3]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[3]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[4]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[4]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[5]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[5]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[6]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[6]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[7]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[7]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[8]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[8]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_din_a1[9]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_din_a1[9]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[0]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[0]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[10]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[10]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[11]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[11]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[12]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[12]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[13]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[13]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[14]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[14]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[15]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[15]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[16]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[16]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[17]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[17]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[18]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[18]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[19]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[19]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[1]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[1]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[20]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[20]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[21]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[21]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[22]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[22]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[23]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[23]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[24]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[24]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[25]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[25]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[26]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[26]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[27]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[27]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[28]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[28]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[29]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[29]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[2]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[2]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[30]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[30]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[31]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[31]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[3]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[3]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[4]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[4]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[5]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[5]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[6]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[6]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[7]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[7]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[8]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[8]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_din_a2[9]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_din_a2[9]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[0]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[0]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[10]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[10]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[11]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[11]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[12]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[12]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[13]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[13]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[14]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[14]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[15]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[15]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[16]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[16]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[17]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[17]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[18]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[18]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[19]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[19]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[1]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[1]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[20]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[20]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[21]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[21]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[22]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[22]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[23]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[23]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[24]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[24]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[25]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[25]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[26]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[26]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[27]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[27]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[28]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[28]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[29]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[29]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[2]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[2]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[30]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[30]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[31]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[31]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[3]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[3]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[4]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[4]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[5]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[5]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[6]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[6]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[7]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[7]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[8]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[8]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_din_a3[9]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_din_a3[9]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_mask_a0[0]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_mask_a0[0]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_mask_a0[1]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_mask_a0[1]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_mask_a0[2]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_mask_a0[2]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_mask_a0[3]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_mask_a0[3]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_mask_a1[0]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_mask_a1[0]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_mask_a1[1]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_mask_a1[1]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_mask_a1[2]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_mask_a1[2]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_mask_a1[3]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_mask_a1[3]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_mask_a2[0]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_mask_a2[0]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_mask_a2[1]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_mask_a2[1]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_mask_a2[2]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_mask_a2[2]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_mask_a2[3]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_mask_a2[3]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_mask_a3[0]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_mask_a3[0]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_mask_a3[1]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_mask_a3[1]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_mask_a3[2]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_mask_a3[2]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_mask_a3[3]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_mask_a3[3]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[0]}] -min -add_delay [get_ports {mem_web_a[0]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[0]}] -max -add_delay [get_ports {mem_web_a[0]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[1]}] -min -add_delay [get_ports {mem_web_a[1]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[1]}] -max -add_delay [get_ports {mem_web_a[1]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[2]}] -min -add_delay [get_ports {mem_web_a[2]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[2]}] -max -add_delay [get_ports {mem_web_a[2]}]
set_output_delay -0.5000 -clock [get_clocks {bist_mem_clk_a[3]}] -min -add_delay [get_ports {mem_web_a[3]}]
set_output_delay 4.0000 -clock [get_clocks {bist_mem_clk_a[3]}] -max -add_delay [get_ports {mem_web_a[3]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_ack_o}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_ack_o}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[0]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[10]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[10]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[11]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[11]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[12]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[12]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[13]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[13]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[14]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[14]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[15]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[15]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[16]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[16]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[17]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[17]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[18]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[18]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[19]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[19]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[1]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[20]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[20]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[21]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[21]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[22]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[22]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[23]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[23]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[24]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[24]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[25]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[25]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[26]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[26]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[27]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[27]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[28]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[28]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[29]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[29]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[2]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[30]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[30]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[31]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[31]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[3]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[4]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[4]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[5]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[5]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[6]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[6]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[7]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[7]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[8]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[8]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_dat_o[9]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_dat_o[9]}]
set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -min -add_delay [get_ports {wb_err_o}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -max -add_delay [get_ports {wb_err_o}]
set_max_delay\
    -from [get_ports {wbd_clk_int}] 3.5000
###############################################################################
# Environment
###############################################################################
set_load -pin_load 0.0334 [get_ports {scan_en_o}]
set_load -pin_load 0.0334 [get_ports {scan_mode_o}]
set_load -pin_load 0.0334 [get_ports {wb_ack_o}]
set_load -pin_load 0.0334 [get_ports {wb_err_o}]
set_load -pin_load 0.0334 [get_ports {wb_lack_o}]
set_load -pin_load 0.0334 [get_ports {wbd_clk_skew}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a0[8]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a0[7]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a0[6]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a0[5]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a0[4]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a0[3]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a0[2]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a0[1]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a0[0]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a1[8]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a1[7]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a1[6]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a1[5]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a1[4]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a1[3]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a1[2]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a1[1]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a1[0]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a2[8]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a2[7]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a2[6]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a2[5]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a2[4]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a2[3]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a2[2]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a2[1]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a2[0]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a3[8]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a3[7]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a3[6]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a3[5]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a3[4]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a3[3]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a3[2]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a3[1]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a3[0]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b0[8]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b0[7]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b0[6]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b0[5]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b0[4]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b0[3]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b0[2]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b0[1]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b0[0]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b1[8]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b1[7]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b1[6]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b1[5]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b1[4]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b1[3]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b1[2]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b1[1]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b1[0]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b2[8]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b2[7]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b2[6]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b2[5]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b2[4]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b2[3]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b2[2]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b2[1]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b2[0]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b3[8]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b3[7]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b3[6]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b3[5]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b3[4]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b3[3]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b3[2]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b3[1]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b3[0]}]
set_load -pin_load 0.0334 [get_ports {mem_cen_a[3]}]
set_load -pin_load 0.0334 [get_ports {mem_cen_a[2]}]
set_load -pin_load 0.0334 [get_ports {mem_cen_a[1]}]
set_load -pin_load 0.0334 [get_ports {mem_cen_a[0]}]
set_load -pin_load 0.0334 [get_ports {mem_cen_b[3]}]
set_load -pin_load 0.0334 [get_ports {mem_cen_b[2]}]
set_load -pin_load 0.0334 [get_ports {mem_cen_b[1]}]
set_load -pin_load 0.0334 [get_ports {mem_cen_b[0]}]
set_load -pin_load 0.0334 [get_ports {mem_clk_a[3]}]
set_load -pin_load 0.0334 [get_ports {mem_clk_a[2]}]
set_load -pin_load 0.0334 [get_ports {mem_clk_a[1]}]
set_load -pin_load 0.0334 [get_ports {mem_clk_a[0]}]
set_load -pin_load 0.0334 [get_ports {mem_clk_b[3]}]
set_load -pin_load 0.0334 [get_ports {mem_clk_b[2]}]
set_load -pin_load 0.0334 [get_ports {mem_clk_b[1]}]
set_load -pin_load 0.0334 [get_ports {mem_clk_b[0]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[31]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[30]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[29]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[28]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[27]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[26]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[25]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[24]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[23]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[22]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[21]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[20]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[19]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[18]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[17]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[16]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[15]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[14]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[13]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[12]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[11]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[10]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[9]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[8]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[7]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[6]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[5]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[4]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[3]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[2]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[1]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a0[0]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[31]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[30]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[29]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[28]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[27]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[26]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[25]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[24]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[23]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[22]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[21]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[20]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[19]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[18]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[17]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[16]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[15]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[14]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[13]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[12]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[11]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[10]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[9]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[8]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[7]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[6]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[5]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[4]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[3]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[2]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[1]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a1[0]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[31]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[30]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[29]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[28]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[27]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[26]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[25]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[24]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[23]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[22]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[21]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[20]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[19]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[18]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[17]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[16]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[15]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[14]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[13]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[12]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[11]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[10]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[9]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[8]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[7]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[6]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[5]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[4]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[3]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[2]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[1]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a2[0]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[31]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[30]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[29]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[28]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[27]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[26]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[25]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[24]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[23]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[22]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[21]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[20]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[19]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[18]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[17]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[16]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[15]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[14]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[13]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[12]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[11]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[10]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[9]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[8]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[7]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[6]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[5]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[4]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[3]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[2]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[1]}]
set_load -pin_load 0.0334 [get_ports {mem_din_a3[0]}]
set_load -pin_load 0.0334 [get_ports {mem_mask_a0[3]}]
set_load -pin_load 0.0334 [get_ports {mem_mask_a0[2]}]
set_load -pin_load 0.0334 [get_ports {mem_mask_a0[1]}]
set_load -pin_load 0.0334 [get_ports {mem_mask_a0[0]}]
set_load -pin_load 0.0334 [get_ports {mem_mask_a1[3]}]
set_load -pin_load 0.0334 [get_ports {mem_mask_a1[2]}]
set_load -pin_load 0.0334 [get_ports {mem_mask_a1[1]}]
set_load -pin_load 0.0334 [get_ports {mem_mask_a1[0]}]
set_load -pin_load 0.0334 [get_ports {mem_mask_a2[3]}]
set_load -pin_load 0.0334 [get_ports {mem_mask_a2[2]}]
set_load -pin_load 0.0334 [get_ports {mem_mask_a2[1]}]
set_load -pin_load 0.0334 [get_ports {mem_mask_a2[0]}]
set_load -pin_load 0.0334 [get_ports {mem_mask_a3[3]}]
set_load -pin_load 0.0334 [get_ports {mem_mask_a3[2]}]
set_load -pin_load 0.0334 [get_ports {mem_mask_a3[1]}]
set_load -pin_load 0.0334 [get_ports {mem_mask_a3[0]}]
set_load -pin_load 0.0334 [get_ports {mem_web_a[3]}]
set_load -pin_load 0.0334 [get_ports {mem_web_a[2]}]
set_load -pin_load 0.0334 [get_ports {mem_web_a[1]}]
set_load -pin_load 0.0334 [get_ports {mem_web_a[0]}]
set_load -pin_load 0.0334 [get_ports {scan_so[7]}]
set_load -pin_load 0.0334 [get_ports {scan_so[6]}]
set_load -pin_load 0.0334 [get_ports {scan_so[5]}]
set_load -pin_load 0.0334 [get_ports {scan_so[4]}]
set_load -pin_load 0.0334 [get_ports {scan_so[3]}]
set_load -pin_load 0.0334 [get_ports {scan_so[2]}]
set_load -pin_load 0.0334 [get_ports {scan_so[1]}]
set_load -pin_load 0.0334 [get_ports {scan_so[0]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[31]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[30]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[29]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[28]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[27]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[26]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[25]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[24]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[23]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[22]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[21]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[20]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[19]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[18]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[17]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[16]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[15]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[14]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[13]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[12]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[11]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[10]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[9]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[8]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[7]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[6]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[5]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[4]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[3]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[2]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[1]}]
set_load -pin_load 0.0334 [get_ports {wb_dat_o[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_en}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_mode}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_bry_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk2_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_cyc_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_stb_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_we_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_mbist[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_mbist[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_mbist[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_mbist[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a0[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a1[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a2[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a3[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_si[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_si[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_si[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_si[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_si[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_si[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_si[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scan_si[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_bl_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_bl_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_bl_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_bl_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_bl_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_bl_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_bl_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_bl_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_bl_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_bl_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[0]}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
###############################################################################
# Design Rules
###############################################################################
set_max_fanout 4.0000 [current_design]