tree: 96ee71a8e17dea70047776e84b114034a7bd0fc1 [path history] [tgz]
  1. rtl/
  2. LICENSE
  3. README.md
verilog/rtl/leorv-fpga/leorv32/README.md

LeoRV32

LeoRV32 is a simple RV32I RISC-V CPU written in SystemVerilog.

All SystemVerilog features used are supported by Yosys and Icarus Verilog.