tree: c2f912da29e483ebc63495473f7a4571c63bf86f [path history] [tgz]
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. lib/
  7. mag/
  8. maglef/
  9. mpw_precheck/
  10. openlane/
  11. sdc/
  12. sdf/
  13. signoff/
  14. spef/
  15. spi/
  16. tapeout/
  17. verilog/
  18. .gitignore
  19. LICENSE
  20. Makefile
  21. README.md
README.md

LeoSoC

License UPRJ_CI Caravel Build

This is a simple SoC with the following:

  • 1 LeoRV32 Core (RV32I)
  • 8 kB Work RAM
  • 8 kB Video RAM (can also be used as Work RAM)
  • SVGA Core (800 x 600, 40 MHz)
    • Resolution decreased to 100 x 75 pixel
    • 1 Byte per Pixel with direct color format (BBGGGRRR)
  • UART
    • 9600 baud fixed at 40 MHz
  • Blink
    • Simple output to blink an LED

Address Layout

PeripheralAddress
WRAM_BASE0x000000
VRAM_BASE0x010000
UART_BASE0x0A0000
BLINK_BASE0x0F0000