commit	f60153a881dd1a9da675fe2556b49e79065cd96b	[log] [tgz]
author	mole99 <leomoser99@gmail.com>	Thu Dec 22 18:53:53 2022 +0100
committer	mole99 <leomoser99@gmail.com>	Thu Dec 22 18:53:53 2022 +0100
tree	33e02db06faf16b303dfce0da526a3d568bdbbb4
parent	9242a6d4d5b70928960a833eff07183dbbb1c586 [diff]

Add init_ram and run_cpu simulation files

verilog/dv/init_ram/Makefile[Added - diff]
verilog/dv/init_ram/init_ram.c[Added - diff]
verilog/dv/init_ram/init_ram_tb.v[Added - diff]
verilog/dv/run_cpu/Makefile[Added - diff]
verilog/dv/run_cpu/run_cpu.c[Added - diff]
verilog/dv/run_cpu/run_cpu_tb.v[Added - diff]

6 files changed

tree: 33e02db06faf16b303dfce0da526a3d568bdbbb4

README.md

LeoSoC

This is a simple SoC with the following:

1 LeoRV32 Core (RV32I)
8 kB Work RAM
8 kB Video RAM (can also be used as Work RAM)
SVGA Core (800 x 600, 40 MHz)
- Resolution decreased to 100 x 75 pixel
- 1 Byte per Pixel with direct color format (BBGGGRRR)
UART
- 9600 baud fixed at 40 MHz
Blink
- Simple output to blink an LED

Address Layout

Peripheral	Address
WRAM_BASE	0x000000
VRAM_BASE	0x010000
UART_BASE	0x0A0000
BLINK_BASE	0x0F0000