Add init_vram simulation
5 files changed
tree: 232c1dedcd58bac83e868c56d58fd1a812c34d8c
  1. .github/
  2. docs/
  3. openlane/
  4. signoff/
  5. verilog/
  6. .gitignore
  7. .gitmodules
  8. LICENSE
  9. Makefile
  10. README.md
README.md

LeoSoC

License UPRJ_CI Caravel Build

This is a simple SoC with the following:

  • 1 LeoRV32 Core (RV32I)
  • 8 kB Work RAM
  • 8 kB Video RAM (can also be used as Work RAM)
  • SVGA Core (800 x 600, 40 MHz)
    • Resolution decreased to 100 x 75 pixel
    • 1 Byte per Pixel with direct color format (BBGGGRRR)
  • UART
    • 9600 baud fixed at 40 MHz
  • Blink
    • Simple output to blink an LED

Address Layout

PeripheralAddress
WRAM_BASE0x000000
VRAM_BASE0x010000
UART_BASE0x0A0000
BLINK_BASE0x0F0000