Add configurations
diff --git a/openlane/leorv32/config.json b/openlane/leorv32/config.json
new file mode 100644
index 0000000..0fd5a13
--- /dev/null
+++ b/openlane/leorv32/config.json
@@ -0,0 +1,33 @@
+{
+ "DESIGN_NAME": "leorv32",
+ "DESIGN_IS_CORE": 0,
+ "VERILOG_FILES": [
+ "dir::../../verilog/rtl/defines.v",
+ "dir::../../verilog/rtl/leorv-fpga/leorv32/rtl/leorv32_pkg.sv",
+ "dir::../../verilog/rtl/leorv-fpga/leorv32/rtl/leorv32.sv"
+ ],
+ "CLOCK_PORT": "clk",
+ "CLOCK_NET": "clk",
+ "FP_SIZING": "absolute",
+ "DIE_AREA": "0 0 500 500",
+ "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
+ "PL_BASIC_PLACEMENT": 0,
+ "PL_TARGET_DENSITY": 0.55,
+ "VDD_NETS": ["vccd1"],
+ "GND_NETS": ["vssd1"],
+ "DIODE_INSERTION_STRATEGY": 4,
+ "RUN_CVC": 1,
+ "pdk::sky130*": {
+ "FP_CORE_UTIL": 45,
+ "RT_MAX_LAYER": "met4",
+ "CLOCK_PERIOD": 20
+ },
+ "pdk::gf180mcuC": {
+ "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
+ "CLOCK_PERIOD": 24.0,
+ "FP_CORE_UTIL": 40,
+ "RT_MAX_LAYER": "Metal4",
+ "SYNTH_MAX_FANOUT": 4,
+ "PL_TARGET_DENSITY": 0.45
+ }
+}
diff --git a/openlane/leorv32/pin_order.cfg b/openlane/leorv32/pin_order.cfg
new file mode 100644
index 0000000..dcad451
--- /dev/null
+++ b/openlane/leorv32/pin_order.cfg
@@ -0,0 +1,24 @@
+#BUS_SORT
+
+#N
+
+mem_addr.*
+
+#E
+
+mem_wdata.*
+mem_wmask.*
+
+#S
+
+clk
+reset
+mhartid_0
+
+mem_rstrb
+mem_rbusy
+mem_wbusy
+
+#W
+
+mem_rdata.*
diff --git a/openlane/soc/config.json b/openlane/soc/config.json
new file mode 100644
index 0000000..ac808c1
--- /dev/null
+++ b/openlane/soc/config.json
@@ -0,0 +1,71 @@
+{
+ "DESIGN_NAME": "soc",
+ "DESIGN_IS_CORE": false,
+ "FP_PDN_CORE_RING": false,
+ "VERILOG_FILES": [
+ "dir::../../verilog/rtl/defines.v",
+ "dir::../../verilog/rtl/leorv-fpga/soc/rtl/dual_soc_svga.sv",
+ "dir::../../verilog/rtl/leorv-fpga/sram/rtl/sram.sv",
+ "dir::../../verilog/rtl/leorv-fpga/svga/rtl/svga_gen.sv",
+ "dir::../../verilog/rtl/leorv-fpga/svga/rtl/svga_gen_top.sv",
+ "dir::../../verilog/rtl/leorv-fpga/uart/rtl/my_uart_rx.sv",
+ "dir::../../verilog/rtl/leorv-fpga/uart/rtl/my_uart_tx.sv",
+ "dir::../../verilog/rtl/leorv-fpga/util/rtl/synchronizer.sv"
+ ],
+ "CLOCK_PORT": "clk",
+ "FP_PDN_MACRO_HOOKS": [
+ "leorv32_core0 vccd1 vssd1 vccd1 vssd1,",
+ "leorv32_core1 vccd1 vssd1 vccd1 vssd1"
+ ],
+ "MACRO_PLACEMENT_CFG": "dir::macro.cfg",
+ "VERILOG_FILES_BLACKBOX": [
+ "dir::../../verilog/rtl/defines.v",
+ "dir::../../verilog/gl/leorv32.v",
+ "dir::../../../dependencies/pdks/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+ ],
+ "EXTRA_LEFS": [
+ "dir::../../lef/leorv32.lef",
+ "dir::../../../dependencies/pdks/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef"
+ ],
+ "EXTRA_GDS_FILES": [
+ "dir::../../gds/leorv32.gds",
+ "dir::../../../dependencies/pdks/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds"
+ ],
+ "FP_SIZING": "absolute",
+ "DIE_AREA": "0 0 2350 1400",
+ "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
+ "PL_BASIC_PLACEMENT": 0,
+ "PL_TARGET_DENSITY": 0.55,
+ "VDD_NETS": ["vccd1"],
+ "GND_NETS": ["vssd1"],
+ "DIODE_INSERTION_STRATEGY": 4,
+ "RUN_CVC": 1,
+ "pdk::sky130*": {
+ "FP_CORE_UTIL": 45,
+ "RT_MAX_LAYER": "met4",
+ "CLOCK_PERIOD": 20
+ },
+ "pdk::gf180mcuC": {
+ "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
+ "CLOCK_PERIOD": 24.0,
+ "FP_CORE_UTIL": 40,
+ "RT_MAX_LAYER": "Metal4",
+ "SYNTH_MAX_FANOUT": 4,
+ "PL_TARGET_DENSITY": 0.45
+ },
+
+ "LVS_CONNECT_BY_LABEL": 1,
+ "MAGIC_DRC_USE_GDS": 0,
+ "RUN_MAGIC_DRC": 0,
+ "QUIT_ON_MAGIC_DRC": 0,
+ "RUN_KLAYOUT_XOR": 0,
+ "ROUTING_CORES": 6,
+ "FP_PDN_VWIDTH": 3.1,
+ "FP_PDN_HWIDTH": 3.1,
+ "FP_PDN_VOFFSET": 5,
+ "FP_PDN_HOFFSET": 5,
+ "FP_PDN_VPITCH": 180,
+ "FP_PDN_HPITCH": 180,
+ "FP_PDN_VSPACING": "expr::(5 * $FP_PDN_VWIDTH)",
+ "FP_PDN_HSPACING": "expr::(5 * $FP_PDN_HWIDTH)"
+}
diff --git a/openlane/soc/macro.cfg b/openlane/soc/macro.cfg
new file mode 100644
index 0000000..32c0461
--- /dev/null
+++ b/openlane/soc/macro.cfg
@@ -0,0 +1,6 @@
+#wram.memory\[0\].sky130_sram_2kbyte_1rw1r_32x512_8 100 100 E
+#wram.memory\[1\].sky130_sram_2kbyte_1rw1r_32x512_8 650 100 E
+leorv32_core0 300 500 N
+leorv32_core1 1400 500 N
+#svga_gen_top.vram.memory\[0\].sky130_sram_2kbyte_1rw1r_32x512_8 100 1700 E
+#svga_gen_top.vram.memory\[1\].sky130_sram_2kbyte_1rw1r_32x512_8 650 1700 E
diff --git a/openlane/soc/pin_order.cfg b/openlane/soc/pin_order.cfg
new file mode 100644
index 0000000..35d29b3
--- /dev/null
+++ b/openlane/soc/pin_order.cfg
@@ -0,0 +1,53 @@
+#BUS_SORT
+
+#N
+
+vram_select_instance_0.*
+vram_select_instance_1.*
+
+vram_web0
+vram_wmask0.*
+
+vram_addr0.*
+vram_addr1.*
+
+vram_din0.*
+
+vram_select_dout0.*
+vram_select_dout1.*
+
+#E
+
+blink
+clk
+
+reset
+uart_rx
+uart_tx
+
+#S
+
+wram_select_instance_0.*
+wram_select_instance_1.*
+
+wram_web0
+wram_wmask0.*
+
+wram_addr0.*
+wram_addr1.*
+
+wram_din0.*
+
+wram_select_dout0.*
+wram_select_dout1.*
+
+#W
+
+dvi_clk
+dvi_de
+dvi_hsync
+dvi_vsync
+
+dvi_b.*
+dvi_g.*
+dvi_r.*
diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json
deleted file mode 100644
index 370d74c..0000000
--- a/openlane/user_proj_example/config.json
+++ /dev/null
@@ -1,45 +0,0 @@
-{
- "DESIGN_NAME": "user_proj_example",
- "DESIGN_IS_CORE": 0,
- "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"],
- "CLOCK_PERIOD": 10,
- "CLOCK_PORT": "wb_clk_i",
- "CLOCK_NET": "counter.clk",
- "FP_SIZING": "absolute",
- "DIE_AREA": "0 0 900 600",
- "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
- "PL_BASIC_PLACEMENT": 0,
- "PL_TARGET_DENSITY": 0.55,
- "VDD_NETS": ["vccd1"],
- "GND_NETS": ["vssd1"],
- "DIODE_INSERTION_STRATEGY": 4,
- "RUN_CVC": 1,
- "pdk::sky130*": {
- "FP_CORE_UTIL": 45,
- "RT_MAX_LAYER": "met4",
- "scl::sky130_fd_sc_hd": {
- "CLOCK_PERIOD": 10
- },
- "scl::sky130_fd_sc_hdll": {
- "CLOCK_PERIOD": 10
- },
- "scl::sky130_fd_sc_hs": {
- "CLOCK_PERIOD": 8
- },
- "scl::sky130_fd_sc_ls": {
- "CLOCK_PERIOD": 10,
- "SYNTH_MAX_FANOUT": 5
- },
- "scl::sky130_fd_sc_ms": {
- "CLOCK_PERIOD": 10
- }
- },
- "pdk::gf180mcuC": {
- "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
- "CLOCK_PERIOD": 24.0,
- "FP_CORE_UTIL": 40,
- "RT_MAX_LAYER": "Metal4",
- "SYNTH_MAX_FANOUT": 4,
- "PL_TARGET_DENSITY": 0.45
- }
-}
\ No newline at end of file
diff --git a/openlane/user_proj_example/pin_order.cfg b/openlane/user_proj_example/pin_order.cfg
deleted file mode 100644
index 2fda806..0000000
--- a/openlane/user_proj_example/pin_order.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-#BUS_SORT
-
-#S
-wb_.*
-wbs_.*
-la_.*
-irq.*
-
-#N
-io_.*
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
index 22a00ee..c24df5e 100644
--- a/openlane/user_project_wrapper/config.json
+++ b/openlane/user_project_wrapper/config.json
@@ -1,27 +1,59 @@
{
"DESIGN_NAME": "user_project_wrapper",
- "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_project_wrapper.v"],
- "CLOCK_PERIOD": 10,
- "CLOCK_PORT": "user_clock2",
- "CLOCK_NET": "mprj.clk",
- "FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1",
+ "VERILOG_FILES": [
+ "dir::../../verilog/rtl/defines.v",
+ "dir::../../verilog/rtl/user_project_wrapper.v",
+ "dir::../../verilog/rtl/leorv-fpga/soc/rtl/dual_soc_svga.sv",
+ "dir::../../verilog/rtl/leorv-fpga/sram/rtl/sram.sv",
+ "dir::../../verilog/rtl/leorv-fpga/svga/rtl/svga_gen.sv",
+ "dir::../../verilog/rtl/leorv-fpga/svga/rtl/svga_gen_top.sv",
+ "dir::../../verilog/rtl/leorv-fpga/uart/rtl/my_uart_rx.sv",
+ "dir::../../verilog/rtl/leorv-fpga/uart/rtl/my_uart_tx.sv",
+ "dir::../../verilog/rtl/leorv-fpga/util/rtl/synchronizer.sv",
+ "dir::../../verilog/rtl/leorv-fpga/wb_memory/rtl/wb_memory.sv",
+ "dir::../../verilog/rtl/leorv-fpga/mem_port_switch/rtl/mem_port_switch.sv"
+ ],
+
+ "CLOCK_PORT": "wb_clk_i",
+ "FP_PDN_MACRO_HOOKS": [
+ "soc_inst.leorv32_core0 vccd1 vssd1 vccd1 vssd1,",
+ "soc_inst.leorv32_core1 vccd1 vssd1 vccd1 vssd1,",
+ "soc_inst.wram.mem0 vccd1 vssd1 vccd1 vssd1,",
+ "soc_inst.wram.mem1 vccd1 vssd1 vccd1 vssd1,",
+ "soc_inst.wram.mem2 vccd1 vssd1 vccd1 vssd1,",
+ "soc_inst.wram.mem3 vccd1 vssd1 vccd1 vssd1,",
+ "soc_inst.svga_gen_top.vram.mem0 vccd1 vssd1 vccd1 vssd1,",
+ "soc_inst.svga_gen_top.vram.mem1 vccd1 vssd1 vccd1 vssd1,",
+ "soc_inst.svga_gen_top.vram.mem2 vccd1 vssd1 vccd1 vssd1,",
+ "soc_inst.svga_gen_top.vram.mem3 vccd1 vssd1 vccd1 vssd1"
+ ],
"MACRO_PLACEMENT_CFG": "dir::macro.cfg",
- "VERILOG_FILES_BLACKBOX": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"],
- "EXTRA_LEFS": "dir::../../lef/user_proj_example.lef",
- "EXTRA_GDS_FILES": "dir::../../gds/user_proj_example.gds",
- "FP_PDN_CHECK_NODES": 0,
- "SYNTH_ELABORATE_ONLY": 1,
- "PL_RANDOM_GLB_PLACEMENT": 1,
- "PL_RESIZER_DESIGN_OPTIMIZATIONS": 0,
- "PL_RESIZER_TIMING_OPTIMIZATIONS": 0,
- "PL_RESIZER_BUFFER_INPUT_PORTS": 0,
- "FP_PDN_ENABLE_RAILS": 0,
- "DIODE_INSERTION_STRATEGY": 0,
- "RUN_FILL_INSERTION": 0,
- "RUN_TAP_DECAP_INSERTION": 0,
+ "VERILOG_FILES_BLACKBOX": [
+ "dir::../../verilog/rtl/defines.v",
+ "dir::../../verilog/gl/leorv32.v",
+ "dir::../../../dependencies/pdks/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+ ],
+ "EXTRA_LEFS": [
+ "dir::../../lef/leorv32.lef",
+ "dir::../../../dependencies/pdks/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef"
+ ],
+ "EXTRA_GDS_FILES": [
+ "dir::../../gds/leorv32.gds",
+ "dir::../../../dependencies/pdks/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds"
+ ],
+ "EXTRA_LIBS": [
+ "dir::../../lib/leorv32.lib",
+ "dir::../../../dependencies/pdks/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib"
+ ],
+ "FP_PDN_CHECK_NODES": 1,
+ "CLOCK_TREE_SYNTH": 1,
+ "DIODE_INSERTION_STRATEGY": 4,
+ "RUN_FILL_INSERTION": 1,
+ "RUN_TAP_DECAP_INSERTION": 1,
+ "PL_TARGET_DENSITY": 0.6,
+
"FP_PDN_VPITCH": 180,
"FP_PDN_HPITCH": 180,
- "CLOCK_TREE_SYNTH": 0,
"FP_PDN_VOFFSET": 5,
"FP_PDN_HOFFSET": 5,
"MAGIC_ZEROIZE_ORIGIN": 0,
@@ -52,22 +84,7 @@
"RT_MAX_LAYER": "met4",
"DIE_AREA": "0 0 2920 3520",
"FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def",
- "scl::sky130_fd_sc_hd": {
- "CLOCK_PERIOD": 10
- },
- "scl::sky130_fd_sc_hdll": {
- "CLOCK_PERIOD": 10
- },
- "scl::sky130_fd_sc_hs": {
- "CLOCK_PERIOD": 8
- },
- "scl::sky130_fd_sc_ls": {
- "CLOCK_PERIOD": 10,
- "SYNTH_MAX_FANOUT": 5
- },
- "scl::sky130_fd_sc_ms": {
- "CLOCK_PERIOD": 10
- }
+ "CLOCK_PERIOD": 25
},
"pdk::gf180mcuC": {
"STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
@@ -81,5 +98,12 @@
"FP_PDN_CHECK_NODES": 0,
"MAGIC_WRITE_FULL_LEF": 0,
"FP_PDN_ENABLE_RAILS": 0
- }
+ },
+ "MAGIC_DRC_USE_GDS": 0,
+ "RUN_MAGIC_DRC": 0,
+ "QUIT_ON_MAGIC_DRC": 0,
+ "RUN_KLAYOUT_XOR": 0,
+ "ROUTING_CORES": 12,
+ "PL_ESTIMATE_PARASITICS": 0,
+ "MAGIC_WRITE_FULL_LEF": 0
}
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a7365ab..d9c373d 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1,27 @@
-mprj 1175 1690 N
+# LeoRV Cores
+soc_inst.leorv32_core0 500 1510 N
+soc_inst.leorv32_core1 1900 1510 N
+
+# WRAM
+#soc_inst.wram.memory\[0\].sky130_sram_2kbyte_1rw1r_32x512_8 300 300 N
+#soc_inst.wram.memory\[1\].sky130_sram_2kbyte_1rw1r_32x512_8 300 950 N
+#soc_inst.wram.memory\[2\].sky130_sram_2kbyte_1rw1r_32x512_8 1900 300 N
+#soc_inst.wram.memory\[3\].sky130_sram_2kbyte_1rw1r_32x512_8 1900 950 N
+
+# VRAM
+#soc_inst.svga_gen_top.vram.memory\[0\].sky130_sram_2kbyte_1rw1r_32x512_8 300 2250 N
+#soc_inst.svga_gen_top.vram.memory\[1\].sky130_sram_2kbyte_1rw1r_32x512_8 300 2900 N
+#soc_inst.svga_gen_top.vram.memory\[2\].sky130_sram_2kbyte_1rw1r_32x512_8 1900 2250 N
+#soc_inst.svga_gen_top.vram.memory\[3\].sky130_sram_2kbyte_1rw1r_32x512_8 1900 2900 N
+
+# WRAM
+soc_inst.wram.mem0 300 300 N
+soc_inst.wram.mem1 300 950 N
+soc_inst.wram.mem2 1900 300 N
+soc_inst.wram.mem3 1900 950 N
+
+# VRAM
+soc_inst.svga_gen_top.vram.mem0 300 2250 N
+soc_inst.svga_gen_top.vram.mem1 300 2900 N
+soc_inst.svga_gen_top.vram.mem2 1900 2250 N
+soc_inst.svga_gen_top.vram.mem3 1900 2900 N
