commit	359bab6d45a32ab3dfb3bd28a1dd5195196a2a47	[log] [tgz]
author	mole99 <leomoser99@gmail.com>	Thu Dec 22 18:52:37 2022 +0100
committer	mole99 <leomoser99@gmail.com>	Thu Dec 22 18:52:37 2022 +0100
tree	79a4381241efad9b0a71127d1b9337e2065086bc
parent	7baadfdd07b1b53b250f5e9f11ec25391800e0d9 [diff]

Add configurations

openlane/leorv32/config.json[Added - diff]
openlane/leorv32/pin_order.cfg[Added - diff]
openlane/soc/config.json[Added - diff]
openlane/soc/macro.cfg[Added - diff]
openlane/soc/pin_order.cfg[Added - diff]
openlane/user_proj_example/config.json[Deleted - diff]
openlane/user_proj_example/pin_order.cfg[Deleted - diff]
openlane/user_project_wrapper/config.json[diff]
openlane/user_project_wrapper/macro.cfg[diff]

9 files changed

tree: 79a4381241efad9b0a71127d1b9337e2065086bc

README.md

LeoSoC

This is a simple SoC with the following:

1 LeoRV32 Core (RV32I)
8 kB Work RAM
8 kB Video RAM (can also be used as Work RAM)
SVGA Core (800 x 600, 40 MHz)
- Resolution decreased to 100 x 75 pixel
- 1 Byte per Pixel with direct color format (BBGGGRRR)
UART
- 9600 baud fixed at 40 MHz
Blink
- Simple output to blink an LED

Address Layout

Peripheral	Address
WRAM_BASE	0x000000
VRAM_BASE	0x010000
UART_BASE	0x0A0000
BLINK_BASE	0x0F0000