Fixed minor bug of user_module

verilog/rtl/user_module.v

diff --git a/verilog/rtl/user_module.v b/verilog/rtl/user_module.v
index c6e02c9..9fc4caf 100644
--- a/verilog/rtl/user_module.v
+++ b/verilog/rtl/user_module.v
@@ -18,7 +18,7 @@
     wire        clk;
     wire        clock_syn;
     
-    assign  clk = io_in[0]
+    assign  clk = io_in[0];
     assign  clock_select = io_in[2:1];
     assign  clock_syn = div_clock[clock_select];
     assign  clock_div_factor_a = io_in[8:3];