commit 3fa5620566b6a7596fc98e9adc9a4494d08efa56
author t-sasatani <33111879+t-sasatani@users.noreply.github.com> Fri Dec 30 03:56:44 2022 +0900
committer t-sasatani <33111879+t-sasatani@users.noreply.github.com> Fri Dec 30 03:56:44 2022 +0900
tree 324fb301946a5f9b2a18cc47d3147d0609aeaa9b
parent 9b8beb2f8199707572b6f825f0c9899b7b3ab4fd

Fixed minor bug of user_module

verilog/rtl/user_module.v

diff --git a/verilog/rtl/user_module.v b/verilog/rtl/user_module.v
index c6e02c9..9fc4caf 100644
--- a/verilog/rtl/user_module.v
+++ b/verilog/rtl/user_module.v
@@ -18,7 +18,7 @@
     wire        clk;
     wire        clock_syn;
     
-    assign  clk = io_in[0]
+    assign  clk = io_in[0];
     assign  clock_select = io_in[2:1];
     assign  clock_syn = div_clock[clock_select];
     assign  clock_div_factor_a = io_in[8:3];