changed CLOCK_PORT to clk

openlane/tiny_user_project/config.json

diff --git a/openlane/tiny_user_project/config.json b/openlane/tiny_user_project/config.json
index 43a2604..9b7dcf5 100644
--- a/openlane/tiny_user_project/config.json
+++ b/openlane/tiny_user_project/config.json
@@ -8,8 +8,8 @@
         "dir::../../verilog/rtl/tiny_user_project.v"
     ],
     "CLOCK_TREE_SYNTH": 1,
-    "CLOCK_PORT": "io_in[0]",
-    "CLOCK_NET": "io_in[0]",
+    "CLOCK_PORT": "clk",
+    "CLOCK_NET": "clk",
     "FP_SIZING": "absolute",
     "DIE_AREA": "0 0 120 150",
     "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",