commit	23745ed8472f521e1f6bb44babf986f0f8ccbfa6	[log] [tgz]
author	t-sasatani <33111879+t-sasatani@users.noreply.github.com>	Fri Dec 30 03:34:39 2022 +0900
committer	t-sasatani <33111879+t-sasatani@users.noreply.github.com>	Fri Dec 30 03:34:39 2022 +0900
tree	fef9d30fa87225fc94398fbb75edc1dbf2c42f1c
parent	d0f9f893eaf88dee74a468ae40977bfbbf693e92 [diff]

tree: fef9d30fa87225fc94398fbb75edc1dbf2c42f1c

README.md

Tiny User Project

Template for submitting TinyTapeout based projects to the Open MPW shuttle program.

Usage

Generate a new project based on this template.
Set GitHub Pages Sources as GitHub Actions.
If using Wokwi:
- Reuse or create a new Wokwi project.
- Edit info.yaml:
  - In project:
    - Update wokwi_id with the last component of the Wokwi URL.
  - In documentation:
    - Update inputs to document the input wire of your project.
    - Update outputs to document the output wire of your project.
If using Verilog:
- Add your HDL code in verilog/rtl/.
- Edit info.yaml:
  - In project:
    - Set wokwi_id to 0.
    - Uncomment and update top_module to match your top-level module.
    - Uncomment and list your Verilog sources in src_files (paths relative to the root of the repository).
  - In documentation:
    - Update inputs to document the input wire of your top-level module.
    - Update outputs to document the output wire of your top-level module.
Commit, push and check the workflow summary (if successful a new commit including the hardened files will be automatically created).
Submit your project github repository to the next Open MPW shuttle.