changed division factor to 6-bit

info.yaml

diff --git a/info.yaml b/info.yaml
index 639b2c9..2e71847 100644
--- a/info.yaml
+++ b/info.yaml
@@ -35,32 +35,24 @@
     - clock_A_division_factor_bit3
     - clock_A_division_factor_bit4
     - clock_A_division_factor_bit5
-    - clock_A_division_factor_bit6
-    - clock_A_division_factor_bit7
     - clock_B_division_factor_bit0
     - clock_B_division_factor_bit1
     - clock_B_division_factor_bit2
     - clock_B_division_factor_bit3
     - clock_B_division_factor_bit4
     - clock_B_division_factor_bit5
-    - clock_B_division_factor_bit6
-    - clock_B_division_factor_bit7
     - clock_C_division_factor_bit0
     - clock_C_division_factor_bit1
     - clock_C_division_factor_bit2
     - clock_C_division_factor_bit3
     - clock_C_division_factor_bit4
     - clock_C_division_factor_bit5
-    - clock_C_division_factor_bit6
-    - clock_C_division_factor_bit7
     - clock_D_division_factor_bit0
     - clock_D_division_factor_bit1
     - clock_D_division_factor_bit2
     - clock_D_division_factor_bit3
     - clock_D_division_factor_bit4
     - clock_D_division_factor_bit5
-    - clock_D_division_factor_bit6
-    - clock_D_division_factor_bit7
   outputs:
     - clock_selected
 

openlane/tiny_user_project/pin_order.cfg

diff --git a/openlane/tiny_user_project/pin_order.cfg b/openlane/tiny_user_project/pin_order.cfg
index 315428b..db72f7b 100644
--- a/openlane/tiny_user_project/pin_order.cfg
+++ b/openlane/tiny_user_project/pin_order.cfg
@@ -28,15 +28,6 @@
 io_in\[23\]
 io_in\[24\]
 io_in\[25\]
-io_in\[26\]
-io_in\[27\]
-io_in\[28\]
-io_in\[29\]
-io_in\[30\]
-io_in\[31\]
-io_in\[32\]
-io_in\[33\]
-io_in\[34\]
 
 #E
 out.*

verilog/rtl/user_module.v

diff --git a/verilog/rtl/user_module.v b/verilog/rtl/user_module.v
index ef37643..f70bd6d 100644
--- a/verilog/rtl/user_module.v
+++ b/verilog/rtl/user_module.v
@@ -1,29 +1,29 @@
 
 module user_module(
         input   wire    clk,
-        input   wire    [33:0] io_in,
+        input   wire    [25:0] io_in,
         output  wire    out
     );
     
-    reg [8:0]   clock_counter_a     =   9'b000000000;
-    reg [8:0]   clock_counter_b     =   9'b000000000;
-    reg [8:0]   clock_counter_c     =   9'b000000000;
-    reg [8:0]   clock_counter_d     =   9'b000000000;
+    reg [6:0]   clock_counter_a     =   7'b0000000;
+    reg [6:0]   clock_counter_b     =   7'b0000000;
+    reg [6:0]   clock_counter_c     =   7'b0000000;
+    reg [6:0]   clock_counter_d     =   7'b0000000;
     reg [3:0]   div_clock         =   4'b0000;
 
-    wire [7:0]  clock_div_factor_a;
-    wire [7:0]  clock_div_factor_b;
-    wire [7:0]  clock_div_factor_c;
-    wire [7:0]  clock_div_factor_d;
+    wire [5:0]  clock_div_factor_a;
+    wire [5:0]  clock_div_factor_b;
+    wire [5:0]  clock_div_factor_c;
+    wire [5:0]  clock_div_factor_d;
     wire [1:0]  clock_select;
     wire        clock_syn;
     
     assign  clock_select = io_in[1:0];
     assign  clock_syn = div_clock[clock_select];
-    assign  clock_div_factor_a = io_in[9:2];
-    assign  clock_div_factor_b = io_in[17:10];
-    assign  clock_div_factor_c = io_in[25:18];
-    assign  clock_div_factor_d = io_in[33:26];
+    assign  clock_div_factor_a = io_in[7:2];
+    assign  clock_div_factor_b = io_in[13:8];
+    assign  clock_div_factor_c = io_in[19:14];
+    assign  clock_div_factor_d = io_in[25:20];
     
     
     always @ (posedge clk) begin
@@ -34,19 +34,19 @@
 
         if (clock_div_factor_a < clock_counter_a) begin
             div_clock[0] <= ~div_clock[0];
-            clock_counter_a <= 9'b000000000;
+            clock_counter_a <= 7'b0000000;
         end
         if (clock_div_factor_b < clock_counter_b) begin
             div_clock[1] <= ~div_clock[1];
-            clock_counter_b <= 9'b000000000;
+            clock_counter_b <= 7'b0000000;
         end
         if (clock_div_factor_c < clock_counter_c) begin
             div_clock[2] <= ~div_clock[2];
-            clock_counter_c <= 9'b000000000;
+            clock_counter_c <= 7'b0000000;
         end
         if (clock_div_factor_d < clock_counter_d) begin
             div_clock[3] <= ~div_clock[3];
-            clock_counter_d <= 9'b000000000;
+            clock_counter_d <= 7'b0000000;
         end
     end