commit	8ff945884147b76002c6d62aedd00adc8af43832	[log] [tgz]
author	Mathis Salmen <mathis.salmen@matsal.de>	Sun Nov 27 19:25:22 2022 +0100
committer	Mathis Salmen <mathis.salmen@matsal.de>	Sun Nov 27 19:25:22 2022 +0100
tree	d3723cce18b80e4db46946a6020ca14b93670dde
parent	26332ea78fb8a50b683342638de9d72c60d91c5f [diff]

Tapeout

def/user_project_wrapper.def.gz[diff]
gds/user_project_wrapper.gds.gz.00.split[diff]
gds/user_project_wrapper.gds.gz.01.split[diff]
lef/user_project_wrapper.lef[diff]
lib/user_project_wrapper.lib[diff]
mag/user_project_wrapper.mag.gz.00.split[diff]
mag/user_project_wrapper.mag.gz.01.split[diff]
maglef/user_project_wrapper.mag[diff]
openlane/user_project_wrapper/config.tcl[diff]
sdc/user_project_wrapper.sdc[diff]
sdf/multicorner/max/RF.ff.sdf[Deleted - diff]
sdf/multicorner/max/RF.ss.sdf[Deleted - diff]
sdf/multicorner/max/RF.tt.sdf[Deleted - diff]
sdf/multicorner/max/user_project_wrapper.ff.sdf.gz[diff]
sdf/multicorner/max/user_project_wrapper.ss.sdf.gz[diff]
sdf/multicorner/max/user_project_wrapper.tt.sdf.gz[diff]
sdf/multicorner/min/RF.ff.sdf[Deleted - diff]
sdf/multicorner/min/RF.ss.sdf[Deleted - diff]
sdf/multicorner/min/RF.tt.sdf[Deleted - diff]
sdf/multicorner/min/user_project_wrapper.ff.sdf.gz[diff]
sdf/multicorner/min/user_project_wrapper.ss.sdf.gz[diff]
sdf/multicorner/min/user_project_wrapper.tt.sdf.gz[diff]
sdf/multicorner/nom/RF.ff.sdf[Deleted - diff]
sdf/multicorner/nom/RF.ss.sdf[Deleted - diff]
sdf/multicorner/nom/RF.tt.sdf[Deleted - diff]
sdf/multicorner/nom/user_project_wrapper.ff.sdf.gz[diff]
sdf/multicorner/nom/user_project_wrapper.ss.sdf.gz[diff]
sdf/multicorner/nom/user_project_wrapper.tt.sdf.gz[diff]
sdf/user_project_wrapper.sdf.gz[diff]
signoff/build/__gpio_defaults.out[Added - diff]
signoff/build/gpio_defaults.out[Added - diff]
spef/multicorner/RF.max.spef[Deleted - diff]
spef/multicorner/RF.min.spef[Deleted - diff]
spef/multicorner/RF.nom.spef[Deleted - diff]
spef/multicorner/user_project_wrapper.max.spef.gz.00.split[diff]
spef/multicorner/user_project_wrapper.max.spef.gz.01.split[diff]
spef/multicorner/user_project_wrapper.min.spef.gz.00.split[diff]
spef/multicorner/user_project_wrapper.min.spef.gz.01.split[diff]
spef/multicorner/user_project_wrapper.nom.spef.gz.00.split[diff]
spef/multicorner/user_project_wrapper.nom.spef.gz.01.split[diff]
spef/user_project_wrapper.spef.gz.00.split[diff]
spef/user_project_wrapper.spef.gz.01.split[diff]
spi/lvs/user_project_wrapper.spice[diff]
verilog/dv/core/core.c[diff]
verilog/dv/core/core_tb.v[diff]
verilog/dv/io_ports/io_ports.c[Deleted - diff]
verilog/dv/io_ports/io_ports_tb.v[Deleted - diff]
verilog/dv/la_test1/Makefile[Deleted - diff]
verilog/dv/la_test1/la_test1.c[Deleted - diff]
verilog/dv/la_test1/la_test1_tb.v[Deleted - diff]
verilog/dv/la_test2/Makefile[Deleted - diff]
verilog/dv/la_test2/la_test2.c[Deleted - diff]
verilog/dv/mprj_stimulus/Makefile[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus.c[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus_tb.v[Deleted - diff]
verilog/dv/primes/Makefile[Renamed from verilog/dv/io_ports/Makefile - diff]
verilog/dv/primes/primes.c[Added - diff]
verilog/dv/primes/primes_tb.v[Renamed from verilog/dv/la_test2/la_test2_tb.v - diff]
verilog/gl/user_project_wrapper.nl.v[diff]
verilog/gl/user_project_wrapper.v.gz[diff]
verilog/includes/includes.gl.caravel_user_project[diff]
verilog/includes/includes.rtl.caravel_user_project[diff]
verilog/rtl/AGU.v[diff]
verilog/rtl/BranchSelector.v[diff]
verilog/rtl/BranchTargetBuffer.v[diff]
verilog/rtl/CacheController.v[diff]
verilog/rtl/ControlRegs.v[diff]
verilog/rtl/Core.v[diff]
verilog/rtl/ExternalMemorySim.v[diff]
verilog/rtl/InstrDecoder.v[diff]
verilog/rtl/IssueQueue.v[diff]
verilog/rtl/Multiply.v[diff]
verilog/rtl/ROB.v[diff]
verilog/rtl/Rename.v[diff]
verilog/rtl/StoreAGU.v[diff]
verilog/rtl/TagBuffer.v[diff]
verilog/rtl/TageTable.v[diff]
verilog/rtl/Top.v[diff]
verilog/rtl/user_project_wrapper.v[diff]

79 files changed

tree: d3723cce18b80e4db46946a6020ca14b93670dde

README.md

SoomRV

Description

SoomRV is a simple superscalar Out-of-Order RISC-V microprocessor. It can execute up to 4 Instructions per cycle completely out of order, and also supports speculative execution and precise exceptions.

Features

RV32IMCZfinxZbaZbbZicbom Instruction Set (other instructions can be emulated via traps)
4-wide, Ports: 2 Integer/FP, 1 Load, 1 Store
Fully Out-of-Order Load/Store
TAGE-Predictor with 64-entry 8-way associative BTB.
Tag-based OoO execution, 64 registers
64 entry Reorder Buffer
4KiB ICache + 4KiB DCache
32-bit bus (on GPIOs) for memory expansion

Repo

The Verilog source files can be found in verilog/rtl. These are converted from SystemVerilog via zachjs' sv2v, the original SystemVerilog source code is available here.