commit	26332ea78fb8a50b683342638de9d72c60d91c5f	[log] [tgz]
author	Mathis Salmen <mathis.salmen@matsal.de>	Wed Nov 23 19:42:31 2022 +0100
committer	Mathis Salmen <mathis.salmen@matsal.de>	Wed Nov 23 19:42:31 2022 +0100
tree	14f49ed7147ae61926d5c4f8832b68fda160e894
parent	39279e5db787dad301c2d078125ea1f0badf632f [diff]

Re-hardened with gpio defaults

def/RF.def[Added - diff]
def/user_project_wrapper.def.gz[diff]
gds/RF.gds.gz[Added - diff]
gds/user_project_wrapper.gds.gz.00.split[diff]
gds/user_project_wrapper.gds.gz.01.split[diff]
lef/RF.lef[Added - diff]
lef/user_project_wrapper.lef[diff]
lib/RF.lib[Added - diff]
lib/user_project_wrapper.lib[diff]
mag/RF.mag[Added - diff]
mag/user_project_wrapper.mag.gz.00.split[diff]
mag/user_project_wrapper.mag.gz.01.split[diff]
maglef/RF.mag[Added - diff]
maglef/user_project_wrapper.mag[diff]
openlane/rf/config.tcl[diff]
openlane/rf/flow_it.tcl[diff]
openlane/user_project_wrapper/config.tcl[diff]
sdc/RF.sdc[Added - diff]
sdc/user_project_wrapper.sdc[diff]
sdf/RF.sdf[Added - diff]
sdf/multicorner/max/RF.ff.sdf[Added - diff]
sdf/multicorner/max/RF.ss.sdf[Added - diff]
sdf/multicorner/max/RF.tt.sdf[Added - diff]
sdf/multicorner/max/user_project_wrapper.ff.sdf.gz[diff]
sdf/multicorner/max/user_project_wrapper.ss.sdf.gz[diff]
sdf/multicorner/max/user_project_wrapper.tt.sdf.gz[diff]
sdf/multicorner/min/RF.ff.sdf[Added - diff]
sdf/multicorner/min/RF.ss.sdf[Added - diff]
sdf/multicorner/min/RF.tt.sdf[Added - diff]
sdf/multicorner/min/user_project_wrapper.ff.sdf.gz[diff]
sdf/multicorner/min/user_project_wrapper.ss.sdf.gz[diff]
sdf/multicorner/min/user_project_wrapper.tt.sdf.gz[diff]
sdf/multicorner/nom/RF.ff.sdf[Added - diff]
sdf/multicorner/nom/RF.ss.sdf[Added - diff]
sdf/multicorner/nom/RF.tt.sdf[Added - diff]
sdf/multicorner/nom/user_project_wrapper.ff.sdf.gz[diff]
sdf/multicorner/nom/user_project_wrapper.ss.sdf.gz[diff]
sdf/multicorner/nom/user_project_wrapper.tt.sdf.gz[diff]
sdf/user_project_wrapper.sdf.gz[diff]
spef/RF.spef[Added - diff]
spef/multicorner/RF.max.spef[Added - diff]
spef/multicorner/RF.min.spef[Added - diff]
spef/multicorner/RF.nom.spef[Added - diff]
spef/multicorner/user_project_wrapper.max.spef.gz[Deleted - diff]
spef/multicorner/user_project_wrapper.max.spef.gz.00.split[Added - diff]
spef/multicorner/user_project_wrapper.max.spef.gz.01.split[Added - diff]
spef/multicorner/user_project_wrapper.min.spef.gz[Deleted - diff]
spef/multicorner/user_project_wrapper.min.spef.gz.00.split[Added - diff]
spef/multicorner/user_project_wrapper.min.spef.gz.01.split[Added - diff]
spef/multicorner/user_project_wrapper.nom.spef.gz[Deleted - diff]
spef/multicorner/user_project_wrapper.nom.spef.gz.00.split[Added - diff]
spef/multicorner/user_project_wrapper.nom.spef.gz.01.split[Added - diff]
spef/user_project_wrapper.spef.gz[Deleted - diff]
spef/user_project_wrapper.spef.gz.00.split[Added - diff]
spef/user_project_wrapper.spef.gz.01.split[Added - diff]
spi/lvs/RF.spice[Added - diff]
spi/lvs/user_project_wrapper.spice[diff]
verilog/gl/RF.nl.v[Added - diff]
verilog/gl/user_project_wrapper.nl.v[diff]
verilog/gl/user_project_wrapper.v.gz[diff]
verilog/rtl/ControlRegs.v[diff]
verilog/rtl/Core.v[diff]
verilog/rtl/FMul.v[Added - diff]
verilog/rtl/FPU.v[diff]
verilog/rtl/InstrDecoder.v[diff]
verilog/rtl/IssueQueue.v[diff]
verilog/rtl/Load.v[diff]
verilog/rtl/Multiply.v[diff]
verilog/rtl/ROB.v[diff]
verilog/rtl/Rename.v[diff]
verilog/rtl/StoreQueue.v[diff]
verilog/rtl/Top.v[diff]
verilog/rtl/user_defines.v[diff]

73 files changed

tree: 14f49ed7147ae61926d5c4f8832b68fda160e894

README.md

SoomRV

Description

SoomRV is a simple superscalar Out-of-Order RISC-V microprocessor. It can execute up to 4 Instructions per cycle completely out of order, and also supports speculative execution and precise exceptions.

Features

RV32IMCZfinxZbaZbbZicbom Instruction Set (other instructions can be emulated via traps)
4-wide, Ports: 2 Integer/FP, 1 Load, 1 Store
Fully Out-of-Order Load/Store
TAGE-Predictor with 64-entry 8-way associative BTB.
Tag-based OoO execution, 64 registers
64 entry Reorder Buffer
4KiB ICache + 4KiB DCache
32-bit bus (on GPIOs) for memory expansion

Repo

The Verilog source files can be found in verilog/rtl. These are converted from SystemVerilog via zachjs' sv2v, the original SystemVerilog source code is available here.