| ############################################################################### |
| # Created by write_sdc |
| # Tue Nov 22 22:11:28 2022 |
| ############################################################################### |
| current_design RF |
| ############################################################################### |
| # Timing Constraints |
| ############################################################################### |
| create_clock -name clk -period 20.0000 [get_ports {clk}] |
| set_clock_transition 0.1500 [get_clocks {clk}] |
| set_clock_uncertainty 0.2500 clk |
| set_propagated_clock [get_clocks {clk}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr0[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr0[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr0[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr0[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr0[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr0[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr1[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr1[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr1[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr1[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr1[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr1[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr2[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr2[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr2[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr2[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr2[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr2[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr3[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr3[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr3[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr3[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr3[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr3[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr4[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr4[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr4[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr4[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr4[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr4[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr5[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr5[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr5[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr5[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr5[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr5[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr6[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr6[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr6[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr6[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr6[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr6[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr7[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr7[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr7[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr7[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr7[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {raddr7[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {waddr0[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {waddr0[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {waddr0[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {waddr0[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {waddr0[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {waddr0[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {waddr1[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {waddr1[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {waddr1[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {waddr1[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {waddr1[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {waddr1[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {waddr2[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {waddr2[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {waddr2[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {waddr2[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {waddr2[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {waddr2[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {waddr3[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {waddr3[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {waddr3[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {waddr3[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {waddr3[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {waddr3[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[29]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[30]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[31]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata0[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[29]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[30]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[31]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata1[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[29]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[30]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[31]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata2[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[29]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[30]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[31]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wdata3[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wen0}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wen1}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wen2}] |
| set_input_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wen3}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[29]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[30]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[31]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata0[9]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[29]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[30]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[31]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata1[9]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[29]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[30]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[31]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata2[9]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[29]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[30]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[31]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata3[9]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[29]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[30]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[31]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata4[9]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[29]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[30]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[31]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata5[9]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[29]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[30]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[31]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata6[9]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[29]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[30]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[31]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rdata7[9]}] |
| ############################################################################### |
| # Environment |
| ############################################################################### |
| set_load -pin_load 0.0334 [get_ports {rdata0[31]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[30]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[29]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[28]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[27]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[26]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[25]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[24]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[23]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[22]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[21]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[20]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[19]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[18]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[17]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[16]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[15]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[14]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[13]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[12]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[11]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[10]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[9]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[8]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[7]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[6]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[5]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[4]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[3]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[2]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[1]}] |
| set_load -pin_load 0.0334 [get_ports {rdata0[0]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[31]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[30]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[29]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[28]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[27]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[26]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[25]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[24]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[23]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[22]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[21]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[20]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[19]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[18]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[17]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[16]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[15]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[14]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[13]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[12]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[11]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[10]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[9]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[8]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[7]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[6]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[5]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[4]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[3]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[2]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[1]}] |
| set_load -pin_load 0.0334 [get_ports {rdata1[0]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[31]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[30]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[29]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[28]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[27]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[26]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[25]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[24]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[23]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[22]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[21]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[20]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[19]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[18]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[17]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[16]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[15]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[14]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[13]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[12]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[11]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[10]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[9]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[8]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[7]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[6]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[5]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[4]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[3]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[2]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[1]}] |
| set_load -pin_load 0.0334 [get_ports {rdata2[0]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[31]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[30]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[29]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[28]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[27]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[26]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[25]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[24]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[23]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[22]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[21]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[20]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[19]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[18]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[17]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[16]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[15]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[14]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[13]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[12]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[11]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[10]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[9]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[8]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[7]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[6]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[5]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[4]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[3]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[2]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[1]}] |
| set_load -pin_load 0.0334 [get_ports {rdata3[0]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[31]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[30]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[29]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[28]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[27]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[26]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[25]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[24]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[23]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[22]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[21]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[20]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[19]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[18]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[17]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[16]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[15]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[14]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[13]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[12]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[11]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[10]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[9]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[8]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[7]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[6]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[5]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[4]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[3]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[2]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[1]}] |
| set_load -pin_load 0.0334 [get_ports {rdata4[0]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[31]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[30]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[29]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[28]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[27]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[26]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[25]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[24]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[23]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[22]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[21]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[20]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[19]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[18]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[17]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[16]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[15]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[14]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[13]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[12]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[11]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[10]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[9]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[8]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[7]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[6]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[5]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[4]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[3]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[2]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[1]}] |
| set_load -pin_load 0.0334 [get_ports {rdata5[0]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[31]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[30]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[29]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[28]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[27]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[26]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[25]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[24]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[23]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[22]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[21]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[20]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[19]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[18]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[17]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[16]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[15]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[14]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[13]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[12]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[11]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[10]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[9]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[8]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[7]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[6]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[5]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[4]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[3]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[2]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[1]}] |
| set_load -pin_load 0.0334 [get_ports {rdata6[0]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[31]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[30]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[29]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[28]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[27]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[26]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[25]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[24]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[23]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[22]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[21]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[20]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[19]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[18]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[17]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[16]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[15]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[14]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[13]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[12]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[11]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[10]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[9]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[8]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[7]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[6]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[5]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[4]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[3]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[2]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[1]}] |
| set_load -pin_load 0.0334 [get_ports {rdata7[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clk}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wen0}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wen1}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wen2}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wen3}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr0[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr0[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr0[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr0[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr0[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr0[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr1[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr1[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr1[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr1[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr1[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr1[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr2[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr2[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr2[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr2[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr2[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr2[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr3[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr3[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr3[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr3[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr3[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr3[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr4[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr4[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr4[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr4[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr4[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr4[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr5[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr5[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr5[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr5[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr5[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr5[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr6[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr6[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr6[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr6[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr6[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr6[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr7[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr7[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr7[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr7[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr7[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {raddr7[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {waddr0[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {waddr0[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {waddr0[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {waddr0[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {waddr0[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {waddr0[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {waddr1[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {waddr1[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {waddr1[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {waddr1[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {waddr1[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {waddr1[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {waddr2[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {waddr2[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {waddr2[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {waddr2[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {waddr2[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {waddr2[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {waddr3[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {waddr3[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {waddr3[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {waddr3[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {waddr3[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {waddr3[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata0[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata1[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata2[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wdata3[0]}] |
| set_timing_derate -early 0.9500 |
| set_timing_derate -late 1.0500 |
| ############################################################################### |
| # Design Rules |
| ############################################################################### |
| set_max_fanout 10.0000 [current_design] |
