verilog/includes/includes.gl.caravel_user_project

# Caravel user project includes	     
-v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v
-v $(USER_PROJECT_VERILOG)/rtl/ExternalMemorySim.v 
-v $(USER_PROJECT_VERILOG)/rtl/sky130_sram_8kbyte_1rw_64x1024_8.v
-v $(USER_PROJECT_VERILOG)/rtl/sky130_sram_8kbyte_1rw1r_32x2048_8.v
-v $(USER_PROJECT_VERILOG)/../openlane/rf/runs/RUN_2022.10.21_13.44.58/results/final/verilog/gl/RF.v