| /* Generated by Yosys 0.22+1 (git sha1 c4a52b1b0, clang 14.0.0-1ubuntu1 -fPIC -Os) */ |
| |
| module adamgreig_tt02_adc_dac(io_in, io_out); |
| reg \$auto$verilog_backend.cc:2083:dump_module$1 = 0; |
| wire [8:0] \$1 ; |
| wire [8:0] \$2 ; |
| wire [8:0] \$4 ; |
| wire [8:0] \$5 ; |
| reg [7:0] acc = 8'h00; |
| reg [7:0] \acc$next ; |
| wire clk; |
| wire [7:0] dac_data; |
| wire dac_out; |
| input [7:0] io_in; |
| wire [7:0] io_in; |
| output [7:0] io_out; |
| wire [7:0] io_out; |
| reg [9:0] ready_sr = 10'h000; |
| reg [9:0] \ready_sr$next ; |
| wire rst; |
| wire [7:0] uart_tx_data; |
| wire uart_tx_ready; |
| wire uart_tx_tx_o; |
| wire uart_tx_valid; |
| assign \$2 = acc - 1'h1; |
| assign \$5 = acc + 1'h1; |
| always @(posedge clk) |
| acc <= \acc$next ; |
| always @(posedge clk) |
| ready_sr <= \ready_sr$next ; |
| dac dac ( |
| .clk(clk), |
| .data(dac_data), |
| .out(dac_out), |
| .rst(rst) |
| ); |
| uart_tx uart_tx ( |
| .clk(clk), |
| .data(uart_tx_data), |
| .ready(uart_tx_ready), |
| .rst(rst), |
| .tx_o(uart_tx_tx_o), |
| .valid(uart_tx_valid) |
| ); |
| always @* begin |
| if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end |
| (* full_case = 32'd1 *) |
| casez (io_in[2]) |
| 1'h1: |
| \acc$next = \$2 [7:0]; |
| default: |
| \acc$next = \$5 [7:0]; |
| endcase |
| casez (rst) |
| 1'h1: |
| \acc$next = 8'h00; |
| endcase |
| end |
| always @* begin |
| if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end |
| \ready_sr$next = { ready_sr[8:0], uart_tx_ready }; |
| casez (rst) |
| 1'h1: |
| \ready_sr$next = 10'h000; |
| endcase |
| end |
| assign \$1 = \$2 ; |
| assign \$4 = \$5 ; |
| assign uart_tx_valid = ready_sr[9]; |
| assign uart_tx_data = acc; |
| assign io_out[1] = uart_tx_tx_o; |
| assign io_out[0] = dac_out; |
| assign io_out[7:2] = 6'h00; |
| assign dac_data = acc; |
| assign rst = io_in[1]; |
| assign clk = io_in[0]; |
| endmodule |
| |
| module dac(rst, data, out, clk); |
| reg \$auto$verilog_backend.cc:2083:dump_module$2 = 0; |
| wire [8:0] \$1 ; |
| reg [8:0] acc = 9'h000; |
| reg [8:0] \acc$next ; |
| input clk; |
| wire clk; |
| input [7:0] data; |
| wire [7:0] data; |
| output out; |
| wire out; |
| input rst; |
| wire rst; |
| assign \$1 = acc[7:0] + data; |
| always @(posedge clk) |
| acc <= \acc$next ; |
| always @* begin |
| if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end |
| \acc$next = \$1 ; |
| casez (rst) |
| 1'h1: |
| \acc$next = 9'h000; |
| endcase |
| end |
| assign out = acc[8]; |
| endmodule |
| |
| module uart_tx(rst, data, tx_o, ready, valid, clk); |
| reg \$auto$verilog_backend.cc:2083:dump_module$3 = 0; |
| wire \$1 ; |
| wire \$3 ; |
| wire \$5 ; |
| wire [4:0] \$7 ; |
| wire [4:0] \$8 ; |
| input clk; |
| wire clk; |
| input [7:0] data; |
| wire [7:0] data; |
| output ready; |
| reg ready; |
| input rst; |
| wire rst; |
| reg [3:0] tx_cnt = 4'h0; |
| reg [3:0] \tx_cnt$next ; |
| output tx_o; |
| wire tx_o; |
| reg [9:0] tx_reg = 10'h001; |
| reg [9:0] \tx_reg$next ; |
| input valid; |
| wire valid; |
| always @(posedge clk) |
| tx_reg <= \tx_reg$next ; |
| always @(posedge clk) |
| tx_cnt <= \tx_cnt$next ; |
| assign \$1 = ! tx_cnt; |
| assign \$3 = ! tx_cnt; |
| assign \$5 = ! tx_cnt; |
| assign \$8 = tx_cnt - 1'h1; |
| always @* begin |
| if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end |
| (* full_case = 32'd1 *) |
| casez (\$1 ) |
| 1'h1: |
| ready = 1'h1; |
| default: |
| ready = 1'h0; |
| endcase |
| end |
| always @* begin |
| if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end |
| \tx_reg$next = tx_reg; |
| (* full_case = 32'd1 *) |
| casez (\$3 ) |
| 1'h1: |
| casez (valid) |
| 1'h1: |
| \tx_reg$next = { 1'h1, data, 1'h0 }; |
| endcase |
| default: |
| \tx_reg$next = { 1'h1, tx_reg[9:1] }; |
| endcase |
| casez (rst) |
| 1'h1: |
| \tx_reg$next = 10'h001; |
| endcase |
| end |
| always @* begin |
| if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end |
| \tx_cnt$next = tx_cnt; |
| (* full_case = 32'd1 *) |
| casez (\$5 ) |
| 1'h1: |
| casez (valid) |
| 1'h1: |
| \tx_cnt$next = 4'ha; |
| endcase |
| default: |
| \tx_cnt$next = \$8 [3:0]; |
| endcase |
| casez (rst) |
| 1'h1: |
| \tx_cnt$next = 4'h0; |
| endcase |
| end |
| assign \$7 = \$8 ; |
| assign tx_o = tx_reg[0]; |
| endmodule |
| |