verilog/includes/includes.rtl.caravel_user_project

-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/scan_controller/scan_controller.v
-v $(USER_PROJECT_VERILOG)/rtl/scanchain/scanchain.v
-v $(USER_PROJECT_VERILOG)/rtl/cells.v
-v $(USER_PROJECT_VERILOG)/rtl/user_module_339501025136214612.v
-v $(USER_PROJECT_VERILOG)/rtl/user_module_340805072482992722.v
-v $(USER_PROJECT_VERILOG)/rtl/user_module_341535056611770964.v