verilog/rtl/059_user_module_nickoe.v

// -----------------------------------------------------------------------------
// Auto-Generated by:        __   _ __      _  __
//                          / /  (_) /____ | |/_/
//                         / /__/ / __/ -_)>  <
//                        /____/_/\__/\__/_/|_|
//                     Build your hardware, easily!
//                   https://github.com/enjoy-digital/litex
//
// Filename   : user_module_nickoe.v
// Device     : tapeout
// LiteX sha1 : 5b8d3651
// Date       : 2022-11-16 16:11:17
//------------------------------------------------------------------------------


//------------------------------------------------------------------------------
// Module
//------------------------------------------------------------------------------

module user_module_nickoe (
	input  wire [7:0] io_in,
	output reg  [7:0] io_out
);


//------------------------------------------------------------------------------
// Signals
//------------------------------------------------------------------------------

wire sys_clk;
wire sys_rst;
wire por_clk;
reg  int_rst = 1'd1;
reg  [7:0] storage = 8'd0;
reg  re = 1'd0;
reg  [7:0] chaser = 8'd0;
reg  mode = 1'd0;
wire wait_1;
wire done;
reg  [9:0] count = 10'd625;
reg  [7:0] leds = 8'd0;
reg  pwm = 1'd0;
reg  enable = 1'd1;
reg  [31:0] width = 32'd25;
reg  [31:0] period = 32'd31;
reg  [31:0] counter = 32'd0;
wire [7:0] comb_slice_proxy0;
wire [7:0] comb_slice_proxy1;
wire [7:0] sync_slice_proxy0;
wire [7:0] sync_slice_proxy1;

//------------------------------------------------------------------------------
// Combinatorial Logic
//------------------------------------------------------------------------------

assign sys_clk = comb_slice_proxy0[0];
assign por_clk = comb_slice_proxy1[0];
assign sys_rst = int_rst;
assign wait_1 = (~done);
always @(*) begin
	leds <= 8'd0;
	if ((mode == 1'd1)) begin
		leds <= storage;
	end else begin
		leds <= chaser;
	end
end
always @(*) begin
	io_out <= 8'd0;
	{io_out} <= (leds ^ 1'd0);
	if ((~pwm)) begin
		{io_out} <= 1'd0;
	end
end
assign done = (count == 1'd0);
assign comb_slice_proxy0 = {io_in};
assign comb_slice_proxy1 = {io_in};
assign sync_slice_proxy0 = {io_in};
assign sync_slice_proxy1 = {io_in};


//------------------------------------------------------------------------------
// Synchronous Logic
//------------------------------------------------------------------------------

always @(posedge por_clk) begin
	int_rst <= sync_slice_proxy0[1];
end

always @(posedge sys_clk) begin
	width <= sync_slice_proxy1[7:2];
	if (done) begin
		chaser <= {chaser, (~chaser[7])};
	end
	if (re) begin
		mode <= 1'd1;
	end
	if (wait_1) begin
		if ((~done)) begin
			count <= (count - 1'd1);
		end
	end else begin
		count <= 10'd625;
	end
	if (enable) begin
		counter <= (counter + 1'd1);
		if ((counter < width)) begin
			pwm <= 1'd1;
		end else begin
			pwm <= 1'd0;
		end
		if ((counter >= (period - 1'd1))) begin
			counter <= 1'd0;
		end
	end else begin
		counter <= 1'd0;
		pwm <= 1'd0;
	end
	if (sys_rst) begin
		chaser <= 8'd0;
		mode <= 1'd0;
		count <= 10'd625;
		pwm <= 1'd0;
		width <= 32'd25;
	end
end


//------------------------------------------------------------------------------
// Specialized Logic
//------------------------------------------------------------------------------

endmodule

// -----------------------------------------------------------------------------
//  Auto-Generated by LiteX on 2022-11-16 16:11:17.
//------------------------------------------------------------------------------