| commit | b7fefa7d35b98280ab8358f64c0c4aa651af7322 | [log] [tgz] |
|---|---|---|
| author | Matt Venn <matt@mattvenn.net> | Fri Dec 02 14:01:04 2022 +0100 |
| committer | Matt Venn <matt@mattvenn.net> | Fri Dec 02 14:01:04 2022 +0100 |
| tree | 916c146515dac8652c4cf9f714e3dd99233c2ba9 | |
| parent | f48e7e351642e1bc4e3a6ff4315d341cda037592 [diff] [blame] |
integrate new designs
diff --git a/verilog/rtl/078_top.v b/verilog/rtl/078_top.v new file mode 100644 index 0000000..01583e2 --- /dev/null +++ b/verilog/rtl/078_top.v
@@ -0,0 +1,9 @@ + +`default_nettype none + +module davidsiaw_stackcalc ( + input wire [7:0] io_in, + output wire [7:0] io_out +); + stack_cpu cpu(.io_in(io_in), .io_out(io_out)); +endmodule