integrate new designs
diff --git a/verilog/rtl/008_mccoy.v b/verilog/rtl/008_mccoy.v
index 581ac51..96f7b19 100644
--- a/verilog/rtl/008_mccoy.v
+++ b/verilog/rtl/008_mccoy.v
@@ -14,8 +14,6 @@
wire clk = io_in[0];
wire reset = io_in[1];
wire [5:0] instr = io_in[7:2];
- // opcode instr[2:0]
- // reg or imm instr[5:3]
// decode signals
wire bez;
@@ -28,18 +26,18 @@
wire [1:0] x8Sel;
// Other wires
- wire [5:0] pc;
- wire [5:0] pc1;
- wire [5:0] nextPC;
+ wire [7:0] pc;
+ wire [7:0] pc1;
+ wire [7:0] nextPC;
wire pcSel;
- wire [5:0] aluOut;
- wire [5:0] x8;
- wire [5:0] newx8;
- wire [5:0] op1;
- wire [5:0] op2;
- wire [5:0] regOut;
- wire [5:0] imm;
- wire [5:0] notx8;
+ wire [7:0] aluOut;
+ wire [7:0] x8;
+ wire [7:0] newx8;
+ wire [7:0] op1;
+ wire [7:0] op2;
+ wire [7:0] regOut;
+ wire [7:0] imm;
+ wire [7:0] notx8;
/* Misc. blocks */
@@ -78,7 +76,7 @@
mux4 x8Mux( .in0(regOut), .in1(imm), .in2(aluOut), .in3(notx8), .sel(x8Sel), .out(newx8));
- assign io_out = clk ? {2'b00, pc} : {2'b00, x8};
+ assign io_out = clk ? pc : x8;
endmodule
diff --git a/verilog/rtl/033_mbikovitsky_top.v b/verilog/rtl/033_mbikovitsky_top.v
index e3c2a51..2dfb8a4 100644
--- a/verilog/rtl/033_mbikovitsky_top.v
+++ b/verilog/rtl/033_mbikovitsky_top.v
@@ -1,5 +1,7 @@
module mbikovitsky_top #(
- parameter CLOCK_HZ = 1000
+ parameter CLOCK_HZ = 625,
+ parameter BAUD = 78,
+ parameter ROM_WORDS = 4
) (
input [7:0] io_in,
output [7:0] io_out
@@ -8,13 +10,24 @@
localparam LFSR_BITS = 5;
wire clk = io_in[0];
+
+ wire mode_cpu = reset_lfsr & reset_taps;
+
+ assign io_out = mode_cpu ? cpu_io_out[7:0] : segments;
+
+ //
+ // LFSR
+ //
+
wire reset_lfsr = io_in[1];
wire reset_taps = io_in[2];
wire [LFSR_BITS-1:0] data_in = io_in[3+LFSR_BITS-1:3];
+ wire [7:0] segments;
+
seven_segment seven_segment (
.value_i(lfsr_out),
- .segments_o(io_out)
+ .segments_o(segments)
);
wire [LFSR_BITS-1:0] lfsr_out;
@@ -31,4 +44,105 @@
.state_o(lfsr_out)
);
+ //
+ // CPU
+ //
+
+ wire cpu_reset = (!mode_cpu) || (mode_cpu && io_in[3]);
+ wire mem_reset = (!mode_cpu) || (mode_cpu && io_in[4]);
+ wire uart_reset = (!mode_cpu) || (mode_cpu && io_in[6]);
+ wire uart_rx = io_in[5];
+
+ CPU cpu (
+ .clk(clk),
+ .reset(cpu_reset),
+ .instruction(instruction),
+ .next_instruction_addr_o(next_instruction_addr),
+ .memory_we_o(memory_we),
+ .memory_i(cpu_io_out),
+ .memory_o(cpu_memory_out)
+ );
+
+ wire [15:0] instruction;
+ wire [14:0] next_instruction_addr;
+
+ wire memory_we;
+ wire [15:0] cpu_memory_out;
+
+ // Address map (in 16-bit words)
+ // ---
+ // 0 - 0x3FFF - Zeroes
+ // 0x4000 - 0x4000 - io_in (high 8 bits are always 0 on read)
+ // 0x4001 - 0x4001 - io_out (high 8 bits are ignored on write,
+ // 0 on read)
+
+ // I/O output
+ reg [15:0] cpu_io_out;
+ always @(posedge clk) begin
+ if (mem_reset) begin
+ cpu_io_out <= 0;
+ end else begin
+ if (!cpu_reset && memory_we) begin
+ cpu_io_out <= cpu_memory_out;
+ end
+ end
+ end
+
+ // PROM
+
+ reg [16-1:0] prom [ROM_WORDS];
+
+ assign instruction = prom[next_instruction_addr[$clog2(ROM_WORDS)-1:0]];
+
+ // UART to fill the PROM
+
+ UART #(
+ .CLOCK_HZ(CLOCK_HZ),
+ .BAUD(BAUD)
+ ) uart(
+ .reset(uart_reset),
+ .clk(clk),
+ .rx_i(uart_rx),
+ .rx_data_o(rx_data),
+ .rx_ready_o(rx_ready),
+ .rx_ack_i(1'b1)
+ );
+
+ wire [7:0] rx_data;
+ wire rx_ready;
+
+ reg [$clog2(ROM_WORDS)-1:0] uart_write_address;
+ reg [0:0] uart_state;
+
+ localparam UART_RECEIVE_LOW = 2'd0,
+ UART_RECEIVE_HIGH = 2'd1;
+
+ always @(posedge clk) begin
+ if (uart_reset) begin
+ uart_write_address <= 0;
+ uart_state <= UART_RECEIVE_LOW;
+ end else begin
+ case (uart_state)
+ UART_RECEIVE_LOW: begin
+ if (rx_ready) begin
+ prom[uart_write_address][7:0] <= rx_data;
+ uart_state <= UART_RECEIVE_HIGH;
+ end
+ end
+ UART_RECEIVE_HIGH: begin
+ if (rx_ready) begin
+ prom[uart_write_address][15:8] <= rx_data;
+ uart_state <= UART_RECEIVE_LOW;
+
+ if (uart_write_address == ROM_WORDS - 1) begin
+ uart_write_address <= 0;
+ end else begin
+ uart_write_address <= uart_write_address + 1;
+ end
+ end
+ end
+ endcase
+ end
+ end
+
endmodule
diff --git a/verilog/rtl/036_jar_pi.v b/verilog/rtl/036_jar_pi.v
new file mode 100644
index 0000000..f44a72d
--- /dev/null
+++ b/verilog/rtl/036_jar_pi.v
@@ -0,0 +1,1052 @@
+module jar_pi
+(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+ wire clk = io_in[0];
+ wire reset = io_in[1];
+
+ reg [9:0] index;
+ reg [3:0] code;
+
+ always @(posedge clk) begin
+ if (reset) begin
+ index <= 0;
+ end
+ else begin
+ index <= index + 1;
+
+ /* verilator lint_off CASEX */
+ casex(index)
+ 0: code <= 4'bx011;
+ 1: code <= 4'b1010;
+ 2: code <= 4'b0001;
+ 3: code <= 4'bx100;
+ 4: code <= 4'b0001;
+ 5: code <= 4'bx101;
+ 6: code <= 4'b1001;
+ 7: code <= 4'b0010;
+ 8: code <= 4'bx110;
+ 9: code <= 4'bx101;
+ 10: code <= 4'bx011;
+ 11: code <= 4'bx101;
+ 12: code <= 4'b1000;
+ 13: code <= 4'b1001;
+ 14: code <= 4'bx111;
+ 15: code <= 4'b1001;
+ 16: code <= 4'bx011;
+ 17: code <= 4'b0010;
+ 18: code <= 4'bx011;
+ 19: code <= 4'b1000;
+ 20: code <= 4'bx100;
+ 21: code <= 4'bx110;
+ 22: code <= 4'b0010;
+ 23: code <= 4'bx110;
+ 24: code <= 4'bx100;
+ 25: code <= 4'bx011;
+ 26: code <= 4'bx011;
+ 27: code <= 4'b1000;
+ 28: code <= 4'bx011;
+ 29: code <= 4'b0010;
+ 30: code <= 4'bx111;
+ 31: code <= 4'b1001;
+ 32: code <= 4'bx101;
+ 33: code <= 4'b0000;
+ 34: code <= 4'b0010;
+ 35: code <= 4'b1000;
+ 36: code <= 4'b1000;
+ 37: code <= 4'bx100;
+ 38: code <= 4'b0001;
+ 39: code <= 4'b1001;
+ 40: code <= 4'bx111;
+ 41: code <= 4'b0001;
+ 42: code <= 4'bx110;
+ 43: code <= 4'b1001;
+ 44: code <= 4'bx011;
+ 45: code <= 4'b1001;
+ 46: code <= 4'b1001;
+ 47: code <= 4'bx011;
+ 48: code <= 4'bx111;
+ 49: code <= 4'bx101;
+ 50: code <= 4'b0001;
+ 51: code <= 4'b0000;
+ 52: code <= 4'bx101;
+ 53: code <= 4'b1000;
+ 54: code <= 4'b0010;
+ 55: code <= 4'b0000;
+ 56: code <= 4'b1001;
+ 57: code <= 4'bx111;
+ 58: code <= 4'bx100;
+ 59: code <= 4'b1001;
+ 60: code <= 4'bx100;
+ 61: code <= 4'bx100;
+ 62: code <= 4'bx101;
+ 63: code <= 4'b1001;
+ 64: code <= 4'b0010;
+ 65: code <= 4'bx011;
+ 66: code <= 4'b0000;
+ 67: code <= 4'bx111;
+ 68: code <= 4'b1000;
+ 69: code <= 4'b0001;
+ 70: code <= 4'bx110;
+ 71: code <= 4'bx100;
+ 72: code <= 4'b0000;
+ 73: code <= 4'bx110;
+ 74: code <= 4'b0010;
+ 75: code <= 4'b1000;
+ 76: code <= 4'bx110;
+ 77: code <= 4'b0010;
+ 78: code <= 4'b0000;
+ 79: code <= 4'b1000;
+ 80: code <= 4'b1001;
+ 81: code <= 4'b1001;
+ 82: code <= 4'b1000;
+ 83: code <= 4'bx110;
+ 84: code <= 4'b0010;
+ 85: code <= 4'b1000;
+ 86: code <= 4'b0000;
+ 87: code <= 4'bx011;
+ 88: code <= 4'bx100;
+ 89: code <= 4'b1000;
+ 90: code <= 4'b0010;
+ 91: code <= 4'bx101;
+ 92: code <= 4'bx011;
+ 93: code <= 4'bx100;
+ 94: code <= 4'b0010;
+ 95: code <= 4'b0001;
+ 96: code <= 4'b0001;
+ 97: code <= 4'bx111;
+ 98: code <= 4'b0000;
+ 99: code <= 4'bx110;
+ 100: code <= 4'bx111;
+ 101: code <= 4'b1001;
+ 102: code <= 4'b1000;
+ 103: code <= 4'b0010;
+ 104: code <= 4'b0001;
+ 105: code <= 4'bx100;
+ 106: code <= 4'b1000;
+ 107: code <= 4'b0000;
+ 108: code <= 4'b1000;
+ 109: code <= 4'bx110;
+ 110: code <= 4'bx101;
+ 111: code <= 4'b0001;
+ 112: code <= 4'bx011;
+ 113: code <= 4'b0010;
+ 114: code <= 4'b1000;
+ 115: code <= 4'b0010;
+ 116: code <= 4'bx011;
+ 117: code <= 4'b0000;
+ 118: code <= 4'bx110;
+ 119: code <= 4'bx110;
+ 120: code <= 4'bx100;
+ 121: code <= 4'bx111;
+ 122: code <= 4'b0000;
+ 123: code <= 4'b1001;
+ 124: code <= 4'bx011;
+ 125: code <= 4'b1000;
+ 126: code <= 4'bx100;
+ 127: code <= 4'bx100;
+ 128: code <= 4'bx110;
+ 129: code <= 4'b0000;
+ 130: code <= 4'b1001;
+ 131: code <= 4'bx101;
+ 132: code <= 4'bx101;
+ 133: code <= 4'b0000;
+ 134: code <= 4'bx101;
+ 135: code <= 4'b1000;
+ 136: code <= 4'b0010;
+ 137: code <= 4'b0010;
+ 138: code <= 4'bx011;
+ 139: code <= 4'b0001;
+ 140: code <= 4'bx111;
+ 141: code <= 4'b0010;
+ 142: code <= 4'bx101;
+ 143: code <= 4'bx011;
+ 144: code <= 4'bx101;
+ 145: code <= 4'b1001;
+ 146: code <= 4'bx100;
+ 147: code <= 4'b0000;
+ 148: code <= 4'b1000;
+ 149: code <= 4'b0001;
+ 150: code <= 4'b0010;
+ 151: code <= 4'b1000;
+ 152: code <= 4'bx100;
+ 153: code <= 4'b1000;
+ 154: code <= 4'b0001;
+ 155: code <= 4'b0001;
+ 156: code <= 4'b0001;
+ 157: code <= 4'bx111;
+ 158: code <= 4'bx100;
+ 159: code <= 4'bx101;
+ 160: code <= 4'b0000;
+ 161: code <= 4'b0010;
+ 162: code <= 4'b1000;
+ 163: code <= 4'bx100;
+ 164: code <= 4'b0001;
+ 165: code <= 4'b0000;
+ 166: code <= 4'b0010;
+ 167: code <= 4'bx111;
+ 168: code <= 4'b0000;
+ 169: code <= 4'b0001;
+ 170: code <= 4'b1001;
+ 171: code <= 4'bx011;
+ 172: code <= 4'b1000;
+ 173: code <= 4'bx101;
+ 174: code <= 4'b0010;
+ 175: code <= 4'b0001;
+ 176: code <= 4'b0001;
+ 177: code <= 4'b0000;
+ 178: code <= 4'bx101;
+ 179: code <= 4'bx101;
+ 180: code <= 4'bx101;
+ 181: code <= 4'b1001;
+ 182: code <= 4'bx110;
+ 183: code <= 4'bx100;
+ 184: code <= 4'bx100;
+ 185: code <= 4'bx110;
+ 186: code <= 4'b0010;
+ 187: code <= 4'b0010;
+ 188: code <= 4'b1001;
+ 189: code <= 4'bx100;
+ 190: code <= 4'b1000;
+ 191: code <= 4'b1001;
+ 192: code <= 4'bx101;
+ 193: code <= 4'bx100;
+ 194: code <= 4'b1001;
+ 195: code <= 4'bx011;
+ 196: code <= 4'b0000;
+ 197: code <= 4'bx011;
+ 198: code <= 4'b1000;
+ 199: code <= 4'b0001;
+ 200: code <= 4'b1001;
+ 201: code <= 4'bx110;
+ 202: code <= 4'bx100;
+ 203: code <= 4'bx100;
+ 204: code <= 4'b0010;
+ 205: code <= 4'b1000;
+ 206: code <= 4'b1000;
+ 207: code <= 4'b0001;
+ 208: code <= 4'b0000;
+ 209: code <= 4'b1001;
+ 210: code <= 4'bx111;
+ 211: code <= 4'bx101;
+ 212: code <= 4'bx110;
+ 213: code <= 4'bx110;
+ 214: code <= 4'bx101;
+ 215: code <= 4'b1001;
+ 216: code <= 4'bx011;
+ 217: code <= 4'bx011;
+ 218: code <= 4'bx100;
+ 219: code <= 4'bx100;
+ 220: code <= 4'bx110;
+ 221: code <= 4'b0001;
+ 222: code <= 4'b0010;
+ 223: code <= 4'b1000;
+ 224: code <= 4'bx100;
+ 225: code <= 4'bx111;
+ 226: code <= 4'bx101;
+ 227: code <= 4'bx110;
+ 228: code <= 4'bx100;
+ 229: code <= 4'b1000;
+ 230: code <= 4'b0010;
+ 231: code <= 4'bx011;
+ 232: code <= 4'bx011;
+ 233: code <= 4'bx111;
+ 234: code <= 4'b1000;
+ 235: code <= 4'bx110;
+ 236: code <= 4'bx111;
+ 237: code <= 4'b1000;
+ 238: code <= 4'bx011;
+ 239: code <= 4'b0001;
+ 240: code <= 4'bx110;
+ 241: code <= 4'bx101;
+ 242: code <= 4'b0010;
+ 243: code <= 4'bx111;
+ 244: code <= 4'b0001;
+ 245: code <= 4'b0010;
+ 246: code <= 4'b0000;
+ 247: code <= 4'b0001;
+ 248: code <= 4'b1001;
+ 249: code <= 4'b0000;
+ 250: code <= 4'b1001;
+ 251: code <= 4'b0001;
+ 252: code <= 4'bx100;
+ 253: code <= 4'bx101;
+ 254: code <= 4'bx110;
+ 255: code <= 4'bx100;
+ 256: code <= 4'b1000;
+ 257: code <= 4'bx101;
+ 258: code <= 4'bx110;
+ 259: code <= 4'bx110;
+ 260: code <= 4'b1001;
+ 261: code <= 4'b0010;
+ 262: code <= 4'bx011;
+ 263: code <= 4'bx100;
+ 264: code <= 4'bx110;
+ 265: code <= 4'b0000;
+ 266: code <= 4'bx011;
+ 267: code <= 4'bx100;
+ 268: code <= 4'b1000;
+ 269: code <= 4'bx110;
+ 270: code <= 4'b0001;
+ 271: code <= 4'b0000;
+ 272: code <= 4'bx100;
+ 273: code <= 4'bx101;
+ 274: code <= 4'bx100;
+ 275: code <= 4'bx011;
+ 276: code <= 4'b0010;
+ 277: code <= 4'bx110;
+ 278: code <= 4'bx110;
+ 279: code <= 4'bx100;
+ 280: code <= 4'b1000;
+ 281: code <= 4'b0010;
+ 282: code <= 4'b0001;
+ 283: code <= 4'bx011;
+ 284: code <= 4'bx011;
+ 285: code <= 4'b1001;
+ 286: code <= 4'bx011;
+ 287: code <= 4'bx110;
+ 288: code <= 4'b0000;
+ 289: code <= 4'bx111;
+ 290: code <= 4'b0010;
+ 291: code <= 4'bx110;
+ 292: code <= 4'b0000;
+ 293: code <= 4'b0010;
+ 294: code <= 4'bx100;
+ 295: code <= 4'b1001;
+ 296: code <= 4'b0001;
+ 297: code <= 4'bx100;
+ 298: code <= 4'b0001;
+ 299: code <= 4'b0010;
+ 300: code <= 4'bx111;
+ 301: code <= 4'bx011;
+ 302: code <= 4'bx111;
+ 303: code <= 4'b0010;
+ 304: code <= 4'bx100;
+ 305: code <= 4'bx101;
+ 306: code <= 4'b1000;
+ 307: code <= 4'bx111;
+ 308: code <= 4'b0000;
+ 309: code <= 4'b0000;
+ 310: code <= 4'bx110;
+ 311: code <= 4'bx110;
+ 312: code <= 4'b0000;
+ 313: code <= 4'bx110;
+ 314: code <= 4'bx011;
+ 315: code <= 4'b0001;
+ 316: code <= 4'bx101;
+ 317: code <= 4'bx101;
+ 318: code <= 4'b1000;
+ 319: code <= 4'b1000;
+ 320: code <= 4'b0001;
+ 321: code <= 4'bx111;
+ 322: code <= 4'bx100;
+ 323: code <= 4'b1000;
+ 324: code <= 4'b1000;
+ 325: code <= 4'b0001;
+ 326: code <= 4'bx101;
+ 327: code <= 4'b0010;
+ 328: code <= 4'b0000;
+ 329: code <= 4'b1001;
+ 330: code <= 4'b0010;
+ 331: code <= 4'b0000;
+ 332: code <= 4'b1001;
+ 333: code <= 4'bx110;
+ 334: code <= 4'b0010;
+ 335: code <= 4'b1000;
+ 336: code <= 4'b0010;
+ 337: code <= 4'b1001;
+ 338: code <= 4'b0010;
+ 339: code <= 4'bx101;
+ 340: code <= 4'bx100;
+ 341: code <= 4'b0000;
+ 342: code <= 4'b1001;
+ 343: code <= 4'b0001;
+ 344: code <= 4'bx111;
+ 345: code <= 4'b0001;
+ 346: code <= 4'bx101;
+ 347: code <= 4'bx011;
+ 348: code <= 4'bx110;
+ 349: code <= 4'bx100;
+ 350: code <= 4'bx011;
+ 351: code <= 4'bx110;
+ 352: code <= 4'bx111;
+ 353: code <= 4'b1000;
+ 354: code <= 4'b1001;
+ 355: code <= 4'b0010;
+ 356: code <= 4'bx101;
+ 357: code <= 4'b1001;
+ 358: code <= 4'b0000;
+ 359: code <= 4'bx011;
+ 360: code <= 4'bx110;
+ 361: code <= 4'b0000;
+ 362: code <= 4'b0000;
+ 363: code <= 4'b0001;
+ 364: code <= 4'b0001;
+ 365: code <= 4'bx011;
+ 366: code <= 4'bx011;
+ 367: code <= 4'b0000;
+ 368: code <= 4'bx101;
+ 369: code <= 4'bx011;
+ 370: code <= 4'b0000;
+ 371: code <= 4'bx101;
+ 372: code <= 4'bx100;
+ 373: code <= 4'b1000;
+ 374: code <= 4'b1000;
+ 375: code <= 4'b0010;
+ 376: code <= 4'b0000;
+ 377: code <= 4'bx100;
+ 378: code <= 4'bx110;
+ 379: code <= 4'bx110;
+ 380: code <= 4'bx101;
+ 381: code <= 4'b0010;
+ 382: code <= 4'b0001;
+ 383: code <= 4'bx011;
+ 384: code <= 4'b1000;
+ 385: code <= 4'bx100;
+ 386: code <= 4'b0001;
+ 387: code <= 4'bx100;
+ 388: code <= 4'bx110;
+ 389: code <= 4'b1001;
+ 390: code <= 4'bx101;
+ 391: code <= 4'b0001;
+ 392: code <= 4'b1001;
+ 393: code <= 4'bx100;
+ 394: code <= 4'b0001;
+ 395: code <= 4'bx101;
+ 396: code <= 4'b0001;
+ 397: code <= 4'b0001;
+ 398: code <= 4'bx110;
+ 399: code <= 4'b0000;
+ 400: code <= 4'b1001;
+ 401: code <= 4'bx100;
+ 402: code <= 4'bx011;
+ 403: code <= 4'bx011;
+ 404: code <= 4'b0000;
+ 405: code <= 4'bx101;
+ 406: code <= 4'bx111;
+ 407: code <= 4'b0010;
+ 408: code <= 4'bx111;
+ 409: code <= 4'b0000;
+ 410: code <= 4'bx011;
+ 411: code <= 4'bx110;
+ 412: code <= 4'bx101;
+ 413: code <= 4'bx111;
+ 414: code <= 4'bx101;
+ 415: code <= 4'b1001;
+ 416: code <= 4'bx101;
+ 417: code <= 4'b1001;
+ 418: code <= 4'b0001;
+ 419: code <= 4'b1001;
+ 420: code <= 4'bx101;
+ 421: code <= 4'bx011;
+ 422: code <= 4'b0000;
+ 423: code <= 4'b1001;
+ 424: code <= 4'b0010;
+ 425: code <= 4'b0001;
+ 426: code <= 4'b1000;
+ 427: code <= 4'bx110;
+ 428: code <= 4'b0001;
+ 429: code <= 4'b0001;
+ 430: code <= 4'bx111;
+ 431: code <= 4'bx011;
+ 432: code <= 4'b1000;
+ 433: code <= 4'b0001;
+ 434: code <= 4'b1001;
+ 435: code <= 4'bx011;
+ 436: code <= 4'b0010;
+ 437: code <= 4'bx110;
+ 438: code <= 4'b0001;
+ 439: code <= 4'b0001;
+ 440: code <= 4'bx111;
+ 441: code <= 4'b1001;
+ 442: code <= 4'bx011;
+ 443: code <= 4'b0001;
+ 444: code <= 4'b0000;
+ 445: code <= 4'bx101;
+ 446: code <= 4'b0001;
+ 447: code <= 4'b0001;
+ 448: code <= 4'b1000;
+ 449: code <= 4'bx101;
+ 450: code <= 4'bx100;
+ 451: code <= 4'b1000;
+ 452: code <= 4'b0000;
+ 453: code <= 4'bx111;
+ 454: code <= 4'bx100;
+ 455: code <= 4'bx100;
+ 456: code <= 4'bx110;
+ 457: code <= 4'b0010;
+ 458: code <= 4'bx011;
+ 459: code <= 4'bx111;
+ 460: code <= 4'b1001;
+ 461: code <= 4'b1001;
+ 462: code <= 4'bx110;
+ 463: code <= 4'b0010;
+ 464: code <= 4'bx111;
+ 465: code <= 4'bx100;
+ 466: code <= 4'b1001;
+ 467: code <= 4'bx101;
+ 468: code <= 4'bx110;
+ 469: code <= 4'bx111;
+ 470: code <= 4'bx011;
+ 471: code <= 4'bx101;
+ 472: code <= 4'b0001;
+ 473: code <= 4'b1000;
+ 474: code <= 4'b1000;
+ 475: code <= 4'bx101;
+ 476: code <= 4'bx111;
+ 477: code <= 4'bx101;
+ 478: code <= 4'b0010;
+ 479: code <= 4'bx111;
+ 480: code <= 4'b0010;
+ 481: code <= 4'bx100;
+ 482: code <= 4'b1000;
+ 483: code <= 4'b1001;
+ 484: code <= 4'b0001;
+ 485: code <= 4'b0010;
+ 486: code <= 4'b0010;
+ 487: code <= 4'bx111;
+ 488: code <= 4'b1001;
+ 489: code <= 4'bx011;
+ 490: code <= 4'b1000;
+ 491: code <= 4'b0001;
+ 492: code <= 4'b1000;
+ 493: code <= 4'bx011;
+ 494: code <= 4'b0000;
+ 495: code <= 4'b0001;
+ 496: code <= 4'b0001;
+ 497: code <= 4'b1001;
+ 498: code <= 4'bx100;
+ 499: code <= 4'b1001;
+ 500: code <= 4'b0001;
+ 501: code <= 4'b0010;
+ 502: code <= 4'b1001;
+ 503: code <= 4'b1000;
+ 504: code <= 4'bx011;
+ 505: code <= 4'bx011;
+ 506: code <= 4'bx110;
+ 507: code <= 4'bx111;
+ 508: code <= 4'bx011;
+ 509: code <= 4'bx011;
+ 510: code <= 4'bx110;
+ 511: code <= 4'b0010;
+ 512: code <= 4'bx100;
+ 513: code <= 4'bx100;
+ 514: code <= 4'b0000;
+ 515: code <= 4'bx110;
+ 516: code <= 4'bx101;
+ 517: code <= 4'bx110;
+ 518: code <= 4'bx110;
+ 519: code <= 4'bx100;
+ 520: code <= 4'bx011;
+ 521: code <= 4'b0000;
+ 522: code <= 4'b1000;
+ 523: code <= 4'bx110;
+ 524: code <= 4'b0000;
+ 525: code <= 4'b0010;
+ 526: code <= 4'b0001;
+ 527: code <= 4'bx011;
+ 528: code <= 4'b1001;
+ 529: code <= 4'bx100;
+ 530: code <= 4'b1001;
+ 531: code <= 4'bx100;
+ 532: code <= 4'bx110;
+ 533: code <= 4'bx011;
+ 534: code <= 4'b1001;
+ 535: code <= 4'bx101;
+ 536: code <= 4'b0010;
+ 537: code <= 4'b0010;
+ 538: code <= 4'bx100;
+ 539: code <= 4'bx111;
+ 540: code <= 4'bx011;
+ 541: code <= 4'bx111;
+ 542: code <= 4'b0001;
+ 543: code <= 4'b1001;
+ 544: code <= 4'b0000;
+ 545: code <= 4'bx111;
+ 546: code <= 4'b0000;
+ 547: code <= 4'b0010;
+ 548: code <= 4'b0001;
+ 549: code <= 4'bx111;
+ 550: code <= 4'b1001;
+ 551: code <= 4'b1000;
+ 552: code <= 4'bx110;
+ 553: code <= 4'b0000;
+ 554: code <= 4'b1001;
+ 555: code <= 4'bx100;
+ 556: code <= 4'bx011;
+ 557: code <= 4'bx111;
+ 558: code <= 4'b0000;
+ 559: code <= 4'b0010;
+ 560: code <= 4'bx111;
+ 561: code <= 4'bx111;
+ 562: code <= 4'b0000;
+ 563: code <= 4'bx101;
+ 564: code <= 4'bx011;
+ 565: code <= 4'b1001;
+ 566: code <= 4'b0010;
+ 567: code <= 4'b0001;
+ 568: code <= 4'bx111;
+ 569: code <= 4'b0001;
+ 570: code <= 4'bx111;
+ 571: code <= 4'bx110;
+ 572: code <= 4'b0010;
+ 573: code <= 4'b1001;
+ 574: code <= 4'bx011;
+ 575: code <= 4'b0001;
+ 576: code <= 4'bx111;
+ 577: code <= 4'bx110;
+ 578: code <= 4'bx111;
+ 579: code <= 4'bx101;
+ 580: code <= 4'b0010;
+ 581: code <= 4'bx011;
+ 582: code <= 4'b1000;
+ 583: code <= 4'bx100;
+ 584: code <= 4'bx110;
+ 585: code <= 4'bx111;
+ 586: code <= 4'bx100;
+ 587: code <= 4'b1000;
+ 588: code <= 4'b0001;
+ 589: code <= 4'b1000;
+ 590: code <= 4'bx100;
+ 591: code <= 4'bx110;
+ 592: code <= 4'bx111;
+ 593: code <= 4'bx110;
+ 594: code <= 4'bx110;
+ 595: code <= 4'b1001;
+ 596: code <= 4'bx100;
+ 597: code <= 4'b0000;
+ 598: code <= 4'bx101;
+ 599: code <= 4'b0001;
+ 600: code <= 4'bx011;
+ 601: code <= 4'b0010;
+ 602: code <= 4'b0000;
+ 603: code <= 4'b0000;
+ 604: code <= 4'b0000;
+ 605: code <= 4'bx101;
+ 606: code <= 4'bx110;
+ 607: code <= 4'b1000;
+ 608: code <= 4'b0001;
+ 609: code <= 4'b0010;
+ 610: code <= 4'bx111;
+ 611: code <= 4'b0001;
+ 612: code <= 4'bx100;
+ 613: code <= 4'bx101;
+ 614: code <= 4'b0010;
+ 615: code <= 4'bx110;
+ 616: code <= 4'bx011;
+ 617: code <= 4'bx101;
+ 618: code <= 4'bx110;
+ 619: code <= 4'b0000;
+ 620: code <= 4'b1000;
+ 621: code <= 4'b0010;
+ 622: code <= 4'bx111;
+ 623: code <= 4'bx111;
+ 624: code <= 4'b1000;
+ 625: code <= 4'bx101;
+ 626: code <= 4'bx111;
+ 627: code <= 4'bx111;
+ 628: code <= 4'b0001;
+ 629: code <= 4'bx011;
+ 630: code <= 4'bx100;
+ 631: code <= 4'b0010;
+ 632: code <= 4'bx111;
+ 633: code <= 4'bx101;
+ 634: code <= 4'bx111;
+ 635: code <= 4'bx111;
+ 636: code <= 4'b1000;
+ 637: code <= 4'b1001;
+ 638: code <= 4'bx110;
+ 639: code <= 4'b0000;
+ 640: code <= 4'b1001;
+ 641: code <= 4'b0001;
+ 642: code <= 4'bx111;
+ 643: code <= 4'bx011;
+ 644: code <= 4'bx110;
+ 645: code <= 4'bx011;
+ 646: code <= 4'bx111;
+ 647: code <= 4'b0001;
+ 648: code <= 4'bx111;
+ 649: code <= 4'b1000;
+ 650: code <= 4'bx111;
+ 651: code <= 4'b0010;
+ 652: code <= 4'b0001;
+ 653: code <= 4'bx100;
+ 654: code <= 4'bx110;
+ 655: code <= 4'b1000;
+ 656: code <= 4'bx100;
+ 657: code <= 4'bx100;
+ 658: code <= 4'b0000;
+ 659: code <= 4'b1001;
+ 660: code <= 4'b0000;
+ 661: code <= 4'b0001;
+ 662: code <= 4'b0010;
+ 663: code <= 4'b0010;
+ 664: code <= 4'bx100;
+ 665: code <= 4'b1001;
+ 666: code <= 4'bx101;
+ 667: code <= 4'bx011;
+ 668: code <= 4'bx100;
+ 669: code <= 4'bx011;
+ 670: code <= 4'b0000;
+ 671: code <= 4'b0001;
+ 672: code <= 4'bx100;
+ 673: code <= 4'bx110;
+ 674: code <= 4'bx101;
+ 675: code <= 4'bx100;
+ 676: code <= 4'b1001;
+ 677: code <= 4'bx101;
+ 678: code <= 4'b1000;
+ 679: code <= 4'bx101;
+ 680: code <= 4'bx011;
+ 681: code <= 4'bx111;
+ 682: code <= 4'b0001;
+ 683: code <= 4'b0000;
+ 684: code <= 4'bx101;
+ 685: code <= 4'b0000;
+ 686: code <= 4'bx111;
+ 687: code <= 4'b1001;
+ 688: code <= 4'b0010;
+ 689: code <= 4'b0010;
+ 690: code <= 4'bx111;
+ 691: code <= 4'b1001;
+ 692: code <= 4'bx110;
+ 693: code <= 4'b1000;
+ 694: code <= 4'b1001;
+ 695: code <= 4'b0010;
+ 696: code <= 4'bx101;
+ 697: code <= 4'b1000;
+ 698: code <= 4'b1001;
+ 699: code <= 4'b0010;
+ 700: code <= 4'bx011;
+ 701: code <= 4'bx101;
+ 702: code <= 4'bx100;
+ 703: code <= 4'b0010;
+ 704: code <= 4'b0000;
+ 705: code <= 4'b0001;
+ 706: code <= 4'b1001;
+ 707: code <= 4'b1001;
+ 708: code <= 4'bx101;
+ 709: code <= 4'bx110;
+ 710: code <= 4'b0001;
+ 711: code <= 4'b0001;
+ 712: code <= 4'b0010;
+ 713: code <= 4'b0001;
+ 714: code <= 4'b0010;
+ 715: code <= 4'b1001;
+ 716: code <= 4'b0000;
+ 717: code <= 4'b0010;
+ 718: code <= 4'b0001;
+ 719: code <= 4'b1001;
+ 720: code <= 4'bx110;
+ 721: code <= 4'b0000;
+ 722: code <= 4'b1000;
+ 723: code <= 4'bx110;
+ 724: code <= 4'bx100;
+ 725: code <= 4'b0000;
+ 726: code <= 4'bx011;
+ 727: code <= 4'bx100;
+ 728: code <= 4'bx100;
+ 729: code <= 4'b0001;
+ 730: code <= 4'b1000;
+ 731: code <= 4'b0001;
+ 732: code <= 4'bx101;
+ 733: code <= 4'b1001;
+ 734: code <= 4'b1000;
+ 735: code <= 4'b0001;
+ 736: code <= 4'bx011;
+ 737: code <= 4'bx110;
+ 738: code <= 4'b0010;
+ 739: code <= 4'b1001;
+ 740: code <= 4'bx111;
+ 741: code <= 4'bx111;
+ 742: code <= 4'bx100;
+ 743: code <= 4'bx111;
+ 744: code <= 4'bx111;
+ 745: code <= 4'b0001;
+ 746: code <= 4'bx011;
+ 747: code <= 4'b0000;
+ 748: code <= 4'b1001;
+ 749: code <= 4'b1001;
+ 750: code <= 4'bx110;
+ 751: code <= 4'b0000;
+ 752: code <= 4'bx101;
+ 753: code <= 4'b0001;
+ 754: code <= 4'b1000;
+ 755: code <= 4'bx111;
+ 756: code <= 4'b0000;
+ 757: code <= 4'bx111;
+ 758: code <= 4'b0010;
+ 759: code <= 4'b0001;
+ 760: code <= 4'b0001;
+ 761: code <= 4'bx011;
+ 762: code <= 4'bx100;
+ 763: code <= 4'b1001;
+ 764: code <= 4'b1001;
+ 765: code <= 4'b1001;
+ 766: code <= 4'b1001;
+ 767: code <= 4'b1001;
+ 768: code <= 4'b1001;
+ 769: code <= 4'b1000;
+ 770: code <= 4'bx011;
+ 771: code <= 4'bx111;
+ 772: code <= 4'b0010;
+ 773: code <= 4'b1001;
+ 774: code <= 4'bx111;
+ 775: code <= 4'b1000;
+ 776: code <= 4'b0000;
+ 777: code <= 4'bx100;
+ 778: code <= 4'b1001;
+ 779: code <= 4'b1001;
+ 780: code <= 4'bx101;
+ 781: code <= 4'b0001;
+ 782: code <= 4'b0000;
+ 783: code <= 4'bx101;
+ 784: code <= 4'b1001;
+ 785: code <= 4'bx111;
+ 786: code <= 4'bx011;
+ 787: code <= 4'b0001;
+ 788: code <= 4'bx111;
+ 789: code <= 4'bx011;
+ 790: code <= 4'b0010;
+ 791: code <= 4'b1000;
+ 792: code <= 4'b0001;
+ 793: code <= 4'bx110;
+ 794: code <= 4'b0000;
+ 795: code <= 4'b1001;
+ 796: code <= 4'bx110;
+ 797: code <= 4'bx011;
+ 798: code <= 4'b0001;
+ 799: code <= 4'b1000;
+ 800: code <= 4'bx101;
+ 801: code <= 4'b1001;
+ 802: code <= 4'bx101;
+ 803: code <= 4'b0000;
+ 804: code <= 4'b0010;
+ 805: code <= 4'bx100;
+ 806: code <= 4'bx100;
+ 807: code <= 4'bx101;
+ 808: code <= 4'b1001;
+ 809: code <= 4'bx100;
+ 810: code <= 4'bx101;
+ 811: code <= 4'bx101;
+ 812: code <= 4'bx011;
+ 813: code <= 4'bx100;
+ 814: code <= 4'bx110;
+ 815: code <= 4'b1001;
+ 816: code <= 4'b0000;
+ 817: code <= 4'b1000;
+ 818: code <= 4'bx011;
+ 819: code <= 4'b0000;
+ 820: code <= 4'b0010;
+ 821: code <= 4'bx110;
+ 822: code <= 4'bx100;
+ 823: code <= 4'b0010;
+ 824: code <= 4'bx101;
+ 825: code <= 4'b0010;
+ 826: code <= 4'b0010;
+ 827: code <= 4'bx011;
+ 828: code <= 4'b0000;
+ 829: code <= 4'b1000;
+ 830: code <= 4'b0010;
+ 831: code <= 4'bx101;
+ 832: code <= 4'bx011;
+ 833: code <= 4'bx011;
+ 834: code <= 4'bx100;
+ 835: code <= 4'bx100;
+ 836: code <= 4'bx110;
+ 837: code <= 4'b1000;
+ 838: code <= 4'bx101;
+ 839: code <= 4'b0000;
+ 840: code <= 4'bx011;
+ 841: code <= 4'bx101;
+ 842: code <= 4'b0010;
+ 843: code <= 4'bx110;
+ 844: code <= 4'b0001;
+ 845: code <= 4'b1001;
+ 846: code <= 4'bx011;
+ 847: code <= 4'b0001;
+ 848: code <= 4'b0001;
+ 849: code <= 4'b1000;
+ 850: code <= 4'b1000;
+ 851: code <= 4'b0001;
+ 852: code <= 4'bx111;
+ 853: code <= 4'b0001;
+ 854: code <= 4'b0000;
+ 855: code <= 4'b0001;
+ 856: code <= 4'b0000;
+ 857: code <= 4'b0000;
+ 858: code <= 4'b0000;
+ 859: code <= 4'bx011;
+ 860: code <= 4'b0001;
+ 861: code <= 4'bx011;
+ 862: code <= 4'bx111;
+ 863: code <= 4'b1000;
+ 864: code <= 4'bx011;
+ 865: code <= 4'b1000;
+ 866: code <= 4'bx111;
+ 867: code <= 4'bx101;
+ 868: code <= 4'b0010;
+ 869: code <= 4'b1000;
+ 870: code <= 4'b1000;
+ 871: code <= 4'bx110;
+ 872: code <= 4'bx101;
+ 873: code <= 4'b1000;
+ 874: code <= 4'bx111;
+ 875: code <= 4'bx101;
+ 876: code <= 4'bx011;
+ 877: code <= 4'bx011;
+ 878: code <= 4'b0010;
+ 879: code <= 4'b0000;
+ 880: code <= 4'b1000;
+ 881: code <= 4'bx011;
+ 882: code <= 4'b1000;
+ 883: code <= 4'b0001;
+ 884: code <= 4'bx100;
+ 885: code <= 4'b0010;
+ 886: code <= 4'b0000;
+ 887: code <= 4'bx110;
+ 888: code <= 4'b0001;
+ 889: code <= 4'bx111;
+ 890: code <= 4'b0001;
+ 891: code <= 4'bx111;
+ 892: code <= 4'bx111;
+ 893: code <= 4'bx110;
+ 894: code <= 4'bx110;
+ 895: code <= 4'b1001;
+ 896: code <= 4'b0001;
+ 897: code <= 4'bx100;
+ 898: code <= 4'bx111;
+ 899: code <= 4'bx011;
+ 900: code <= 4'b0000;
+ 901: code <= 4'bx011;
+ 902: code <= 4'bx101;
+ 903: code <= 4'b1001;
+ 904: code <= 4'b1000;
+ 905: code <= 4'b0010;
+ 906: code <= 4'bx101;
+ 907: code <= 4'bx011;
+ 908: code <= 4'bx100;
+ 909: code <= 4'b1001;
+ 910: code <= 4'b0000;
+ 911: code <= 4'bx100;
+ 912: code <= 4'b0010;
+ 913: code <= 4'b1000;
+ 914: code <= 4'bx111;
+ 915: code <= 4'bx101;
+ 916: code <= 4'bx101;
+ 917: code <= 4'bx100;
+ 918: code <= 4'bx110;
+ 919: code <= 4'b1000;
+ 920: code <= 4'bx111;
+ 921: code <= 4'bx011;
+ 922: code <= 4'b0001;
+ 923: code <= 4'b0001;
+ 924: code <= 4'bx101;
+ 925: code <= 4'b1001;
+ 926: code <= 4'bx101;
+ 927: code <= 4'bx110;
+ 928: code <= 4'b0010;
+ 929: code <= 4'b1000;
+ 930: code <= 4'bx110;
+ 931: code <= 4'bx011;
+ 932: code <= 4'b1000;
+ 933: code <= 4'b1000;
+ 934: code <= 4'b0010;
+ 935: code <= 4'bx011;
+ 936: code <= 4'bx101;
+ 937: code <= 4'bx011;
+ 938: code <= 4'bx111;
+ 939: code <= 4'b1000;
+ 940: code <= 4'bx111;
+ 941: code <= 4'bx101;
+ 942: code <= 4'b1001;
+ 943: code <= 4'bx011;
+ 944: code <= 4'bx111;
+ 945: code <= 4'bx101;
+ 946: code <= 4'b0001;
+ 947: code <= 4'b1001;
+ 948: code <= 4'bx101;
+ 949: code <= 4'bx111;
+ 950: code <= 4'bx111;
+ 951: code <= 4'b1000;
+ 952: code <= 4'b0001;
+ 953: code <= 4'b1000;
+ 954: code <= 4'bx101;
+ 955: code <= 4'bx111;
+ 956: code <= 4'bx111;
+ 957: code <= 4'b1000;
+ 958: code <= 4'b0000;
+ 959: code <= 4'bx101;
+ 960: code <= 4'bx011;
+ 961: code <= 4'b0010;
+ 962: code <= 4'b0001;
+ 963: code <= 4'bx111;
+ 964: code <= 4'b0001;
+ 965: code <= 4'b0010;
+ 966: code <= 4'b0010;
+ 967: code <= 4'bx110;
+ 968: code <= 4'b1000;
+ 969: code <= 4'b0000;
+ 970: code <= 4'bx110;
+ 971: code <= 4'bx110;
+ 972: code <= 4'b0001;
+ 973: code <= 4'bx011;
+ 974: code <= 4'b0000;
+ 975: code <= 4'b0000;
+ 976: code <= 4'b0001;
+ 977: code <= 4'b1001;
+ 978: code <= 4'b0010;
+ 979: code <= 4'bx111;
+ 980: code <= 4'b1000;
+ 981: code <= 4'bx111;
+ 982: code <= 4'bx110;
+ 983: code <= 4'bx110;
+ 984: code <= 4'b0001;
+ 985: code <= 4'b0001;
+ 986: code <= 4'b0001;
+ 987: code <= 4'b1001;
+ 988: code <= 4'bx101;
+ 989: code <= 4'b1001;
+ 990: code <= 4'b0000;
+ 991: code <= 4'b1001;
+ 992: code <= 4'b0010;
+ 993: code <= 4'b0001;
+ 994: code <= 4'bx110;
+ 995: code <= 4'bx100;
+ 996: code <= 4'b0010;
+ 997: code <= 4'b0000;
+ 998: code <= 4'b0001;
+ 999: code <= 4'b1001;
+ 1000: code <= 4'b1000;
+ 1001: code <= 4'b1001;
+ 1002: code <= 4'bx011;
+ 1003: code <= 4'b1000;
+ 1004: code <= 4'b0000;
+ 1005: code <= 4'b1001;
+ 1006: code <= 4'bx101;
+ 1007: code <= 4'b0010;
+ 1008: code <= 4'bx101;
+ 1009: code <= 4'bx111;
+ 1010: code <= 4'b0010;
+ 1011: code <= 4'b0000;
+ 1012: code <= 4'b0001;
+ 1013: code <= 4'b0000;
+ 1014: code <= 4'bx110;
+ 1015: code <= 4'bx101;
+ 1016: code <= 4'bx100;
+ 1017: code <= 4'b1000;
+ 1018: code <= 4'bx101;
+ 1019: code <= 4'b1000;
+ 1020: code <= 4'bx110;
+ 1021: code <= 4'bx011;
+ 1022: code <= 4'b0010;
+ 1023: code <= 4'bx111;
+ endcase
+ /* verilator lint_on CASEX */
+ end
+ end
+
+ decoder decoder(.code(code), .segments(io_out));
+
+endmodule
diff --git a/verilog/rtl/065_sqrt.v b/verilog/rtl/065_sqrt.v
new file mode 100644
index 0000000..91c4589
--- /dev/null
+++ b/verilog/rtl/065_sqrt.v
@@ -0,0 +1,128 @@
+// TinyTapeout Square Root Engine
+// Copyright (C) 2022 Davit Margarian
+
+`default_nettype none
+
+// Top level io for this module should stay the same to fit into the scan_wrapper.
+// The pin connections within the user_module are up to you,
+// although (if one is present) it is recommended to place a clock on io_in[0].
+// This allows use of the internal clock divider if you wish.
+module udxs_sqrt_top(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+
+ wire [10:0] result;
+ assign io_out = result[7:0];
+
+ udxs_sqrt sqrt_core(
+ .clk(io_in[0]),
+ .query({io_in[7:1], 4'b0}),
+ .result(result)
+ );
+
+endmodule
+
+
+// SQRT Iteration Unit
+// Copyright (C) 2022 Davit Margarian
+
+module udxs_sqrtiu (
+ input [10:0] prev_att,
+ input [10:0] prev_eps,
+ input [10:0] prev_res,
+
+ output [10:0] this_att,
+ output [10:0] this_eps,
+ output [10:0] this_res
+);
+
+ assign this_att = {1'b0, prev_att[10:1]};
+
+ wire [10:0] this_delta_term1_half;
+ wire [10:0] this_delta;
+ reg [3:0] this_att_msb;
+ wire [4:0] this_att_sq_exp;
+ wire [10:0] this_att_sq;
+
+ assign this_att_sq_exp = {this_att_msb, 1'b0};
+ assign this_att_sq = 11'b1 << this_att_sq_exp;
+
+ assign this_delta_term1_half = prev_res << this_att_msb;
+ assign this_delta = {this_delta_term1_half[9:0], 1'b0} + this_att_sq;
+
+ wire cond_met;
+ assign cond_met = this_delta <= prev_eps;
+ assign this_eps = cond_met ? prev_eps - this_delta : prev_eps;
+ assign this_res = cond_met ? prev_res | this_att : prev_res;
+
+ integer msb_idx;
+ always @* begin
+ this_att_msb = 0;
+
+ for (msb_idx=0; msb_idx < 11; msb_idx++) begin
+ if(this_att == (1 << msb_idx))
+ this_att_msb = msb_idx[3:0];
+ end
+
+ end
+
+endmodule
+
+// SQRT Control Logic
+// Copyright (C) 2022 Davit Margarian
+
+module udxs_sqrt(
+ input clk,
+ input [10:0] query,
+ output reg [10:0] result
+);
+
+ reg [10:0] att;
+ reg [10:0] eps;
+ reg [10:0] res;
+
+ wire [10:0] att_mid;
+ wire [10:0] res_mid;
+ wire [10:0] eps_mid;
+
+ wire [10:0] att_next;
+ wire [10:0] res_next;
+ wire [10:0] eps_next;
+
+ udxs_sqrtiu iteratorA(
+ .prev_att(att),
+ .prev_eps(eps),
+ .prev_res(res),
+ .this_att(att_mid),
+ .this_eps(eps_mid),
+ .this_res(res_mid)
+ );
+
+ udxs_sqrtiu iteratorB(
+ .prev_att(att_mid),
+ .prev_eps(eps_mid),
+ .prev_res(res_mid),
+ .this_att(att_next),
+ .this_eps(eps_next),
+ .this_res(res_next)
+ );
+
+ reg [1:0] iteration;
+
+ always @(posedge clk) begin
+ if (iteration != 3) begin
+ att <= att_next;
+ eps <= eps_next;
+ res <= res_next;
+ iteration <= iteration + 1;
+ end else begin
+ result <= res;
+ eps <= query;
+ att <= 1 << 6;
+ res <= 0;
+ iteration <= 0;
+ end
+ end
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/066_pwm_gen.v b/verilog/rtl/066_pwm_gen.v
new file mode 100644
index 0000000..81ddb25
--- /dev/null
+++ b/verilog/rtl/066_pwm_gen.v
@@ -0,0 +1,69 @@
+`default_nettype none
+
+module pwm_gen (
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+
+wire clk = io_in[0];
+wire reset = io_in[1];
+reg counter_state;
+reg [5:0] pwm_counter;
+reg [6:0] duty;
+reg pwm;
+assign io_out = {duty, pwm};
+
+ //upcounter which determines pwm period
+always @(posedge clk) begin
+ if (reset)
+ pwm_counter <= 0;
+ else
+ pwm_counter <= pwm_counter + 1;
+end
+ //duty state machine to determine countup or countdown
+always @(posedge clk) begin
+ if (reset) begin
+ counter_state = 0;
+ end else begin
+ case (counter_state)
+ 0:
+ if (duty == 8'b111110)
+ counter_state = 1;
+ else
+ counter_state = 0;
+ 1:
+ if (duty == 8'b000001)
+ counter_state = 0;
+ else
+ counter_state = 1;
+ endcase
+ end
+end
+ //generate duty
+always @(posedge clk) begin
+ if (reset) begin
+ duty <= 0;
+ end else begin
+ if (pwm_counter == 6'b000000) begin
+ if (counter_state == 0) begin
+ duty <= duty + 1;
+ end else if(counter_state == 1) begin
+ duty <= duty - 1;
+ end
+ end
+ end
+end
+ //generate pwm where duty determines it's duty cycle
+always @(posedge clk) begin
+ if(reset) begin
+ pwm <= 0;
+ end else begin
+ if (pwm_counter == 6'b000000) begin
+ pwm <= 1;
+ end else if (pwm_counter == duty[6:0]) begin
+ pwm <= 0;
+ end
+ end
+end
+
+endmodule
diff --git a/verilog/rtl/067_user_module_341164910646919762.v b/verilog/rtl/067_user_module_341164910646919762.v
new file mode 100644
index 0000000..8a57b27
--- /dev/null
+++ b/verilog/rtl/067_user_module_341164910646919762.v
@@ -0,0 +1,297 @@
+/* Custom verilog based on the template automatically generated from
+/* https://wokwi.com/projects/341164910646919762 */
+
+`ifdef SIM
+`define UNIT_DELAY #1
+`define FUNCTIONAL
+`define USE_POWER_PINS
+`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+`endif
+
+`default_nettype none
+
+module user_module_341164910646919762
+ (
+ input wire [7:0] io_in,
+ output wire [7:0] io_out
+ );
+ wire clk = io_in[0];
+ wire output_select = io_in[1];
+ wire gold_out;
+
+ gold_code_module_341164910646919762 gold_code_generator
+ (.clk(clk), .loadn(io_in[3]), .b_load({io_in[7:4], io_in[2:1]}),
+ .gold(gold_out));
+
+ wire [7:0] io_out_fibonacci;
+ wire fib_clk;
+ wire fib_rstn;
+
+ // Buffers to fix slew failures
+ sky130_fd_sc_hd__buf_2 fib_clk_buf
+ (.A(clk), .X(fib_clk),
+ .VPWR(1'b1), .VGND(1'b0));
+
+ sky130_fd_sc_hd__buf_2 fib_rstn_buf
+ (.A(io_in[2]), .X(fib_rstn),
+ .VPWR(1'b1), .VGND(1'b0));
+
+ fibonacci_module_341164910646919762 #(.DIGITS(7)) fibonacci_inst
+ (.clk(fib_clk), .rstn(fib_rstn), .io_out(io_out_fibonacci));
+
+ assign io_out[7] = output_select ? gold_out : io_out_fibonacci[7];
+ assign io_out[6:0] = io_out_fibonacci[6:0];
+endmodule // user_module_341164910646919762
+
+module gold_code_module_341164910646919762
+ (
+ input wire clk,
+ input wire loadn,
+ input wire [5:0] b_load,
+ output wire gold
+ );
+
+ reg [12:0] a;
+ reg [6:0] b_async;
+ reg [5:0] b_sync;
+ wire [12:0] b = {b_async, b_sync};
+
+ always @(posedge clk or negedge loadn) begin
+ a <= {a[0] ^ a[1] ^ a[3] ^ a[4], a[12:1]};
+ b_async <= {b[0] ^ b[4] ^ b[5] ^ b[7] ^ b[9] ^ b[10], b[12:7]};
+
+ if (!loadn) begin
+ a <= {1'b1, 12'b0};
+ b_async <= {1'b0, 1'b1, 5'b0};
+ end
+ end
+
+ always @(posedge clk) b_sync <= loadn ? b[6:1] : b_load;
+
+ assign gold = a[0] ^ b[0];
+endmodule // gold_code_module_341164910646919762
+
+module fibonacci_module_341164910646919762
+ #(
+ parameter DIGITS = 7
+ )
+ (
+ input wire clk,
+ input wire rstn,
+ output wire [7:0] io_out
+ );
+
+ wire [3:0] digit;
+ wire lsb_marker;
+
+ fibonacci_341164910646919762 #(.DIGITS(DIGITS)) fib
+ (.clk(clk), .rstn(rstn), .digit(digit),
+ .lsb_marker(lsb_marker));
+
+ wire [7:0] seven_segment_out;
+
+ seven_segment_341164910646919762 seven_segment_encoder
+ (.digit(digit), .dot(lsb_marker), .seven_segment(seven_segment_out));
+
+ assign io_out = clk ? seven_segment_out : 8'b0;
+endmodule // fibonacci_module_341164910646919762
+
+module fibonacci_341164910646919762
+ #(
+ parameter DIGITS = 7
+ )
+ (
+ input wire clk,
+ input wire rstn,
+ output wire [3:0] digit,
+ output wire lsb_marker
+ );
+
+ localparam WIDTH = 4 * DIGITS;
+
+ reg [WIDTH-1:0] a;
+ assign digit = a[3:0];
+ reg [WIDTH-1:0] b;
+ reg carry;
+
+ wire [3:0] digit_sum;
+ wire cout;
+
+ reg [DIGITS-1:0] lsb_control;
+ wire lsb_marker_prev;
+ assign lsb_marker_prev = lsb_control[DIGITS-1];
+ assign lsb_marker = lsb_control[0];
+
+ adder4_341164910646919762 adder
+ (.a(a[3:0]), .b(b[3:0]), .cin(carry),
+ .sum(digit_sum), .cout(cout));
+
+ always @(posedge clk or negedge rstn) begin
+ a <= {b[3:0], a[WIDTH-1:4]};
+ b <= {digit_sum, b[WIDTH-1:4]};
+ carry <= lsb_marker_prev ? 1'b0 : cout;
+ lsb_control <= {lsb_control[DIGITS-2:0], lsb_control[DIGITS-1]};
+
+ if (!rstn) begin
+ a <= 1'b0;
+ b <= 1'b1;
+ carry <= 1'b0;
+ lsb_control <= 1'b1;
+ end
+ end
+endmodule // fibonacci_341164910646919762
+
+module adder4_341164910646919762
+ (
+ input wire [3:0] a,
+ input wire [3:0] b,
+ input wire cin,
+ output wire [3:0] sum,
+ output wire cout
+ );
+
+ wire [3:0] adder_cin;
+ wire [3:0] adder_cout;
+ assign cout = adder_cout[3];
+ assign adder_cin = {adder_cout[2:0], cin};
+
+ sky130_fd_sc_hd__fa_1 adder [3:0]
+ (.A(a), .B(b), .CIN(adder_cin),
+ .COUT(adder_cout), .SUM(sum),
+ .VPWR(1'b1), .VGND(1'b0));
+endmodule // adder4_341164910646919762
+
+module seven_segment_341164910646919762
+ (
+ input wire [3:0] digit,
+ input wire dot,
+ output wire [7:0] seven_segment
+ );
+
+ reg up, mid, down, left_up,
+ left_down, right_up, right_down;
+ assign seven_segment = {dot, mid, left_up, left_down,
+ down, right_down, right_up, up};
+
+ always @(*) begin
+ up = 1'b0;
+ mid = 1'b0;
+ down = 1'b0;
+ left_up = 1'b0;
+ left_down = 1'b0;
+ right_up = 1'b0;
+ right_down = 1'b0;
+ case (digit)
+ 4'h0: begin
+ up = 1'b1;
+ down = 1'b1;
+ left_up = 1'b1;
+ left_down = 1'b1;
+ right_up = 1'b1;
+ right_down = 1'b1;
+ end
+ 4'h1: begin
+ right_up = 1'b1;
+ right_down = 1'b1;
+ end
+ 4'h2: begin
+ up = 1'b1;
+ mid = 1'b1;
+ down = 1'b1;
+ right_up = 1'b1;
+ left_down = 1'b1;
+ end
+ 4'h3: begin
+ up = 1'b1;
+ mid = 1'b1;
+ down = 1'b1;
+ right_up = 1'b1;
+ right_down = 1'b1;
+ end
+ 4'h4: begin
+ left_up = 1'b1;
+ right_up = 1'b1;
+ mid = 1'b1;
+ right_down = 1'b1;
+ end
+ 4'h5: begin
+ up = 1'b1;
+ mid = 1'b1;
+ down = 1'b1;
+ left_up = 1'b1;
+ right_down = 1'b1;
+ end
+ 4'h6: begin
+ up = 1'b1;
+ mid = 1'b1;
+ down = 1'b1;
+ left_up = 1'b1;
+ left_down = 1'b1;
+ right_down = 1'b1;
+ end
+ 4'h7: begin
+ up = 1'b1;
+ right_up = 1'b1;
+ right_down = 1'b1;
+ end
+ 4'h8: begin
+ up = 1'b1;
+ mid = 1'b1;
+ down = 1'b1;
+ left_up = 1'b1;
+ left_down = 1'b1;
+ right_up = 1'b1;
+ right_down = 1'b1;
+ end
+ 4'h9: begin
+ up = 1'b1;
+ mid = 1'b1;
+ left_up = 1'b1;
+ right_up = 1'b1;
+ right_down = 1'b1;
+ end
+ 4'ha: begin
+ up = 1'b1;
+ mid = 1'b1;
+ left_up = 1'b1;
+ left_down = 1'b1;
+ right_up = 1'b1;
+ right_down = 1'b1;
+ end
+ 4'hb: begin
+ mid = 1'b1;
+ down = 1'b1;
+ left_up = 1'b1;
+ left_down = 1'b1;
+ right_down = 1'b1;
+ end
+ 4'hc: begin
+ up = 1'b1;
+ down = 1'b1;
+ left_up = 1'b1;
+ left_down = 1'b1;
+ end
+ 4'hd: begin
+ mid = 1'b1;
+ down = 1'b1;
+ left_down = 1'b1;
+ right_up = 1'b1;
+ right_down = 1'b1;
+ end
+ 4'he: begin
+ up = 1'b1;
+ mid = 1'b1;
+ down = 1'b1;
+ left_up = 1'b1;
+ left_down = 1'b1;
+ end
+ 4'hf: begin
+ up = 1'b1;
+ mid = 1'b1;
+ left_up = 1'b1;
+ left_down = 1'b1;
+ end
+ endcase // case (digit)
+ end // always @ (*)
+endmodule // seven_segment_341164910646919762
diff --git a/verilog/rtl/069_navray_top.sv b/verilog/rtl/069_navray_top.sv
new file mode 100644
index 0000000..fa8f8d2
--- /dev/null
+++ b/verilog/rtl/069_navray_top.sv
@@ -0,0 +1,45 @@
+// Title: Top-level wrapper in SystemVerilog
+// File: navray_top.sv
+// Author: Wallace Everest
+// Date: 23-NOV-2022
+// URL: https://github.com/navray/tt02-square-root
+//
+// Description:
+// The square-root of an unsigned 7-bit input is displayed on a 7-segment output.
+// The decimal point is unused.
+// Pipeline delay is 5 clocks.
+// Implementation:
+// TinyTapeout-02 constraints identify io_in[0] as a clock tree.
+// FPGA synthesis reports 46 flip-flops
+// Stye Guide:
+// https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md
+
+`default_nettype none
+
+localparam K_WIDTH = 8; // size must be even
+
+module navray_top (
+ input wire [7:0] io_in,
+ output wire [7:0] io_out
+);
+ logic clk;
+ logic [K_WIDTH-1:0] data_in;
+ logic [K_WIDTH/2-1:0] sqrt_val;
+
+ assign clk = io_in[0];
+ assign data_in = {1'b0, io_in[7:1]};
+
+ sqrt #(
+ .G_WIDTH(K_WIDTH)
+ ) sqrt_inst (
+ .clk (clk),
+ .data_in (data_in),
+ .data_out(sqrt_val)
+ );
+
+ seg7 seg7_inst (
+ .clk (clk),
+ .data_in (sqrt_val),
+ .segments(io_out)
+ );
+endmodule
diff --git a/verilog/rtl/071_pwm.v b/verilog/rtl/071_pwm.v
new file mode 100644
index 0000000..6e43451
--- /dev/null
+++ b/verilog/rtl/071_pwm.v
@@ -0,0 +1,139 @@
+`default_nettype none
+
+module krasin_tt02_verilog_spi_7_channel_pwm_driver (
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+
+ wire clk = io_in[0];
+ wire reset = io_in[1];
+ wire sclk = io_in[2];
+ wire cs = io_in[3];
+ wire mosi = io_in[4];
+
+ wire [6:0] pwm_out;
+ assign io_out[6:0] = pwm_out;
+ wire miso;
+ assign io_out[7] = miso;
+
+ // Previous value of sclk.
+ // This is to track SPI clock transitions within the main clock trigger.
+ reg prev_sclk;
+ // SPI counter that tracks 8 bit.
+ reg [2:0] spi_counter;
+ // is_writing is set if we received a write command.
+ reg is_writing;
+ reg is_reading;
+ reg [2:0] cur_addr;
+
+ // Buffer from mosi.
+ reg [7:0] in_buf;
+ // Buffer for miso.
+ reg [7:0] out_buf;
+
+ // out_buf is advanced on each falling sclk.
+ assign miso = out_buf[7];
+
+ // 8-bit PWM counter that goes from 0 to 254.
+ reg [7:0] counter;
+
+ // PWM levels for each channel.
+ // 0 means always off.
+ // 1 means that PWM will be on for just 1 clock cycle and then off for the other 254, giving 1/255 on average.
+ // 254 means 254/255 on.
+ // 255 means always on.
+ reg [7:0] pwm_level[6:0];
+
+ function is_on(input [7:0] level, input[7:0] counter);
+ begin
+ is_on = (counter < level);
+ end
+ endfunction // is_on
+
+ assign pwm_out[0] = is_on(pwm_level[0], counter);
+ assign pwm_out[1] = is_on(pwm_level[1], counter);
+ assign pwm_out[2] = is_on(pwm_level[2], counter);
+ assign pwm_out[3] = is_on(pwm_level[3], counter);
+ assign pwm_out[4] = is_on(pwm_level[4], counter);
+ assign pwm_out[5] = is_on(pwm_level[5], counter);
+ assign pwm_out[6] = is_on(pwm_level[6], counter);
+
+ // external clock is 1000Hz.
+ // PWM logic.
+ always @(posedge clk) begin
+ // if reset, set counter and pwm levels to 0
+ if (reset) begin
+ counter <= 0;
+ pwm_level[0] <= 0;
+ pwm_level[1] <= 0;
+ pwm_level[2] <= 0;
+ pwm_level[3] <= 0;
+ pwm_level[4] <= 0;
+ pwm_level[5] <= 0;
+ pwm_level[6] <= 0;
+ end else begin // if (reset)
+ if (counter == 254) begin
+ // Roll over.
+ counter <= 0;
+ end else begin
+ // increment counter
+ counter <= counter + 1'b1;
+ end
+ end // if (reset)
+
+ // SPI reset logic.
+ if (reset || cs) begin
+ // The chip is not selected or we are being reset. Reset all SPI registers.
+ in_buf <= 0;
+ out_buf <= 0;
+ prev_sclk <= 0;
+ spi_counter <= 0;
+ is_writing <= 0;
+ is_reading <= 0;
+ cur_addr <= 0;
+ end // if (reset || cs)
+
+ // regular SPI logic.
+ if (~reset && ~cs && (prev_sclk != sclk)) begin
+ // The chip is selected and the SPI clock changed.
+ // On rising edge we read from mosi, on falling edge, we write to miso.
+ if (sclk) begin
+ // Rising SCLK edge: reading from mosi.
+ in_buf <= (in_buf << 1) | mosi;
+ spi_counter <= spi_counter + 1'b1;
+ end else begin // if (sclk)
+ // Falling SCLK edge
+ if ((spi_counter == 0) && is_writing) begin
+ // Writing. We saved the cur_addr after reading the first byte.
+ if (cur_addr <= 6) begin
+ pwm_level[cur_addr] <= in_buf;
+ end
+ is_writing <= 0;
+ is_reading <= 1;
+ end // if ((spi_counter == 0) && is_writing
+ if ((spi_counter == 0) && ~is_writing) begin
+ if (in_buf[7]) begin
+ // We're writing, but the value will come as the next byte.
+ is_writing <= 1;
+ end else begin
+ is_reading <= 1;
+ end
+ cur_addr <= in_buf[2:0];
+ end // ((spi_counter == 0) && ~is_writing)
+ if ((spi_counter == 1) && is_reading) begin
+ if (cur_addr <= 6) begin
+ out_buf <= pwm_level[cur_addr];
+ end else begin
+ out_buf <= 0;
+ end
+ is_reading <= 0;
+ cur_addr <= 0;
+ end else begin // if ((spi_counter == 1) && is_reading)
+ // Advancing out_buf, so that miso sees a new value.
+ out_buf <= out_buf << 1;
+ end
+ end
+ prev_sclk <= sclk;
+ end // if (~reset && ~cs && (prev_sclk != sclk))
+ end // always @ (posedge clk)
+endmodule
diff --git a/verilog/rtl/072_hex_sr.v b/verilog/rtl/072_hex_sr.v
new file mode 100644
index 0000000..e66feeb
--- /dev/null
+++ b/verilog/rtl/072_hex_sr.v
@@ -0,0 +1,31 @@
+// Hex shift register
+// Copyright 2022 Eric Smith <spacewar@gmail.com>
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+module hex_sr #( parameter LENGTH = 40 ) (
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+
+ wire clk;
+ wire recirc;
+ wire [5:0] data_in;
+
+ wire [5:0] data_out;
+
+ assign clk = io_in[0];
+ assign recirc = io_in[1];
+ assign data_in = io_in[7:2];
+
+ assign io_out[7:2] = data_out;
+ assign io_out[1:0] = 2'b0;
+
+ genvar i;
+ generate
+ for (i = 0; i < 6; i = i + 1)
+ sr_recirc #(.LENGTH(LENGTH)) sr0(clk, recirc, data_in[i], data_out[i]);
+ endgenerate
+
+endmodule
diff --git a/verilog/rtl/073_speed_test.v b/verilog/rtl/073_speed_test.v
new file mode 100644
index 0000000..8510d6b
--- /dev/null
+++ b/verilog/rtl/073_speed_test.v
@@ -0,0 +1,209 @@
+`timescale 1ns/10ps
+
+//`define COCOTB_SIM
+
+module rdffe(input clk,d,en,rst, output q);
+ `ifdef COCOTB_SIM
+ reg rq;
+ assign #0.1 q = rq;
+ always @(posedge clk or posedge rst)
+ rq <= rst ? 1'b0 : ( en ? d : q);
+ `else
+ wire b;
+ assign b = en ? d : q;
+ sky130_fd_sc_hd__dfrtp_4 dfrtp(
+ .D(b),
+ .RESET_B(~rst),
+ .CLK(clk),
+ .Q(q)
+ );
+ `endif
+endmodule
+
+module sdffe(input clk,d,en,pre, output q);
+ `ifdef COCOTB_SIM
+ reg rq;
+ assign #0.1 q = rq;
+ always @(posedge clk or posedge pre)
+ rq <= pre ? 1'b1 : ( en ? d : q);
+ `else
+ wire b;
+ assign b = en ? d : q;
+ sky130_fd_sc_hd__dfstp_4 dfstp(
+ .D(b),
+ .SET_B(~pre),
+ .CLK(clk),
+ .Q(q)
+ );
+ `endif
+endmodule
+
+module inv_with_delay(input A,output Y);
+ `ifdef COCOTB_SIM
+ assign #0.02 Y = ~A; // pick a fairly quick delay from the tt_025C_1v80 liberty file
+ // the actualy delay per stage is going to be slower
+ `else
+ sky130_fd_sc_hd__inv_2 inv(.A(A),.Y(Y));
+ `endif
+endmodule
+
+module nand2_with_delay(input A,input B,output Y);
+ `ifdef COCOTB_SIM
+ assign #0.05 Y = ~(A & B);
+ `else
+ sky130_fd_sc_hd__nand2_2 nand2(.A(A),.B(B),.Y(Y));
+ `endif
+endmodule
+
+module ring_osc(input nrst,output osc);
+ // We count for 1 scan_clk period which expected at 166uS (6KHz).
+ // If the delay of one inverter is 20ps and the ring is 150 inverters long,
+ // then the ring period is 6nS (2*150inv*20pS/inv)
+ // This is 166MHz so expect a count of 166*166 nominally.
+ // For more time resolution make scan_clk slower but that requires more
+ // counter depth.
+ // scan clk slowing can be done externally to the TT IC or with the clk div.
+
+ localparam NUM_INVERTERS = 150; // must be an even number
+
+ // setup loop of inverters
+ // http://svn.clairexen.net/handicraft/2015/ringosc/ringosc.v
+ wire [NUM_INVERTERS-1:0] delay_in, delay_out;
+ wire osc_out;
+ inv_with_delay idelay [NUM_INVERTERS-1:0] (
+ .A(delay_in),
+ .Y(delay_out)
+ );
+ assign delay_in = {delay_out[NUM_INVERTERS-2:0], osc_out};
+ nand2_with_delay nand2_with_delay(.A(nrst),.B(delay_out[NUM_INVERTERS-1]),.Y(osc_out));
+ assign osc = osc_out;
+endmodule
+
+module ring_with_counter #(parameter WIDTH=24) (input nrst, ring_en, count_en, output [WIDTH-1:0] count);
+
+ wire [WIDTH:0] value;
+ wire rst,count_en_s0,count_en_s1,osc,nosc_buf;
+ genvar i;
+
+ ring_osc ring_osc(.nrst(ring_en),.osc(osc));
+
+ inv_with_delay inv_r(.A(nrst),.Y(rst));
+
+ // logic in this module should minimize loading the ring, so buffer the ring output
+ inv_with_delay inv_b(.A(osc),.Y(nosc_buf));
+
+ // synchronize the counter enable time to the ring oscillator frequency
+ // so metastability doesnt corrupt the count. note: we count on the ring frequency domain
+
+ rdffe ds0(.clk(nosc_buf),.rst(rst),.en(1'b1), .d(count_en), .q(count_en_s0));
+ rdffe ds1(.clk(nosc_buf),.rst(rst),.en(1'b1), .d(count_en_s0), .q(count_en_s1));
+
+ // Count down toward zero from (signed)-1
+
+ assign value[0] = nosc_buf;
+
+ generate
+ for (i = 1; i < WIDTH; i = i + 1)
+ sdffe dcg(.clk(value[i-1]),.pre(rst),.en(count_en_s1),.d(~value[i]),.q(value[i]));
+ endgenerate
+
+ // value[WIDTH] is the overflow bit. Make it sticky.
+ // This bit should never be cleared if the measurement is designed correctly.
+
+ sdffe dcg(.clk(value[WIDTH-1]),.pre(rst),.en(count_en_s1),.d(1'b0),.q(value[WIDTH]));
+
+ assign count[WIDTH-1:0] = value[WIDTH:1];
+
+endmodule
+
+module ericsmi_speed_test(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+
+parameter WIDTH=24;
+localparam COUNTER_WIDTH = 23; // TinyTapeout is small, so find a value that fits by trial and error
+
+wire force_trig, fired, count_en;
+wire [2:0] sel;
+wire [2:0] trig_q;
+wire [1:0] ring_en;
+wire [WIDTH-1:0] value0,value1;
+wire [COUNTER_WIDTH-1:0] count0,count1;
+
+wire clk = io_in[0];
+wire nrst = io_in[1];
+wire trig = io_in[2];
+
+assign sel[2:0] = io_in[5:3];
+assign ring_en[1:0] = io_in[7:6];
+
+assign force_trig = &sel; // force the oscillators and counters to run to test their operation
+ // not really a controlled measurement. Only for debug.
+
+inv_with_delay inv_r(.A(nrst),.Y(rst));
+
+// Enable the counters for one clk period upon trig rising edge.
+// Asserting nrst arms the measurements. Clear nrst before fire.
+
+rdffe dt0(.clk(clk),.rst(rst),.en(1'b1), .d(trig ), .q(trig_q[0]));
+rdffe dt1(.clk(clk),.rst(rst),.en(1'b1), .d(trig_q[0]), .q(trig_q[1]));
+
+rdffe dt2(
+ .clk(clk),
+ .rst(rst),
+ .en(1'b1),
+ .d((trig_q[0] & ~trig_q[1])),
+ .q(trig_q[2])
+);
+
+rdffe dt3(
+ .clk(clk),
+ .rst(rst),
+ .en(1'b1),
+ .d(trig_q[2] | fired),
+ .q(fired)
+);
+
+assign count_en = force_trig | trig_q[2];
+
+ring_with_counter #(.WIDTH(COUNTER_WIDTH)) ring0(
+ .nrst(nrst),
+ .ring_en(ring_en[0]),
+ .count_en(count_en),
+ .count(count0[COUNTER_WIDTH-1:0])
+);
+
+assign value0[WIDTH-1:0] = {{WIDTH-COUNTER_WIDTH{count0[COUNTER_WIDTH-1]}},count0[COUNTER_WIDTH-1:0]};
+
+ring_with_counter #(.WIDTH(COUNTER_WIDTH)) ring1(
+ .nrst(nrst),
+ .ring_en(ring_en[1]),
+ .count_en(count_en),
+ .count(count1[COUNTER_WIDTH-1:0])
+);
+
+assign value1[WIDTH-1:0] = {{WIDTH-COUNTER_WIDTH{count1[COUNTER_WIDTH-1]}},count1[COUNTER_WIDTH-1:0]};
+
+wire [7:0] status;
+
+// when force_trigger is asserted put the status byte on the output, everything is free running.
+assign status[7:0] = {1'b1,
+ fired,
+ value1[COUNTER_WIDTH-1], // overflow
+ value0[COUNTER_WIDTH-1], // overflow
+ value1[COUNTER_WIDTH-2],
+ value0[COUNTER_WIDTH-2],
+ value1[16], // 16=Ceiling@Log2[166*166]+1
+ value0[16]};
+
+assign io_out[7:0] = sel[2:0] == 3'b000 ? 8'd0 :
+ sel[2:0] == 3'b001 ? {value0[7:0]} :
+ sel[2:0] == 3'b010 ? {value0[15:8]} :
+ sel[2:0] == 3'b011 ? {value0[23:16]} :
+ sel[2:0] == 3'b100 ? {value1[7:0]} :
+ sel[2:0] == 3'b101 ? {value1[15:8]} :
+ sel[2:0] == 3'b110 ? {value1[23:16]} :
+ status[7:0] ;
+
+endmodule
diff --git a/verilog/rtl/074_tt2.v b/verilog/rtl/074_tt2.v
new file mode 100644
index 0000000..c32b838
--- /dev/null
+++ b/verilog/rtl/074_tt2.v
@@ -0,0 +1,151 @@
+/** tt2.v
+ * Author: Aidan Medcalf
+ *
+ * Top-level TinyTapeout 2 wrapper
+ */
+
+`default_nettype none
+
+module AidanMedcalf_pid_controller (
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+
+ wire clk;
+ wire reset;
+ //wire enable;
+ wire cfg_clk;
+ wire cfg_mosi;
+ wire cfg_cs;
+ wire pv_in_miso;
+
+ assign clk = io_in[0];
+ assign reset = io_in[1];
+ // io_in[2] not used
+ //assign enable = io_in[2];
+ assign cfg_clk = io_in[3];
+ assign cfg_mosi = io_in[4];
+ // io_in[5] not used
+ assign cfg_cs = io_in[6];
+ assign pv_in_miso = io_in[7];
+
+ wire pv_in_clk;
+ wire pv_in_cs;
+ reg [1:0] pv_in_cs_hist;
+ wire out_clk, out_cs, out_mosi;
+
+ assign io_out[0] = pv_in_clk;
+ assign io_out[1] = pv_in_cs;
+ //assign io_out[2] = 1'b0; // io_out[2] not used
+ //assign io_out[3] = pid_stb_d1;
+ //assign io_out[7:4] = out;
+ assign io_out[2] = out_clk;
+ assign io_out[3] = out_mosi;
+ assign io_out[4] = out_cs;
+ assign io_out[7:5] = 1'b0; // not used
+
+ // Configuration registers
+ //reg [7:0] cfg_buf[4];
+ wire [7:0] sp;
+ wire [7:0] kp;
+ wire [7:0] ki;
+ //wire [7:0] kd;
+
+ //assign sp = cfg_buf[0][3:0];
+ //assign kp = cfg_buf[0][7:4];
+ //assign ki = cfg_buf[1][3:0];
+ //assign kd = cfg_buf[1][7:4];
+ //assign stb_level[7:0] = cfg_buf[2];
+ //assign stb_level[15:8] = cfg_buf[3];
+
+ assign sp = cfg_spi_buffer[7:0];
+ assign kp = cfg_spi_buffer[15:8];
+ assign ki = cfg_spi_buffer[23:16];
+ //assign kd = cfg_spi_buffer[31:24];
+
+ wire pv_stb;
+ wire pid_stb;
+ reg pid_stb_d1;
+
+ wire pid_rst;
+ assign pid_rst = reset || !cfg_cs;
+
+ // I/O registers
+ reg [7:0] in_pv;
+ reg [7:0] out;
+
+ // Slave SPI for configuration
+ //wire cfg_spi_done;
+ wire [23:0] cfg_spi_buffer;
+ spi_slave_in #(.BITS(24)) cfg_spi(.reset(reset), .clk(clk), .cs(cfg_cs), .sck(cfg_clk), .mosi(cfg_mosi), .out_buf(cfg_spi_buffer));
+
+ // Shift input in
+ spi_master_in spi_in(.reset(pid_rst), .clk(clk),
+ .miso(pv_in_miso), .start(pv_stb),
+ .out_buf(in_pv), .sck(pv_in_clk), .cs(pv_in_cs));
+
+ // Shift output out
+ spi_master_out spi_out(.reset(pid_rst), .clk(clk), .in_buf(out),
+ .start(pid_stb_d1),
+ .sck(out_clk), .cs(out_cs), .mosi(out_mosi));
+
+ // PID core
+ pid pid (.reset(pid_rst), .clk(clk), .pv_stb(pid_stb),
+ .sp(sp), .pv(in_pv),
+ .kp(kp), .ki(ki),
+ .stimulus(out));
+
+ strobe #(.BITS(16)) pv_stb_gen(.reset(reset), .clk(clk), .out(pv_stb));
+
+ assign pid_stb = pv_in_cs_hist[0] && !pv_in_cs_hist[1];
+
+ always @(posedge clk) begin
+ if (reset) begin
+ pid_stb_d1 <= 'b0;
+ pv_in_cs_hist <= 'b0;
+ end else begin
+ pv_in_cs_hist <= { pv_in_cs_hist[0], pv_in_cs };
+ pid_stb_d1 <= pid_stb;
+ end
+ end
+
+endmodule
+
+/*
+module edge_detect (
+ input reset,
+ input clk,
+ input sig,
+ input pol,
+ output out
+);
+ reg sigin;
+ reg siglast;
+ assign out = reset ? 1'b0 : (pol ? ((!siglast) && sigin) : (siglast && (!sigin)));
+ always @(posedge clk) begin
+ { siglast, sigin } <= { sigin, sig };
+ //sigin <= sig;
+ //siglast <= sigin;
+ end
+endmodule
+*/
+
+module strobe #(
+ parameter BITS=8
+) (
+ input reset,
+ input clk,
+ output out
+);
+ reg [BITS-1:0] count;
+ wire [BITS-1:0] next;
+ assign next = count + 'b1;
+ assign out = next == 'b0;
+ always @(posedge clk) begin
+ if (reset) begin
+ count <= 'b0;
+ end else begin
+ count <= next;
+ end
+ end
+endmodule
diff --git a/verilog/rtl/075_TrainLED2_top.v b/verilog/rtl/075_TrainLED2_top.v
new file mode 100644
index 0000000..c122685
--- /dev/null
+++ b/verilog/rtl/075_TrainLED2_top.v
@@ -0,0 +1,19 @@
+module cpldcpu_TrainLED2top(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+
+// Instance 1
+TrainLED2 TrainLED2_top1 (
+ .clk(io_in[0]),
+ .rst(io_in[1]),
+ .din(io_in[2]),
+ .dout(io_out[0]),
+ .led1(io_out[1]),
+ .led2(io_out[2]),
+ .led3(io_out[3])
+ );
+
+
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/076_mcpu5plus.v b/verilog/rtl/076_mcpu5plus.v
new file mode 100644
index 0000000..61b42cc
--- /dev/null
+++ b/verilog/rtl/076_mcpu5plus.v
@@ -0,0 +1,76 @@
+
+`default_nettype none
+
+module cpldcpu_MCPU5plus(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+
+MCPU5plus MCPU5plus_top (
+ .clk(io_in[0]),
+ .rst(io_in[1]),
+ .inst_in(io_in[7:2]),
+ .cpu_out(io_out[7:0])
+);
+
+endmodule
+
+
+module MCPU5plus(inst_in,cpu_out,rst,clk);
+
+input [5:0] inst_in;
+output [7:0] cpu_out;
+input rst;
+input clk;
+
+localparam OP_BCC = 2'b00; //00IIII
+localparam OP_STA = 3'b101; //101RRR
+localparam OP_JMPA = 6'b111010; //111010
+
+reg [8:0] accu; // accu(6) is carry !
+reg [7:0] pc;
+reg [7:0] regfile [0:8];
+reg iflag;
+integer i;
+
+ //handle register file writes (STA)
+ always @(*)
+ if ((inst_in[5:3] == OP_STA) && ~rst && ~clk)
+ regfile[inst_in[2:0]] <= accu;
+
+ always @(posedge clk)
+ if (rst) begin
+ accu <= 0;
+ pc <= 0;
+ iflag <= 0;
+ end
+ else begin
+ // PC
+ if ((inst_in[5:4] == OP_BCC) && ~accu[8]) // conditional branch (BCC)
+ pc <= pc + (iflag ? { inst_in[3:0], accu[3:0]}: {{4{inst_in[3]}}, inst_in[3:0]});
+ else
+ pc <= pc + 1'b1;
+
+ // ALU path + carry flag
+ casex(inst_in)
+ 6'b00????: accu[8] <= 1'b0; // BCC #imm4
+ 6'b01????: accu[7:0] <= iflag ? { inst_in[3:0], accu[3:0]}: {{4{inst_in[3]}}, inst_in[3:0]} ; // LDI #simm4
+ 6'b100???: accu[8:0] <= {1'b0,regfile[inst_in[2:0]]} + {1'b0,accu[7:0]}; // ADD reg8
+ 6'b101???: ; // STA reg8
+ 6'b110???: accu[7:0] <= regfile[inst_in[2:0]]; // LDA reg8
+ 6'b11100?: accu[8:0] <= {~inst_in[0] & accu[8], ~accu[7:0]} + inst_in[0]; // NEG / NOT
+ 6'b111010: ; // Free
+ 6'b111011: ; // OUT
+ 6'b1111??: ; // Free imm2
+ endcase
+
+ // Flags
+ casex(inst_in)
+ 6'b01????: iflag <= 1'b1; // LDI #simm4
+ default: iflag <= 1'b0; // all others
+ endcase
+ end
+
+ assign cpu_out = clk ? {pc[7:0]} : accu[7:0] ;
+
+endmodule
diff --git a/verilog/rtl/077_cpu.v b/verilog/rtl/077_cpu.v
new file mode 100644
index 0000000..c025225
--- /dev/null
+++ b/verilog/rtl/077_cpu.v
@@ -0,0 +1,273 @@
+
+//
+// (C) Copyright Paul Campbell 2022 taniwha@gmail.com
+// Released under an Apache License 2.0
+//
+
+`default_nettype none
+
+module moonbase_cpu_4bit #(parameter MAX_COUNT=1000) (input [7:0] io_in, output [7:0] io_out);
+
+ //
+ // External interfacex
+ //
+ // external address latch
+ // the external 7 bit address latch is loaded from io_out[6:0] when io_out[7] is 1
+ // external SRAM (eg MWS5101AEL3):
+ // the external RAM always produces what is at the latch's addresses on io_in[5:2]
+ // the external SRAM is written when io_out[7] is 0 and io_out[5] is 0
+ // io_out[6] can be used as an extra address bit to split the address space between
+ // code (1) and data (0) to use a 256-nibble sram (woot!)
+ // external devices:
+ // external devices can be read from io_in[7:6] (at address pointed to by the address latch)
+ // external devices can be written from io_out[3:0] (at address pointed to by the address latch)
+ // when io_out[7] is 0 and io_out[4] is 0
+ //
+ //
+ // SRAM address space (data accesses):
+ // 0-127 external
+ // 128-131 internal (internal ram cells, for filling up the die :-)
+ //
+
+ localparam N_LOCAL_RAM = 24;
+
+ wire clk = io_in[0];
+ wire reset = io_in[1];
+ wire [3:0]ram_in = io_in[5:2];
+ wire [1:0]data_in = io_in[7:6];
+
+ reg strobe_out; // address strobe - designed to be wired to a 7 bit latch and a MWS5101AEL3
+ reg write_data_n; // write enable for data
+ reg write_ram_n; // write enable for ram
+ reg addr_pc;
+ reg data_pc;
+ wire [6:0]data_addr = ((r_tmp[3]?r_y[6:0]:r_x[6:0])+{4'b000, r_tmp[2:0]});
+ wire is_local_ram = (r_tmp[3]?r_y[7]:r_x[7]);
+ wire write_local_ram = is_local_ram & !write_ram_n;
+ wire [$clog2(N_LOCAL_RAM)-1:0]local_ram_addr = data_addr[$clog2(N_LOCAL_RAM)-1:0];
+ wire [6:0]addr_out = addr_pc ? r_pc : data_addr; // address out mux (PC or X/Y+off)
+ assign io_out = {strobe_out, strobe_out? addr_out : {data_pc, write_ram_n|is_local_ram, write_data_n, r_a}}; // mux address and data out
+
+ reg [6:0]r_pc, c_pc; // program counter // actual flops in the system
+ reg [7:0]r_x, c_x; // x index register // by convention r_* is a flop, c_* is the combinatorial that feeds it
+ reg [7:0]r_y, c_y; // y index register
+ reg [3:0]r_a, c_a; // accumulator
+ reg r_c, c_c; // carry flag
+ reg [3:0]r_tmp2, c_tmp2;// operand temp (high)
+ reg [3:0]r_tmp, c_tmp;// operand temp (low)
+ reg [6:0]r_s0, c_s0; // call stack
+ reg [6:0]r_s1, c_s1;
+ reg [6:0]r_s2, c_s2;
+ reg [6:0]r_s3, c_s3;
+
+ //
+ // phase:
+ // 0 - instruction fetch addr
+ // 1 - instruction fetch data
+ // 2 - const fetch addr
+ // 3 - const fetch data
+ // 4 - data/const fetch addr
+ // 5 - data/const fetch data
+ // 6 - execute/data store addr
+ // 7 - data store data (might not do this)
+ //
+ reg [2:0]r_phase, c_phase; // CPU internal state machine
+
+
+ // instructions
+ //
+ // 0 v: add a, v(x/y) - sets C
+ // 1 v: sub a, v(x/y) - sets C
+ // 2 v: or a, v(x/y)
+ // 3 v: and a, v(x/y)
+ // 4 v: xor a, v(x/y)
+ // 5 v: mov a, v(x/y)
+ // 6 v: movd a, v(x/y)
+ // 7 0: swap x, y
+ // 1: add a, c
+ // 2: mov x.l, a
+ // 3: ret
+ // 4: add y, a
+ // 5: add x, a
+ // 6: add y, #1
+ // 7: add x, #1
+ // 8 v: mov a, #v
+ // 9 v: add a, #v
+ // a v: movd v(x/y), a
+ // b v: mov v(x/y), a
+ // c h l: mov x, #hl
+ // d h l: jne a/c, hl if h[3] the test c otherwise test a
+ // e h l: jeq a/c, hl if h[3] the test c otherwise test a
+ // f h l: jmp/call hl
+ //
+ // Memory access - addresses are 7 bits - v(X/y) is a 3-bit offset v[2:0]
+ // if v[3] it's Y+v[2:0]
+ // if !v[3] it's X+v[2:0]
+ //
+ // The general idea is that X normally points to a bank of in sram 8 'registers',
+ // a bit like an 8051's r0-7, while X is a more general index register
+ // (but you can use both if you need to do some copying)
+ //
+
+ reg [3:0]r_ins, c_ins; // fetched instruction
+
+ wire [4:0]c_add = {1'b0, r_a}+{1'b0, r_tmp}; // ALUs
+ wire [4:0]c_sub = {1'b0, r_a}-{1'b0, r_tmp};
+ wire [6:0]c_i_add = (r_tmp[0]?r_x:r_y)+(r_tmp[1]?7'b1:{3'b0, r_a});
+ wire [6:0]c_pc_inc = r_pc+1;
+
+
+ reg [3:0] r_local_ram[0:N_LOCAL_RAM-1];
+
+ wire [3:0] local_ram = r_local_ram[local_ram_addr];
+ always @(posedge clk)
+ if (write_local_ram)
+ r_local_ram[local_ram_addr] <= r_a;
+
+ always @(*) begin
+ c_ins = r_ins;
+ c_x = r_x;
+ c_y = r_y;
+ c_a = r_a;
+ c_s0 = r_s0;
+ c_s1 = r_s1;
+ c_s2 = r_s2;
+ c_s3 = r_s3;
+ c_tmp = r_tmp;
+ c_tmp2 = r_tmp2;
+ c_pc = r_pc;
+ c_c = r_c;
+ write_data_n = 1;
+ write_ram_n = 1;
+ addr_pc = 'bx;
+ data_pc = 'bx;
+ if (reset) begin // reset clears the state machine and sets PC to 0
+ c_pc = 0;
+ c_phase = 0;
+ strobe_out = 1;
+ end else
+ case (r_phase) // synthesis full_case parallel_case
+ 0: begin // 0: address latch instruction PC
+ strobe_out = 1;
+ addr_pc = 1;
+ c_phase = 1;
+ end
+ 1: begin // 1: read data in
+ strobe_out = 0;
+ data_pc = 1;
+ c_ins = ram_in;
+ c_pc = c_pc_inc;
+ c_phase = 2;
+ end
+ 2: begin
+ strobe_out = 1; // 2: address latch operand PC
+ addr_pc = 1;
+ c_phase = 3;
+ end
+ 3: begin
+ strobe_out = 0; // 3: read operand
+ c_tmp = ram_in;
+ c_pc = c_pc_inc;
+ data_pc = 1;
+ case (r_ins) // synthesis full_case parallel_case
+ 7, 8, 9, 10, 11: c_phase = 6;// some instructions don't have a 2nd fetch
+ default: c_phase = 4;
+ endcase
+ end
+ 4: begin // 4 address latch for next operand
+ strobe_out = 1;
+ addr_pc = r_ins[3:2] == 3; // some instructions read a 2nd operand, the rest the come here read a memory location
+ c_phase = 5;
+ end
+ 5: begin // 5 read next operand
+ strobe_out = 0;
+ data_pc = r_ins[3:2] == 3;
+ c_tmp2 = r_tmp; // low->high for 2 byte cases
+ c_tmp = (r_ins[3:1] == 3?{2'b0,data_in}:is_local_ram&&r_ins[3:2] != 3?local_ram:ram_in); // read the actial data, movd comes from upper bits
+ if (r_ins[3:2] == 3) // if we fetched from PC increment it
+ c_pc = c_pc_inc;
+ c_phase = 6;
+ end
+ 6: begin // 6 execute stage
+ strobe_out = r_ins[3:1] == 5; // if writing to anything latch address
+ addr_pc = 0;
+ c_phase = 0; // if not writing go back
+ case (r_ins)// synthesis full_case parallel_case
+ 0, // add a, v(x)
+ 9: begin c_c = c_add[4]; c_a = c_add[3:0]; end // add a, #v
+ 1: begin c_c = c_sub[4]; c_a = c_sub[3:0]; end // sub a, v(x)
+ 2: c_a = r_a|r_tmp; // or a, v(x)
+ 3: c_a = r_a&r_tmp; // sub a, v(x)
+ 4: c_a = r_a^r_tmp; // xor a, v(x)
+ 5, // mov a, v(x)
+ 6, // movd a, v(x)
+ 8: c_a = r_tmp; // mov a, #v
+ 7: case (r_tmp) // synthesis full_case parallel_case
+ 0: begin c_x = r_y; c_y = r_x; end // 0 swap y, x
+ 1: c_a = r_a+{3'b000, r_c}; // 1 add a, c
+ 2: c_x[3:0] = r_a; // 2 mov x.l, a
+ 3: begin // 3 ret
+ c_pc = r_s0;
+ c_s0 = r_s1;
+ c_s1 = r_s2;
+ c_s2 = r_s3;
+ end
+ 4: c_y = c_i_add; // 4 add y, a
+ 5: c_x = c_i_add; // 5 add x, a
+ 6: c_y = c_i_add; // 6 add y, #1
+ 7: c_x = c_i_add; // 7 add y, #1
+ default: ;
+ endcase
+ 10, // movd v(x), a
+ 11: c_phase = 7; // mov v(x), a
+ 12: c_x = {r_tmp2, r_tmp}; // mov x, #VV
+ 13: c_pc = (r_tmp2[3]?!r_c : r_a != 0) ? {r_tmp2[2:0], r_tmp} : r_pc; // jne a/c, VV
+ 14: c_pc = (r_tmp2[3]? r_c : r_a == 0) ? {r_tmp2[2:0], r_tmp} : r_pc; // jeq a/c, VV
+ 15: begin c_pc = {r_tmp2[2:0], r_tmp}; // jmp VV
+ if (r_tmp2[3]) begin // call
+ c_s0 = r_pc;
+ c_s1 = r_s0;
+ c_s2 = r_s1;
+ c_s3 = r_s2;
+ end
+ end
+ endcase
+ end
+ 7: begin // 7 write data stage - assert appropriate write strobe
+ strobe_out = 0;
+ data_pc = 0;
+ write_data_n = r_ins[0];
+ write_ram_n = ~r_ins[0];
+ c_phase = 0;
+ end
+ endcase
+ end
+
+ always @(posedge clk) begin
+ r_a <= c_a;
+ r_c <= c_c;
+ r_x <= c_x;
+ r_y <= c_y;
+ r_ins <= c_ins;
+ r_tmp <= c_tmp;
+ r_tmp2 <= c_tmp2;
+ r_pc <= c_pc;
+ r_phase <= c_phase;
+ r_s0 <= c_s0;
+ r_s1 <= c_s1;
+ r_s2 <= c_s2;
+ r_s3 <= c_s3;
+ end
+
+endmodule
+
+/* For Emacs:
+ * Local Variables:
+ * mode:c
+ * indent-tabs-mode:t
+ * tab-width:4
+ * c-basic-offset:4
+ * End:
+ * For VIM:
+ * vim:set softtabstop=4 shiftwidth=4 tabstop=4:
+ */
diff --git a/verilog/rtl/078_top.v b/verilog/rtl/078_top.v
new file mode 100644
index 0000000..01583e2
--- /dev/null
+++ b/verilog/rtl/078_top.v
@@ -0,0 +1,9 @@
+
+`default_nettype none
+
+module davidsiaw_stackcalc (
+ input wire [7:0] io_in,
+ output wire [7:0] io_out
+);
+ stack_cpu cpu(.io_in(io_in), .io_out(io_out));
+endmodule
diff --git a/verilog/rtl/083_cpu.v b/verilog/rtl/083_cpu.v
new file mode 100644
index 0000000..451fe33
--- /dev/null
+++ b/verilog/rtl/083_cpu.v
@@ -0,0 +1,369 @@
+
+//
+// (C) Copyright Paul Campbell 2022 taniwha@gmail.com
+// Released under an Apache License 2.0
+//
+
+`default_nettype none
+
+module moonbase_cpu_8bit #(parameter MAX_COUNT=1000) (input [7:0] io_in, output [7:0] io_out);
+
+ //
+ // External interface
+ //
+ // external address latch
+ // the external 12 bit address latch is loaded [5:0] from io_out[5:0] when io_out[7:6] is 10
+ // the external 12 bit address latch is loaded [11:6] from io_out[5:0] when io_out[7:6] is 11
+ // external SRAM (eg MWS5101AEL3) when io_out[7] is 0
+ // which nibble is from io_out[6]
+ // the external RAM always produces what is at the latch's addresses on io_in[5:2] when
+ // the external SRAM is written when io_out[7] is 0 and io_out[5] is 0
+ // io_out[6] can be used as an extra address bit to split the address space between
+ // code (1) and data (0) to use a 256-nibble sram (woot!)
+ // external devices when io_out[7] is 0:
+ // which nibble is from io_out[6]
+ // external devices can be read from io_in[7:6] (at address pointed to by the address latch)
+ // external devices can be written from io_out[3:0] (at address pointed to by the address latch)
+ // when io_out[4] is 0
+ //
+ // SRAM address space (data accesses):
+ // 0-0xfff external
+ // 0x1000-131 internal (internal ram cells, for filling up the die :-)
+ //
+
+ localparam N_LOCAL_RAM = 4;
+
+ wire clk = io_in[0];
+ wire reset = io_in[1];
+ wire [3:0]ram_in = io_in[5:2];
+ wire [1:0]data_in = io_in[7:6];
+
+ reg strobe_out; // address strobe - designed to be wired to a 7 bit latch and a MWS5101AEL3
+ reg nibble; // address/data nibble
+ reg write_data_n; // write enable for data
+ reg write_ram_n; // write enable for ram
+ reg addr_pc;
+ wire [11:0]data_addr = ((r_v[3]?r_y[11:0]:r_x[11:0])+{8'b000, r_v[2:0]});
+ wire is_local_ram = (r_v[3]?r_y[12]:r_x[12]);
+ wire write_local_ram = is_local_ram & !write_ram_n;
+ wire write_ext_ram_n = is_local_ram | write_ram_n;
+ wire [$clog2(N_LOCAL_RAM)-1:0]local_ram_addr = data_addr[$clog2(N_LOCAL_RAM)-1:0];
+ wire [11:0]addr_out = addr_pc ? r_pc : data_addr; // address out mux (PC or X/Y+off)
+ wire [5:0]addr_out_mux = (nibble?addr_out[11:6]:addr_out[5:0]); // mux-d by portion
+ assign io_out = {strobe_out, nibble, strobe_out? addr_out_mux : {write_ext_ram_n, write_data_n, !nibble?r_a[7:4]:r_a[3:0]}}; // mux address and data out
+
+ reg [11:0]r_pc, c_pc; // program counter // actual flops in the system
+ reg [12:0]r_x, c_x; // x index register // by convention r_* is a flop, c_* is the combinatorial that feeds it
+ reg [12:0]r_y, c_y; // y index register
+ reg [7:0]r_a, c_a; // accumulator
+ reg [7:0]r_b, c_b; // temp accumulator
+ reg r_c, c_c; // carry flag
+ reg [3:0]r_h, c_h; // operand temp (high)
+ reg [3:0]r_l, c_l; // operand temp (low)
+ reg [4:0]r_ee, c_ee; // extended const (bits 12:4)
+ reg [3:0]r_v, c_v; // operand temp (low)
+ reg [11:0]r_s0, c_s0; // call stack
+ reg [11:0]r_s1, c_s1;
+
+ //
+ // phase:
+ // 0 - instruction fetch addr
+ // 1 - instruction fetch dataL ins
+ // 2 - instruction fetch dataH V
+ // 4 - data/const fetch addr
+ // 5 - data/const fetch dataL tmp
+ // 6 - data/const fetch dataH tmp2
+ // 8 - execute/data store addr
+ // 9 - data store dataL (might not do this)
+ // a - data store dataH (might not do this)
+ //
+ reg [3:0]r_phase, c_phase; // CPU internal state machine
+
+ // instructions
+ //
+ // Registers: a,b 8 bit, x,y 13 bits, pc 12 bits
+ //
+ // 0v: add a, v(x/y) - sets C
+ // 1v: sub a, v(x/y) - sets C
+ // 2v: or a, v(x/y)
+ // 3v: and a, v(x/y)
+ // 4v: xor a, v(x/y)
+ // 5v: mov a, v(x/y)
+ // 6v: movd a, v(x/y)
+ // 70: add a, c
+ // 71: inc a
+ // 72: swap x, y
+ // 73: ret
+ // 74: add y, a
+ // 75: add x, a
+ // 76: inc y
+ // 77: inc x
+ // 78: mov a, y
+ // 79: mov a, x
+ // 7a: mov b, a
+ // 7b: swap b, a
+ // 7c: mov y, a
+ // 7d: mov x, a
+ // 7e: clr a
+ // 7f: mov a, pc
+ // 8v: nop
+ // 9v: nop
+ // av: movd v(x/y), a
+ // bv: mov v(x/y), a
+ // cv: nop
+ // dv: nop
+ // ev: nop
+ // f0 HL: mov a, #HL
+ // f1 HL: add a, #HL
+ // f2 HL: mov y, #EELL
+ // f3 HL: mov x, #EEHL
+ // f4 HL: jne a/c, EEHL if EE[4] then test c otherwise test a
+ // f5 HL: jeq a/c, EEHL if EE[4] then test c otherwise test a
+ // f6 HL: jmp/call EEHL if EE[4] call else jmp
+ // f7 HL: nop
+ //
+ // Memory access - addresses are 7 bits - v(X/y) is a 3-bit offset v[2:0]
+ // if v[3] it's Y+v[2:0]
+ // if !v[3] it's X+v[2:0]
+ //
+ // The general idea is that X normally points to a bank of in sram 8 'registers',
+ // a bit like an 8051's r0-7, while X is a more general index register
+ // (but you can use both if you need to do some copying)
+ //
+
+ reg [3:0]r_ins, c_ins; // fetched instruction
+
+ wire [8:0]c_add = {1'b0, r_a}+{1'b0, r_h, r_l}; // ALUs
+ wire [8:0]c_sub = {1'b0, r_a}-{1'b0, r_h, r_l};
+ wire [12:0]c_i_add = {r_v[0]?r_x[12]:r_y[12], (r_v[0]?r_x[11:0]:r_y[11:0])+(r_v[1]?12'b1:{4'b0,r_a})};
+ wire [11:0]c_pc_inc = r_pc+1;
+ wire [7:0]c_a_inc = r_a + {7'b0, r_c|r_v[0]};
+
+ reg [7:0]r_local_ram[0:N_LOCAL_RAM-1];
+
+ wire [7:0]local_ram = r_local_ram[local_ram_addr];
+ always @(posedge clk)
+ if (write_local_ram)
+ r_local_ram[local_ram_addr] <= r_a;
+
+ always @(*) begin
+ c_ins = r_ins;
+ c_x = r_x;
+ c_y = r_y;
+ c_a = r_a;
+ c_b = r_b;
+ c_s0 = r_s0;
+ c_s1 = r_s1;
+ c_l = r_l;
+ c_h = r_h;
+ c_ee = r_ee;
+ c_pc = r_pc;
+ c_c = r_c;
+ c_v = r_v;
+ write_data_n = 1;
+ write_ram_n = 1;
+ addr_pc = 'bx;
+ nibble = 'bx;
+ if (reset) begin // reset clears the state machine and sets PC to 0
+ c_y = 13'h1000; // point at internal sram
+ c_pc = 0;
+ c_phase = 0;
+ strobe_out = 1;
+ end else
+ case (r_phase) // synthesis full_case parallel_case
+ 0: begin // 0: address latch instruction PC
+ strobe_out = 1;
+ addr_pc = 1;
+ nibble = 0;
+ c_phase = 1;
+ end
+ 1: begin // 0: address latch instruction PC
+ strobe_out = 1;
+ addr_pc = 1;
+ nibble = 1;
+ c_phase = 2;
+ end
+ 2: begin // 1: read data in r_ins
+ strobe_out = 0;
+ c_ins = ram_in;
+ nibble = 0;
+ c_phase = 3;
+ end
+ 3: begin // 3: read data in r_v
+ strobe_out = 0;
+ c_v = ram_in;
+ nibble = 1;
+ c_pc = c_pc_inc;
+ case (r_ins) // synthesis full_case parallel_case
+ 7, 8, 9, 10, 11, 12, 13, 14: c_phase = 12;// some instructions don't have a 2nd fetch
+ default: c_phase = 4;
+ endcase
+ end
+ 4: begin // 4 address latch for next operand
+ strobe_out = 1;
+ addr_pc = r_ins[3:2] == 3; // some instructions read a 2nd operand, the rest the come here read a memory location
+ nibble = 0;
+ c_phase = r_ins[3:2] != 3 && is_local_ram ? 7 : 5;
+ end
+ 5: begin // 4 address latch for next operand
+ strobe_out = 1;
+ addr_pc = r_ins[3:2] == 3; // some instructions read a 2nd operand, the rest the come here read a memory location
+ nibble = 1;
+ c_phase = 6;
+ end
+ 6: begin // 5 read next operand r_hi
+ strobe_out = 0;
+ nibble = 0;
+ c_h = ((r_ins[3:1] == 3)? 4'b0 : ram_in);
+ c_phase = 7;
+ end
+ 7: begin // 5 read next operand r_lo
+ strobe_out = 0;
+ nibble = 1;
+ if (is_local_ram&&r_ins != 4'hf) begin
+ c_h = local_ram[7:4];
+ c_l = local_ram[3:0];
+ end else begin
+ c_l = ((r_ins[3:1] == 3)?{2'b0,data_in}:ram_in); // read the actial data, movd comes from upper bits
+ end
+ if (r_ins == 4'hf) // if we fetched from PC increment it
+ c_pc = c_pc_inc;
+ c_phase = (r_ins == 4'hf && r_v[3:1] != 0) ? 8: 12;
+ end
+ 8: begin // 4 address latch for next operand
+ strobe_out = 1;
+ addr_pc = 1;
+ nibble = 0;
+ c_phase = 9;
+ end
+ 9: begin // 4 address latch for next operand
+ strobe_out = 1;
+ addr_pc = 1;
+ nibble = 1;
+ c_phase = 10;
+ end
+ 10: begin // 5 read next operand r_hi
+ strobe_out = 0;
+ nibble = 0;
+ c_ee[4] = ram_in[0];
+ c_phase = 11;
+ end
+ 11: begin // 5 read next operand r_lo
+ strobe_out = 0;
+ nibble = 1;
+ c_ee[3:0] = ram_in;
+ c_pc = c_pc_inc;
+ c_phase = 12;
+ end
+ 12: begin // 6 execute stage
+ strobe_out = r_ins[3:1] == 5; // if writing to anything latch address
+ addr_pc = 0;
+ c_phase = 0; // if not writing go back
+ nibble = 0;
+ case (r_ins)// synthesis full_case parallel_case
+ 0: begin c_c = c_add[8]; c_a = c_add[7:0]; end // add a, v(x)
+ 1: begin c_c = c_sub[8]; c_a = c_sub[7:0]; end // sub a, v(x)
+ 2: c_a = r_a|{r_h, r_l}; // or a, v(x)
+ 3: c_a = r_a&{r_h, r_l}; // sub a, v(x)
+ 4: c_a = r_a^{r_h, r_l}; // xor a, v(x)
+ 5, // mov a, v(x)
+ 6: c_a = {r_h, r_l}; // movd a, v(x)
+ 7: case (r_v) // synthesis full_case parallel_case
+ 0: c_a = c_a_inc; // 0 add a, c
+ 1: c_a = c_a_inc; // 1 inc a
+ 2: begin c_x = r_y; c_y = r_x; end // 2 swap y, x
+ 3: begin // 3 ret
+ c_pc = r_s0;
+ c_s0 = r_s1;
+ end
+ 4: c_y = c_i_add; // 4 add y, a
+ 5: c_x = c_i_add; // 5 add x, a
+ 6: c_y = c_i_add; // 6 add y, #1
+ 7: c_x = c_i_add; // 7 add y, #1
+ 8: c_a = r_y[7:0]; // 8 mov a, y
+ 9: c_a = r_x[7:0]; // 9 mov a, x
+ 10: c_b = r_a; // a mov b, a
+ 11: begin c_b = r_a; c_a = r_b; end // b swap b, a
+ 12: c_y[7:0] = r_a; // c mov y, a
+ 13: c_x[7:0] = r_a; // d mov x, a
+ 14: c_a = 0; // e clr a
+ 15: c_a = r_pc; // f mov a, pc
+ default: ;
+ endcase
+ 8: ; // noop
+ 9: ; // noop
+ 10, // movd v(x), a
+ 11: c_phase = is_local_ram ? 15:13; // mov v(x), a
+ 12: ; // noop
+ 13: ; // noop
+ 14: ; // noop
+
+ 15: case (r_v) // synthesis full_case parallel_case
+ 0: c_a = {r_h, r_l}; // mov a, #HL
+ 1: begin c_c = c_add[8]; c_a = c_add[7:0]; end // add a, #HL
+ 2: c_y = {r_ee, r_h, r_l}; // mov y, #VV
+ 3: c_x = {r_ee, r_h, r_l}; // mov x, #VV
+ 4: c_pc = (r_ee[4]?!r_c : r_a != 0) ? {r_ee[3:0], r_h, r_l} : r_pc; // jne a/c, VV
+ 5: c_pc = (r_ee[4]? r_c : r_a == 0) ? {r_ee[3:0], r_h, r_l} : r_pc; // jeq a/c, VV
+ 6: begin c_pc = {r_ee[3:0], r_h, r_l}; // jmp VV
+ if (r_ee[4]) begin // call
+ c_s0 = r_pc;
+ c_s1 = r_s0;
+ end
+ end
+ default: ;
+ endcase
+ endcase
+ end
+ 13: begin
+ strobe_out = 1;
+ addr_pc = 0;
+ nibble = 1;
+ c_phase = 14;
+ end
+ 14: begin // 7 write data stage - assert appropriate write strobe
+ strobe_out = 0;
+ write_data_n = r_ins[0];
+ write_ram_n = ~r_ins[0];
+ nibble = 0;
+ c_phase = 15;
+ end
+ 15: begin // 7 write data stage - assert appropriate write strobe
+ strobe_out = 0;
+ nibble = 1;
+ write_data_n = r_ins[0];
+ write_ram_n = ~r_ins[0];
+ c_phase = 0;
+ end
+ endcase
+ end
+
+ always @(posedge clk) begin
+ r_a <= c_a;
+ r_b <= c_b;
+ r_c <= c_c;
+ r_x <= c_x;
+ r_y <= c_y;
+ r_ins <= c_ins;
+ r_v <= c_v;
+ r_l <= c_l;
+ r_h <= c_h;
+ r_ee <= c_ee;
+ r_pc <= c_pc;
+ r_phase <= c_phase;
+ r_s0 <= c_s0;
+ r_s1 <= c_s1;
+ end
+
+endmodule
+
+/* For Emacs:
+ * Local Variables:
+ * mode:c
+ * indent-tabs-mode:t
+ * tab-width:4
+ * c-basic-offset:4
+ * End:
+ * For VIM:
+ * vim:set softtabstop=4 shiftwidth=4 tabstop=4:
+ */
diff --git a/verilog/rtl/086_freq_counter.v b/verilog/rtl/086_freq_counter.v
new file mode 100644
index 0000000..7881e09
--- /dev/null
+++ b/verilog/rtl/086_freq_counter.v
@@ -0,0 +1,73 @@
+`default_nettype none
+
+module aramsey118_freq_counter #(
+ parameter DEPTH = 200
+) (
+ input wire [7:0] io_in,
+ output wire [7:0] io_out
+);
+
+ // Precalculate the boundaries
+ localparam integer freq_0 = $ceil(DEPTH * 0.0); // not used, here for completeness
+ localparam integer freq_1 = $ceil(DEPTH * 0.1);
+ localparam integer freq_2 = $ceil(DEPTH * 0.2);
+ localparam integer freq_3 = $ceil(DEPTH * 0.3);
+ localparam integer freq_4 = $ceil(DEPTH * 0.4);
+ localparam integer freq_5 = $ceil(DEPTH * 0.5);
+ localparam integer freq_6 = $ceil(DEPTH * 0.6);
+ localparam integer freq_7 = $ceil(DEPTH * 0.7);
+ localparam integer freq_8 = $ceil(DEPTH * 0.8);
+ localparam integer freq_9 = $ceil(DEPTH * 0.9);
+
+ wire clk = io_in[0];
+ wire reset = io_in[1];
+ wire sig = io_in[2];
+ wire [6:0] led_out;
+ assign io_out[6:0] = led_out;
+ assign io_out[7] = sig;
+
+ wire [$clog2(DEPTH)-1:0] avg;
+ reg sig_d1;
+ reg diff;
+ reg [3:0] digit;
+
+
+ always @(posedge clk) begin
+ // if reset, set counter to 0
+ if (reset) begin
+ sig_d1 <= 0;
+ diff <= 0;
+ digit <= 0;
+ end else begin
+ sig_d1 <= sig;
+ diff <= (sig ^ sig_d1);
+ if ((avg <= $unsigned(freq_1))) begin
+ digit <= 0;
+ end else if ((avg > $unsigned(freq_1)) && (avg <= $unsigned(freq_2))) begin
+ digit <= 1;
+ end else if ((avg > $unsigned(freq_2)) && (avg <= $unsigned(freq_3))) begin
+ digit <= 2;
+ end else if ((avg > $unsigned(freq_3)) && (avg <= $unsigned(freq_4))) begin
+ digit <= 3;
+ end else if ((avg > $unsigned(freq_4)) && (avg <= $unsigned(freq_5))) begin
+ digit <= 4;
+ end else if ((avg > $unsigned(freq_5)) && (avg <= $unsigned(freq_6))) begin
+ digit <= 5;
+ end else if ((avg > $unsigned(freq_6)) && (avg <= $unsigned(freq_7))) begin
+ digit <= 6;
+ end else if ((avg > $unsigned(freq_7)) && (avg <= $unsigned(freq_8))) begin
+ digit <= 7;
+ end else if ((avg > $unsigned(freq_8)) && (avg <= $unsigned(freq_9))) begin
+ digit <= 8;
+ end else begin
+ digit <= 9;
+ end
+ end
+ end
+
+ // instantiate segment display
+ seg7 seg7(.counter(digit), .segments(led_out));
+
+ // instantiate moving average
+ moving_avg #(.DEPTH(DEPTH)) moving_avg(.data_i(diff), .reset, .clk, .avg_o(avg));
+endmodule
diff --git a/verilog/rtl/087_thunderbird_taillight_ctrl.v b/verilog/rtl/087_thunderbird_taillight_ctrl.v
new file mode 100644
index 0000000..d632a83
--- /dev/null
+++ b/verilog/rtl/087_thunderbird_taillight_ctrl.v
@@ -0,0 +1,108 @@
+`default_nettype none `timescale 1ns / 1ps
+// coded by Hirosh Dabui 2012
+// based on T-Bird tail-lights machine from digital design book
+// table 9-20 in VHDL
+/* verilator lint_off MULTITOP */
+module thunderbird_taillight_ctrl #(
+ parameter MAX_COUNT = 1000,
+ parameter SYSTEM_FREQ = 6250,
+ parameter HZ = 8
+) (
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+
+ wire clk = io_in[0];
+ wire reset = io_in[1];
+ wire left = io_in[2];
+ wire right = io_in[3];
+ wire haz = io_in[4];
+
+ wire [5:0] lights = state;
+ assign io_out[7:0] = {2'b00, lights};
+
+ wire div;
+ divider #(
+ .SYSTEM_FREQ(SYSTEM_FREQ),
+ .HZ (HZ)
+ ) divider_i (
+ .clk (clk),
+ .reset (reset),
+ .divider(div)
+ );
+
+ localparam IDLE = 6'b000_000;
+ localparam L3 = 6'b111_000;
+ localparam L2 = 6'b011_000;
+ localparam L1 = 6'b001_000;
+ localparam R3 = 6'b000_111;
+ localparam R2 = 6'b000_110;
+ localparam R1 = 6'b000_100;
+ localparam LR3 = 6'b111_111;
+
+ reg [5:0] state, next_state;
+
+ always @(posedge clk) begin
+ if (reset) begin
+ state <= IDLE;
+ end else begin
+ if (div) begin
+ state <= next_state;
+ end
+ end
+ end
+
+ always @(*) begin
+ next_state = state;
+
+ case (state)
+ IDLE: begin
+ case (1'b1)
+ haz | (left & right): next_state = LR3;
+ left: next_state = L1;
+ right: next_state = R1;
+ default: next_state = IDLE;
+ endcase
+ end
+
+ L1: next_state = haz ? LR3 : L2;
+ L2: next_state = haz ? LR3 : L3;
+ L3: next_state = haz ? LR3 : IDLE;
+
+ R1: next_state = haz ? LR3 : R2;
+ R2: next_state = haz ? LR3 : R3;
+ R3: next_state = haz ? LR3 : IDLE;
+
+ LR3: next_state = IDLE;
+
+ default: next_state = state;
+ endcase
+ end
+
+endmodule
+
+module divider #(
+ parameter SYSTEM_FREQ = 6250,
+ parameter HZ = 8
+) (
+ input clk,
+ input reset,
+ output divider
+);
+ localparam CYCLES = SYSTEM_FREQ / HZ;
+ reg [$clog2(CYCLES) -1:0] cnt;
+ always @(posedge clk) begin
+ if (reset) begin
+ cnt <= 0;
+ end else begin
+ cnt <= cnt + 1;
+ /* verilator lint_off WIDTH */
+ if (cnt >= (CYCLES - 1)) begin
+ cnt <= 0;
+ end
+ /* verilator lint_on WIDTH */
+ end
+ end
+ assign divider = cnt == 0;
+endmodule
+/* verilator lint_on MULTITOP */
diff --git a/verilog/rtl/088_fpga.v b/verilog/rtl/088_fpga.v
new file mode 100644
index 0000000..2fb7e91
--- /dev/null
+++ b/verilog/rtl/088_fpga.v
@@ -0,0 +1,180 @@
+`default_nettype none
+`default_nettype none
+
+// Top level io for this module should stay the same to fit into the scan_wrapper.
+// The pin connections within the user_module are up to you,
+// although (if one is present) it is recommended to place a clock on io_in[0].
+// This allows use of the internal clock divider if you wish.
+module gatecat_fpga_top(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+
+ wire cfg_mode, cfg_frameinc, cfg_framestrb, cfg_dataclk;
+ wire [3:0] cfg_sel;
+
+ sky130_fd_sc_hd__clkbuf_2 mode_clkbuf(.A(io_in[3]), .X(cfg_mode));
+ sky130_fd_sc_hd__clkbuf_2 frameinc_clkbuf(.A(io_in[1]), .X(cfg_frameinc));
+ sky130_fd_sc_hd__clkbuf_2 framestrb_clkbuf(.A(io_in[2]), .X(cfg_framestrb));
+ assign cfg_dataclk = io_in[0];
+
+ wire cfg_datain;
+ sky130_fd_sc_hd__buf_2 din_buf (.A(io_in[4]), .X(cfg_datain));
+
+ localparam W = 5;
+ localparam H = 6;
+ localparam FW = W * 4;
+ localparam FH = H * 2;
+
+ reg [$clog2(FH)-1:0] frame_ctr;
+ reg [FW-1:0] frame_sr;
+
+ always @(posedge cfg_frameinc, negedge cfg_mode)
+ if (~cfg_mode)
+ frame_ctr <= 0;
+ else
+ frame_ctr <= frame_ctr + 1'b1;
+
+ // avoid a shift register for the frame data because that's the highest hold risk
+ always @(posedge cfg_dataclk)
+ frame_sr <= {cfg_datain, frame_sr[FW-1:1]};
+
+ wire [FH-1:0] frame_strb;
+ wire gated_strobe = cfg_mode & cfg_framestrb;
+ generate;
+ genvar ii;
+ for (ii = 0; ii < FH; ii = ii + 1'b1) begin
+ //make sure this is glitch free
+ sky130_fd_sc_hd__nand2_2 cfg_nand (.A(gated_strobe), .B(frame_ctr == ii), .Y(frame_strb[ii]));
+ end
+ endgenerate
+
+ wire fab_clk = io_in[0];
+ wire [6:0] fab_din;
+ sky130_fd_sc_hd__buf_1 din_buf[6:0] (.A(io_in[7:1]), .X(fab_din));
+
+ wire [0:W-1] cell_q[0:H-1];
+ generate
+ genvar xx;
+ genvar yy;
+ for (yy = 0; yy < H; yy = yy + 1'b1) begin: y_c
+ for (xx = 0; xx < W; xx = xx + 1'b1) begin: x_c
+ wire ti, bi, li, ri;
+ if (yy > 0) assign ti = cell_q[yy-1][xx]; else assign ti = fab_din[xx];
+ if (yy < H-1) assign bi = cell_q[yy+1][xx]; else assign bi = cell_q[yy][xx];
+ if (xx > 0) assign li = cell_q[yy][xx-1]; else assign li = fab_din[yy + 1];
+ if (xx < W-1) assign ri = cell_q[yy][xx+1]; else assign ri = cell_q[yy][xx];
+ gatecat_logic_cell #(.has_ff(1'b1)) lc_i (
+ .CLK(fab_clk),
+ .cfg_mode(cfg_mode),
+ .cfg_strb(frame_strb[yy * 2 +: 2]),
+ .cfg_data(frame_sr[xx * 4 +: 4]),
+ .T(ti), .B(bi), .L(li),. R(ri),
+ .Q(cell_q[yy][xx])
+ );
+ end
+ end
+ endgenerate
+
+ assign io_out = {cell_q[5][W-1], cell_q[4][W-1], cell_q[3][W-1], cell_q[H-1]};
+
+
+endmodule
+
+module gatecat_logic_cell (
+ input CLK,
+ input cfg_mode,
+ input [1:0] cfg_strb,
+ input [3:0] cfg_data,
+ input T, L, R, B,
+ output Q
+);
+ parameter has_ff = 1'b0;
+ // config storage
+ wire [7:0] cfg;
+ generate
+ genvar ii, jj;
+ for (ii = 0; ii < 2; ii = ii + 1'b1)
+ for (jj = 0; jj < 4; jj = jj + 1'b1)
+ sky130_fd_sc_hd__dlxtn_1 cfg_lat_i (
+ .D(cfg_data[jj]),
+ .GATE_N(cfg_strb[ii]),
+ .Q(cfg[ii*4 + jj])
+ );
+ endgenerate
+
+ wire i0, i1;
+ // I input muxes
+ wire i0a, i0b;
+ sky130_fd_sc_hd__nand2_1 i0muxa0 (
+ .A(T), .B(cfg[0]),
+ .Y(i0a)
+ );
+ sky130_fd_sc_hd__mux2i_1 i0muxa1 (
+ .A0(R), .A1(L), .S(cfg[0]),
+ .Y(i0b)
+ );
+
+ sky130_fd_sc_hd__mux2i_1 i0muxb (
+ .A0(i0a), .A1(i0b), .S(cfg[1]),
+ .Y(i0)
+ );
+
+ wire i1a, i1b;
+ sky130_fd_sc_hd__and2_1 i1muxa0 (
+ .A(cfg[2]), .B(L),
+ .X(i1a)
+ );
+ sky130_fd_sc_hd__mux2i_1 i1muxa1 (
+ .A0(B), .A1(R), .S(cfg[2]),
+ .Y(i1b)
+ );
+ sky130_fd_sc_hd__mux2i_1 i1muxb (
+ .A0(i1a), .A1(i1b), .S(cfg[3]),
+ .Y(i1)
+ );
+ // S input mux
+ wire s0s, s0, s0a, s0b;
+
+ sky130_fd_sc_hd__nand2_1 s0muxa0 (
+ .A(T), .B(cfg[4]),
+ .Y(s0a)
+ );
+ sky130_fd_sc_hd__mux2i_1 s0muxa1 (
+ .A0(R), .A1(L), .S(cfg[4]),
+ .Y(s0b)
+ );
+
+ sky130_fd_sc_hd__mux2i_1 s0muxb (
+ .A0(s0a), .A1(s0b), .S(cfg[5]),
+ .Y(s0s)
+ );
+ // S invert
+ sky130_fd_sc_hd__xnor2_1 sinv (
+ .A(s0s), .B(cfg[6]), .Y(s0)
+ );
+ // The logic element
+ wire muxo_n;
+ sky130_fd_sc_hd__mux2i_1 lmux (
+ .A0(i0), .A1(i1), .S(s0), .Y(muxo_n)
+ );
+ // The DFF
+ generate if (has_ff) begin: dff
+ wire dffo_n;
+ sky130_fd_sc_hd__dfsbp_1 dff(
+ .D(muxo_n),
+ .SET_B(~cfg_mode),
+ .CLK(CLK),
+ .Q(dffo_n)
+ );
+ // The final output mux
+ sky130_fd_sc_hd__mux2i_1 ffsel (
+ .A0(muxo_n), .A1(dffo_n), .S(cfg[7]), .Y(Q)
+ );
+ end else begin
+ sky130_fd_sc_hd__inv_1 linv (
+ .A(muxo_n), .Y(Q)
+ );
+ end
+ endgenerate
+endmodule
diff --git a/verilog/rtl/091_whisk.v b/verilog/rtl/091_whisk.v
new file mode 100644
index 0000000..b15d594
--- /dev/null
+++ b/verilog/rtl/091_whisk.v
@@ -0,0 +1,1173 @@
+// ============================================================================
+// Whisk: a 16-bit bit-serial RISC processor (c) Luke Wren 2022
+// SPDX-License-Identifier: Apache-2.0
+// ============================================================================
+
+// Whisk is a 16-bit bit-serial processor, with external SPI SRAM interface,
+// designed in a hurry for Tiny Tapeout 2. See README.md for an overview of
+// the instruction set. Supporting hardware:
+//
+// - SPI SRAM with sequential mode and 16-bit addressing, e.g. Microchip
+// 23K256T-I (32 kiB SRAM)
+//
+// - One 8-bit parallel-to-serial shift register, for input port
+//
+// - Two 8-bit serial-to-parallel shift registers, for output port
+//
+// - A host device capable of loading the SPI SRAM, setting it to sequential
+// mode, and releasing Whisk's reset. I'll probably use a Pico.
+//
+// There will be a board with all of these components ready for bringup, and
+// it will be added to this repository (also I will probably make a few of
+// them, and will gladly send you one if you ask). However this will not be
+// done before tapeout, as I started this project a week before the
+// deadline!
+
+`ifdef WHISK_DEFAULT_NETTYPE_NONE
+`default_nettype none
+`endif
+
+`ifndef WHISK_NO_CELLS
+`define WHISK_CELLS_SKY130
+`endif
+
+// ============================================================================
+// Module wren6991_whisk_tt2_io_wrapper: Top level for TT2 synthesis.
+// instantiate whisk_top, and map named ports to numbered TT2 inputs/outputs
+// ============================================================================
+
+module wren6991_whisk_tt2_io_wrapper (
+ input wire [7:0] io_in,
+ output wire [7:0] io_out
+);
+
+// Global signals
+wire io_clk = io_in[0];
+wire io_rst_n = io_in[1];
+
+// SPI memory interface
+wire io_mem_sdi = io_in[2];
+
+wire io_mem_csn;
+wire io_mem_sck;
+wire io_mem_sdo;
+
+assign io_out[0] = io_mem_csn;
+assign io_out[1] = io_mem_sck;
+assign io_out[2] = io_mem_sdo;
+
+wire io_retime_mem_out = io_in[4];
+wire [1:0] io_retime_mem_in = io_in[6:5];
+
+// IO port (shift register interface)
+wire io_ioport_sdi = io_in[3];
+
+wire io_ioport_sck;
+wire io_ioport_sdo;
+wire io_ioport_latch_i;
+wire io_ioport_latch_o;
+
+assign io_out[3] = io_ioport_sck;
+assign io_out[4] = io_ioport_sdo;
+assign io_out[5] = io_ioport_latch_i;
+assign io_out[6] = io_ioport_latch_o;
+
+// Be a good neighbour
+assign io_out[7] = 1'b0;
+
+whisk_top top_u (
+ .io_clk (io_clk),
+ .io_rst_n (io_rst_n),
+
+ .io_mem_sdi (io_mem_sdi),
+ .io_mem_csn (io_mem_csn),
+ .io_mem_sck (io_mem_sck),
+ .io_mem_sdo (io_mem_sdo),
+
+ .io_retime_mem_out (io_retime_mem_out),
+ .io_retime_mem_in (io_retime_mem_in),
+
+ .io_ioport_sdi (io_ioport_sdi),
+ .io_ioport_sck (io_ioport_sck),
+ .io_ioport_sdo (io_ioport_sdo),
+ .io_ioport_latch_i (io_ioport_latch_i),
+ .io_ioport_latch_o (io_ioport_latch_o)
+);
+
+endmodule
+
+// ============================================================================
+// Module whisk_top: instantiate the CPU core together with the SPI mem
+// serdes and IO port serdes.
+// ============================================================================
+
+module whisk_top (
+ input wire io_clk,
+ input wire io_rst_n,
+
+ input wire io_mem_sdi,
+ output wire io_mem_csn,
+ output wire io_mem_sck,
+ output wire io_mem_sdo,
+
+ input wire io_retime_mem_out,
+ input wire [1:0] io_retime_mem_in,
+
+ input wire io_ioport_sdi,
+ output wire io_ioport_sck,
+ output wire io_ioport_sdo,
+ output wire io_ioport_latch_i,
+ output wire io_ioport_latch_o
+);
+
+// ----------------------------------------------------------------------------
+// Clock/reset wrangling
+
+// Don't buffer the clock -- seems like the scripts define a clock on io_in[0]?
+wire clk = io_clk;
+
+// Synchronise reset removal to clk
+reg [1:0] reset_sync;
+wire rst_n = reset_sync[1];
+
+always @ (posedge clk or negedge io_rst_n) begin
+ if (!io_rst_n) begin
+ reset_sync <= 2'd00;
+ end else begin
+ reset_sync <= ~(~reset_sync << 1);
+ end
+end
+
+// ----------------------------------------------------------------------------
+// Processor instantiation
+
+wire mem_sck_en_next;
+wire mem_sdo_next;
+wire mem_csn_next;
+wire mem_sdi_prev;
+
+wire ioport_sck_en_next;
+wire ioport_sdo_next;
+wire ioport_sdi_prev;
+wire ioport_latch_i_next;
+wire ioport_latch_o_next;
+
+whisk_cpu cpu (
+ .clk (clk),
+ .rst_n (rst_n),
+
+ .mem_sck_en_next (mem_sck_en_next),
+ .mem_sdo_next (mem_sdo_next),
+ .mem_csn_next (mem_csn_next),
+ .mem_sdi_prev (mem_sdi_prev),
+
+ .ioport_sck_en_next (ioport_sck_en_next),
+ .ioport_sdo_next (ioport_sdo_next),
+ .ioport_sdi_prev (ioport_sdi_prev),
+ .ioport_latch_i_next (ioport_latch_i_next),
+ .ioport_latch_o_next (ioport_latch_o_next)
+);
+
+// ----------------------------------------------------------------------------
+// Serdes (IO registers)
+
+whisk_spi_serdes mem_serdes_u (
+ .clk (clk),
+ .rst_n (rst_n),
+
+ .sdo (mem_sdo_next),
+ .sck_en (mem_sck_en_next),
+ .csn (mem_csn_next),
+ .sdi (mem_sdi_prev),
+
+ .padout_sck (io_mem_sck),
+ .padout_csn (io_mem_csn),
+ .padout_sdo (io_mem_sdo),
+ .padin_sdi (io_mem_sdi),
+
+ .padin_retime_mem_out (io_retime_mem_out),
+ .padin_retime_mem_in (io_retime_mem_in),
+);
+
+whisk_ioport_serdes io_serdes_u (
+ .clk (clk),
+ .rst_n (rst_n),
+
+ .sdo (ioport_sdo_next),
+ .sck_en (ioport_sck_en_next),
+ .latch_i (ioport_latch_i_next),
+ .latch_o (ioport_latch_o_next),
+ .sdi (ioport_sdi_prev),
+
+ .padout_sdo (io_ioport_sdo),
+ .padout_sck (io_ioport_sck),
+ .padout_latch_i (io_ioport_latch_i),
+ .padout_latch_o (io_ioport_latch_o),
+ .padin_sdi (io_ioport_sdi)
+);
+
+endmodule
+
+// ============================================================================
+// Module whisk_cpu: top-level for the Whisk processor, minus the IO wrapper
+// and the SPI/IOPORT serdes
+// ============================================================================
+
+module whisk_cpu (
+ input wire clk,
+ input wire rst_n,
+
+ // SPI SRAM interface
+ output wire mem_sck_en_next,
+ output wire mem_sdo_next,
+ output wire mem_csn_next,
+ input wire mem_sdi_prev,
+
+ // Shift registers for IO port
+ output wire ioport_sck_en_next,
+ output wire ioport_sdo_next,
+ input wire ioport_sdi_prev,
+ output wire ioport_latch_i_next,
+ output wire ioport_latch_o_next
+);
+
+// ----------------------------------------------------------------------------
+// Constants
+
+// Machine size
+localparam W_INSTR = 16;
+localparam W_DATA = 16;
+localparam N_REGS = 6;
+
+// Instruction layout
+localparam INSTR_OP_LSB = 0;
+localparam INSTR_OP_MSB = 3;
+localparam INSTR_COND_LSB = 4;
+localparam INSTR_COND_MSB = 6;
+localparam INSTR_RT_LSB = 7;
+localparam INSTR_RT_MSB = 9;
+localparam INSTR_RS_LSB = 10;
+localparam INSTR_RS_MSB = 12;
+localparam INSTR_RD_LSB = 13;
+localparam INSTR_RD_MSB = 15;
+
+// Major opcodes (instr[3:0])
+localparam [3:0] OP_ADD = 4'h0; // rd = rs + rt
+localparam [3:0] OP_SUB = 4'h1; // rd = rs - rt
+localparam [3:0] OP_AND = 4'h2; // rd = rs & rt
+localparam [3:0] OP_ANDN = 4'h3; // rd = rs & ~rt
+localparam [3:0] OP_OR = 4'h4; // rd = rs | rt
+localparam [3:0] OP_SHIFT = 4'h5; // Minor opcode in rt
+localparam [3:0] OP_INOUT = 4'h6; // Minor opcode in rs
+
+localparam [3:0] OP_LB = 4'h8; // rd = mem[rs ];
+localparam [3:0] OP_LH_IA = 4'h9; // rd = mem[rs ]; rs += rt;
+localparam [3:0] OP_LH_ADD = 4'ha; // rd = mem[rs + rt];
+localparam [3:0] OP_LH_IB = 4'hb; // rd = mem[rs + rt]; rs += rt;
+
+localparam [3:0] OP_SB = 4'hc; // mem[rs ] = rd;
+localparam [3:0] OP_SH_IA = 4'hd; // mem[rs ] = rd; rs += rt;
+localparam [3:0] OP_SH_ADD = 4'he; // mem[rs + rt] = rd;
+localparam [3:0] OP_SH_IB = 4'hf; // mem[rs + rt] = rd; rs += rt;
+
+// Minor opcodes (rt)
+localparam [2:0] OP2_SRL = 3'h0;
+localparam [2:0] OP2_SRA = 3'h1;
+localparam [2:0] OP2_SLL = 3'h4;
+
+// Minor opcodes (rs)
+localparam [2:0] OP2_IN = 3'h0;
+localparam [2:0] OP2_OUT = 3'h4;
+
+// ----------------------------------------------------------------------------
+// Main control state machine
+
+reg [W_INSTR-1:0] instr;
+
+wire [INSTR_OP_MSB -INSTR_OP_LSB :0] instr_op;
+wire [INSTR_COND_MSB-INSTR_COND_LSB:0] instr_cond;
+wire [INSTR_RT_MSB -INSTR_RT_LSB :0] instr_rt;
+wire [INSTR_RS_MSB -INSTR_RS_LSB :0] instr_rs;
+wire [INSTR_RD_MSB -INSTR_RD_LSB :0] instr_rd;
+
+assign {instr_rd, instr_rs, instr_rt, instr_cond, instr_op} = instr;
+
+wire instr_op_ls = instr_op[3]; // Whether an instruction is a load/store
+wire instr_op_st_nld = instr_op[2]; // Whether a load/store is a load or store
+wire instr_op_ls_suma = instr_op[1]; // Whether sum is used for address
+wire instr_op_ls_sumr = instr_op[0]; // Whether sum is written back to register
+
+reg [3:0] bit_ctr;
+reg [2:0] state;
+reg instr_cond_true;
+reg instr_has_imm_operand;
+
+
+// Note there is a 2 cycle delay from issuing a bit on SDO to getting a bit
+// back on SDI. This is handled with a 1-cycle gap after issuing a read
+// address, so that e.g. S_FETCH always has the first instruction bit
+// available on the first cycle.
+
+localparam [2:0] S_FETCH = 3'd0; // Sample 16 instr bits, increment PC
+localparam [2:0] S_EXEC = 3'd1; // Loop all GPRs, write one GPR
+localparam [2:0] S_PC_NONSEQ0 = 3'd2; // Issue cmd, then issue 1 PC bit
+localparam [2:0] S_PC_NONSEQ1 = 3'd3; // Issue rest of PC, then 1 cyc delay
+localparam [2:0] S_LS_ADDR0 = 3'd4; // Deferred LS SPI cmd following immediate
+localparam [2:0] S_LS_ADDR1 = 3'd5; // Issue addr then, if load, 1 cyc delay
+localparam [2:0] S_LS_DATA = 3'd6; // Issue store data, or sample load data
+localparam [2:0] S_SKIP_IMM = 3'd7; // Skip immediate following false condition
+
+reg [2:0] state_nxt_wrap;
+reg [2:0] state_nxt;
+
+always @ (*) begin
+ state_nxt_wrap = state;
+ case (state)
+ S_FETCH: begin
+ if (!instr_cond_true) begin
+ if (instr_has_imm_operand) begin
+ state_nxt_wrap = S_SKIP_IMM;
+ end else begin
+ state_nxt_wrap = S_FETCH;
+ end
+ end else begin
+ state_nxt_wrap = S_EXEC;
+ end
+ end
+ S_EXEC: begin
+ if (instr_op_ls && instr_has_imm_operand) begin
+ // Command was deferred due to immediate read keeping SPI busy
+ state_nxt_wrap = S_LS_ADDR0;
+ end else if (instr_op_ls) begin
+ // Command was issued concurrently, skip straight to address issue
+ state_nxt_wrap = S_LS_ADDR1;
+ end else if (instr_rd == 3'd7) begin
+ state_nxt_wrap = S_PC_NONSEQ0;
+ end else begin
+ state_nxt_wrap = S_FETCH;
+ end
+ end
+ S_PC_NONSEQ0: begin
+ state_nxt_wrap = S_PC_NONSEQ1;
+ end
+ S_PC_NONSEQ1: begin
+ if (!instr_cond_true) begin
+ // Have just been reset, instr is invalid
+ state_nxt_wrap = S_FETCH;
+ end else begin
+ state_nxt_wrap = S_FETCH;
+ end
+ end
+ S_LS_ADDR0: begin
+ state_nxt_wrap = S_LS_ADDR1;
+ end
+ S_LS_ADDR1: begin
+ state_nxt_wrap = S_LS_DATA;
+ end
+ S_LS_DATA: begin
+ state_nxt_wrap = S_PC_NONSEQ0;
+ end
+ S_SKIP_IMM: begin
+ state_nxt_wrap = S_FETCH;
+ end
+ endcase
+ state_nxt = &bit_ctr ? state_nxt_wrap : state;
+end
+
+// Start of day:
+//
+// - The only resettable flops are state, bit_ctr, and instr_cond_true.
+//
+// - We reset state/bit_ctr to a nonsequential fetch, and reset
+// instr_cond_true=0 (usually unreachable)
+//
+// - instr_cond_true=0 masks the fetch address to 0, regardless of PC
+//
+// - The first instruction must be `add pc, zero, #4` to initialise PC
+
+always @ (posedge clk or negedge rst_n) begin
+ if (!rst_n) begin
+ state <= S_PC_NONSEQ0;
+ bit_ctr <= 4'h0;
+ end else begin
+ state <= state_nxt;
+ bit_ctr <= bit_ctr + 4'h1;
+ end
+end
+
+// ----------------------------------------------------------------------------
+// Instruction shifter and early decode
+
+always @ (posedge clk) begin
+ if (state == S_FETCH) begin
+ instr <= {mem_sdi_prev, instr[15:1]};
+ end
+end
+
+// Decode condition and imm operand flags as the instruction comes in, so we
+// can use them to steer the state machine at the end of S_FETCH.
+
+reg instr_has_imm_operand_nxt;
+reg instr_cond_true_nxt;
+
+// From ALU:
+wire [7:0] condition_vec8;
+
+always @ (*) begin
+ instr_has_imm_operand_nxt = instr_has_imm_operand;
+ instr_cond_true_nxt = instr_cond_true;
+
+ if (instr_has_imm_operand && !instr_cond_true) begin
+ // In this case we must be in S_FETCH. Hold instr_cond_true for an
+ // additional fetch cycle so that the immediate operand is also
+ // dumped, but clear the operand flag so we don't loop forever.
+ if (&bit_ctr) begin
+ instr_has_imm_operand_nxt = 1'b0;
+ end
+ end else if (state == S_FETCH) begin
+ if (bit_ctr == (INSTR_RT_MSB + 1)) begin
+ // Grab rt as it goes past (this is why rt is not the MSBs!)
+ instr_has_imm_operand_nxt = instr[W_INSTR-1 -: 3] == 3'd7;
+ end
+ if (bit_ctr == (INSTR_COND_MSB + 1)) begin
+ // Decode condition as it goes past
+ instr_cond_true_nxt = condition_vec8[instr[W_INSTR-1 -: 3]];
+ end
+ end
+end
+
+// instr_cond_true must reset to 0, because we use it to recognise the first
+// fetch after reset. We don't care about instr_has_imm_operand, because it
+// is initialised during S_FETCH before first use.
+
+always @ (posedge clk or negedge rst_n) begin
+ if (!rst_n) begin
+ instr_cond_true <= 1'b0;
+ end else begin
+ instr_cond_true <= instr_cond_true_nxt;
+ end
+end
+
+always @ (posedge clk) begin
+ instr_has_imm_operand <= instr_has_imm_operand_nxt;
+end
+
+// ----------------------------------------------------------------------------
+// Register file
+
+wire reg_rd_qr;
+wire reg_rs_qr, reg_rs_qr_next;
+wire reg_rt_qr;
+
+wire alu_result;
+
+wire writeback_wen =
+ state == S_EXEC && !(instr_op_ls && !instr_op_ls_sumr) ||
+ state == S_LS_DATA && !instr_op_st_nld;
+
+wire writeback_data = alu_result;
+
+wire [INSTR_RD_MSB-INSTR_RD_LSB:0] writeback_reg =
+ instr_op_ls && state != S_LS_DATA ? instr_rs : instr_rd;
+
+whisk_regfile #(
+ .W (W_DATA),
+ .N (N_REGS)
+) regfile_u (
+ .clk (clk),
+
+ .rd (writeback_reg),
+ .rd_q (reg_rd_qr),
+ .rd_wen (writeback_wen),
+ .rd_d (writeback_data),
+
+ .rs (instr_rs),
+ .rs_q (reg_rs_qr),
+ .rs_q_next (reg_rs_qr_next),
+
+ .rt (instr_rt),
+ .rt_q (reg_rt_qr)
+);
+
+// ----------------------------------------------------------------------------
+// Program counter
+
+wire pc_dl;
+wire pc_qr;
+
+wire [15:0] pc_q_all;
+wire pc_qr_next = pc_q_all[1];
+
+whisk_shiftreg_right #(
+ .W (16)
+) pc_u (
+ .clk (clk),
+ .dl (pc_dl),
+ .q_all (pc_q_all),
+ .qr (pc_qr)
+);
+
+wire pc_increment =
+ state == S_FETCH ||
+ state == S_EXEC && instr_has_imm_operand ||
+ state == S_SKIP_IMM;
+
+reg pc_ci;
+wire pc_co, pc_sum;
+
+assign {pc_co, pc_sum} = pc_qr + (~|bit_ctr[3:1] ? bit_ctr[0] && pc_increment : pc_ci);
+
+always @ (posedge clk) begin
+ pc_ci <= pc_co;
+end
+
+wire rd_is_pc = instr_rd == 3'd7;
+
+assign pc_dl =
+ state == S_EXEC && rd_is_pc ? alu_result :
+ state == S_LS_DATA && rd_is_pc && !instr_op_st_nld ? mem_sdi_prev : pc_sum;
+
+// ----------------------------------------------------------------------------
+// ALU
+
+wire alu_op_s =
+ instr_rs == 3'd7 ? pc_qr : reg_rs_qr;
+
+wire alu_op_s_next =
+ instr_rs == 3'd7 ? pc_qr_next : reg_rs_qr_next;
+
+wire alu_op_t =
+ instr_rt == 3'd7 ? mem_sdi_prev : reg_rt_qr;
+
+reg alu_ci;
+wire [1:0] alu_add = alu_op_s + alu_op_t + (~|bit_ctr ? 1'b0 : alu_ci);
+wire [1:0] alu_sub = alu_op_s + !alu_op_t + (~|bit_ctr ? 1'b1 : alu_ci);
+
+// Left shift uses the carry flop as a 1-cycle delay, counter to the
+// register's rightward rotation. Right shift looks ahead to advance its
+// rotation. The final carry flag is the bit shifted "out of" the register.
+
+wire [1:0] alu_shift_l = {
+ alu_op_s,
+ |alu_ci && |bit_ctr
+};
+
+wire [1:0] alu_shift_r = {
+ |bit_ctr ? alu_ci : alu_op_s,
+ &bit_ctr ? alu_op_s && instr_rt[0] : alu_op_s_next
+};
+
+// Carry is an all-ones flag for bitwise ops
+wire bit_co = alu_result && (alu_ci || ~|bit_ctr);
+
+// Byte loads must be zero- or sign-extended. Use the carry to
+// propagate the sign.
+wire instr_op_ls_byte = !(instr_op_ls_sumr || instr_op_ls_suma);
+wire instr_op_ls_sbyte = instr_rt[2];
+
+wire [1:0] alu_load = {
+ bit_ctr[3] ? alu_ci : mem_sdi_prev,
+ bit_ctr[3] && instr_op_ls_byte ? alu_ci && instr_op_ls_sbyte : mem_sdi_prev
+};
+
+wire alu_co;
+assign {alu_co, alu_result} =
+ state == S_LS_DATA ? alu_load :
+ instr_op_ls ? alu_add :
+ instr_op == OP_ADD ? alu_add :
+ instr_op == OP_SUB ? alu_sub :
+ instr_op == OP_AND ? {bit_co, alu_op_s && alu_op_t} :
+ instr_op == OP_ANDN ? {bit_co, alu_op_s && !alu_op_t} :
+ instr_op == OP_OR ? {bit_co, alu_op_s || alu_op_t} :
+ instr_op == OP_SHIFT && instr_rt[2] ? alu_shift_l :
+ instr_op == OP_SHIFT && !instr_rt[2] ? alu_shift_r :
+ instr_op == OP_INOUT ? ioport_sdi_prev : alu_add;
+
+always @ (posedge clk) begin
+ alu_ci <= alu_co;
+end
+
+// ----------------------------------------------------------------------------
+// Flags
+
+reg flag_z;
+reg flag_c;
+reg flag_n;
+
+wire update_flags = (state == S_EXEC || state == S_LS_DATA) && ~|instr_cond;
+
+always @ (posedge clk) begin
+ if (update_flags) begin
+ flag_z <= (flag_z || ~|bit_ctr) && !alu_result;
+ flag_n <= alu_result;
+ flag_c <= alu_co;
+ end
+end
+
+assign condition_vec8 = {
+ !flag_z, flag_z,
+ !flag_c, flag_c,
+ !flag_n, flag_n,
+ 1'b1, 1'b1
+};
+
+// ----------------------------------------------------------------------------
+// Address register
+
+// Captures address calculations LSB-first and then replays them MSB-first.
+
+wire ar_l_nr;
+wire ar_dl;
+wire ar_dr;
+wire ar_ql;
+wire ar_qr;
+
+// Need to look ahead by one bit to get correct timing for read addresses:
+wire [15:0] ar_q_all;
+wire ar_ql_next = ar_q_all[14];
+
+whisk_shiftreg_leftright #(
+ .W (16)
+) ar_u (
+ .clk (clk),
+ .l_nr (ar_l_nr),
+ .dl (ar_dl),
+ .ql (ar_ql),
+ .dr (ar_dr),
+ .qr (ar_qr),
+ .q_all (ar_q_all)
+);
+
+// Shift left when replaying addresses. Also shift left in LS_ADDR0 to
+// recirculate the address generated during EXEC for use in LS_ADDR1.
+assign ar_l_nr =
+ state == S_LS_ADDR1 ||
+ state == S_PC_NONSEQ1 ||
+ state == S_LS_ADDR0;
+
+assign ar_dr = ar_ql;
+
+assign ar_dl =
+ state == S_PC_NONSEQ0 ? pc_qr :
+ instr_op_ls_suma ? alu_add : reg_rs_qr;
+// ----------------------------------------------------------------------------
+// SPI controls
+
+// Deassert CSn before issuing a nonsequential address.
+
+// Note LS_ADDR0 state is skipped if we are able to issue from EXEC:
+wire issue_ls_addr_ph0 =
+ state == S_LS_ADDR0 ||
+ state == S_EXEC && instr_op_ls && !instr_has_imm_operand && instr_cond_true;
+
+wire [3:0] spi_cmd_start_cycle =
+ state == S_PC_NONSEQ0 ? 4'h7 :
+ instr_op_st_nld ? 4'h8 : 4'h7;
+
+assign mem_csn_next = bit_ctr < spi_cmd_start_cycle && (
+ state == S_PC_NONSEQ0 || issue_ls_addr_ph0
+);
+
+// Pedal to the metal on SCK except when pulling CSn for a nonsequential
+// access, or when executing an unskipped instruction without immediate or
+// early address issue. (Also mask for second half of byte accesses.)
+
+wire mem_sck_disable_on_imm =
+ state == (&bit_ctr[3:1] ? S_FETCH : S_EXEC) && instr_cond_true &&
+ !(instr_has_imm_operand || issue_ls_addr_ph0);
+
+wire mem_sck_disable_on_byte_ls =
+ state == S_LS_DATA && instr_op_ls_byte && bit_ctr[3];
+
+assign mem_sck_en_next = !(
+ mem_csn_next ||
+ mem_sck_disable_on_imm ||
+ mem_sck_disable_on_byte_ls
+);
+
+// Store address replays entirely in LS_ADDR1, but load/fetch extend one cycle
+// into previous state, so carefully pick what delay to observe the address
+// with. (Also mask address to zero for very first fetch at start of day.)
+//
+// Note in LS_ADDR0 that we are actually recirculating an address generated in
+// EXEC, because the address issue was deferred due to an immediate read, so
+// this case looks like load-LS_ADDR1 rather than like load-EXEC.
+
+wire mem_spi_addr =
+ !instr_cond_true ? 1'b0 :
+ state == S_PC_NONSEQ1 ? ar_ql_next :
+ state == S_LS_ADDR1 && instr_op_st_nld ? ar_ql :
+ state == S_LS_ADDR1 && !instr_op_st_nld ? ar_ql_next :
+ state == S_LS_ADDR0 ? ar_ql_next : ar_dl;
+
+// Note: SPI commands are MSB-first (the commands here are 03h and 02h).
+localparam [15:0] SPI_INSTR_READ = 16'hc000 >> 1;
+localparam [15:0] SPI_INSTR_WRITE = 16'h4000;
+
+wire mem_sdo_ls_addr_ph0 =
+ instr_op_st_nld ? SPI_INSTR_WRITE[bit_ctr] :
+ &bit_ctr ? mem_spi_addr : SPI_INSTR_READ[bit_ctr];
+
+assign mem_sdo_next =
+ state == S_PC_NONSEQ0 ? (&bit_ctr ? pc_qr : SPI_INSTR_READ[bit_ctr]) :
+ state == S_PC_NONSEQ1 ? mem_spi_addr :
+ issue_ls_addr_ph0 ? mem_sdo_ls_addr_ph0 :
+ state == S_LS_ADDR1 ? mem_spi_addr :
+ state == S_LS_DATA ? (instr_rd == 3'd7 ? pc_qr : reg_rd_qr) : 1'b0;
+
+// ----------------------------------------------------------------------------
+// IO port
+
+// Expected hardware is a 1x 8-bit PISO, and 2x 8-bit SIPO shift registers:
+//
+// - OUT: Clock out 16 bits from rt[15:0]/imm[15:0], then pulse latch_o high.
+//
+// - IN: Clock 8 bits into rd[15:8], with latch_i low for the first clock.
+//
+// The IN interface is still driven when executing an OUT, with more clocks.
+// Abusable for 6 extra inputs if a second PISO register is chained.
+//
+// rt[13:6] is actually clocked out on an IN, there's just no latch_o pulse.
+// Abusable to drive longer SIPO chains using multiple INs and a final OUT.
+
+wire exec_io_instr = state == S_EXEC && instr_op == OP_INOUT;
+wire io_instr_out = (instr_rs & (OP2_OUT | OP2_IN)) == OP2_OUT;
+
+// The instruction is still valid on the first cycle of FETCH. This lets us
+// latch outputs *after* the last clock pulse, without spending a flop.
+assign ioport_latch_o_next = state == S_FETCH && ~|bit_ctr &&
+ instr_op == OP_INOUT && io_instr_out && instr_cond_true;
+
+assign ioport_latch_i_next = !(exec_io_instr && bit_ctr == 4'h6);
+
+assign ioport_sdo_next = exec_io_instr && alu_op_t;
+
+assign ioport_sck_en_next = exec_io_instr && (
+ (bit_ctr >= 4'h6 && bit_ctr < 4'he) ||
+ io_instr_out
+);
+
+endmodule
+
+// ============================================================================
+// Module whisk_regfile: a register file of multiple shift registers, with 3
+// read ports (rd/rs/rt) and one write port (rd).
+// ============================================================================
+
+// All registers rotate right by one bit every cycle. No enable, so do things
+// in multiples of 16 cycles. Registers not written to are recirculated.
+//
+// q is the value of the rightmost flop in each register. The rs port also has
+// a q_next value, which taps in one flop from the end, and is required for
+// performing right-shift-by-one in 16 cycles.
+//
+// Out-of-range indices read as 0, and ignore writes.
+
+module whisk_regfile #(
+ parameter W = 16,
+ parameter N = 6
+) (
+ input wire clk,
+
+ input wire [$clog2(N)-1:0] rd,
+ output wire rd_q,
+ input wire rd_wen,
+ input wire rd_d,
+
+ input wire [$clog2(N)-1:0] rs,
+ output wire rs_q,
+ output wire rs_q_next,
+
+ input wire [$clog2(N)-1:0] rt,
+ output wire rt_q,
+);
+
+localparam N_PADDED = 1 << $clog2(N);
+
+wire [N-1:0] d;
+wire [N-1:0] d;
+wire [W-1:0] q [N_PADDED-1:0];
+
+assign rd_q = q[rd][0];
+assign rs_q = q[rs][0];
+assign rs_q_next = q[rs][1];
+assign rt_q = q[rt][0];
+
+genvar g;
+generate
+for (g = 0; g < N_PADDED; g = g + 1) begin: loop_gprs
+ if (g >= N) begin: gpr_tieoff
+
+ assign q[g] = {W{1'b0}};
+
+ end else begin: gpr_shifter
+
+ // Recirculate unless register is addressed as rd.
+ wire qr;
+ assign d[g] = rd_wen && rd == g ? rd_d : qr;
+
+ whisk_shiftreg_right #(
+ .W (W)
+ ) reg_u (
+ .clk (clk),
+ .dl (d[g]),
+ .qr (qr),
+ .q_all (q[g])
+ );
+
+ end
+end
+endgenerate
+
+endmodule
+
+// ============================================================================
+// Module whisk_shiftreg_leftright: a shift register that always shifts left
+// or right each cycle.
+// ============================================================================
+
+// Note there is no enable because the underlying scan flops do not have an
+// enable (there is an enable version, but it's larger, and more routing
+// required!). If you don't want to shift, just shift back and forth for an
+// even number of cycles, or do a full loop :)
+//
+// dl and ql are the leftmost inputs and outputs. If l_nr is low (right), ql
+// becomes dl on every posedge of clk. (Yes, it's confusing!)
+//
+// dr and qr are the rightmost inputs and outputs. If l_nr is high (left), qr
+// becomes dr on every posedge of clk.
+
+module whisk_shiftreg_leftright #(
+ parameter W = 16
+) (
+ input wire clk,
+ input wire l_nr,
+ input wire dl,
+ input wire dr,
+ output wire ql,
+ output wire qr,
+ output wire [W-1:0] q_all
+);
+
+wire [W+1:0] chain_q;
+
+assign chain_q[0 ] = dr;
+assign chain_q[W + 1] = dl;
+
+assign qr = chain_q[1];
+assign ql = chain_q[W];
+assign q_all = chain_q[W:1];
+
+genvar g;
+generate
+for (g = 1; g < W + 1; g = g + 1) begin: shift_stage
+ // Shift-to-left means select the input to your right, and vice versa.
+ whisk_flop_scanmux flop_u (
+ .clk (clk),
+ .sel (l_nr),
+ .d ({chain_q[g - 1], chain_q[g + 1]}),
+ .q (chain_q[g])
+ );
+end
+endgenerate
+
+endmodule
+
+// ============================================================================
+// Module whisk_shiftreg_right: register that only shifts right, like Zoolander
+// ============================================================================
+
+// Cost per bit is lower than whisk_shiftreg_leftright
+
+module whisk_shiftreg_right #(
+ parameter W = 16
+) (
+ input wire clk,
+ input wire dl,
+ output wire qr,
+ output reg [W-1:0] q_all
+);
+
+always @ (posedge clk) begin
+ q_all <= {dl, q_all[W-1:1]};
+end
+
+assign qr = q_all[0];
+
+endmodule
+
+// ============================================================================
+// Module whisk_flop_scanmux: a flop with a mux on its input. Usually reserved
+// for DFT scan insertion, but we don't need that where we're going >:)
+// ============================================================================
+
+module whisk_flop_scanmux (
+ input wire clk,
+ input wire sel,
+ input wire [1:0] d,
+ output wire q
+);
+
+`ifdef WHISK_CELLS_SKY130
+
+// (scanchain in TT2 uses sky130_fd_sc_hd__sdfxtp, a simple flop with scan
+// mux. An enable version, sky130_fd_sc_hd__sedfxtp, is also available, but
+// this is significantly larger. Instantiate the unit-drive version because
+// we have a ridiculously long clock period; not sure whether the backend is
+// allowed to change the drive.)
+
+sky130_fd_sc_hd__sdfxtp_1 sdff_u (
+ .CLK (clk),
+ .D (d[0]),
+ .SCD (d[1]),
+ .SCE (sel),
+ .Q (q),
+ .VPWR (1'b1),
+ .VGND (1'b0)
+);
+
+`else
+
+// Synthesisable model
+
+reg q_r;
+always @ (posedge clk) begin
+ q_r <= d[sel];
+end
+
+assign q = q_r;
+
+`endif
+
+endmodule
+
+// ============================================================================
+// Module whisk_spi_serdes: handle the timing of the SPI interface, and
+// provide a slightly abstracted interface to the Whisk core
+// ============================================================================
+
+// Note the assumption in the core is that if it asserts the last address bit
+// by the end of cycle k then it can sample the first data bit at the end of
+// cycle k + 2.
+//
+// - clk posedge k: outputs are registered and go straight into scan chain
+// - clk negedge k: SCK rising edge for last address bit is launched into scan chain
+// - clk posedge k + 1: SCK falling edge following last address bit is launched into scan chain
+// - clk negedge k + 1: sample taken at falling SCK edge comes back through scan
+// - clk posedge k + 2: sample taken at SCK rising edge comes back through scan
+//
+// Unfortunately the sample coming back is not meaningfully constrained with
+// respect to clk, so we have some options to shmoo things around. The winner
+// is probably to launch our outputs a half cycle earlier (on the negedge) so
+// that the input is stable at the point the core samples it on its posedge.
+// This creates a half cycle path in the core, but the clock period is long
+// so we don't care. This is the default.
+//
+// Note without the scan problems the core's assumption about delay would be a
+// reasonable one.
+
+module whisk_spi_serdes(
+ input wire clk,
+ input wire rst_n,
+
+ // Core
+ input wire sdo,
+ input wire sck_en,
+ input wire csn,
+ output wire sdi,
+
+ // IOs
+ output wire padout_sck,
+ output wire padout_csn,
+ output wire padout_sdo,
+ input wire padin_sdi,
+
+ input wire padin_retime_mem_out,
+ input wire [1:0] padin_retime_mem_in
+);
+
+// ----------------------------------------------------------------------------
+// Output paths
+
+// There are multiple through-paths from the clock input to SPI outputs
+// (*mostly* via DFF CK-to-Q) and these should fully settle between the scan
+// input latches going transparent, and the outputs being registered back out
+// into the scan chain. We can't add IO constraints, but there are plenty of
+// wait states in the scan chain driver around this point. Hopefully on TT3
+// the scan chain stuff will go away and we can build a normal SPI
+// interface.
+
+reg sdo_pos_r;
+reg sck_en_pos_r;
+reg csn_pos_r;
+
+always @ (posedge clk or negedge rst_n) begin
+ if (!rst_n) begin
+ sdo_pos_r <= 1'b0;
+ sck_en_pos_r <= 1'b1;
+ csn_pos_r <= 1'b0;
+ end else begin
+ sdo_pos_r <= sdo;
+ sck_en_pos_r <= csn;
+ csn_pos_r <= sck_en;
+ end
+end
+
+// Through-path for clock input to SCK output. This *will* glitch, but gating
+// cell not required for TT2, as this signal is sampled by the scan flops at
+// the tile output.
+wire padout_sck_p = sck_en_pos_r && !clk;
+
+// Very dirty option to advance all outputs by a half cycle.
+
+reg sdo_neg_r;
+reg sck_en_neg_r;
+reg csn_neg_r;
+
+always @ (negedge clk or negedge rst_n) begin
+ if (!rst_n) begin
+ sdo_neg_r <= 1'b0;
+ csn_neg_r <= 1'b1;
+ sck_en_neg_r <= 1'b0;
+ end else begin
+ sdo_neg_r <= sdo;
+ csn_neg_r <= csn;
+ sck_en_neg_r <= sck_en;
+ end
+end
+
+wire padout_sck_n = sck_en_neg_r && clk;
+
+assign padout_sdo = padin_retime_mem_out ? sdo_pos_r : sdo_neg_r;
+assign padout_csn = padin_retime_mem_out ? csn_pos_r : csn_neg_r;
+// Literally a behavioural mux on a clock lmao
+assign padout_sck = padin_retime_mem_out ? padout_sck_p : padout_sck_n;
+
+// ----------------------------------------------------------------------------
+// Input paths
+
+// 4 options:
+// - 0: Nothing
+// - 1: Some delay buffers
+// - 2: An active-high latch after delay buffers
+// - 3: A negedge flop
+
+wire padin_sdi_delay;
+`ifdef WHISK_CELLS_SKY130
+wire [2:0] padin_sdi_delay_int;
+sky130_fd_sc_hd__dlymetal6s6s_1 delbuf[3:0] (
+ .A ({padin_sdi_delay_int, padin_sdi}),
+ .X ({padin_sdi_delay, padin_sdi_delay_int}),
+ .VPWR (1'b1),
+ .VGND (1'b0)
+);
+`else
+assign padin_sdi_delay = padin_sdi;
+`endif
+
+wire padin_sdi_delay = padin_sdi;
+
+reg sdi_latch;
+
+always @ (*) begin
+ if (clk) begin
+ sdi_latch <= padin_sdi_delay;
+ end
+end
+
+reg sdi_negedge;
+
+always @ (negedge clk) begin
+ sdi_negedge <= padin_sdi;
+end
+
+wire [3:0] sdi_retime_opt = {
+ sdi_negedge,
+ sdi_latch,
+ padin_sdi_delay,
+ padin_sdi
+};
+
+assign sdi = sdi_retime_opt[padin_retime_mem_in];
+
+endmodule
+
+// ============================================================================
+// Module whisk_ioport_serdes: similar to whisk_spi_serdes, but for the
+// shift-register-based IO port.
+// ============================================================================
+
+module whisk_ioport_serdes(
+ input wire clk,
+ input wire rst_n,
+
+ // Core
+ input wire sdo,
+ input wire sck_en,
+ input wire latch_i,
+ input wire latch_o,
+ output wire sdi,
+
+ // IOs
+ output wire padout_sdo,
+ output wire padout_sck,
+ output wire padout_latch_i,
+ output wire padout_latch_o,
+ input wire padin_sdi
+);
+
+// ----------------------------------------------------------------------------
+// Output paths
+
+reg sdo_r;
+reg sck_en_r;
+reg latch_i_r;
+reg latch_o_r;
+
+always @ (posedge clk or negedge rst_n) begin
+ if (!rst_n) begin
+ sdo_r <= 1'b0;
+ sck_en_r <= 1'b0;
+ latch_i_r <= 1'b0;
+ latch_o_r <= 1'b0;
+ end else begin
+ sdo_r <= sdo;
+ sck_en_r <= sck_en;
+ latch_i_r <= latch_i;
+ latch_o_r <= latch_o;
+ end
+end
+
+assign padout_sdo = sdo_r;
+assign padout_latch_i = latch_i_r;
+assign padout_latch_o = latch_o_r;
+
+// Again, no clock gating cell for TT2, but must revisit in future.
+assign padout_sck = sck_en_r && !clk;
+
+// ----------------------------------------------------------------------------
+// Input paths
+
+assign sdi = padin_sdi;
+
+endmodule
+
+// ============================================================================
+//
+// _ _ _
+// | | (_) | |
+// __ _| |__ _ ___| | __
+// \ \ /\ / / '_ \| / __| |/ /
+// \ V V /| | | | \__ \ <
+// \_/\_/ |_| |_|_|___/_|\_\
+//
+//
+// When I was 16 I designed a 7400-series breadboard processor called Fork,
+// with a language called Spoon. Now I'm 26 and I'm designing a processor
+// called Whisk. I wonder what I'll do when I grow up.
+//
+// Many mistakes were made in this ISA. What did you think? My aim with this
+// version of Whisk is to run enough software to discover exactly why my
+// instruction set is bad. Hopefully Tiny Tapeout 3 will bring faster IOs,
+// with 2D muxing instead of a scan chain, and then I can try getting some
+// serious software running on Whisk v2, at a few MHz instead of 12 kHz.
diff --git a/verilog/rtl/095_mcpi.v b/verilog/rtl/095_mcpi.v
new file mode 100644
index 0000000..d976b2e
--- /dev/null
+++ b/verilog/rtl/095_mcpi.v
@@ -0,0 +1,175 @@
+`default_nettype none
+
+// Top level io for this module should stay the same to fit into the scan_wrapper.
+// The pin connections within the user_module are up to you,
+// although (if one is present) it is recommended to place a clock on io_in[0].
+// This allows use of the internal clock divider if you wish.
+//
+// so, just somehow calculate x^2+y^2 with random
+// 0<x, y<1, and compare it with 1
+// using 8-bit fixed point, [7:0]x means x/2**8
+// 0.0039 resolution is really coarse...
+module regymm_mcpi(
+ input [7:0] io_in,
+ output reg [7:0] io_out
+);
+ wire clk = io_in[0];
+ wire rst = io_in[1];
+ wire [5:0]sw1 = io_in[7:2];
+
+ always @ (*) begin
+ io_out = 0;
+ case(sw1[1:0])
+ 0: io_out = cnt[7:0];
+ 1: io_out = cnt_in[7:0];
+ 2: io_out = {6'b0, cnt[0], cnt_in[0]};
+ endcase
+ end
+
+ reg [8:0]breg;
+ reg [7:0]breg2; // shouldn't exceed 7:0 because x^2<1 when 0<x<1
+ reg [7:0]x;
+
+ reg [3:0]mulin1;
+ reg [3:0]mulin2;
+ wire [7:0]mulout;
+ mul4_341521390605697619 mul_inst(
+ .a(mulin1),
+ .b(mulin2),
+ .c(mulout)
+ );
+
+ reg [7:0]addin1;
+ reg [7:0]addin2;
+ wire [8:0]addout;
+ assign addout = addin1 + addin2;
+
+ // not very random actually, should somehow
+ // receive seed from outside
+ reg [7:0]random = 8'h01;
+ always @ (posedge clk) begin
+ random <= {random[6:0], (random[7] ^ random[5] ^ random[4] ^ random[3])};
+ end
+
+ reg [3:0]sts;
+ reg [7:0]cnt;
+ reg [7:0]cnt_in;
+ always @ (posedge clk) begin
+ if (rst) begin
+ sts <= 0;
+ cnt <= 0;
+ cnt_in <= 0;
+ //x <= 0;
+ end else begin
+ if (sw1[5] == 0) begin
+ case (sts)
+ 0: begin
+ breg <= 0;
+ x <= random;
+ end
+ 4: begin
+ x <= random;
+ breg2 <= breg_in;
+ end
+ 9: begin
+ cnt <= cnt + 1;
+ if (addout[8]) cnt_in <= cnt_in + 1;
+ end
+ endcase
+ sts <= sts == 10 ? 0 : sts + 1;
+ breg <= breg_in;
+ end
+ end
+ end
+
+ reg [8:0]breg_in;
+ always @ (*) begin
+ mulin1 = 0;
+ mulin2 = 0;
+ addin1 = 0;
+ addin2 = 0;
+ breg_in = 0;
+ if (sts == 9) begin
+ addin1 = breg;
+ addin2 = breg2;
+ end else begin
+ case(sts[1:0])
+ 2'b01: begin
+ mulin1 = x[3:0];
+ mulin2 = x[3:0];
+ breg_in = {1'b0, mulout};
+ end
+ 2'b10: begin
+ mulin1 = x[7:4];
+ mulin2 = x[3:0];
+ addin1 = {4'b0, breg[7:4]};
+ addin2 = mulout;
+ breg_in = addout;
+ end
+ 2'b11: begin
+ mulin1 = x[3:0];
+ mulin2 = x[7:4];
+ addin1 = breg[7:0];
+ addin2 = mulout;
+ breg_in = addout;
+ end
+ 2'b00: begin
+ mulin1 = x[7:4];
+ mulin2 = x[7:4];
+ addin1 = {3'b0, breg[8:4]};
+ addin2 = mulout;
+ breg_in = addout;
+ end
+ endcase
+ end
+ end
+endmodule
+
+module add_341521390605697619
+#(parameter WIDTH = 8)
+(
+ input [WIDTH-1:0]a,
+ input [WIDTH-1:0]b,
+ output [WIDTH:0]c
+);
+assign c = a + b;
+endmodule
+
+module mul4_341521390605697619
+(
+ input [3:0] a,
+ input [3:0] b,
+ output [7:0] c
+);
+wire [3:0]x = b[0] ? a : 0;
+wire [3:0]y = b[1] ? a : 0;
+wire [3:0]z = b[2] ? a : 0;
+wire [3:0]t = b[3] ? a : 0;
+
+assign c = {
+ add3,
+ add2[0],
+ add1[0],
+ x[0]
+ };
+wire [4:0]add1;
+add_341521390605697619 #(.WIDTH(4)) add_1(
+ .a({1'b0, x[3:1]}),
+ .b(y),
+ .c(add1)
+);
+
+wire [4:0]add2;
+add_341521390605697619 #(.WIDTH(4)) add_2(
+ .a(add1[4:1]),
+ .b(z),
+ .c(add2)
+);
+
+wire [4:0]add3;
+add_341521390605697619 #(.WIDTH(4)) add_3(
+ .a(add2[4:1]),
+ .b(t),
+ .c(add3)
+);
+endmodule
diff --git a/verilog/rtl/096_funnyblinky.v b/verilog/rtl/096_funnyblinky.v
new file mode 100644
index 0000000..d47c43a
--- /dev/null
+++ b/verilog/rtl/096_funnyblinky.v
@@ -0,0 +1,94 @@
+`default_nettype none
+
+// Top level io for this module should stay the same to fit into the scan_wrapper.
+// The pin connections within the user_module are up to you,
+// although (if one is present) it is recommended to place a clock on io_in[0].
+// This allows use of the internal clock divider if you wish.
+module regymm_funnyblinky(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+ wire clk25 = io_in[0];
+ wire rst = io_in[1];
+
+ wire sw_switch = io_in[7];
+
+ // for funny
+ wire [2:0]sw1 = io_in[4:2];
+
+ // for counter
+ wire [1:0]sw_outctrl = io_in[5:4];
+ wire sw_pause = io_in[6];
+ wire signal1 = io_in[2];
+ wire signal2 = io_in[3];
+ reg sig1r;
+ reg sig2r;
+ reg sig1rr;
+ reg sig2rr;
+
+ reg [13:0]cnt = 0;
+ reg [13:0]cnt2 = 0;
+ always @ (posedge clk25) begin
+ sig1r <= signal1;
+ sig2r <= signal2;
+ sig1rr <= sig1r;
+ sig2rr <= sig2r;
+ if (sw_switch) begin
+ if (rst) begin
+ cnt <= 0;
+ cnt2 <= 0;
+ end else begin
+ if (!sw_pause) begin
+ if (sig1r != sig1rr) cnt <= cnt + 1;
+ if (sig2r != sig2rr) cnt2 <= cnt2 + 1;
+ end
+ end
+ end else begin
+ cnt <= cnt + 1;
+ end
+ end
+ wire clkslow = cnt[3 + sw1];
+ reg [6:0]cntslow = 0;
+ reg [2:0]cntf = 0;
+ always @ (posedge clkslow) begin
+ cntslow <= cntslow == 105 ? 0 : cntslow + 1;
+ if (!cntslow[0]) begin
+ if (cntslow >= 73) begin
+ cntf <= cntf == 4 ? 0 : cntf + 1;
+ end else
+ cntf <= 0;
+ end
+ end
+ reg [2:0]finalpos;
+ always @ (*) begin
+ finalpos = 0;
+ case (cntf)
+ 0: finalpos = 2;
+ 1: finalpos = 6;
+ 2: finalpos = 0;
+ 3: finalpos = 3;
+ 4: finalpos = 5;
+ endcase
+ end
+ reg [7:0]io_out_funny;
+ reg [7:0]io_out_cnter;
+ always @ (*) begin
+ io_out_funny = 0;
+ if (cntslow >= 1 && cntslow <= 8) io_out_funny = 8'b11111111 << (8 - cntslow);
+ else if (cntslow >= 9 && cntslow <= 17) io_out_funny = 8'b11111111 << (cntslow - 9);
+ else if (cntslow >= 18 && cntslow <= 25) io_out_funny = 8'b10000000 >> (cntslow - 18);
+ else if (cntslow >= 26 && cntslow <= 33) io_out_funny = 8'b00000001 << (cntslow - 26);
+ else if (cntslow >= 35 && cntslow <= 55) io_out_funny = cntslow[0] ? 8'b00000000 : 8'b11111111;
+ else if (cntslow >= 56 && cntslow <= 72) io_out_funny = cntslow[0] ? 8'b11110000 : 8'b00001111;
+ else if (cntslow >= 73 && cntslow[0] == 0) io_out_funny = 8'b10000000 >> finalpos;
+
+ io_out_cnter = 0;
+ case (sw_outctrl)
+ 2'b00: io_out_cnter = cnt[7:0];
+ 2'b01: io_out_cnter = {2'b0, cnt[13:8]};
+ 2'b10: io_out_cnter = cnt2[7:0];
+ 2'b11: io_out_cnter = {2'b0, cnt2[13:8]};
+ endcase
+ end
+ assign io_out = sw_switch ? io_out_cnter : io_out_funny;
+endmodule
diff --git a/verilog/rtl/097_gps_ca_prn.v b/verilog/rtl/097_gps_ca_prn.v
new file mode 100644
index 0000000..c3e6412
--- /dev/null
+++ b/verilog/rtl/097_gps_ca_prn.v
@@ -0,0 +1,291 @@
+/* Generated by Yosys 0.22+1 (git sha1 c4a52b1b0, clang 14.0.0-1ubuntu1 -fPIC -Os) */
+
+module adamgreig_tt02_gps_ca_prn(io_in, io_out);
+ reg \$auto$verilog_backend.cc:2083:dump_module$1 = 0;
+ wire \$1 ;
+ wire \$101 ;
+ wire \$103 ;
+ wire \$105 ;
+ wire \$107 ;
+ wire \$109 ;
+ wire \$11 ;
+ wire \$111 ;
+ wire \$113 ;
+ wire \$115 ;
+ wire \$117 ;
+ wire \$119 ;
+ wire \$121 ;
+ wire \$123 ;
+ wire \$125 ;
+ wire \$127 ;
+ wire \$129 ;
+ wire \$13 ;
+ wire \$131 ;
+ wire \$133 ;
+ wire \$135 ;
+ wire \$137 ;
+ wire \$139 ;
+ wire \$15 ;
+ wire \$17 ;
+ wire \$19 ;
+ wire \$21 ;
+ wire \$23 ;
+ wire \$25 ;
+ wire \$27 ;
+ wire \$29 ;
+ wire \$3 ;
+ wire \$31 ;
+ wire \$33 ;
+ wire \$35 ;
+ wire \$37 ;
+ wire \$39 ;
+ wire \$41 ;
+ wire \$43 ;
+ wire \$45 ;
+ wire \$47 ;
+ wire \$49 ;
+ wire \$5 ;
+ wire \$51 ;
+ wire \$53 ;
+ wire \$55 ;
+ wire \$57 ;
+ wire \$59 ;
+ wire \$61 ;
+ wire \$63 ;
+ wire \$65 ;
+ wire \$67 ;
+ wire \$69 ;
+ wire \$7 ;
+ wire \$71 ;
+ wire \$73 ;
+ wire \$75 ;
+ wire \$77 ;
+ wire \$79 ;
+ wire \$81 ;
+ wire \$83 ;
+ wire \$85 ;
+ wire \$87 ;
+ wire \$89 ;
+ wire \$9 ;
+ wire \$91 ;
+ wire \$93 ;
+ wire \$95 ;
+ wire \$97 ;
+ wire \$99 ;
+ wire clk;
+ reg [9:0] g1 = 10'h3ff;
+ reg [9:0] \g1$next ;
+ reg [9:0] g2 = 10'h3ff;
+ reg [9:0] \g2$next ;
+ input [7:0] io_in;
+ wire [7:0] io_in;
+ output [7:0] io_out;
+ reg [7:0] io_out = 8'h00;
+ reg [7:0] \io_out$next ;
+ wire [31:0] prns;
+ wire rst;
+ assign \$9 = \$7 ^ g2[8];
+ assign \$99 = \$97 ^ g1[9];
+ assign \$101 = g2[0] ^ g2[2];
+ assign \$103 = \$101 ^ g1[9];
+ assign \$105 = g2[3] ^ g2[5];
+ assign \$107 = \$105 ^ g1[9];
+ assign \$109 = g2[4] ^ g2[6];
+ assign \$111 = \$109 ^ g1[9];
+ assign \$113 = g2[5] ^ g2[7];
+ assign \$115 = \$113 ^ g1[9];
+ assign \$117 = g2[6] ^ g2[8];
+ assign \$11 = \$9 ^ g2[9];
+ assign \$119 = \$117 ^ g1[9];
+ assign \$121 = g2[7] ^ g2[9];
+ assign \$123 = \$121 ^ g1[9];
+ assign \$125 = g2[0] ^ g2[5];
+ assign \$127 = \$125 ^ g1[9];
+ assign \$129 = g2[1] ^ g2[6];
+ assign \$131 = \$129 ^ g1[9];
+ assign \$133 = g2[2] ^ g2[7];
+ assign \$135 = \$133 ^ g1[9];
+ assign \$137 = g2[3] ^ g2[8];
+ assign \$13 = g2[1] ^ g2[5];
+ assign \$139 = \$137 ^ g1[9];
+ always @(posedge clk)
+ g1 <= \g1$next ;
+ always @(posedge clk)
+ io_out <= \io_out$next ;
+ always @(posedge clk)
+ g2 <= \g2$next ;
+ assign \$15 = \$13 ^ g1[9];
+ assign \$17 = g2[2] ^ g2[6];
+ assign \$1 = g1[2] ^ g1[9];
+ assign \$19 = \$17 ^ g1[9];
+ assign \$21 = g2[3] ^ g2[7];
+ assign \$23 = \$21 ^ g1[9];
+ assign \$25 = g2[4] ^ g2[8];
+ assign \$27 = \$25 ^ g1[9];
+ assign \$29 = g2[0] ^ g2[8];
+ assign \$31 = \$29 ^ g1[9];
+ assign \$33 = g2[1] ^ g2[9];
+ assign \$35 = \$33 ^ g1[9];
+ assign \$37 = g2[0] ^ g2[7];
+ assign \$3 = g2[1] ^ g2[2];
+ assign \$39 = \$37 ^ g1[9];
+ assign \$41 = g2[1] ^ g2[8];
+ assign \$43 = \$41 ^ g1[9];
+ assign \$45 = g2[2] ^ g2[9];
+ assign \$47 = \$45 ^ g1[9];
+ assign \$49 = g2[1] ^ g2[2];
+ assign \$51 = \$49 ^ g1[9];
+ assign \$53 = g2[2] ^ g2[3];
+ assign \$55 = \$53 ^ g1[9];
+ assign \$57 = g2[4] ^ g2[5];
+ assign \$5 = \$3 ^ g2[5];
+ assign \$59 = \$57 ^ g1[9];
+ assign \$61 = g2[5] ^ g2[6];
+ assign \$63 = \$61 ^ g1[9];
+ assign \$65 = g2[6] ^ g2[7];
+ assign \$67 = \$65 ^ g1[9];
+ assign \$69 = g2[7] ^ g2[8];
+ assign \$71 = \$69 ^ g1[9];
+ assign \$73 = g2[8] ^ g2[9];
+ assign \$75 = \$73 ^ g1[9];
+ assign \$77 = g2[0] ^ g2[3];
+ assign \$7 = \$5 ^ g2[7];
+ assign \$79 = \$77 ^ g1[9];
+ assign \$81 = g2[1] ^ g2[4];
+ assign \$83 = \$81 ^ g1[9];
+ assign \$85 = g2[2] ^ g2[5];
+ assign \$87 = \$85 ^ g1[9];
+ assign \$89 = g2[3] ^ g2[6];
+ assign \$91 = \$89 ^ g1[9];
+ assign \$93 = g2[4] ^ g2[7];
+ assign \$95 = \$93 ^ g1[9];
+ assign \$97 = g2[5] ^ g2[8];
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
+ \g1$next = { g1[8:0], \$1 };
+ casez (rst)
+ 1'h1:
+ \g1$next = 10'h3ff;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
+ \io_out$next [7:3] = io_out[7:3];
+ \io_out$next [0] = g1[9];
+ \io_out$next [1] = g2[9];
+ (* full_case = 32'd1 *)
+ casez (io_in[6:2])
+ 5'h00:
+ \io_out$next [2] = prns[0];
+ 5'h01:
+ \io_out$next [2] = prns[1];
+ 5'h02:
+ \io_out$next [2] = prns[2];
+ 5'h03:
+ \io_out$next [2] = prns[3];
+ 5'h04:
+ \io_out$next [2] = prns[4];
+ 5'h05:
+ \io_out$next [2] = prns[5];
+ 5'h06:
+ \io_out$next [2] = prns[6];
+ 5'h07:
+ \io_out$next [2] = prns[7];
+ 5'h08:
+ \io_out$next [2] = prns[8];
+ 5'h09:
+ \io_out$next [2] = prns[9];
+ 5'h0a:
+ \io_out$next [2] = prns[10];
+ 5'h0b:
+ \io_out$next [2] = prns[11];
+ 5'h0c:
+ \io_out$next [2] = prns[12];
+ 5'h0d:
+ \io_out$next [2] = prns[13];
+ 5'h0e:
+ \io_out$next [2] = prns[14];
+ 5'h0f:
+ \io_out$next [2] = prns[15];
+ 5'h10:
+ \io_out$next [2] = prns[16];
+ 5'h11:
+ \io_out$next [2] = prns[17];
+ 5'h12:
+ \io_out$next [2] = prns[18];
+ 5'h13:
+ \io_out$next [2] = prns[19];
+ 5'h14:
+ \io_out$next [2] = prns[20];
+ 5'h15:
+ \io_out$next [2] = prns[21];
+ 5'h16:
+ \io_out$next [2] = prns[22];
+ 5'h17:
+ \io_out$next [2] = prns[23];
+ 5'h18:
+ \io_out$next [2] = prns[24];
+ 5'h19:
+ \io_out$next [2] = prns[25];
+ 5'h1a:
+ \io_out$next [2] = prns[26];
+ 5'h1b:
+ \io_out$next [2] = prns[27];
+ 5'h1c:
+ \io_out$next [2] = prns[28];
+ 5'h1d:
+ \io_out$next [2] = prns[29];
+ 5'h1e:
+ \io_out$next [2] = prns[30];
+ 5'h??:
+ \io_out$next [2] = prns[31];
+ endcase
+ casez (rst)
+ 1'h1:
+ \io_out$next = 8'h00;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
+ \g2$next = { g2[8:0], \$11 };
+ casez (rst)
+ 1'h1:
+ \g2$next = 10'h3ff;
+ endcase
+ end
+ assign prns[31] = \$139 ;
+ assign prns[30] = \$135 ;
+ assign prns[29] = \$131 ;
+ assign prns[28] = \$127 ;
+ assign prns[27] = \$123 ;
+ assign prns[26] = \$119 ;
+ assign prns[25] = \$115 ;
+ assign prns[24] = \$111 ;
+ assign prns[23] = \$107 ;
+ assign prns[22] = \$103 ;
+ assign prns[21] = \$99 ;
+ assign prns[20] = \$95 ;
+ assign prns[19] = \$91 ;
+ assign prns[18] = \$87 ;
+ assign prns[17] = \$83 ;
+ assign prns[16] = \$79 ;
+ assign prns[15] = \$75 ;
+ assign prns[14] = \$71 ;
+ assign prns[13] = \$67 ;
+ assign prns[12] = \$63 ;
+ assign prns[11] = \$59 ;
+ assign prns[10] = \$55 ;
+ assign prns[9] = \$51 ;
+ assign prns[8] = \$47 ;
+ assign prns[7] = \$43 ;
+ assign prns[6] = \$39 ;
+ assign prns[5] = \$35 ;
+ assign prns[4] = \$31 ;
+ assign prns[3] = \$27 ;
+ assign prns[2] = \$23 ;
+ assign prns[1] = \$19 ;
+ assign prns[0] = \$15 ;
+ assign rst = io_in[1];
+ assign clk = io_in[0];
+endmodule
+
diff --git a/verilog/rtl/098_adc_dac.v b/verilog/rtl/098_adc_dac.v
new file mode 100644
index 0000000..bcf005f
--- /dev/null
+++ b/verilog/rtl/098_adc_dac.v
@@ -0,0 +1,605 @@
+/* Generated by Yosys 0.22+1 (git sha1 c4a52b1b0, clang 14.0.0-1ubuntu1 -fPIC -Os) */
+
+module adamgreig_tt02_adc_dac(io_in, io_out);
+ reg \$auto$verilog_backend.cc:2083:dump_module$1 = 0;
+ wire adc_comp;
+ wire [11:0] adc_data;
+ wire adc_out;
+ wire [11:0] adc_uart_data;
+ wire adc_uart_ready;
+ wire adc_uart_tx_o;
+ wire adc_uart_valid;
+ wire clk;
+ wire [7:0] dac_data;
+ wire dac_out;
+ wire [7:0] dac_uart_data;
+ wire dac_uart_rx_i;
+ input [7:0] io_in;
+ wire [7:0] io_in;
+ output [7:0] io_out;
+ wire [7:0] io_out;
+ reg [9:0] ready_sr = 10'h000;
+ reg [9:0] \ready_sr$next ;
+ wire rst;
+ always @(posedge clk)
+ ready_sr <= \ready_sr$next ;
+ adc adc (
+ .clk(clk),
+ .comp(adc_comp),
+ .data(adc_data),
+ .out(adc_out),
+ .rst(rst)
+ );
+ adc_uart adc_uart (
+ .clk(clk),
+ .data(adc_uart_data),
+ .ready(adc_uart_ready),
+ .rst(rst),
+ .tx_o(adc_uart_tx_o),
+ .valid(adc_uart_valid)
+ );
+ \dac$1 dac (
+ .clk(clk),
+ .data(dac_data),
+ .out(dac_out),
+ .rst(rst)
+ );
+ dac_uart dac_uart (
+ .clk(clk),
+ .data(dac_uart_data),
+ .rst(rst),
+ .rx_i(dac_uart_rx_i)
+ );
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
+ \ready_sr$next = { ready_sr[8:0], adc_uart_ready };
+ casez (rst)
+ 1'h1:
+ \ready_sr$next = 10'h000;
+ endcase
+ end
+ assign dac_uart_rx_i = io_in[3];
+ assign dac_data = dac_uart_data;
+ assign adc_uart_valid = ready_sr[9];
+ assign adc_uart_data = adc_data;
+ assign io_out[2] = dac_out;
+ assign io_out[1] = adc_uart_tx_o;
+ assign io_out[0] = adc_out;
+ assign io_out[7:3] = 5'h00;
+ assign adc_comp = io_in[2];
+ assign rst = io_in[1];
+ assign clk = io_in[0];
+endmodule
+
+module adc(rst, comp, out, data, clk);
+ reg \$auto$verilog_backend.cc:2083:dump_module$2 = 0;
+ wire [12:0] \$1 ;
+ wire [12:0] \$2 ;
+ wire [12:0] \$4 ;
+ wire [12:0] \$5 ;
+ input clk;
+ wire clk;
+ input comp;
+ wire comp;
+ wire [11:0] dac_data;
+ wire dac_out;
+ output [11:0] data;
+ reg [11:0] data = 12'h000;
+ reg [11:0] \data$next ;
+ output out;
+ wire out;
+ input rst;
+ wire rst;
+ assign \$2 = data - 1'h1;
+ assign \$5 = data + 1'h1;
+ always @(posedge clk)
+ data <= \data$next ;
+ dac dac (
+ .clk(clk),
+ .data(dac_data),
+ .out(dac_out),
+ .rst(rst)
+ );
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
+ (* full_case = 32'd1 *)
+ casez (comp)
+ 1'h1:
+ \data$next = \$2 [11:0];
+ default:
+ \data$next = \$5 [11:0];
+ endcase
+ casez (rst)
+ 1'h1:
+ \data$next = 12'h000;
+ endcase
+ end
+ assign \$1 = \$2 ;
+ assign \$4 = \$5 ;
+ assign dac_data = data;
+ assign out = dac_out;
+endmodule
+
+module adc_uart(rst, tx_o, data, ready, valid, clk);
+ reg \$auto$verilog_backend.cc:2083:dump_module$3 = 0;
+ wire \$1 ;
+ wire [8:0] \$10 ;
+ wire [7:0] \$3 ;
+ wire [6:0] \$4 ;
+ wire [8:0] \$7 ;
+ wire [7:0] \$8 ;
+ input clk;
+ wire clk;
+ input [11:0] data;
+ wire [11:0] data;
+ reg [11:0] data_reg = 12'h000;
+ reg [11:0] \data_reg$next ;
+ reg [2:0] fsm_state = 3'h0;
+ reg [2:0] \fsm_state$next ;
+ reg [3:0] nibble;
+ output ready;
+ reg ready;
+ input rst;
+ wire rst;
+ output tx_o;
+ wire tx_o;
+ reg [7:0] uart_data;
+ wire uart_ready;
+ wire uart_tx_o;
+ reg uart_valid;
+ input valid;
+ wire valid;
+ assign \$10 = \$8 - 4'ha;
+ always @(posedge clk)
+ data_reg <= \data_reg$next ;
+ always @(posedge clk)
+ fsm_state <= \fsm_state$next ;
+ assign \$1 = nibble < 4'ha;
+ assign \$4 = nibble + 6'h30;
+ assign \$3 = + \$4 ;
+ assign \$8 = nibble + 7'h41;
+ uart uart (
+ .clk(clk),
+ .data(uart_data),
+ .ready(uart_ready),
+ .rst(rst),
+ .tx_o(uart_tx_o),
+ .valid(uart_valid)
+ );
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
+ (* full_case = 32'd1 *)
+ casez (\$1 )
+ 1'h1:
+ uart_data = \$3 ;
+ default:
+ uart_data = \$10 [7:0];
+ endcase
+ casez (fsm_state)
+ 3'h0:
+ /* empty */;
+ 3'h1:
+ /* empty */;
+ 3'h2:
+ /* empty */;
+ 3'h3:
+ /* empty */;
+ 3'h4:
+ uart_data = 8'h0a;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
+ ready = 1'h0;
+ casez (fsm_state)
+ 3'h0:
+ ready = uart_ready;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
+ \data_reg$next = data_reg;
+ casez (fsm_state)
+ 3'h0:
+ \data_reg$next = data;
+ endcase
+ casez (rst)
+ 1'h1:
+ \data_reg$next = 12'h000;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
+ \fsm_state$next = fsm_state;
+ casez (fsm_state)
+ 3'h0:
+ casez (valid)
+ 1'h1:
+ \fsm_state$next = 3'h1;
+ endcase
+ 3'h1:
+ casez (uart_ready)
+ 1'h1:
+ \fsm_state$next = 3'h2;
+ endcase
+ 3'h2:
+ casez (uart_ready)
+ 1'h1:
+ \fsm_state$next = 3'h3;
+ endcase
+ 3'h3:
+ casez (uart_ready)
+ 1'h1:
+ \fsm_state$next = 3'h4;
+ endcase
+ 3'h4:
+ casez (uart_ready)
+ 1'h1:
+ \fsm_state$next = 3'h0;
+ endcase
+ endcase
+ casez (rst)
+ 1'h1:
+ \fsm_state$next = 3'h0;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
+ nibble = 4'h0;
+ casez (fsm_state)
+ 3'h0:
+ /* empty */;
+ 3'h1:
+ nibble = data_reg[11:8];
+ 3'h2:
+ nibble = data_reg[7:4];
+ 3'h3:
+ nibble = data_reg[3:0];
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
+ uart_valid = 1'h0;
+ casez (fsm_state)
+ 3'h0:
+ /* empty */;
+ 3'h1:
+ uart_valid = 1'h1;
+ 3'h2:
+ uart_valid = 1'h1;
+ 3'h3:
+ uart_valid = 1'h1;
+ 3'h4:
+ uart_valid = 1'h1;
+ endcase
+ end
+ assign \$7 = \$10 ;
+ assign tx_o = uart_tx_o;
+endmodule
+
+module dac(rst, out, data, clk);
+ reg \$auto$verilog_backend.cc:2083:dump_module$4 = 0;
+ wire [12:0] \$1 ;
+ reg [12:0] acc = 13'h0000;
+ reg [12:0] \acc$next ;
+ input clk;
+ wire clk;
+ input [11:0] data;
+ wire [11:0] data;
+ output out;
+ wire out;
+ input rst;
+ wire rst;
+ assign \$1 = acc[11:0] + data;
+ always @(posedge clk)
+ acc <= \acc$next ;
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$4 ) begin end
+ \acc$next = \$1 ;
+ casez (rst)
+ 1'h1:
+ \acc$next = 13'h0000;
+ endcase
+ end
+ assign out = acc[12];
+endmodule
+
+module \dac$1 (rst, out, data, clk);
+ reg \$auto$verilog_backend.cc:2083:dump_module$5 = 0;
+ wire [8:0] \$1 ;
+ reg [8:0] acc = 9'h000;
+ reg [8:0] \acc$next ;
+ input clk;
+ wire clk;
+ input [7:0] data;
+ wire [7:0] data;
+ output out;
+ wire out;
+ input rst;
+ wire rst;
+ assign \$1 = acc[7:0] + data;
+ always @(posedge clk)
+ acc <= \acc$next ;
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$5 ) begin end
+ \acc$next = \$1 ;
+ casez (rst)
+ 1'h1:
+ \acc$next = 9'h000;
+ endcase
+ end
+ assign out = acc[8];
+endmodule
+
+module dac_uart(rst, data, rx_i, clk);
+ reg \$auto$verilog_backend.cc:2083:dump_module$6 = 0;
+ wire \$1 ;
+ wire \$10 ;
+ wire [4:0] \$12 ;
+ wire [4:0] \$13 ;
+ wire \$15 ;
+ wire \$17 ;
+ wire \$19 ;
+ wire \$21 ;
+ wire \$23 ;
+ wire \$25 ;
+ wire \$27 ;
+ wire [4:0] \$3 ;
+ wire [4:0] \$4 ;
+ wire \$6 ;
+ wire \$8 ;
+ reg [3:0] bit_idx = 4'h0;
+ reg [3:0] \bit_idx$next ;
+ input clk;
+ wire clk;
+ reg [3:0] ctr = 4'h0;
+ reg [3:0] \ctr$next ;
+ output [7:0] data;
+ reg [7:0] data = 8'h00;
+ reg [7:0] \data$next ;
+ reg fsm_state = 1'h0;
+ reg \fsm_state$next ;
+ input rst;
+ wire rst;
+ input rx_i;
+ wire rx_i;
+ reg [7:0] sr = 8'h00;
+ reg [7:0] \sr$next ;
+ reg valid = 1'h0;
+ reg \valid$next ;
+ assign \$10 = ~ rx_i;
+ assign \$13 = ctr - 1'h1;
+ assign \$15 = ! ctr;
+ assign \$17 = ~ rx_i;
+ assign \$1 = ! ctr;
+ assign \$19 = ! ctr;
+ assign \$21 = bit_idx == 4'h8;
+ assign \$23 = ! ctr;
+ assign \$25 = ! ctr;
+ assign \$27 = bit_idx == 4'h8;
+ always @(posedge clk)
+ bit_idx <= \bit_idx$next ;
+ always @(posedge clk)
+ valid <= \valid$next ;
+ always @(posedge clk)
+ ctr <= \ctr$next ;
+ always @(posedge clk)
+ fsm_state <= \fsm_state$next ;
+ always @(posedge clk)
+ sr <= \sr$next ;
+ always @(posedge clk)
+ data <= \data$next ;
+ assign \$4 = bit_idx + 1'h1;
+ assign \$6 = ! ctr;
+ assign \$8 = bit_idx == 4'h8;
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$6 ) begin end
+ \bit_idx$next = bit_idx;
+ (* full_case = 32'd1 *)
+ casez (fsm_state)
+ 1'h0:
+ \bit_idx$next = 4'h0;
+ 1'h1:
+ casez (\$1 )
+ 1'h1:
+ \bit_idx$next = \$4 [3:0];
+ endcase
+ endcase
+ casez (rst)
+ 1'h1:
+ \bit_idx$next = 4'h0;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$6 ) begin end
+ \valid$next = valid;
+ (* full_case = 32'd1 *)
+ casez (fsm_state)
+ 1'h0:
+ \valid$next = 1'h0;
+ 1'h1:
+ casez (\$6 )
+ 1'h1:
+ casez (\$8 )
+ 1'h1:
+ \valid$next = 1'h1;
+ endcase
+ endcase
+ endcase
+ casez (rst)
+ 1'h1:
+ \valid$next = 1'h0;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$6 ) begin end
+ \ctr$next = ctr;
+ (* full_case = 32'd1 *)
+ casez (fsm_state)
+ 1'h0:
+ casez (\$10 )
+ 1'h1:
+ \ctr$next = 4'he;
+ endcase
+ 1'h1:
+ begin
+ \ctr$next = \$13 [3:0];
+ casez (\$15 )
+ 1'h1:
+ \ctr$next = 4'h9;
+ endcase
+ end
+ endcase
+ casez (rst)
+ 1'h1:
+ \ctr$next = 4'h0;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$6 ) begin end
+ \fsm_state$next = fsm_state;
+ (* full_case = 32'd1 *)
+ casez (fsm_state)
+ 1'h0:
+ casez (\$17 )
+ 1'h1:
+ \fsm_state$next = 1'h1;
+ endcase
+ 1'h1:
+ casez (\$19 )
+ 1'h1:
+ casez (\$21 )
+ 1'h1:
+ \fsm_state$next = 1'h0;
+ endcase
+ endcase
+ endcase
+ casez (rst)
+ 1'h1:
+ \fsm_state$next = 1'h0;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$6 ) begin end
+ \sr$next = sr;
+ (* full_case = 32'd1 *)
+ casez (fsm_state)
+ 1'h0:
+ /* empty */;
+ 1'h1:
+ casez (\$23 )
+ 1'h1:
+ \sr$next = { rx_i, sr[7:1] };
+ endcase
+ endcase
+ casez (rst)
+ 1'h1:
+ \sr$next = 8'h00;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$6 ) begin end
+ \data$next = data;
+ (* full_case = 32'd1 *)
+ casez (fsm_state)
+ 1'h0:
+ /* empty */;
+ 1'h1:
+ casez (\$25 )
+ 1'h1:
+ casez (\$27 )
+ 1'h1:
+ \data$next = sr;
+ endcase
+ endcase
+ endcase
+ casez (rst)
+ 1'h1:
+ \data$next = 8'h00;
+ endcase
+ end
+ assign \$3 = \$4 ;
+ assign \$12 = \$13 ;
+endmodule
+
+module uart(rst, tx_o, data, ready, valid, clk);
+ reg \$auto$verilog_backend.cc:2083:dump_module$7 = 0;
+ wire \$1 ;
+ wire \$3 ;
+ wire \$5 ;
+ wire [4:0] \$7 ;
+ wire [4:0] \$8 ;
+ input clk;
+ wire clk;
+ input [7:0] data;
+ wire [7:0] data;
+ output ready;
+ reg ready;
+ input rst;
+ wire rst;
+ reg [3:0] tx_cnt = 4'h0;
+ reg [3:0] \tx_cnt$next ;
+ output tx_o;
+ wire tx_o;
+ reg [9:0] tx_reg = 10'h001;
+ reg [9:0] \tx_reg$next ;
+ input valid;
+ wire valid;
+ always @(posedge clk)
+ tx_reg <= \tx_reg$next ;
+ always @(posedge clk)
+ tx_cnt <= \tx_cnt$next ;
+ assign \$1 = ! tx_cnt;
+ assign \$3 = ! tx_cnt;
+ assign \$5 = ! tx_cnt;
+ assign \$8 = tx_cnt - 1'h1;
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$7 ) begin end
+ (* full_case = 32'd1 *)
+ casez (\$1 )
+ 1'h1:
+ ready = 1'h1;
+ default:
+ ready = 1'h0;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$7 ) begin end
+ \tx_reg$next = tx_reg;
+ (* full_case = 32'd1 *)
+ casez (\$3 )
+ 1'h1:
+ casez (valid)
+ 1'h1:
+ \tx_reg$next = { 1'h1, data, 1'h0 };
+ endcase
+ default:
+ \tx_reg$next = { 1'h1, tx_reg[9:1] };
+ endcase
+ casez (rst)
+ 1'h1:
+ \tx_reg$next = 10'h001;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$7 ) begin end
+ \tx_cnt$next = tx_cnt;
+ (* full_case = 32'd1 *)
+ casez (\$5 )
+ 1'h1:
+ casez (valid)
+ 1'h1:
+ \tx_cnt$next = 4'ha;
+ endcase
+ default:
+ \tx_cnt$next = \$8 [3:0];
+ endcase
+ casez (rst)
+ 1'h1:
+ \tx_cnt$next = 4'h0;
+ endcase
+ end
+ assign \$7 = \$8 ;
+ assign tx_o = tx_reg[0];
+endmodule
+
diff --git a/verilog/rtl/099_jglim_7seg.v b/verilog/rtl/099_jglim_7seg.v
new file mode 100644
index 0000000..eec8ba5
--- /dev/null
+++ b/verilog/rtl/099_jglim_7seg.v
@@ -0,0 +1,15 @@
+`default_nettype none
+
+module jglim_7seg(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+
+hex7seg seg7(
+ .counter(io_in[3:0]),
+ .dot(io_in[4]),
+ .inv(io_in[5]),
+ .segments(io_out[7:0])
+);
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/102_alu.v b/verilog/rtl/102_alu.v
new file mode 100644
index 0000000..235e875
--- /dev/null
+++ b/verilog/rtl/102_alu.v
@@ -0,0 +1,99 @@
+`timescale 1ns / 1ps
+
+/* ALU Arithmetic and Logic Operations
+----------------------------------------------------------------------
+|opcode | ALU Operation
+----------------------------------------------------------------------
+| 0000 | ALU_Out = A + B;
+----------------------------------------------------------------------
+| 0001 | ALU_Out = A - B;
+----------------------------------------------------------------------
+| 0010 | ALU_Out = A * B;
+----------------------------------------------------------------------
+| 0011 | ALU_Out = A / B;
+----------------------------------------------------------------------
+| 0100 | ALU_Out = A << 1;
+----------------------------------------------------------------------
+| 0101 | ALU_Out = A >> 1;
+----------------------------------------------------------------------
+| 0110 | ALU_Out = A << B;
+----------------------------------------------------------------------
+| 0111 | ALU_Out = A >> B;
+----------------------------------------------------------------------
+| 1000 | ALU_Out = A and B;
+----------------------------------------------------------------------
+| 1001 | ALU_Out = A or B;
+----------------------------------------------------------------------
+| 1010 | ALU_Out = A xor B;
+----------------------------------------------------------------------
+| 1011 | ALU_Out = A nor B;
+----------------------------------------------------------------------
+| 1100 | ALU_Out = A nand B;
+----------------------------------------------------------------------
+| 1101 | ALU_Out = A xnor B;
+----------------------------------------------------------------------
+| 1110 | ALU_Out = 1 if A>B else 0;
+----------------------------------------------------------------------
+| 1111 | ALU_Out = 1 if A=B else 0;
+----------------------------------------------------------------------*/
+
+module shan1293_2bitalu(
+ input [7:0] io_in,
+ output [7:0] io_out
+ );
+ alu alu(
+ .A(io_in[7:6]),
+ .B(io_in[5:4]),
+ .opcode(io_in[3:0]),
+ .ALU_Out(io_out[7:0])
+ );
+endmodule
+
+module alu(
+ input [1:0] A,
+ input [1:0] B,
+ input [3:0] opcode,
+ output [7:0] ALU_Out
+);
+
+ reg [7:0] ALU_Result;
+ assign ALU_Out = ALU_Result; // ALU out
+ always @(*)
+ begin
+ case(opcode)
+ 4'b0000: // Addition
+ ALU_Result = A + B ;
+ 4'b0001: // Subtraction
+ ALU_Result = A - B ;
+ 4'b0010: // Multiplication
+ ALU_Result = A * B;
+ 4'b0011: // Division
+ ALU_Result = A/B;
+ 4'b0100: // Logical shift left one time
+ ALU_Result = A<<1;
+ 4'b0101: // Logical shift right one time
+ ALU_Result = A>>1;
+ 4'b0110: // Logical shift left B times
+ ALU_Result = A<<B;
+ 4'b0111: // Logical shift right B times
+ ALU_Result = A>>B;
+ 4'b1000: // Logical and
+ ALU_Result = A & B;
+ 4'b1001: // Logical or
+ ALU_Result = A | B;
+ 4'b1010: // Logical xor
+ ALU_Result = A ^ B;
+ 4'b1011: // Logical nor
+ ALU_Result = ~(A | B);
+ 4'b1100: // Logical nand
+ ALU_Result = ~(A & B);
+ 4'b1101: // Logical xnor
+ ALU_Result = ~(A ^ B);
+ 4'b1110: // Greater comparison
+ ALU_Result = (A>B)?4'd1:4'd0 ;
+ 4'b1111: // Equal comparison
+ ALU_Result = (A==B)?4'd1:4'd0 ;
+ default: ALU_Result = A + B ;
+ endcase
+ end
+ endmodule
\ No newline at end of file
diff --git a/verilog/rtl/104_pic.v b/verilog/rtl/104_pic.v
new file mode 100644
index 0000000..5c24e3c
--- /dev/null
+++ b/verilog/rtl/104_pic.v
@@ -0,0 +1,199 @@
+module pic10_core(input clock, reset, output [3:0] prog_adr, input [11:0] prog_data, input [3:0] gpi, output reg [7:0] gpo);
+ wire [7:0] reg_rdata;
+ reg [7:0] result;
+ reg [7:0] w;
+ reg [1:0] phase;
+ reg [3:0] pc;
+ reg [3:0] next_pc;
+ reg skip, next_skip, next_skip_zero;
+ reg reg_we, w_we;
+
+ assign prog_adr = pc;
+
+ always @(posedge clock, negedge reset)
+ begin
+ if (!reset) begin
+ phase <= 2'b0;
+ end else begin
+ phase <= phase + 1'b1;
+ end
+ end
+
+ always @(posedge clock, negedge reset)
+ begin
+ if (!reset) begin
+ pc <= 1'b0;
+ next_pc <= 1'b0;
+ w <= 1'b0;
+ next_skip <= 1'b0;
+ end else begin
+ if (phase == 0) begin
+ skip <= next_skip;
+ next_skip <= 1'b0;
+ next_skip_zero <= 1'b0;
+ reg_we <= 1'b0;
+ w_we <= 1'b0;
+ pc <= next_pc;
+ end else if (phase == 1) begin
+ next_pc <= prog_adr + 1'b1;
+ if (prog_data[11:10] == 2'b00) begin
+ reg_we <= prog_data[5];
+ w_we <= ~prog_data[5];
+ case (prog_data[9:6])
+ 4'b0000: result <= w;
+ 4'b0001: result <= 0;
+ 4'b0010: result <= reg_rdata - w;
+ 4'b0011: result <= reg_rdata - 1;
+ 4'b0100: result <= reg_rdata | w;
+ 4'b0101: result <= reg_rdata & w;
+ 4'b0110: result <= reg_rdata ^ w;
+ 4'b0111: result <= reg_rdata + w;
+ 4'b1000: result <= reg_rdata;
+ 4'b1001: result <= ~reg_rdata;
+ 4'b1010: result <= reg_rdata + 1;
+ 4'b1011: begin result <= reg_rdata - 1; next_skip_zero <= 1'b1; end
+ 4'b1111: begin result <= reg_rdata + 1; next_skip_zero <= 1'b1; end
+ endcase
+ end else if (prog_data[11:10] == 2'b01) begin
+ reg_we <= 1'b1;
+ case (prog_data[9:8])
+ 2'b00: result <= reg_rdata & ~(1 << prog_data[7:5]);
+ 2'b01: result <= reg_rdata | (1 << prog_data[7:5]);
+ 2'b10: begin result <= reg_rdata; next_skip <= ~reg_rdata[prog_data[7:5]]; end
+ 2'b11: begin result <= reg_rdata; next_skip <= reg_rdata[prog_data[7:5]]; end
+ endcase
+ end else if (prog_data[11:10] == 2'b10) begin
+ // no call, return
+ if (!skip)
+ next_pc <= prog_data[3:0];
+ end else if (prog_data[11:10] == 2'b11) begin
+ w_we <= 1'b1;
+ case (prog_data[9:8])
+ 2'b00: result <= prog_data[7:0];
+ 2'b01: result <= prog_data[7:0] | w;
+ 2'b10: result <= prog_data[7:0] & w;
+ 2'b11: result <= prog_data[7:0] ^ w;
+ endcase
+ end
+ end else if (phase == 2) begin
+ if (next_skip_zero) begin
+ next_skip <= (result == 0);
+ end
+ if (!skip) begin
+ if (w_we)
+ w <= result;
+ end
+ end else if (phase == 3) begin
+ // ...
+ end
+ end
+ end
+
+ wire [2:0] reg_addr = prog_data[2:0];
+ always @(posedge clock) begin
+ if (reg_we && regf_we && (reg_addr == 7))
+ gpo <= result;
+ end
+
+ wire [7:0] regf_data[0:7];
+ assign regf_data[6] = {4'b0000, gpi};
+ assign regf_data[7] = gpo;
+
+ assign reg_rdata = regf_data[reg_addr];
+
+ // register file
+ wire regf_we = phase[1] & !skip;
+
+ generate
+ genvar ii, jj;
+ for (ii = 0; ii < 6; ii = ii + 1'b1) begin:word
+ wire word_we;
+ sky130_fd_sc_hd__and3_1 word_we_i ( // make sure this is really glitch free
+ .A(reg_addr[2:0] == ii),
+ .B(regf_we),
+ .C(reg_we),
+ .X(word_we)
+ );
+ for (jj = 0; jj < 8; jj = jj + 1'b1) begin:bits
+ sky130_fd_sc_hd__dlrtp_1 rfbit_i (
+ .GATE(word_we),
+ .RESET_B(reset),
+ .D(result[jj]),
+ .Q(regf_data[ii][jj])
+ );
+ end
+ end
+ endgenerate
+
+endmodule
+
+(* blackbox *)
+module sky130_fd_sc_hd__dlrtp_1(input GATE, RESET_B, D, output reg Q);
+ always @*
+ if (~RESET_B)
+ Q <= 0;
+ else if (GATE)
+ Q <= D;
+endmodule
+
+(* blackbox *)
+module sky130_fd_sc_hd__dlxtp_1(input GATE, D, output reg Q);
+ always @*
+ if (GATE)
+ Q <= D;
+endmodule
+
+(* blackbox *)
+module sky130_fd_sc_hd__and3_1(input A, B, C, output X);
+ assign X = A & B & C;
+endmodule
+
+// latch based program memory
+module pic_progmem(input clock, write_data, write_strobe, input [3:0] adr, output [11:0] rdata);
+ localparam K = 16;
+
+ // the program logic
+ reg [27:0] write_sr;
+ always @(posedge clock)
+ write_sr <= {write_data, write_sr[27:1]};
+
+ wire [11:0] data[0:K-1];
+ generate
+ genvar ii, jj;
+ for (ii = 0; ii < K; ii = ii + 1'b1) begin:word
+ for (jj = 0; jj < 12; jj = jj + 1'b1) begin:bits
+ sky130_fd_sc_hd__dlxtp_1 rfbit_i (
+ .GATE(write_sr[ii + 12] && write_strobe),
+ .D(write_sr[jj]),
+ .Q(data[ii][jj])
+ );
+ end
+ end
+ endgenerate
+ assign rdata = data[adr];
+endmodule
+
+module tiny_kinda_pic(input [7:0] io_in, output [7:0] io_out);
+ wire clk = io_in[0];
+ wire reset = io_in[1];
+
+ wire [3:0] prog_adr;
+ wire [11:0] prog_data;
+ pic10_core pic_i (
+ .clock(clk),
+ .reset(reset),
+ .prog_adr(prog_adr),
+ .prog_data(prog_data),
+ .gpi(io_in[7:4]),
+ .gpo(io_out)
+ );
+
+ pic_progmem progmem_i (
+ .clock(clk),
+ .write_strobe(io_in[2]),
+ .write_data(io_in[3]),
+ .adr(prog_adr),
+ .rdata(prog_data)
+ );
+
+endmodule
diff --git a/verilog/rtl/105_browndeer_rv8u.v b/verilog/rtl/105_browndeer_rv8u.v
new file mode 100644
index 0000000..a1ed38b
--- /dev/null
+++ b/verilog/rtl/105_browndeer_rv8u.v
@@ -0,0 +1,781 @@
+/* browndeer_rv8u.v
+ *
+ * Copyright (c) 2022 Brown Deer Technology, LLC. (www.browndeertechnology.com)
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* DAR */
+
+/*
+ * RV8U - 8-bit RISC-V Microcore Processor
+ *
+ * The rv8u (Barentsburg core) is a custom 8-bit RISC-V core supporting
+ * 8-bit data operations with instructions encoded into 16-bit double-words.
+ * The core supports the full RISC-V base ISA with the following exceptions.
+ * Register file is reduced to 8 registers, with rs2 access limited to x0-x3.
+ * Additionally the auipc instruction was removed. The non-standard ISA
+ * designation 'u' was chosen to mean 'microcore' since the core is very small.
+ * Programming is supported by a custom assembler we use for developing custom
+ * RISC-V cores. A simple post-processor could be written for other assemblers
+ * to directly map instructions generated for the rv32i base ISA, if the
+ * assembly instrucitons comply with the reduced rv8u ISA limitations.
+ *
+ * Pin definitions:
+ * input in_clk base serdes clock
+ * input io_in[1] reset
+ * input io_in[7:2] 6-bit serdes input
+ * output io_out[7:0] 8-bit serdes output
+ *
+ */
+
+//module barentsburg_core(
+module browndeer_rv8u(
+
+// input in_clk,
+// input [7:1] io_in,
+ input [7:0] io_in, // ZZZ
+ output [7:0] io_out
+
+// output [BITS-3:0] debug_pc,
+// output [IBITS-1:0] debug_instr,
+// output [3:0] debug_valid_out,
+//
+// input [RBITS-1:0] debug_reg_sel,
+// output reg [BITS-1:0] debug_reg_dout
+
+);
+
+ wire in_clk; // ZZZ
+
+ ///////////////////////////////////////////////////////////////////////////
+
+ ////////////////////////////////
+ ////////// Parameters //////////
+ ////////////////////////////////
+
+ parameter BITS = 8;
+ parameter IBITS = 16;
+ parameter RBITS = 3;
+ parameter NREG = 8;
+
+ ///////////////////////////////////////////////////////////////////////////
+
+ //////////////////////////////////
+ ////////// Declarations //////////
+ //////////////////////////////////
+
+ /// pipeline control
+ wire inval;
+ wire valid_out0;
+
+ wire valid_out1;
+
+ reg valid_out3;
+
+ /// flow control
+ reg [BITS-3:0] pc;
+ reg [BITS-3:0] pc_1;
+ reg [BITS-3:0] pc_2;
+ wire pc_jump;
+ reg [BITS-3:0] jump_addr;
+
+ /// instr
+ reg [IBITS-1:0] instr;
+ reg [IBITS-1:0] instr_2;
+
+ /// hazard
+ reg [NREG-1:0] ldr_hzd;
+
+ /// reg control
+// reg [RBITS-1:0] rd;
+// reg [RBITS-1:0] rs1;
+// reg [RBITS-1:0] rs2;
+// reg [RBITS-1:0] rs3;
+ wire [RBITS-1:0] rd;
+ wire [RBITS-1:0] rs1;
+ wire [RBITS-1:0] rs2;
+ wire reg_we;
+ wire reg_we_arb;
+ reg [BITS-1:0] rd_din;
+ reg [BITS-1:0] nxt_rd_din;
+ reg [RBITS-1:0] rd_sel_arb;
+ reg [BITS-1:0] rs1_dout;
+ reg [BITS-1:0] rs2_dout;
+ reg [RBITS-1:0] rd_3;
+
+ /// imm operand
+ wire ri;
+ reg [BITS-1:0] imm;
+
+ /// reg dependency
+ wire use_rd_e1;
+ wire use_rd_e2;
+ wire use_rs1;
+ wire use_rs2;
+
+ /// IALU
+ reg [3:0] op;
+ wire [BITS-1:0] op_result;
+ wire cc_zero;
+ wire cc_neg;
+ wire cc_v;
+
+ /// ins_
+ wire reg_wen;
+ wire ins_br;
+ wire ins_jal;
+ wire ins_jalr;
+ wire ins_str;
+ wire ins_ldr;
+ wire ins_halt;
+ wire ins_lui;
+ reg ins_ldr_3;
+
+ reg ri_3;
+
+ /// bits alias probably not necessary
+ reg [2:0] funct3;
+
+ ///////////////////////////////////////////////////////
+ ////////// Declarations PIPELINE_STAGE_0_ILR //////////
+ ///////////////////////////////////////////////////////
+
+ // pipeline control
+ reg nxt_valid0;
+
+ // flow control
+ reg [BITS-3:0] pc0;
+ reg [BITS-3:0] nxt_pc, nxt_pc0;
+
+ reg valid0;
+
+ ///////////////////////////////////////////////////////
+ /////////// Declarations PIPELINE STAGE 1 IL //////////
+ ///////////////////////////////////////////////////////
+
+ wire [IBITS-1:0] nxt_instr;
+ reg valid1;
+
+ ///////////////////////////////////////////////////////////////////////////
+ ////////// Declarations PIPELINE STAGE 2 ID ///////////////////////////////
+ ///////////////////////////////////////////////////////////////////////////
+
+ wire en2;
+
+// reg [2:0] imm210;
+ reg [3:0] imm3210;
+
+ reg valid2;
+
+ ///////////////////////////////////////////////////////////////////////////
+ ////////// Pipeline Stage 3 E1 Declarations ///////////////////////////////
+ ///////////////////////////////////////////////////////////////////////////
+
+ wire [BITS-1:0] arg0;
+ reg [BITS-1:0] arg1;
+
+ reg stall;
+
+ reg ben;
+
+ ///////////////////////////////////////////////////////////////////////////
+ ////////// Pipeline Stage 4 E2 Declarations ///////////////////////////////
+ ///////////////////////////////////////////////////////////////////////////
+
+ wire en4;
+
+ //////////////////////////////////////////////
+ ////////// ISA Decoder Declarations //////////
+ //////////////////////////////////////////////
+
+ wire rv_itype, rv_stype, rv_btype;
+ wire rv_op, rv_op_imm;
+
+ ///////////////////////////////////////
+ ////////// IALU Declarations //////////
+ ///////////////////////////////////////
+
+ wire [BITS-1:0] a_result_sub;
+ wire [BITS-1:0] a_result_srl;
+ reg [BITS-1:0] a_result;
+ reg [7:0] a_sx;
+ reg [BITS-1:0] a_sign_extend;
+ wire [4:0] a_shamt;
+
+ wire run;
+ wire run_not_stall;
+
+ assign run = (~ rst);
+ assign run_not_stall = run & (~ stall);
+
+
+ /////////////////////////
+ ////////// DES //////////
+ /////////////////////////
+
+// reg des_clk_out;
+ wire des_clk_out;
+ wire [5:0] des_sin;
+// reg [7:0] des_sout;
+ wire [7:0] des_sout;
+ wire [31:0] des_din;
+ wire [23:0] des_dout;
+// reg [2:0] des_counter;
+// reg des_clk_en;
+
+ //////////////////////////
+ ////////// core //////////
+ //////////////////////////
+
+ wire clk;
+ wire rst;
+ reg halt;
+ wire [BITS-3:0] imem_addr;
+ wire [IBITS-1:0] imem_dout;
+ wire [BITS-1:0] dmem_addr;
+ wire [BITS-1:0] dmem_din;
+ wire [BITS-1:0] dmem_dout;
+ wire dmem_we;
+ wire dmem_en;
+
+
+ ///////////////////////////////////////////////////////////////////////////
+
+ ///////////////////////////////////////////////////////////////////////////
+ ////////// DES ////////////////////////////////////////////////////////
+ ///////////////////////////////////////////////////////////////////////////
+
+ des des(
+ .in_clk (in_clk),
+ .rst (rst),
+ .des_sin (des_sin),
+ .des_sout (des_sout),
+ .des_din (des_din),
+ .des_dout (des_dout),
+ .des_clk_out (des_clk_out)
+ );
+
+ assign in_clk = io_in[0]; // ZZZ
+ assign rst = io_in[1];
+ assign des_sin = io_in[7:2];
+
+ assign io_out = des_sout;
+
+
+ assign clk = des_clk_out;
+
+ assign imem_dout[15:0] = des_dout[15:0];
+ assign dmem_dout = des_dout[23:16];
+
+ assign des_din[5:0] = imem_addr;
+ assign des_din[13:6] = dmem_addr;
+ assign des_din[21:14] = dmem_din;
+ assign des_din[22] = dmem_we;
+ assign des_din[23] = dmem_en;
+ assign des_din[24] = halt;
+
+ assign des_din[31:25] = 7'd0;
+
+ ///////////////////////////////////////////////////////////////////////////
+
+ ///////////////////////////////////////////////////////////////////////////
+ ////////// PIPELINE STAGE 0 (ILR) /////////////////////////////////////
+ ///////////////////////////////////////////////////////////////////////////
+
+ /// pipeline control ///
+
+ assign valid_out0 = valid0 & ~ inval;
+
+ always @ (posedge clk)
+ begin
+ if (rst) begin
+ valid0 <= 0;
+ end
+ else if (run) begin
+ if (stall)
+ valid0 <= valid_out0;
+ else
+ valid0 <= 1;
+ end
+ else begin
+ valid0 <= valid_out0;
+ end
+ end
+
+
+ /// flow control ///
+
+ always @ (*)
+ begin
+ if (pc_jump) begin
+ nxt_pc0 = jump_addr;
+ nxt_pc = jump_addr + 1;
+ end
+ else if (stall) begin
+ nxt_pc0 = pc0;
+ nxt_pc = pc;
+ end
+ else begin
+ nxt_pc0 = pc;
+ nxt_pc = pc + 1;
+ end
+ end
+ assign imem_addr = nxt_pc0;
+
+ always @ (posedge clk)
+ begin
+ if (rst) begin
+ pc0 <= 0;
+ pc <= 0;
+ end
+ else if (run) begin
+ pc0 <= nxt_pc0;
+ pc <= nxt_pc;
+ end
+ else begin
+ pc0 <= pc0;
+ pc <= pc;
+ end
+ end
+
+
+ ///////////////////////////////////////////////////////////////////////////
+ ////////// PIPELINE STAGE 1 (IL) //////////////////////////////////////
+ ///////////////////////////////////////////////////////////////////////////
+
+ /// pipeline control ///
+
+ assign valid_out1 = valid1 & ~ inval;
+
+ always @ (posedge clk)
+ begin
+ if (rst) begin
+ valid1 <= 0;
+ pc_1 <= 0;
+ end
+ else if (run_not_stall) begin
+ valid1 <= valid_out0;
+ pc_1 <= pc;
+ end
+ else begin
+ valid1 <= valid_out1;
+ pc_1 <= pc_1;
+ end
+ end
+
+
+ /// generate instruction ///
+
+ assign nxt_instr = imem_dout[IBITS-1:0];
+
+ always @ (posedge clk)
+ begin
+ if (rst)
+ instr <= 0;
+ else if (run_not_stall & valid_out0)
+ instr <= nxt_instr;
+ else
+ instr <= instr;
+ end
+
+
+ ///////////////////////////////////////////////////////////////////////////
+ ////////// PIPELINE STAGE 2 (ID) //////////////////////////////////////
+ ///////////////////////////////////////////////////////////////////////////
+
+ /// pipeline control ///
+
+ assign en2 = valid_out1;
+
+ always @ (posedge clk)
+ begin
+ if (rst) begin
+ valid2 <= 0;
+ end
+ else if (run_not_stall) begin
+ valid2 <= valid_out1;
+ end
+ else begin
+ valid2 <= valid2;
+ end
+ end
+
+
+ /// pc, instr data flow
+
+ always @ (posedge clk)
+ begin
+ if (rst) begin
+ pc_2 <= 0;
+ instr_2 <= 0;
+ end
+ else if (run_not_stall) begin
+ pc_2 <= pc_1;
+ if (valid_out1)
+ instr_2 <= instr;
+ else
+ instr_2 <= 16'hffff;
+ end
+ else begin
+ pc_2 <= pc_2;
+ instr_2 <= instr_2;
+ end
+ end
+
+
+ ///////////////////////////////////////////////////////////////////////////
+ ////////// PIPELINE STAGE 3 (E1) //////////////////////////////////////
+ ///////////////////////////////////////////////////////////////////////////
+
+
+ always @ (posedge clk)
+ begin
+ if (rst)
+ valid_out3 <= 0;
+ else if (run_not_stall)
+ valid_out3 <= valid2;
+ else if (run & en4)
+ valid_out3 <= 0;
+ else
+ valid_out3 <= valid_out3;
+ end
+
+ assign rd = instr_2[5:3];
+ assign funct3 = instr_2[8:6];
+ assign rs1 = instr_2[11:9];
+ assign rs2[1:0] = instr_2[13:12];
+ assign rs2[2] = 0;
+
+ assign ins_lui = (instr_2[2:0] == 3'b111);
+ assign ins_jal = (instr_2[2:0] == 3'b110);
+ assign ins_jalr = (instr_2[2:0] == 3'b100);
+ assign rv_op_imm = (instr_2[2:0] == 3'b001);
+ assign rv_op = (instr_2[2:0] == 3'b011);
+ assign ins_br = (instr_2[2:0] == 3'b010);
+ assign ins_ldr = ((instr_2[2:0] == 3'b000) & (~ funct3[2]));
+ assign ins_str = ((instr_2[2:0] == 3'b000) & funct3[2]);
+
+ assign use_rd_e1 = reg_wen | ins_jal | ins_jalr | ins_lui;
+ assign use_rd_e2 = (~ funct3[2]) & ins_ldr;
+ assign use_rs1 = ins_ldr | reg_wen | ins_jalr | ins_br | ins_str;
+ assign use_rs2 = (reg_wen & ~ ri_3) | ins_br | ins_str;
+
+ assign ins_halt = (instr_2[2:0] == 3'b000) & (funct3 == 3'b000);
+
+ assign rv_itype = ins_ldr | rv_op_imm | ins_jalr;
+ assign rv_stype = ins_str;
+ assign rv_btype = ins_br;
+
+ assign ri = rv_itype | rv_stype;
+ assign reg_wen = rv_op | rv_op_imm;
+
+ always @ (*)
+ begin
+ if (ins_str | ins_ldr | ins_br)
+ op[2:0] = 3'b000;
+ else
+ op[2:0] = funct3;
+
+ op[3] = ins_br | ((rv_op | ( rv_op_imm & funct3[2])) & instr_2[15]);
+ end
+
+ always @ (*)
+ begin
+ if (rv_itype)
+ imm3210 = { instr_2[15:12] };
+ else
+ imm3210 = { instr_2[14], instr_2[5:3] };
+ end
+
+ always @ (*)
+ begin
+ if (rv_itype|rv_btype|rv_stype)
+ imm = { instr_2[15], instr_2[15], instr_2[15], instr_2[15], imm3210 };
+ else
+ imm = instr_2[13:6];
+ end
+
+
+ assign reg_we = valid2
+ & (reg_wen|ins_jal|ins_jalr|ins_lui) & (~ stall);
+
+ assign dmem_we = valid2 & ins_str & (~ stall);
+
+ assign arg0 = rs1_dout;
+
+ always @ (*)
+ begin
+ if (ri) begin
+ arg1 = imm[BITS-1:0];
+ end
+ else
+ arg1 = rs2_dout;
+ end
+
+
+ /// IALU ///
+
+ assign a_shamt = arg1[4:0];
+
+ assign a_result_sub = arg0 - arg1;
+
+ assign a_result_srl = arg0 >> a_shamt;
+
+ always @ (*)
+ begin
+ case (arg1[2:0])
+ 3'b000: a_sx = 8'b00000000;
+ 3'b001: a_sx = 8'b10000000;
+ 3'b010: a_sx = 8'b11000000;
+ 3'b011: a_sx = 8'b11100000;
+ 3'b100: a_sx = 8'b11110000;
+ 3'b101: a_sx = 8'b11111000;
+ 3'b110: a_sx = 8'b11111100;
+ 3'b111: a_sx = 8'b11111110;
+ endcase
+ if (arg0[BITS-1])
+ a_sign_extend = a_sx;
+ else
+ a_sign_extend = 8'd0;
+ end
+
+
+ always @ (*)
+ begin
+ case (op[2:0])
+
+ 3'b000: begin
+ if (op[3])
+ a_result = a_result_sub;
+ else
+ a_result = arg0 + arg1;
+ end
+
+ 3'b001: begin
+ a_result = arg0 << a_shamt; // sll
+ end
+
+ 3'b010: begin
+ a_result = { 7'd0, cc_neg }; // slt
+ end
+
+ 3'b011: begin
+ a_result = { 7'd0, cc_v}; // sltu
+ end
+
+ 3'b100: begin
+ a_result = arg0 ^ arg1; // xor
+ end
+
+ 3'b101: begin
+ if (op[3])
+ a_result = a_sign_extend | a_result_srl; // sra
+ else
+ a_result = a_result_srl; // srl
+ end
+
+ 3'b110: begin
+ a_result = arg0 | arg1;
+ end
+
+ 3'b111: begin
+ a_result = arg0 & arg1;
+ end
+
+ endcase
+ end
+
+ assign cc_neg = a_result_sub[BITS-1];
+ assign cc_zero = (a_result_sub == 0);
+ assign cc_v = ( cc_neg & ~(arg0[BITS-1] ^ arg1[BITS-1]))
+ | ((~arg0[BITS-1]) & arg1[BITS-1] );
+
+ assign op_result = a_result;
+
+
+ assign dmem_addr = op_result[BITS-1:0];
+ assign dmem_din[BITS-1:0] = rs2_dout;
+ assign dmem_en = (ins_str | ins_ldr) & valid2 & (~ stall);
+
+ always @ (*)
+ begin
+ if (ins_lui)
+// rd_din = { imm[1:0], 6'd0 };
+ rd_din = { imm[4:0], 3'd0 };
+ else if (ins_jal|ins_jalr)
+ rd_din = { 2'b00, pc_2 };
+ else
+ rd_din = op_result;
+ end
+
+ always @ (*)
+ begin
+ case(funct3)
+ 3'b000 : ben = cc_zero; // eq
+ 3'b001 : ben = (~cc_zero); // ne
+ 3'b010 : ben = 0;
+ 3'b011 : ben = 0;
+ 3'b100 : ben = cc_neg; // lt
+ 3'b101 : ben = (cc_zero | (~cc_neg)); // ge
+ 3'b110 : ben = cc_v; // ltu
+ 3'b111 : ben = (cc_zero | (~cc_v)); // geu
+ endcase
+ end
+
+
+ always @ (*)
+ begin
+ if (ins_jalr)
+// jump_addr = op_result[BITS-1:2];
+ jump_addr = op_result[BITS-3:0];
+ else
+ jump_addr = pc_2 + { imm[BITS-3:0] };
+ end
+ assign pc_jump = valid2 & ((ben & ins_br) | ins_jal | ins_jalr);
+
+ assign inval = pc_jump & (~ stall);
+
+ always @ (posedge clk)
+ begin
+ if (rst) begin
+ halt <= 0;
+ end
+ else if (run_not_stall & valid2) begin
+ halt <= ins_halt;
+ end
+ else begin
+ halt <= halt;
+ end
+ end
+
+ always @ (posedge clk)
+ begin
+ if (rst) begin
+ ins_ldr_3 <= 0;
+ rd_3 <= 0;
+ ri_3 <= 0;
+ end
+ else if (run_not_stall) begin
+ ins_ldr_3 <= ins_ldr;
+ rd_3 <= rd;
+ ri_3 <= ri;
+ end
+ else begin
+ ins_ldr_3 <= ins_ldr_3;
+ rd_3 <= rd_3;
+ ri_3 <= ri_3;
+ end
+ end
+
+ always @ (*)
+ begin
+
+ if ( ldr_hzd == 'd0 )
+ stall = 0;
+ else if ( (use_rs1 & ldr_hzd[rs1]) | (use_rs2 & ldr_hzd[rs2])) // RAW HZD
+ stall = 1;
+ else if ( (use_rd_e2 & ldr_hzd[rd]) | (use_rd_e1) ) // WAW conflict
+ stall = 1;
+ else
+ stall = 0;
+
+ end
+
+
+ ///////////////////////////////////////////////////////////////////////////
+ ////////// PIPELINE STAGE 4 (E2) //////////////////////////////////////
+ ///////////////////////////////////////////////////////////////////////////
+
+ assign en4 = valid_out3 & (ins_ldr_3 );
+
+ always @ (*)
+ begin
+
+ if (en4 & ins_ldr_3) begin
+ rd_sel_arb = rd_3;
+ end
+ else begin
+ rd_sel_arb = rd;
+ end
+
+ end
+ assign reg_we_arb = reg_we | (en4 & ins_ldr_3);
+
+
+ ///////////////////////////////////////////////////////////////////////////
+ ////////// REGISTERS //////////////////////////////////////////////////////
+ ///////////////////////////////////////////////////////////////////////////
+
+ /// write register
+
+ always @ (*)
+ begin
+ if (en4 & ins_ldr_3) begin
+ nxt_rd_din = dmem_dout[BITS-1:0];
+ end
+ else begin
+ nxt_rd_din = rd_din;
+ end
+ end
+
+ registers registers(
+ .clk (clk),
+ .run (run),
+ .we (reg_we_arb),
+ .rd (rd_sel_arb),
+ .rs1 (rs1),
+ .rs2 (rs2),
+ .rd_din (nxt_rd_din),
+ .rs1_dout (rs1_dout),
+ .rs2_dout (rs2_dout)
+
+// .debug_reg_sel (debug_reg_sel),
+// .debug_reg_dout (debug_reg_dout)
+ );
+
+ ///////////////////////////////////////////////////////////////////////////
+
+ /////////////////////////////
+ //////// Hazard ////////
+ /////////////////////////////
+
+ always @ (posedge clk)
+ begin
+ if (rst) begin
+ ldr_hzd <= 0;
+ end
+ else if (run)
+ if (( ~(rd==0)) & (ins_ldr ) & ~ stall) begin
+ ldr_hzd <= ('d1 << rd);
+ end
+ else begin
+ ldr_hzd <= 0;
+ end
+ else begin
+ ldr_hzd <= ldr_hzd;
+ end
+ end
+
+
+ ///////////////////////////////////////////////////////////////////////////
+
+ ///////////////////////////
+ //////// DEBUG ////////
+ ///////////////////////////
+
+// assign debug_pc = pc_2;
+// assign debug_instr[15:0] = instr_2;
+// assign debug_valid_out = { valid_out0, valid_out1, valid2, valid_out3 };
+
+endmodule
diff --git a/verilog/rtl/105_pic.v b/verilog/rtl/105_pic.v
new file mode 100644
index 0000000..5c24e3c
--- /dev/null
+++ b/verilog/rtl/105_pic.v
@@ -0,0 +1,199 @@
+module pic10_core(input clock, reset, output [3:0] prog_adr, input [11:0] prog_data, input [3:0] gpi, output reg [7:0] gpo);
+ wire [7:0] reg_rdata;
+ reg [7:0] result;
+ reg [7:0] w;
+ reg [1:0] phase;
+ reg [3:0] pc;
+ reg [3:0] next_pc;
+ reg skip, next_skip, next_skip_zero;
+ reg reg_we, w_we;
+
+ assign prog_adr = pc;
+
+ always @(posedge clock, negedge reset)
+ begin
+ if (!reset) begin
+ phase <= 2'b0;
+ end else begin
+ phase <= phase + 1'b1;
+ end
+ end
+
+ always @(posedge clock, negedge reset)
+ begin
+ if (!reset) begin
+ pc <= 1'b0;
+ next_pc <= 1'b0;
+ w <= 1'b0;
+ next_skip <= 1'b0;
+ end else begin
+ if (phase == 0) begin
+ skip <= next_skip;
+ next_skip <= 1'b0;
+ next_skip_zero <= 1'b0;
+ reg_we <= 1'b0;
+ w_we <= 1'b0;
+ pc <= next_pc;
+ end else if (phase == 1) begin
+ next_pc <= prog_adr + 1'b1;
+ if (prog_data[11:10] == 2'b00) begin
+ reg_we <= prog_data[5];
+ w_we <= ~prog_data[5];
+ case (prog_data[9:6])
+ 4'b0000: result <= w;
+ 4'b0001: result <= 0;
+ 4'b0010: result <= reg_rdata - w;
+ 4'b0011: result <= reg_rdata - 1;
+ 4'b0100: result <= reg_rdata | w;
+ 4'b0101: result <= reg_rdata & w;
+ 4'b0110: result <= reg_rdata ^ w;
+ 4'b0111: result <= reg_rdata + w;
+ 4'b1000: result <= reg_rdata;
+ 4'b1001: result <= ~reg_rdata;
+ 4'b1010: result <= reg_rdata + 1;
+ 4'b1011: begin result <= reg_rdata - 1; next_skip_zero <= 1'b1; end
+ 4'b1111: begin result <= reg_rdata + 1; next_skip_zero <= 1'b1; end
+ endcase
+ end else if (prog_data[11:10] == 2'b01) begin
+ reg_we <= 1'b1;
+ case (prog_data[9:8])
+ 2'b00: result <= reg_rdata & ~(1 << prog_data[7:5]);
+ 2'b01: result <= reg_rdata | (1 << prog_data[7:5]);
+ 2'b10: begin result <= reg_rdata; next_skip <= ~reg_rdata[prog_data[7:5]]; end
+ 2'b11: begin result <= reg_rdata; next_skip <= reg_rdata[prog_data[7:5]]; end
+ endcase
+ end else if (prog_data[11:10] == 2'b10) begin
+ // no call, return
+ if (!skip)
+ next_pc <= prog_data[3:0];
+ end else if (prog_data[11:10] == 2'b11) begin
+ w_we <= 1'b1;
+ case (prog_data[9:8])
+ 2'b00: result <= prog_data[7:0];
+ 2'b01: result <= prog_data[7:0] | w;
+ 2'b10: result <= prog_data[7:0] & w;
+ 2'b11: result <= prog_data[7:0] ^ w;
+ endcase
+ end
+ end else if (phase == 2) begin
+ if (next_skip_zero) begin
+ next_skip <= (result == 0);
+ end
+ if (!skip) begin
+ if (w_we)
+ w <= result;
+ end
+ end else if (phase == 3) begin
+ // ...
+ end
+ end
+ end
+
+ wire [2:0] reg_addr = prog_data[2:0];
+ always @(posedge clock) begin
+ if (reg_we && regf_we && (reg_addr == 7))
+ gpo <= result;
+ end
+
+ wire [7:0] regf_data[0:7];
+ assign regf_data[6] = {4'b0000, gpi};
+ assign regf_data[7] = gpo;
+
+ assign reg_rdata = regf_data[reg_addr];
+
+ // register file
+ wire regf_we = phase[1] & !skip;
+
+ generate
+ genvar ii, jj;
+ for (ii = 0; ii < 6; ii = ii + 1'b1) begin:word
+ wire word_we;
+ sky130_fd_sc_hd__and3_1 word_we_i ( // make sure this is really glitch free
+ .A(reg_addr[2:0] == ii),
+ .B(regf_we),
+ .C(reg_we),
+ .X(word_we)
+ );
+ for (jj = 0; jj < 8; jj = jj + 1'b1) begin:bits
+ sky130_fd_sc_hd__dlrtp_1 rfbit_i (
+ .GATE(word_we),
+ .RESET_B(reset),
+ .D(result[jj]),
+ .Q(regf_data[ii][jj])
+ );
+ end
+ end
+ endgenerate
+
+endmodule
+
+(* blackbox *)
+module sky130_fd_sc_hd__dlrtp_1(input GATE, RESET_B, D, output reg Q);
+ always @*
+ if (~RESET_B)
+ Q <= 0;
+ else if (GATE)
+ Q <= D;
+endmodule
+
+(* blackbox *)
+module sky130_fd_sc_hd__dlxtp_1(input GATE, D, output reg Q);
+ always @*
+ if (GATE)
+ Q <= D;
+endmodule
+
+(* blackbox *)
+module sky130_fd_sc_hd__and3_1(input A, B, C, output X);
+ assign X = A & B & C;
+endmodule
+
+// latch based program memory
+module pic_progmem(input clock, write_data, write_strobe, input [3:0] adr, output [11:0] rdata);
+ localparam K = 16;
+
+ // the program logic
+ reg [27:0] write_sr;
+ always @(posedge clock)
+ write_sr <= {write_data, write_sr[27:1]};
+
+ wire [11:0] data[0:K-1];
+ generate
+ genvar ii, jj;
+ for (ii = 0; ii < K; ii = ii + 1'b1) begin:word
+ for (jj = 0; jj < 12; jj = jj + 1'b1) begin:bits
+ sky130_fd_sc_hd__dlxtp_1 rfbit_i (
+ .GATE(write_sr[ii + 12] && write_strobe),
+ .D(write_sr[jj]),
+ .Q(data[ii][jj])
+ );
+ end
+ end
+ endgenerate
+ assign rdata = data[adr];
+endmodule
+
+module tiny_kinda_pic(input [7:0] io_in, output [7:0] io_out);
+ wire clk = io_in[0];
+ wire reset = io_in[1];
+
+ wire [3:0] prog_adr;
+ wire [11:0] prog_data;
+ pic10_core pic_i (
+ .clock(clk),
+ .reset(reset),
+ .prog_adr(prog_adr),
+ .prog_data(prog_data),
+ .gpi(io_in[7:4]),
+ .gpo(io_out)
+ );
+
+ pic_progmem progmem_i (
+ .clock(clk),
+ .write_strobe(io_in[2]),
+ .write_data(io_in[3]),
+ .adr(prog_adr),
+ .rdata(prog_data)
+ );
+
+endmodule
diff --git a/verilog/rtl/106_browndeer_rv8u.v b/verilog/rtl/106_browndeer_rv8u.v
new file mode 100644
index 0000000..9cb6de9
--- /dev/null
+++ b/verilog/rtl/106_browndeer_rv8u.v
@@ -0,0 +1,777 @@
+/* browndeer_rv8u.v
+ *
+ * Copyright (c) 2022 Brown Deer Technology, LLC. (www.browndeertechnology.com)
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* DAR */
+
+/*
+ * RV8U - 8-bit RISC-V Microcore Processor
+ *
+ * The rv8u (Barentsburg core) is a custom 8-bit RISC-V core supporting
+ * 8-bit data operations with instructions encoded into 16-bit double-words.
+ * The core supports the full RISC-V base ISA with the following exceptions.
+ * Register file is reduced to 8 registers, with rs2 access limited to x0-x3.
+ * Additionally the auipc instruction was removed. The non-standard ISA
+ * designation 'u' was chosen to mean 'microcore' since the core is very small.
+ * Programming is supported by a custom assembler we use for developing custom
+ * RISC-V cores. A simple post-processor could be written for other assemblers
+ * to directly map instructions generated for the rv32i base ISA, if the
+ * assembly instrucitons comply with the reduced rv8u ISA limitations.
+ *
+ * Pin definitions:
+ * input in_clk base serdes clock
+ * input io_in[1] reset
+ * input io_in[7:2] 6-bit serdes input
+ * output io_out[7:0] 8-bit serdes output
+ *
+ */
+
+//module barentsburg_core(
+module browndeer_rv8u(
+
+// input in_clk,
+// input [7:1] io_in,
+ input [7:0] io_in, // ZZZ
+ output [7:0] io_out
+
+// output [BITS-3:0] debug_pc,
+// output [IBITS-1:0] debug_instr,
+// output [3:0] debug_valid_out,
+//
+// input [RBITS-1:0] debug_reg_sel,
+// output reg [BITS-1:0] debug_reg_dout
+
+);
+
+ wire in_clk; // ZZZ
+
+ ///////////////////////////////////////////////////////////////////////////
+
+ ////////////////////////////////
+ ////////// Parameters //////////
+ ////////////////////////////////
+
+ parameter BITS = 8;
+ parameter IBITS = 16;
+ parameter RBITS = 3;
+ parameter NREG = 8;
+
+ ///////////////////////////////////////////////////////////////////////////
+
+ //////////////////////////////////
+ ////////// Declarations //////////
+ //////////////////////////////////
+
+ /// pipeline control
+ wire inval;
+ wire valid_out0;
+
+ wire valid_out1;
+
+ reg valid_out3;
+
+ /// flow control
+ reg [BITS-3:0] pc;
+ reg [BITS-3:0] pc_1;
+ reg [BITS-3:0] pc_2;
+ wire pc_jump;
+ reg [BITS-3:0] jump_addr;
+
+ /// instr
+ reg [IBITS-1:0] instr;
+ reg [IBITS-1:0] instr_2;
+
+ /// hazard
+ reg [NREG-1:0] ldr_hzd;
+
+ /// reg control
+ reg [RBITS-1:0] rd;
+ reg [RBITS-1:0] rs1;
+ reg [RBITS-1:0] rs2;
+ reg [RBITS-1:0] rs3;
+ wire reg_we;
+ wire reg_we_arb;
+ reg [BITS-1:0] rd_din;
+ reg [BITS-1:0] nxt_rd_din;
+ reg [RBITS-1:0] rd_sel_arb;
+ reg [BITS-1:0] rs1_dout;
+ reg [BITS-1:0] rs2_dout;
+ reg [RBITS-1:0] rd_3;
+
+ /// imm operand
+ wire ri;
+ reg [BITS-1:0] imm;
+
+ /// reg dependency
+ wire use_rd_e1;
+ wire use_rd_e2;
+ wire use_rs1;
+ wire use_rs2;
+
+ /// IALU
+ reg [3:0] op;
+ wire [BITS-1:0] op_result;
+ wire cc_zero;
+ wire cc_neg;
+ wire cc_v;
+
+ /// ins_
+ wire reg_wen;
+ wire ins_br;
+ wire ins_jal;
+ wire ins_jalr;
+ wire ins_str;
+ wire ins_ldr;
+ wire ins_halt;
+ wire ins_lui;
+ reg ins_ldr_3;
+
+ reg ri_3;
+
+ /// bits alias probably not necessary
+ reg [2:0] funct3;
+
+ ///////////////////////////////////////////////////////
+ ////////// Declarations PIPELINE_STAGE_0_ILR //////////
+ ///////////////////////////////////////////////////////
+
+ // pipeline control
+ reg nxt_valid0;
+
+ // flow control
+ reg [BITS-3:0] pc0;
+ reg [BITS-3:0] nxt_pc, nxt_pc0;
+
+ reg valid0;
+
+ ///////////////////////////////////////////////////////
+ /////////// Declarations PIPELINE STAGE 1 IL //////////
+ ///////////////////////////////////////////////////////
+
+ wire [IBITS-1:0] nxt_instr;
+ reg valid1;
+
+ ///////////////////////////////////////////////////////////////////////////
+ ////////// Declarations PIPELINE STAGE 2 ID ///////////////////////////////
+ ///////////////////////////////////////////////////////////////////////////
+
+ wire en2;
+
+// reg [2:0] imm210;
+ reg [3:0] imm3210;
+
+ reg valid2;
+
+ ///////////////////////////////////////////////////////////////////////////
+ ////////// Pipeline Stage 3 E1 Declarations ///////////////////////////////
+ ///////////////////////////////////////////////////////////////////////////
+
+ wire [BITS-1:0] arg0;
+ reg [BITS-1:0] arg1;
+
+ reg stall;
+
+ reg ben;
+
+ ///////////////////////////////////////////////////////////////////////////
+ ////////// Pipeline Stage 4 E2 Declarations ///////////////////////////////
+ ///////////////////////////////////////////////////////////////////////////
+
+ wire en4;
+
+ //////////////////////////////////////////////
+ ////////// ISA Decoder Declarations //////////
+ //////////////////////////////////////////////
+
+ wire rv_itype, rv_stype, rv_btype;
+ reg rv_op, rv_op_imm;
+
+ ///////////////////////////////////////
+ ////////// IALU Declarations //////////
+ ///////////////////////////////////////
+
+ wire [BITS-1:0] a_result_sub;
+ wire [BITS-1:0] a_result_srl;
+ reg [BITS-1:0] a_result;
+ reg [7:0] a_sx;
+ reg [BITS-1:0] a_sign_extend;
+ wire [4:0] a_shamt;
+
+ wire run;
+ wire run_not_stall;
+
+ assign run = (~ rst);
+ assign run_not_stall = run & (~ stall);
+
+
+ /////////////////////////
+ ////////// DES //////////
+ /////////////////////////
+
+// reg des_clk_out;
+ wire des_clk_out;
+ wire [5:0] des_sin;
+// reg [7:0] des_sout;
+ wire [7:0] des_sout;
+ wire [31:0] des_din;
+ wire [23:0] des_dout;
+// reg [2:0] des_counter;
+// reg des_clk_en;
+
+ //////////////////////////
+ ////////// core //////////
+ //////////////////////////
+
+ wire clk;
+ wire rst;
+ reg halt;
+ wire [BITS-3:0] imem_addr;
+ wire [IBITS-1:0] imem_dout;
+ wire [BITS-1:0] dmem_addr;
+ wire [BITS-1:0] dmem_din;
+ wire [BITS-1:0] dmem_dout;
+ wire dmem_we;
+ wire dmem_en;
+
+
+ ///////////////////////////////////////////////////////////////////////////
+
+ ///////////////////////////////////////////////////////////////////////////
+ ////////// DES ////////////////////////////////////////////////////////
+ ///////////////////////////////////////////////////////////////////////////
+
+ des des(
+ .in_clk (in_clk),
+ .rst (rst),
+ .des_sin (des_sin),
+ .des_sout (des_sout),
+ .des_din (des_din),
+ .des_dout (des_dout),
+ .des_clk_out (des_clk_out)
+ );
+
+ assign in_clk = io_in[0]; // ZZZ
+ assign rst = io_in[1];
+ assign des_sin = io_in[7:2];
+
+ assign io_out = des_sout;
+
+
+ assign clk = des_clk_out;
+
+ assign imem_dout[15:0] = des_dout[15:0];
+ assign dmem_dout = des_dout[23:16];
+
+ assign des_din[5:0] = imem_addr;
+ assign des_din[13:6] = dmem_addr;
+ assign des_din[21:14] = dmem_din;
+ assign des_din[22] = dmem_we;
+ assign des_din[23] = dmem_en;
+ assign des_din[24] = halt;
+
+
+ ///////////////////////////////////////////////////////////////////////////
+
+ ///////////////////////////////////////////////////////////////////////////
+ ////////// PIPELINE STAGE 0 (ILR) /////////////////////////////////////
+ ///////////////////////////////////////////////////////////////////////////
+
+ /// pipeline control ///
+
+ assign valid_out0 = valid0 & ~ inval;
+
+ always @ (posedge clk)
+ begin
+ if (rst) begin
+ valid0 <= 0;
+ end
+ else if (run) begin
+ if (stall)
+ valid0 <= valid_out0;
+ else
+ valid0 <= 1;
+ end
+ else begin
+ valid0 <= valid_out0;
+ end
+ end
+
+
+ /// flow control ///
+
+ always @ (*)
+ begin
+ if (pc_jump) begin
+ nxt_pc0 = jump_addr;
+ nxt_pc = jump_addr + 1;
+ end
+ else if (stall) begin
+ nxt_pc0 = pc0;
+ nxt_pc = pc;
+ end
+ else begin
+ nxt_pc0 = pc;
+ nxt_pc = pc + 1;
+ end
+ end
+ assign imem_addr = nxt_pc0;
+
+ always @ (posedge clk)
+ begin
+ if (rst) begin
+ pc0 <= 0;
+ pc <= 0;
+ end
+ else if (run) begin
+ pc0 <= nxt_pc0;
+ pc <= nxt_pc;
+ end
+ else begin
+ pc0 <= pc0;
+ pc <= pc;
+ end
+ end
+
+
+ ///////////////////////////////////////////////////////////////////////////
+ ////////// PIPELINE STAGE 1 (IL) //////////////////////////////////////
+ ///////////////////////////////////////////////////////////////////////////
+
+ /// pipeline control ///
+
+ assign valid_out1 = valid1 & ~ inval;
+
+ always @ (posedge clk)
+ begin
+ if (rst) begin
+ valid1 <= 0;
+ pc_1 <= 0;
+ end
+ else if (run_not_stall) begin
+ valid1 <= valid_out0;
+ pc_1 <= pc;
+ end
+ else begin
+ valid1 <= valid_out1;
+ pc_1 <= pc_1;
+ end
+ end
+
+
+ /// generate instruction ///
+
+ assign nxt_instr = imem_dout[IBITS-1:0];
+
+ always @ (posedge clk)
+ begin
+ if (rst)
+ instr <= 0;
+ else if (run_not_stall & valid_out0)
+ instr <= nxt_instr;
+ else
+ instr <= instr;
+ end
+
+
+ ///////////////////////////////////////////////////////////////////////////
+ ////////// PIPELINE STAGE 2 (ID) //////////////////////////////////////
+ ///////////////////////////////////////////////////////////////////////////
+
+ /// pipeline control ///
+
+ assign en2 = valid_out1;
+
+ always @ (posedge clk)
+ begin
+ if (rst) begin
+ valid2 <= 0;
+ end
+ else if (run_not_stall) begin
+ valid2 <= valid_out1;
+ end
+ else begin
+ valid2 <= valid2;
+ end
+ end
+
+
+ /// pc, instr data flow
+
+ always @ (posedge clk)
+ begin
+ if (rst) begin
+ pc_2 <= 0;
+ instr_2 <= 0;
+ end
+ else if (run_not_stall) begin
+ pc_2 <= pc_1;
+ if (valid_out1)
+ instr_2 <= instr;
+ else
+ instr_2 <= 16'hffff;
+ end
+ else begin
+ pc_2 <= pc_2;
+ instr_2 <= instr_2;
+ end
+ end
+
+
+ ///////////////////////////////////////////////////////////////////////////
+ ////////// PIPELINE STAGE 3 (E1) //////////////////////////////////////
+ ///////////////////////////////////////////////////////////////////////////
+
+
+ always @ (posedge clk)
+ begin
+ if (rst)
+ valid_out3 <= 0;
+ else if (run_not_stall)
+ valid_out3 <= valid2;
+ else if (run & en4)
+ valid_out3 <= 0;
+ else
+ valid_out3 <= valid_out3;
+ end
+
+ assign rd = instr_2[5:3];
+ assign funct3 = instr_2[8:6];
+ assign rs1 = instr_2[11:9];
+ assign rs2[1:0] = instr_2[13:12];
+ assign rs2[2] = 0;
+
+ assign ins_lui = (instr_2[2:0] == 3'b111);
+ assign ins_jal = (instr_2[2:0] == 3'b110);
+ assign ins_jalr = (instr_2[2:0] == 3'b100);
+ assign rv_op_imm = (instr_2[2:0] == 3'b001);
+ assign rv_op = (instr_2[2:0] == 3'b011);
+ assign ins_br = (instr_2[2:0] == 3'b010);
+ assign ins_ldr = ((instr_2[2:0] == 3'b000) & (~ funct3[2]));
+ assign ins_str = ((instr_2[2:0] == 3'b000) & funct3[2]);
+
+ assign use_rd_e1 = reg_wen | ins_jal | ins_jalr | ins_lui;
+ assign use_rd_e2 = (~ funct3[2]) & ins_ldr;
+ assign use_rs1 = ins_ldr | reg_wen | ins_jalr | ins_br | ins_str;
+ assign use_rs2 = (reg_wen & ~ ri_3) | ins_br | ins_str;
+
+ assign ins_halt = (instr_2[2:0] == 3'b000) & (funct3 == 3'b000);
+
+ assign rv_itype = ins_ldr | rv_op_imm | ins_jalr;
+ assign rv_stype = ins_str;
+ assign rv_btype = ins_br;
+
+ assign ri = rv_itype | rv_stype;
+ assign reg_wen = rv_op | rv_op_imm;
+
+ always @ (*)
+ begin
+ if (ins_str | ins_ldr | ins_br)
+ op[2:0] = 3'b000;
+ else
+ op[2:0] = funct3;
+
+ op[3] = ins_br | ((rv_op | ( rv_op_imm & funct3[2])) & instr_2[15]);
+ end
+
+ always @ (*)
+ begin
+ if (rv_itype)
+ imm3210 = { instr_2[15:12] };
+ else
+ imm3210 = { instr_2[14], instr_2[5:3] };
+ end
+
+ always @ (*)
+ begin
+ if (rv_itype|rv_btype|rv_stype)
+ imm = { instr_2[15], instr_2[15], instr_2[15], instr_2[15], imm3210 };
+ else
+ imm = instr_2[13:6];
+ end
+
+
+ assign reg_we = valid2
+ & (reg_wen|ins_jal|ins_jalr|ins_lui) & (~ stall);
+
+ assign dmem_we = valid2 & ins_str & (~ stall);
+
+ assign arg0 = rs1_dout;
+
+ always @ (*)
+ begin
+ if (ri) begin
+ arg1 = imm[BITS-1:0];
+ end
+ else
+ arg1 = rs2_dout;
+ end
+
+
+ /// IALU ///
+
+ assign a_shamt = arg1[4:0];
+
+ assign a_result_sub = arg0 - arg1;
+
+ assign a_result_srl = arg0 >> a_shamt;
+
+ always @ (*)
+ begin
+ case (arg1[2:0])
+ 3'b000: a_sx = 8'b00000000;
+ 3'b001: a_sx = 8'b10000000;
+ 3'b010: a_sx = 8'b11000000;
+ 3'b011: a_sx = 8'b11100000;
+ 3'b100: a_sx = 8'b11110000;
+ 3'b101: a_sx = 8'b11111000;
+ 3'b110: a_sx = 8'b11111100;
+ 3'b111: a_sx = 8'b11111110;
+ endcase
+ if (arg0[BITS-1])
+ a_sign_extend = a_sx;
+ else
+ a_sign_extend = 8'd0;
+ end
+
+
+ always @ (*)
+ begin
+ case (op[2:0])
+
+ 3'b000: begin
+ if (op[3])
+ a_result = a_result_sub;
+ else
+ a_result = arg0 + arg1;
+ end
+
+ 3'b001: begin
+ a_result = arg0 << a_shamt; // sll
+ end
+
+ 3'b010: begin
+ a_result = { 7'd0, cc_neg }; // slt
+ end
+
+ 3'b011: begin
+ a_result = { 7'd0, cc_v}; // sltu
+ end
+
+ 3'b100: begin
+ a_result = arg0 ^ arg1; // xor
+ end
+
+ 3'b101: begin
+ if (op[3])
+ a_result = a_sign_extend | a_result_srl; // sra
+ else
+ a_result = a_result_srl; // srl
+ end
+
+ 3'b110: begin
+ a_result = arg0 | arg1;
+ end
+
+ 3'b111: begin
+ a_result = arg0 & arg1;
+ end
+
+ endcase
+ end
+
+ assign cc_neg = a_result_sub[BITS-1];
+ assign cc_zero = (a_result_sub == 0);
+ assign cc_v = ( cc_neg & ~(arg0[BITS-1] ^ arg1[BITS-1]))
+ | ((~arg0[BITS-1]) & arg1[BITS-1] );
+
+ assign op_result = a_result;
+
+
+ assign dmem_addr = op_result[BITS-1:0];
+ assign dmem_din[BITS-1:0] = rs2_dout;
+ assign dmem_en = (ins_str | ins_ldr) & valid2 & (~ stall);
+
+ always @ (*)
+ begin
+ if (ins_lui)
+// rd_din = { imm[1:0], 6'd0 };
+ rd_din = { imm[4:0], 3'd0 };
+ else if (ins_jal|ins_jalr)
+ rd_din = { 2'b00, pc_2 };
+ else
+ rd_din = op_result;
+ end
+
+ always @ (*)
+ begin
+ case(funct3)
+ 3'b000 : ben = cc_zero; // eq
+ 3'b001 : ben = (~cc_zero); // ne
+ 3'b010 : ben = 0;
+ 3'b011 : ben = 0;
+ 3'b100 : ben = cc_neg; // lt
+ 3'b101 : ben = (cc_zero | (~cc_neg)); // ge
+ 3'b110 : ben = cc_v; // ltu
+ 3'b111 : ben = (cc_zero | (~cc_v)); // geu
+ endcase
+ end
+
+
+ always @ (*)
+ begin
+ if (ins_jalr)
+// jump_addr = op_result[BITS-1:2];
+ jump_addr = op_result[BITS-3:0];
+ else
+ jump_addr = pc_2 + { imm[BITS-3:0] };
+ end
+ assign pc_jump = valid2 & ((ben & ins_br) | ins_jal | ins_jalr);
+
+ assign inval = pc_jump & (~ stall);
+
+ always @ (posedge clk)
+ begin
+ if (rst) begin
+ halt <= 0;
+ end
+ else if (run_not_stall & valid2) begin
+ halt <= ins_halt;
+ end
+ else begin
+ halt <= halt;
+ end
+ end
+
+ always @ (posedge clk)
+ begin
+ if (rst) begin
+ ins_ldr_3 <= 0;
+ rd_3 <= 0;
+ ri_3 <= 0;
+ end
+ else if (run_not_stall) begin
+ ins_ldr_3 <= ins_ldr;
+ rd_3 <= rd;
+ ri_3 <= ri;
+ end
+ else begin
+ ins_ldr_3 <= ins_ldr_3;
+ rd_3 <= rd_3;
+ ri_3 <= ri_3;
+ end
+ end
+
+ always @ (*)
+ begin
+
+ if ( ldr_hzd == 'd0 )
+ stall = 0;
+ else if ( (use_rs1 & ldr_hzd[rs1]) | (use_rs2 & ldr_hzd[rs2])) // RAW HZD
+ stall = 1;
+ else if ( (use_rd_e2 & ldr_hzd[rd]) | (use_rd_e1) ) // WAW conflict
+ stall = 1;
+ else
+ stall = 0;
+
+ end
+
+
+ ///////////////////////////////////////////////////////////////////////////
+ ////////// PIPELINE STAGE 4 (E2) //////////////////////////////////////
+ ///////////////////////////////////////////////////////////////////////////
+
+ assign en4 = valid_out3 & (ins_ldr_3 );
+
+ always @ (*)
+ begin
+
+ if (en4 & ins_ldr_3) begin
+ rd_sel_arb = rd_3;
+ end
+ else begin
+ rd_sel_arb = rd;
+ end
+
+ end
+ assign reg_we_arb = reg_we | (en4 & ins_ldr_3);
+
+
+ ///////////////////////////////////////////////////////////////////////////
+ ////////// REGISTERS //////////////////////////////////////////////////////
+ ///////////////////////////////////////////////////////////////////////////
+
+ /// write register
+
+ always @ (*)
+ begin
+ if (en4 & ins_ldr_3) begin
+ nxt_rd_din = dmem_dout[BITS-1:0];
+ end
+ else begin
+ nxt_rd_din = rd_din;
+ end
+ end
+
+ registers registers(
+ .clk (clk),
+ .run (run),
+ .we (reg_we_arb),
+ .rd (rd_sel_arb),
+ .rs1 (rs1),
+ .rs2 (rs2),
+ .rd_din (nxt_rd_din),
+ .rs1_dout (rs1_dout),
+ .rs2_dout (rs2_dout)
+
+// .debug_reg_sel (debug_reg_sel),
+// .debug_reg_dout (debug_reg_dout)
+ );
+
+ ///////////////////////////////////////////////////////////////////////////
+
+ /////////////////////////////
+ //////// Hazard ////////
+ /////////////////////////////
+
+ always @ (posedge clk)
+ begin
+ if (rst) begin
+ ldr_hzd <= 0;
+ end
+ else if (run)
+ if (( ~(rd==0)) & (ins_ldr ) & ~ stall) begin
+ ldr_hzd <= ('d1 << rd);
+ end
+ else begin
+ ldr_hzd <= 0;
+ end
+ else begin
+ ldr_hzd <= ldr_hzd;
+ end
+ end
+
+
+ ///////////////////////////////////////////////////////////////////////////
+
+ ///////////////////////////
+ //////// DEBUG ////////
+ ///////////////////////////
+
+// assign debug_pc = pc_2;
+// assign debug_instr[15:0] = instr_2;
+// assign debug_valid_out = { valid_out0, valid_out1, valid2, valid_out3 };
+
+endmodule
diff --git a/verilog/rtl/107_melody.v b/verilog/rtl/107_melody.v
new file mode 100644
index 0000000..d397187
--- /dev/null
+++ b/verilog/rtl/107_melody.v
@@ -0,0 +1,122 @@
+`default_nettype none
+
+module prog_melody_gen (
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+ reg [9:0] div_tmr = 0;
+ reg tick;
+ reg state;
+ reg [7:0] curr_tone;
+
+ reg [5:0] tone_seq;
+ wire [3:0] rom_rdata;
+
+ wire clock = io_in[0];
+ wire reload = io_in[1];
+ wire restart = io_in[2];
+
+ wire pgm_data = io_in[3];
+ wire pgm_strobe = io_in[4];
+
+ assign io_out[7:1] = 1'b0;
+
+ always @(posedge clock, posedge restart) begin
+ if (restart) begin
+ div_tmr <= 0;
+ tone_seq <= 0;
+ curr_tone <= 0;
+ tick <= 1'b0;
+ state <= 1'b0;
+ end else begin
+ {tick, div_tmr} <= div_tmr + 1'b1;
+ if (tick) begin
+ if (!state) begin
+ tone_seq <= tone_seq + 1'b1;
+ if (rom_rdata == 15)
+ curr_tone <= 0; // silence
+ else
+ curr_tone <= 12 + rom_rdata; // note
+ end else begin
+ curr_tone <= 0; // gap between notes
+ end
+ state <= ~state;
+ end
+ end
+ end
+
+ reg [7:0] mel_gen = 0;
+ reg mel_out;
+ always @(posedge clock) begin
+ if (mel_gen >= curr_tone)
+ mel_gen <= 0;
+ else
+ mel_gen <= mel_gen + 1'b1;
+ mel_out <= mel_gen > (curr_tone / 2);
+ end
+
+ assign io_out[0] = mel_out;
+
+ localparam C = 4'd11, CS = 4'd10, D = 4'd9, E = 4'd7, F = 4'd6, FS = 4'd5, G = 4'd4, GS = 4'd3, A = 4'd2, AS = 4'd1, B = 4'd0, S = 4'd15;
+ localparam [4*64:0] JINGLE_BELS = {
+ E, E, E, S, E, E, E, S,
+ E, G, C, D, E, S, F, F,
+ F, F, F, E, E, E, E, E,
+ D, D, E, D, S, G, S, E,
+ E, E, S, E, E, E, S, E,
+ G, C, D, E, S, F, F, F,
+ F, F, E, E, E, E, F, F,
+ E, D, C, S, S, S, S, S
+ };
+
+ wire [3:0] tone_rom[0:63];
+
+ // program shift register
+ reg [10:0] write_sr;
+ always @(posedge clock)
+ write_sr <= {pgm_data, write_sr[10:1]};
+
+ wire [5:0] pgm_word_sel = write_sr[10:5];
+ wire [3:0] pgm_write_data = write_sr[3:0];
+
+ // the tone RAM
+ generate
+ genvar ii;
+ genvar jj;
+ for (ii = 0; ii < 64; ii = ii + 1'b1) begin : words
+ wire word_we;
+ sky130_fd_sc_hd__and2_1 word_we_i ( // make sure this is really glitch free
+ .A(pgm_word_sel == ii),
+ .B(pgm_strobe),
+ .X(word_we)
+ );
+ for (jj = 0; jj < 4; jj = jj + 1'b1) begin : bits
+ localparam pgm_bit = JINGLE_BELS[(63 - ii) * 4 + jj];
+ wire lat_o;
+ sky130_fd_sc_hd__dlrtp_1 rfbit_i (
+ .GATE(word_we),
+ .RESET_B(reload),
+ .D(pgm_write_data[jj]),
+ .Q(lat_o)
+ );
+ assign tone_rom[ii][jj] = lat_o ^ pgm_bit;
+ end
+ end
+ endgenerate
+
+ assign rom_rdata = tone_rom[tone_seq];
+
+endmodule
+
+(* blackbox *)
+module sky130_fd_sc_hd__dlrtp_1(input GATE, RESET_B, D, output reg Q);
+ always @*
+ if (~RESET_B)
+ Q <= 0;
+ else if (GATE)
+ Q <= D;
+endmodule
+(* blackbox *)
+module sky130_fd_sc_hd__and2_1(input A, B, output X);
+ assign X = A & B;
+endmodule
diff --git a/verilog/rtl/108_melody.v b/verilog/rtl/108_melody.v
new file mode 100644
index 0000000..d397187
--- /dev/null
+++ b/verilog/rtl/108_melody.v
@@ -0,0 +1,122 @@
+`default_nettype none
+
+module prog_melody_gen (
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+ reg [9:0] div_tmr = 0;
+ reg tick;
+ reg state;
+ reg [7:0] curr_tone;
+
+ reg [5:0] tone_seq;
+ wire [3:0] rom_rdata;
+
+ wire clock = io_in[0];
+ wire reload = io_in[1];
+ wire restart = io_in[2];
+
+ wire pgm_data = io_in[3];
+ wire pgm_strobe = io_in[4];
+
+ assign io_out[7:1] = 1'b0;
+
+ always @(posedge clock, posedge restart) begin
+ if (restart) begin
+ div_tmr <= 0;
+ tone_seq <= 0;
+ curr_tone <= 0;
+ tick <= 1'b0;
+ state <= 1'b0;
+ end else begin
+ {tick, div_tmr} <= div_tmr + 1'b1;
+ if (tick) begin
+ if (!state) begin
+ tone_seq <= tone_seq + 1'b1;
+ if (rom_rdata == 15)
+ curr_tone <= 0; // silence
+ else
+ curr_tone <= 12 + rom_rdata; // note
+ end else begin
+ curr_tone <= 0; // gap between notes
+ end
+ state <= ~state;
+ end
+ end
+ end
+
+ reg [7:0] mel_gen = 0;
+ reg mel_out;
+ always @(posedge clock) begin
+ if (mel_gen >= curr_tone)
+ mel_gen <= 0;
+ else
+ mel_gen <= mel_gen + 1'b1;
+ mel_out <= mel_gen > (curr_tone / 2);
+ end
+
+ assign io_out[0] = mel_out;
+
+ localparam C = 4'd11, CS = 4'd10, D = 4'd9, E = 4'd7, F = 4'd6, FS = 4'd5, G = 4'd4, GS = 4'd3, A = 4'd2, AS = 4'd1, B = 4'd0, S = 4'd15;
+ localparam [4*64:0] JINGLE_BELS = {
+ E, E, E, S, E, E, E, S,
+ E, G, C, D, E, S, F, F,
+ F, F, F, E, E, E, E, E,
+ D, D, E, D, S, G, S, E,
+ E, E, S, E, E, E, S, E,
+ G, C, D, E, S, F, F, F,
+ F, F, E, E, E, E, F, F,
+ E, D, C, S, S, S, S, S
+ };
+
+ wire [3:0] tone_rom[0:63];
+
+ // program shift register
+ reg [10:0] write_sr;
+ always @(posedge clock)
+ write_sr <= {pgm_data, write_sr[10:1]};
+
+ wire [5:0] pgm_word_sel = write_sr[10:5];
+ wire [3:0] pgm_write_data = write_sr[3:0];
+
+ // the tone RAM
+ generate
+ genvar ii;
+ genvar jj;
+ for (ii = 0; ii < 64; ii = ii + 1'b1) begin : words
+ wire word_we;
+ sky130_fd_sc_hd__and2_1 word_we_i ( // make sure this is really glitch free
+ .A(pgm_word_sel == ii),
+ .B(pgm_strobe),
+ .X(word_we)
+ );
+ for (jj = 0; jj < 4; jj = jj + 1'b1) begin : bits
+ localparam pgm_bit = JINGLE_BELS[(63 - ii) * 4 + jj];
+ wire lat_o;
+ sky130_fd_sc_hd__dlrtp_1 rfbit_i (
+ .GATE(word_we),
+ .RESET_B(reload),
+ .D(pgm_write_data[jj]),
+ .Q(lat_o)
+ );
+ assign tone_rom[ii][jj] = lat_o ^ pgm_bit;
+ end
+ end
+ endgenerate
+
+ assign rom_rdata = tone_rom[tone_seq];
+
+endmodule
+
+(* blackbox *)
+module sky130_fd_sc_hd__dlrtp_1(input GATE, RESET_B, D, output reg Q);
+ always @*
+ if (~RESET_B)
+ Q <= 0;
+ else if (GATE)
+ Q <= D;
+endmodule
+(* blackbox *)
+module sky130_fd_sc_hd__and2_1(input A, B, output X);
+ assign X = A & B;
+endmodule
diff --git a/verilog/rtl/108_rotaryencoder.v b/verilog/rtl/108_rotaryencoder.v
new file mode 100644
index 0000000..02ab56e
--- /dev/null
+++ b/verilog/rtl/108_rotaryencoder.v
@@ -0,0 +1,44 @@
+`default_nettype none
+
+module vaishnavachath_rotary_toplevel (
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+
+ wire clk_in = io_in[0];
+ wire reset = io_in[1];
+ wire rt_a;
+ wire rt_b;
+ wire tm_enable = io_in[4];
+ wire [6:0] led_out;
+ assign io_out[6:0] = led_out;
+ reg [3:0] enc_byte = 0;
+ reg [3:0] counter = 0;
+ reg rt_a_delayed, rt_b_delayed, clk_msb_delayed;
+ assign rt_a = tm_enable ? counter[3] : io_in[2];
+ assign rt_b = tm_enable ? clk_msb_delayed : io_in[3];
+ wire count_enable = rt_a ^ rt_a_delayed ^ rt_b ^ rt_b_delayed;
+ wire count_direction = rt_a ^ rt_b_delayed;
+
+ always @(posedge clk_in) rt_a_delayed <= rt_a;
+ always @(posedge clk_in) rt_b_delayed <= rt_b;
+ always @(posedge clk_in) clk_msb_delayed <= counter[3];
+
+ always @(posedge clk_in) begin
+ if(count_enable) begin
+ if(count_direction) enc_byte<=enc_byte+1; else enc_byte<=enc_byte-1;
+ end
+ end
+
+
+ always @(posedge clk_in) begin
+ if (reset) begin
+ counter <= 0;
+ end else begin
+ counter <= counter + 1'b1;
+ end
+ end
+
+ seg7 seg7(.counter(enc_byte), .segments(led_out));
+
+endmodule
diff --git a/verilog/rtl/109_rotaryencoder.v b/verilog/rtl/109_rotaryencoder.v
new file mode 100644
index 0000000..02ab56e
--- /dev/null
+++ b/verilog/rtl/109_rotaryencoder.v
@@ -0,0 +1,44 @@
+`default_nettype none
+
+module vaishnavachath_rotary_toplevel (
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+
+ wire clk_in = io_in[0];
+ wire reset = io_in[1];
+ wire rt_a;
+ wire rt_b;
+ wire tm_enable = io_in[4];
+ wire [6:0] led_out;
+ assign io_out[6:0] = led_out;
+ reg [3:0] enc_byte = 0;
+ reg [3:0] counter = 0;
+ reg rt_a_delayed, rt_b_delayed, clk_msb_delayed;
+ assign rt_a = tm_enable ? counter[3] : io_in[2];
+ assign rt_b = tm_enable ? clk_msb_delayed : io_in[3];
+ wire count_enable = rt_a ^ rt_a_delayed ^ rt_b ^ rt_b_delayed;
+ wire count_direction = rt_a ^ rt_b_delayed;
+
+ always @(posedge clk_in) rt_a_delayed <= rt_a;
+ always @(posedge clk_in) rt_b_delayed <= rt_b;
+ always @(posedge clk_in) clk_msb_delayed <= counter[3];
+
+ always @(posedge clk_in) begin
+ if(count_enable) begin
+ if(count_direction) enc_byte<=enc_byte+1; else enc_byte<=enc_byte-1;
+ end
+ end
+
+
+ always @(posedge clk_in) begin
+ if (reset) begin
+ counter <= 0;
+ end else begin
+ counter <= counter + 1'b1;
+ end
+ end
+
+ seg7 seg7(.counter(enc_byte), .segments(led_out));
+
+endmodule
diff --git a/verilog/rtl/111_rotary_encoder.v b/verilog/rtl/111_rotary_encoder.v
new file mode 100644
index 0000000..3b1a2ff
--- /dev/null
+++ b/verilog/rtl/111_rotary_encoder.v
@@ -0,0 +1,78 @@
+`timescale 1ns / 1ps
+`default_nettype none
+
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 30.11.2022 08:21:55
+// Design Name:
+// Module Name: rotary_encoder
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+module rotary_encoder (
+ input wire [7:0] io_in,
+ output wire [7:0] io_out
+);
+
+ wire clk = io_in[0];
+ wire reset = io_in[1];
+ wire encA = io_in[2];
+ wire encB = io_in[3];
+ wire [6:0] led_out;
+ assign io_out[6:0] = led_out;
+ assign io_out[7] = 0;
+
+ reg [7:0] delay_counter;
+ reg [3:0] digit;
+ reg old_value;
+
+ always @(posedge clk) begin
+ // if reset, set counter to 0
+ if (reset) begin
+ digit <= 0;
+ old_value <= encA;
+ delay_counter <= 0;
+ end else begin
+ if (delay_counter != 0) begin
+ delay_counter <= delay_counter - 1'b1;
+ end
+ if (encA == 1 && old_value == 0 && delay_counter == 0) begin
+ delay_counter = 125; //IOrefreshrate = 12.5Khz => clock = 6.25KHz => delay 20ms = 125 cycles
+ //rising edge on A
+ if(encB == 0) begin
+ // increment digit
+ digit <= digit + 1'b1;
+
+ // only count from 0 to 9
+ if (digit == 9) begin
+ digit <= 0;
+ end
+ end else begin
+ // decrement digit
+ if (digit == 0) begin
+ digit <= 9;
+ end else begin
+ digit <= digit - 1'b1;
+ end
+ end
+ end
+ old_value = encA;
+ end
+ end
+
+ // instantiate segment display
+ seg7 seg7(.counter(digit), .segments(led_out));
+
+endmodule
diff --git a/verilog/rtl/112_frog.v b/verilog/rtl/112_frog.v
new file mode 100644
index 0000000..d496b40
--- /dev/null
+++ b/verilog/rtl/112_frog.v
@@ -0,0 +1,119 @@
+`default_nettype none
+
+module frog(
+ input [7:0] io_in,
+ output [7:0] io_out
+ );
+
+ localparam OP_NGA = 4'h0;
+ localparam OP_AND = 4'h1;
+ localparam OP_OR = 4'h2;
+ localparam OP_XOR = 4'h3;
+ localparam OP_SLL = 4'h4;
+ localparam OP_SRL = 4'h5;
+ localparam OP_SRA = 4'h6;
+ localparam OP_ADD = 4'h7;
+ localparam OP_NOP = 4'h8;
+ localparam OP_BEQ = 4'h9;
+ localparam OP_BLE = 4'hA;
+ localparam OP_JMP = 4'hB;
+ localparam OP_LDA = 4'hC;
+ localparam OP_LDB = 4'hD;
+ localparam OP_STA = 4'hE;
+ localparam OP_STB = 4'hF;
+
+ wire clk = io_in[0];
+ wire rst_p = io_in[1];
+ wire[3:0] data_in = io_in[5:2];
+ wire fast = io_in[7];
+
+ wire wcyc;
+ wire[6:0] addr;
+
+ reg[3:0] reg_a;
+ reg[3:0] reg_b;
+ reg[6:0] tmp;
+ reg[6:0] pc;
+
+ reg[2:0] opcode_lsb;
+
+ localparam STATE_ADDR = 3'h0; //Fetch
+ localparam STATE_OP = 3'h1; //Execute
+ localparam STATE_MEM1 = 3'h2; //AddrH
+ localparam STATE_MEM2 = 3'h3; //AddrL
+ localparam STATE_MEM3 = 3'h4; //Load or Put Write ADDR
+ localparam STATE_MEM4 = 3'h5; //Write DATA
+ reg[2:0] state;
+ reg[2:0] next_state;
+
+ always@(posedge clk or posedge rst_p) begin
+ if(rst_p) begin
+ opcode_lsb <= 0;
+ end else begin
+ if(next_state == STATE_OP)
+ opcode_lsb <= 0;
+ else if(state == STATE_OP) begin
+ opcode_lsb <= data_in[2:0];
+ end
+ end
+ end
+
+ always@(posedge clk or posedge rst_p) begin
+ if(rst_p) state <= STATE_ADDR;
+ else state <= next_state;
+ end
+
+ always@(*) begin
+ next_state <= fast ? STATE_OP : STATE_ADDR;
+ case(state)
+ STATE_ADDR: next_state <= STATE_OP;
+ STATE_OP: if(data_in[3] & |data_in[2:0]) next_state <= STATE_MEM1;
+ STATE_MEM1: next_state <= STATE_MEM2;
+ STATE_MEM2: if(opcode_lsb[2]) next_state <= STATE_MEM3;
+ STATE_MEM3: if(opcode_lsb[1]) next_state <= STATE_MEM4;
+ endcase
+ end
+
+ always@(posedge clk or posedge rst_p) begin
+ if(rst_p) begin
+ reg_a <= 0;
+ reg_b <= 0;
+ end else begin
+ if(state == STATE_OP)
+ case(data_in[2:0])
+ OP_AND: reg_a <= reg_a & reg_b;
+ OP_NGA: reg_a <= ~reg_a + 1;
+ OP_OR: reg_a <= reg_a | reg_b;
+ OP_XOR: reg_a <= reg_a ^ reg_b;
+ OP_SLL: reg_a <= reg_a << reg_b[1:0];
+ OP_SRL: reg_a <= reg_a >> reg_b[1:0];
+ OP_SRA: reg_a <= reg_a >>> reg_b[1:0];
+ OP_ADD: reg_a <= reg_a + reg_b;
+ endcase
+ else if(state == STATE_MEM3 && !opcode_lsb[1])
+ if(opcode_lsb[0]) reg_b <= data_in;
+ else reg_a <= data_in;
+ end
+ end
+
+ always@(posedge clk or posedge rst_p) begin
+ if(rst_p)
+ tmp <= 0;
+ else if(state == STATE_MEM1) tmp[6:4] <= data_in[2:0];
+ else if(state == STATE_MEM2) tmp[3:0] <= data_in;
+ end
+
+ always@(posedge clk or posedge rst_p) begin
+ if(rst_p) pc <= 0;
+ else if(state == STATE_MEM2 && ((opcode_lsb[2:0]==OP_BLE[2:0]) && (reg_a <= reg_b))) pc <= pc + {tmp[6:4],data_in};
+ else if(state == STATE_MEM2 && ((opcode_lsb[2:0]==OP_BEQ[2:0]) && (reg_a == reg_b))) pc <= pc + {tmp[6:4],data_in};
+ else if(state == STATE_MEM2 && (opcode_lsb[2:0]==OP_JMP)) pc <= {tmp[6:4],data_in};
+ else if(state == STATE_OP || state == STATE_MEM1 || state == STATE_MEM2) pc <= pc + 1;
+ end
+
+ assign wcyc = ((state == STATE_MEM3) || (state == STATE_MEM4)) & opcode_lsb[1];
+ assign addr = ((state == STATE_MEM3) || (state == STATE_MEM4)) ? tmp : pc;
+ assign io_out[6:0] = state == STATE_MEM4 ? (opcode_lsb[0] ? {3'b0,reg_b} : {3'b0,reg_a}) : addr;
+ assign io_out[7] = wcyc;
+
+endmodule
diff --git a/verilog/rtl/112_rotary_encoder.v b/verilog/rtl/112_rotary_encoder.v
new file mode 100644
index 0000000..3b1a2ff
--- /dev/null
+++ b/verilog/rtl/112_rotary_encoder.v
@@ -0,0 +1,78 @@
+`timescale 1ns / 1ps
+`default_nettype none
+
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 30.11.2022 08:21:55
+// Design Name:
+// Module Name: rotary_encoder
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+module rotary_encoder (
+ input wire [7:0] io_in,
+ output wire [7:0] io_out
+);
+
+ wire clk = io_in[0];
+ wire reset = io_in[1];
+ wire encA = io_in[2];
+ wire encB = io_in[3];
+ wire [6:0] led_out;
+ assign io_out[6:0] = led_out;
+ assign io_out[7] = 0;
+
+ reg [7:0] delay_counter;
+ reg [3:0] digit;
+ reg old_value;
+
+ always @(posedge clk) begin
+ // if reset, set counter to 0
+ if (reset) begin
+ digit <= 0;
+ old_value <= encA;
+ delay_counter <= 0;
+ end else begin
+ if (delay_counter != 0) begin
+ delay_counter <= delay_counter - 1'b1;
+ end
+ if (encA == 1 && old_value == 0 && delay_counter == 0) begin
+ delay_counter = 125; //IOrefreshrate = 12.5Khz => clock = 6.25KHz => delay 20ms = 125 cycles
+ //rising edge on A
+ if(encB == 0) begin
+ // increment digit
+ digit <= digit + 1'b1;
+
+ // only count from 0 to 9
+ if (digit == 9) begin
+ digit <= 0;
+ end
+ end else begin
+ // decrement digit
+ if (digit == 0) begin
+ digit <= 9;
+ end else begin
+ digit <= digit - 1'b1;
+ end
+ end
+ end
+ old_value = encA;
+ end
+ end
+
+ // instantiate segment display
+ seg7 seg7(.counter(digit), .segments(led_out));
+
+endmodule
diff --git a/verilog/rtl/113_frog.v b/verilog/rtl/113_frog.v
new file mode 100644
index 0000000..d496b40
--- /dev/null
+++ b/verilog/rtl/113_frog.v
@@ -0,0 +1,119 @@
+`default_nettype none
+
+module frog(
+ input [7:0] io_in,
+ output [7:0] io_out
+ );
+
+ localparam OP_NGA = 4'h0;
+ localparam OP_AND = 4'h1;
+ localparam OP_OR = 4'h2;
+ localparam OP_XOR = 4'h3;
+ localparam OP_SLL = 4'h4;
+ localparam OP_SRL = 4'h5;
+ localparam OP_SRA = 4'h6;
+ localparam OP_ADD = 4'h7;
+ localparam OP_NOP = 4'h8;
+ localparam OP_BEQ = 4'h9;
+ localparam OP_BLE = 4'hA;
+ localparam OP_JMP = 4'hB;
+ localparam OP_LDA = 4'hC;
+ localparam OP_LDB = 4'hD;
+ localparam OP_STA = 4'hE;
+ localparam OP_STB = 4'hF;
+
+ wire clk = io_in[0];
+ wire rst_p = io_in[1];
+ wire[3:0] data_in = io_in[5:2];
+ wire fast = io_in[7];
+
+ wire wcyc;
+ wire[6:0] addr;
+
+ reg[3:0] reg_a;
+ reg[3:0] reg_b;
+ reg[6:0] tmp;
+ reg[6:0] pc;
+
+ reg[2:0] opcode_lsb;
+
+ localparam STATE_ADDR = 3'h0; //Fetch
+ localparam STATE_OP = 3'h1; //Execute
+ localparam STATE_MEM1 = 3'h2; //AddrH
+ localparam STATE_MEM2 = 3'h3; //AddrL
+ localparam STATE_MEM3 = 3'h4; //Load or Put Write ADDR
+ localparam STATE_MEM4 = 3'h5; //Write DATA
+ reg[2:0] state;
+ reg[2:0] next_state;
+
+ always@(posedge clk or posedge rst_p) begin
+ if(rst_p) begin
+ opcode_lsb <= 0;
+ end else begin
+ if(next_state == STATE_OP)
+ opcode_lsb <= 0;
+ else if(state == STATE_OP) begin
+ opcode_lsb <= data_in[2:0];
+ end
+ end
+ end
+
+ always@(posedge clk or posedge rst_p) begin
+ if(rst_p) state <= STATE_ADDR;
+ else state <= next_state;
+ end
+
+ always@(*) begin
+ next_state <= fast ? STATE_OP : STATE_ADDR;
+ case(state)
+ STATE_ADDR: next_state <= STATE_OP;
+ STATE_OP: if(data_in[3] & |data_in[2:0]) next_state <= STATE_MEM1;
+ STATE_MEM1: next_state <= STATE_MEM2;
+ STATE_MEM2: if(opcode_lsb[2]) next_state <= STATE_MEM3;
+ STATE_MEM3: if(opcode_lsb[1]) next_state <= STATE_MEM4;
+ endcase
+ end
+
+ always@(posedge clk or posedge rst_p) begin
+ if(rst_p) begin
+ reg_a <= 0;
+ reg_b <= 0;
+ end else begin
+ if(state == STATE_OP)
+ case(data_in[2:0])
+ OP_AND: reg_a <= reg_a & reg_b;
+ OP_NGA: reg_a <= ~reg_a + 1;
+ OP_OR: reg_a <= reg_a | reg_b;
+ OP_XOR: reg_a <= reg_a ^ reg_b;
+ OP_SLL: reg_a <= reg_a << reg_b[1:0];
+ OP_SRL: reg_a <= reg_a >> reg_b[1:0];
+ OP_SRA: reg_a <= reg_a >>> reg_b[1:0];
+ OP_ADD: reg_a <= reg_a + reg_b;
+ endcase
+ else if(state == STATE_MEM3 && !opcode_lsb[1])
+ if(opcode_lsb[0]) reg_b <= data_in;
+ else reg_a <= data_in;
+ end
+ end
+
+ always@(posedge clk or posedge rst_p) begin
+ if(rst_p)
+ tmp <= 0;
+ else if(state == STATE_MEM1) tmp[6:4] <= data_in[2:0];
+ else if(state == STATE_MEM2) tmp[3:0] <= data_in;
+ end
+
+ always@(posedge clk or posedge rst_p) begin
+ if(rst_p) pc <= 0;
+ else if(state == STATE_MEM2 && ((opcode_lsb[2:0]==OP_BLE[2:0]) && (reg_a <= reg_b))) pc <= pc + {tmp[6:4],data_in};
+ else if(state == STATE_MEM2 && ((opcode_lsb[2:0]==OP_BEQ[2:0]) && (reg_a == reg_b))) pc <= pc + {tmp[6:4],data_in};
+ else if(state == STATE_MEM2 && (opcode_lsb[2:0]==OP_JMP)) pc <= {tmp[6:4],data_in};
+ else if(state == STATE_OP || state == STATE_MEM1 || state == STATE_MEM2) pc <= pc + 1;
+ end
+
+ assign wcyc = ((state == STATE_MEM3) || (state == STATE_MEM4)) & opcode_lsb[1];
+ assign addr = ((state == STATE_MEM3) || (state == STATE_MEM4)) ? tmp : pc;
+ assign io_out[6:0] = state == STATE_MEM4 ? (opcode_lsb[0] ? {3'b0,reg_b} : {3'b0,reg_a}) : addr;
+ assign io_out[7] = wcyc;
+
+endmodule
diff --git a/verilog/rtl/113_swalense_top.v b/verilog/rtl/113_swalense_top.v
new file mode 100644
index 0000000..17f77e9
--- /dev/null
+++ b/verilog/rtl/113_swalense_top.v
@@ -0,0 +1,772 @@
+/* Generated by Yosys 0.23+8 (git sha1 48659ee2b, clang 14.0.0 -fPIC -Os) */
+
+module counter(rst, wrap, init_value, max_value, inc, strobe, reset, value, updating_strobe, clk);
+ reg \$auto$verilog_backend.cc:2083:dump_module$1 = 0;
+ wire \$1 ;
+ wire [9:0] \$11 ;
+ wire [8:0] \$12 ;
+ wire [8:0] \$14 ;
+ wire [1:0] \$15 ;
+ wire [9:0] \$18 ;
+ wire [7:0] \$20 ;
+ wire \$3 ;
+ wire \$5 ;
+ wire \$7 ;
+ wire \$9 ;
+ wire can_update;
+ input clk;
+ wire clk;
+ input inc;
+ wire inc;
+ input [7:0] init_value;
+ wire [7:0] init_value;
+ input [7:0] max_value;
+ wire [7:0] max_value;
+ input reset;
+ wire reset;
+ input rst;
+ wire rst;
+ input strobe;
+ wire strobe;
+ output updating_strobe;
+ wire updating_strobe;
+ output [7:0] value;
+ reg [7:0] value = 8'h00;
+ reg [7:0] \value$next ;
+ input wrap;
+ wire wrap;
+ assign \$9 = strobe & \$7 ;
+ assign \$12 = + value;
+ assign \$15 = inc ? 2'h1 : 2'h3;
+ assign \$14 = + $signed(\$15 );
+ assign \$18 = $signed(\$12 ) + $signed(\$14 );
+ assign \$1 = value != max_value;
+ assign \$20 = inc ? 8'h00 : max_value;
+ always @(posedge clk)
+ value <= \value$next ;
+ assign \$3 = | value;
+ assign \$5 = inc ? \$1 : \$3 ;
+ assign \$7 = wrap | can_update;
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
+ \value$next = value;
+ casez ({ updating_strobe, reset })
+ 2'b?1:
+ \value$next = init_value;
+ 2'b1?:
+ (* full_case = 32'd1 *)
+ casez (can_update)
+ 1'h1:
+ \value$next = \$18 [7:0];
+ default:
+ \value$next = \$20 ;
+ endcase
+ endcase
+ casez (rst)
+ 1'h1:
+ \value$next = 8'h00;
+ endcase
+ end
+ assign \$11 = \$18 ;
+ assign updating_strobe = \$9 ;
+ assign can_update = \$5 ;
+endmodule
+
+module decoder(rst, channels, direction, force_x2, debounce, x1_value, strobe_x2, strobe_x4, strobe_x1, clk);
+ reg \$auto$verilog_backend.cc:2083:dump_module$2 = 0;
+ wire \$1 ;
+ wire \$11 ;
+ wire \$13 ;
+ wire \$15 ;
+ wire \$17 ;
+ wire \$19 ;
+ wire \$21 ;
+ wire \$23 ;
+ wire \$25 ;
+ wire \$27 ;
+ wire \$29 ;
+ wire \$3 ;
+ wire [1:0] \$5 ;
+ wire \$7 ;
+ wire \$9 ;
+ input [1:0] channels;
+ wire [1:0] channels;
+ input clk;
+ wire clk;
+ input debounce;
+ wire debounce;
+ wire dir;
+ output direction;
+ reg direction = 1'h0;
+ reg \direction$next ;
+ input force_x2;
+ wire force_x2;
+ reg [1:0] prev_channels = 2'h0;
+ reg [1:0] \prev_channels$next ;
+ input rst;
+ wire rst;
+ output strobe_x1;
+ wire strobe_x1;
+ output strobe_x2;
+ wire strobe_x2;
+ output strobe_x4;
+ reg strobe_x4 = 1'h0;
+ reg \strobe_x4$next ;
+ input [1:0] x1_value;
+ wire [1:0] x1_value;
+ assign \$9 = \$3 | \$7 ;
+ assign \$11 = strobe_x4 & \$9 ;
+ assign \$13 = channels == x1_value;
+ assign \$15 = strobe_x4 & \$13 ;
+ assign \$17 = force_x2 ? strobe_x2 : \$15 ;
+ assign \$1 = channels[0] ^ prev_channels[1];
+ assign \$19 = channels != prev_channels;
+ assign \$21 = dir == direction;
+ assign \$23 = ~ debounce;
+ assign \$25 = \$21 | \$23 ;
+ assign \$27 = channels != prev_channels;
+ assign \$29 = channels != prev_channels;
+ always @(posedge clk)
+ strobe_x4 <= \strobe_x4$next ;
+ always @(posedge clk)
+ prev_channels <= \prev_channels$next ;
+ always @(posedge clk)
+ direction <= \direction$next ;
+ assign \$3 = channels == x1_value;
+ assign \$5 = ~ x1_value;
+ assign \$7 = channels == \$5 ;
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
+ \strobe_x4$next = 1'h0;
+ casez (\$19 )
+ 1'h1:
+ \strobe_x4$next = \$25 ;
+ endcase
+ casez (rst)
+ 1'h1:
+ \strobe_x4$next = 1'h0;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
+ \prev_channels$next = prev_channels;
+ casez (\$27 )
+ 1'h1:
+ \prev_channels$next = channels;
+ endcase
+ casez (rst)
+ 1'h1:
+ \prev_channels$next = channels;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
+ \direction$next = direction;
+ casez (\$29 )
+ 1'h1:
+ \direction$next = dir;
+ endcase
+ casez (rst)
+ 1'h1:
+ \direction$next = 1'h0;
+ endcase
+ end
+ assign strobe_x1 = \$17 ;
+ assign strobe_x2 = \$11 ;
+ assign dir = \$1 ;
+endmodule
+
+module dev(rst, channels, force_x2, cs, sck, sdi, tx, pwm_signal, direction, counter, clk);
+ wire \$2 ;
+ wire \$4 ;
+ wire \$6 ;
+ wire [1:0] \$signal ;
+ input [1:0] channels;
+ wire [1:0] channels;
+ input clk;
+ wire clk;
+ output [7:0] counter;
+ wire [7:0] counter;
+ wire counter_inc;
+ wire [7:0] counter_init_value;
+ wire [7:0] counter_max_value;
+ wire counter_reset;
+ wire counter_strobe;
+ wire counter_updating_strobe;
+ wire [7:0] counter_value;
+ wire counter_wrap;
+ input cs;
+ wire cs;
+ wire decoder_debounce;
+ wire decoder_force_x2;
+ wire decoder_strobe_x1;
+ wire decoder_strobe_x2;
+ wire decoder_strobe_x4;
+ wire [1:0] decoder_x1_value;
+ output direction;
+ wire direction;
+ input force_x2;
+ wire force_x2;
+ wire gearbox_enable;
+ wire gearbox_strobe;
+ wire [7:0] gearbox_timer_cycles;
+ wire [7:0] pwm_duty;
+ wire [7:0] pwm_max_duty;
+ output pwm_signal;
+ wire pwm_signal;
+ input rst;
+ wire rst;
+ input sck;
+ wire sck;
+ input sdi;
+ wire sdi;
+ wire serial_out_strobe;
+ wire [7:0] serial_out_word;
+ wire spi_busy;
+ wire spi_cs;
+ wire [31:0] spi_data;
+ wire spi_force_x2;
+ wire spi_sck;
+ wire spi_sdi;
+ wire spi_strobe;
+ output tx;
+ wire tx;
+ assign \$2 = force_x2 | spi_force_x2;
+ assign \$4 = ~ spi_busy;
+ assign \$6 = \$4 & gearbox_strobe;
+ counter \counter$1 (
+ .clk(clk),
+ .inc(counter_inc),
+ .init_value(counter_init_value),
+ .max_value(counter_max_value),
+ .reset(counter_reset),
+ .rst(rst),
+ .strobe(counter_strobe),
+ .updating_strobe(counter_updating_strobe),
+ .value(counter_value),
+ .wrap(counter_wrap)
+ );
+ decoder decoder (
+ .channels(channels),
+ .clk(clk),
+ .debounce(decoder_debounce),
+ .direction(direction),
+ .force_x2(decoder_force_x2),
+ .rst(rst),
+ .strobe_x1(decoder_strobe_x1),
+ .strobe_x2(decoder_strobe_x2),
+ .strobe_x4(decoder_strobe_x4),
+ .x1_value(decoder_x1_value)
+ );
+ gearbox gearbox (
+ .clk(clk),
+ .enable(gearbox_enable),
+ .rst(rst),
+ .strobe(gearbox_strobe),
+ .strobe_x1(decoder_strobe_x1),
+ .strobe_x2(decoder_strobe_x2),
+ .strobe_x4(decoder_strobe_x4),
+ .timer_cycles(gearbox_timer_cycles)
+ );
+ pwm pwm (
+ .clk(clk),
+ .duty(pwm_duty),
+ .max_duty(pwm_max_duty),
+ .pwm_signal(pwm_signal),
+ .rst(rst)
+ );
+ serial_out serial_out (
+ .clk(clk),
+ .rst(rst),
+ .strobe(serial_out_strobe),
+ .tx(tx),
+ .word(serial_out_word)
+ );
+ spi spi (
+ .busy(spi_busy),
+ .clk(clk),
+ .cs(spi_cs),
+ .data(spi_data),
+ .rst(rst),
+ .sck(spi_sck),
+ .sdi(spi_sdi),
+ .strobe(spi_strobe)
+ );
+ assign serial_out_strobe = counter_updating_strobe;
+ assign serial_out_word = counter_value;
+ assign pwm_max_duty = counter_max_value;
+ assign pwm_duty = counter_value;
+ assign counter = counter_value;
+ assign counter_reset = spi_strobe;
+ assign counter_strobe = \$6 ;
+ assign counter_inc = direction;
+ assign { counter_max_value, counter_init_value, gearbox_timer_cycles, \$signal , spi_force_x2, decoder_x1_value, decoder_debounce, counter_wrap, gearbox_enable } = spi_data;
+ assign spi_sdi = sdi;
+ assign spi_sck = sck;
+ assign spi_cs = cs;
+ assign decoder_force_x2 = \$2 ;
+endmodule
+
+module gearbox(rst, enable, timer_cycles, strobe, strobe_x2, strobe_x4, strobe_x1, clk);
+ reg \$auto$verilog_backend.cc:2083:dump_module$3 = 0;
+ wire [8:0] \$1 ;
+ wire [5:0] \$10 ;
+ wire [5:0] \$11 ;
+ wire \$13 ;
+ wire \$14 ;
+ wire \$17 ;
+ wire [5:0] \$19 ;
+ wire [8:0] \$2 ;
+ wire [5:0] \$20 ;
+ wire [4:0] \$22 ;
+ wire [4:0] \$23 ;
+ wire [1:0] \$25 ;
+ wire \$27 ;
+ wire \$29 ;
+ wire \$31 ;
+ wire \$4 ;
+ wire \$6 ;
+ wire \$8 ;
+ input clk;
+ wire clk;
+ input enable;
+ wire enable;
+ wire [1:0] g;
+ wire [1:0] gear;
+ reg [7:0] period = 8'h7f;
+ reg [7:0] \period$next ;
+ input rst;
+ wire rst;
+ output strobe;
+ reg strobe;
+ input strobe_x1;
+ wire strobe_x1;
+ input strobe_x2;
+ wire strobe_x2;
+ input strobe_x4;
+ wire strobe_x4;
+ reg [4:0] threshold = 5'h00;
+ reg [4:0] \threshold$next ;
+ input [7:0] timer_cycles;
+ wire [7:0] timer_cycles;
+ assign \$11 = threshold - 1'h1;
+ assign \$14 = & threshold;
+ assign \$13 = ~ \$14 ;
+ assign \$17 = strobe_x4 & \$13 ;
+ assign \$20 = threshold + 1'h1;
+ assign \$25 = g[1] ? 2'h2 : g;
+ assign \$2 = period + 1'h1;
+ assign \$29 = enable ? strobe_x2 : strobe_x1;
+ assign \$31 = enable ? strobe_x4 : strobe_x1;
+ always @(posedge clk)
+ period <= \period$next ;
+ always @(posedge clk)
+ threshold <= \threshold$next ;
+ assign \$4 = period == timer_cycles;
+ assign \$6 = period == timer_cycles;
+ assign \$8 = | threshold;
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
+ \period$next = \$2 [7:0];
+ casez (\$4 )
+ 1'h1:
+ \period$next = 8'h00;
+ endcase
+ casez (rst)
+ 1'h1:
+ \period$next = 8'h7f;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
+ \threshold$next = threshold;
+ casez (\$6 )
+ 1'h1:
+ casez (\$8 )
+ 1'h1:
+ \threshold$next = \$11 [4:0];
+ endcase
+ endcase
+ casez (\$17 )
+ 1'h1:
+ \threshold$next = \$20 [4:0];
+ endcase
+ casez (rst)
+ 1'h1:
+ \threshold$next = 5'h00;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
+ (* full_case = 32'd1 *)
+ casez (gear)
+ 2'h0:
+ strobe = \$27 ;
+ 2'h1:
+ strobe = \$29 ;
+ 2'h?:
+ strobe = \$31 ;
+ endcase
+ end
+ assign \$1 = \$2 ;
+ assign \$10 = \$11 ;
+ assign \$19 = \$20 ;
+ assign \$22 = \$23 ;
+ assign gear = \$25 ;
+ assign g = \$23 [1:0];
+ assign \$23 = { 3'h0, threshold[4:3] };
+ assign \$27 = strobe_x1;
+endmodule
+
+module pwm(rst, pwm_signal, duty, max_duty, clk);
+ reg \$auto$verilog_backend.cc:2083:dump_module$4 = 0;
+ wire [8:0] \$1 ;
+ wire \$10 ;
+ wire \$12 ;
+ wire [8:0] \$2 ;
+ wire \$4 ;
+ wire \$6 ;
+ wire \$8 ;
+ input clk;
+ wire clk;
+ reg [7:0] counter = 8'h00;
+ reg [7:0] \counter$next ;
+ input [7:0] duty;
+ wire [7:0] duty;
+ input [7:0] max_duty;
+ wire [7:0] max_duty;
+ output pwm_signal;
+ reg pwm_signal = 1'h0;
+ reg \pwm_signal$next ;
+ input rst;
+ wire rst;
+ assign \$10 = counter == duty;
+ assign \$12 = | duty;
+ always @(posedge clk)
+ counter <= \counter$next ;
+ always @(posedge clk)
+ pwm_signal <= \pwm_signal$next ;
+ assign \$2 = counter + 1'h1;
+ assign \$4 = counter == max_duty;
+ assign \$6 = counter == duty;
+ assign \$8 = counter == max_duty;
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$4 ) begin end
+ \counter$next = \$2 [7:0];
+ casez ({ \$6 , \$4 })
+ 2'b?1:
+ \counter$next = 8'h00;
+ endcase
+ casez (rst)
+ 1'h1:
+ \counter$next = 8'h00;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$4 ) begin end
+ \pwm_signal$next = pwm_signal;
+ casez ({ \$10 , \$8 })
+ 2'b?1:
+ \pwm_signal$next = \$12 ;
+ 2'b1?:
+ \pwm_signal$next = 1'h0;
+ endcase
+ casez (rst)
+ 1'h1:
+ \pwm_signal$next = 1'h0;
+ endcase
+ end
+ assign \$1 = \$2 ;
+endmodule
+
+module serial_out(rst, tx, word, strobe, clk);
+ reg \$auto$verilog_backend.cc:2083:dump_module$5 = 0;
+ wire \$1 ;
+ wire \$10 ;
+ wire [13:0] \$3 ;
+ wire \$5 ;
+ wire [4:0] \$7 ;
+ wire [4:0] \$8 ;
+ input clk;
+ wire clk;
+ reg [13:0] data = 14'h0001;
+ reg [13:0] \data$next ;
+ reg [3:0] i = 4'h0;
+ reg [3:0] \i$next ;
+ input rst;
+ wire rst;
+ reg start = 1'h0;
+ reg \start$next ;
+ input strobe;
+ wire strobe;
+ output tx;
+ wire tx;
+ input [7:0] word;
+ wire [7:0] word;
+ assign \$10 = | i;
+ always @(posedge clk)
+ data <= \data$next ;
+ always @(posedge clk)
+ i <= \i$next ;
+ always @(posedge clk)
+ start <= \start$next ;
+ assign \$1 = | i;
+ assign \$3 = + data[13:1];
+ assign \$5 = | i;
+ assign \$8 = i - 1'h1;
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$5 ) begin end
+ \data$next = data;
+ casez ({ start, \$1 })
+ 2'b?1:
+ \data$next = \$3 ;
+ 2'b1?:
+ \data$next = { 5'h1f, word, 1'h0 };
+ endcase
+ casez (rst)
+ 1'h1:
+ \data$next = 14'h0001;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$5 ) begin end
+ \i$next = i;
+ casez ({ start, \$5 })
+ 2'b?1:
+ \i$next = \$8 [3:0];
+ 2'b1?:
+ \i$next = 4'hd;
+ endcase
+ casez (rst)
+ 1'h1:
+ \i$next = 4'h0;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$5 ) begin end
+ \start$next = start;
+ casez ({ start, \$10 })
+ 2'b?1:
+ /* empty */;
+ 2'b1?:
+ \start$next = 1'h0;
+ endcase
+ casez (strobe)
+ 1'h1:
+ \start$next = 1'h1;
+ endcase
+ casez (rst)
+ 1'h1:
+ \start$next = 1'h0;
+ endcase
+ end
+ assign \$7 = \$8 ;
+ assign tx = data[0];
+endmodule
+
+module spi(rst, cs, sck, sdi, data, busy, strobe, clk);
+ reg \$auto$verilog_backend.cc:2083:dump_module$6 = 0;
+ wire \$1 ;
+ wire \$11 ;
+ wire \$13 ;
+ wire \$15 ;
+ wire \$17 ;
+ wire \$19 ;
+ wire \$21 ;
+ wire \$23 ;
+ wire \$25 ;
+ wire [6:0] \$27 ;
+ wire [6:0] \$28 ;
+ wire \$3 ;
+ wire \$30 ;
+ wire \$32 ;
+ wire \$34 ;
+ wire \$36 ;
+ wire \$38 ;
+ wire \$40 ;
+ wire \$42 ;
+ wire \$44 ;
+ wire \$46 ;
+ wire \$48 ;
+ wire \$5 ;
+ wire \$50 ;
+ wire \$52 ;
+ wire \$7 ;
+ wire \$9 ;
+ (* \amaranth.sample_reg = 32'd1 *)
+ reg \$sample$s$cs$sync$1 = 1'h0;
+ wire \$sample$s$cs$sync$1$next ;
+ (* \amaranth.sample_reg = 32'd1 *)
+ reg \$sample$s$sck$sync$1 = 1'h0;
+ wire \$sample$s$sck$sync$1$next ;
+ output busy;
+ reg busy = 1'h0;
+ reg \busy$next ;
+ input clk;
+ wire clk;
+ input cs;
+ wire cs;
+ output [31:0] data;
+ reg [31:0] data = 32'd520109572;
+ reg [31:0] \data$next ;
+ reg [5:0] i = 6'h00;
+ reg [5:0] \i$next ;
+ input rst;
+ wire rst;
+ input sck;
+ wire sck;
+ input sdi;
+ wire sdi;
+ output strobe;
+ reg strobe = 1'h0;
+ reg \strobe$next ;
+ assign \$9 = ~ \$sample$s$sck$sync$1 ;
+ assign \$11 = \$9 & sck;
+ assign \$13 = i == 6'h20;
+ assign \$15 = ~ cs;
+ assign \$17 = \$sample$s$cs$sync$1 & \$15 ;
+ assign \$1 = ~ cs;
+ assign \$19 = ~ \$sample$s$cs$sync$1 ;
+ assign \$21 = \$19 & cs;
+ assign \$23 = ~ \$sample$s$sck$sync$1 ;
+ assign \$25 = \$23 & sck;
+ assign \$28 = i + 1'h1;
+ assign \$30 = ~ cs;
+ assign \$32 = \$sample$s$cs$sync$1 & \$30 ;
+ assign \$34 = ~ \$sample$s$cs$sync$1 ;
+ assign \$36 = \$34 & cs;
+ assign \$38 = ~ \$sample$s$sck$sync$1 ;
+ assign \$3 = \$sample$s$cs$sync$1 & \$1 ;
+ assign \$40 = \$38 & sck;
+ assign \$42 = ~ cs;
+ assign \$44 = \$sample$s$cs$sync$1 & \$42 ;
+ assign \$46 = ~ \$sample$s$cs$sync$1 ;
+ assign \$48 = \$46 & cs;
+ assign \$50 = ~ \$sample$s$sck$sync$1 ;
+ assign \$52 = \$50 & sck;
+ always @(posedge clk)
+ \$sample$s$cs$sync$1 <= \$sample$s$cs$sync$1$next ;
+ always @(posedge clk)
+ \$sample$s$sck$sync$1 <= \$sample$s$sck$sync$1$next ;
+ always @(posedge clk)
+ strobe <= \strobe$next ;
+ always @(posedge clk)
+ i <= \i$next ;
+ always @(posedge clk)
+ busy <= \busy$next ;
+ always @(posedge clk)
+ data <= \data$next ;
+ assign \$5 = ~ \$sample$s$cs$sync$1 ;
+ assign \$7 = \$5 & cs;
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$6 ) begin end
+ \strobe$next = 1'h0;
+ casez ({ busy, \$3 })
+ 2'b?1:
+ /* empty */;
+ 2'b1?:
+ casez ({ \$11 , \$7 })
+ 2'b?1:
+ \strobe$next = \$13 ;
+ endcase
+ endcase
+ casez (rst)
+ 1'h1:
+ \strobe$next = 1'h0;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$6 ) begin end
+ \i$next = i;
+ casez ({ busy, \$17 })
+ 2'b?1:
+ \i$next = 6'h00;
+ 2'b1?:
+ casez ({ \$25 , \$21 })
+ 2'b?1:
+ /* empty */;
+ 2'b1?:
+ \i$next = \$28 [5:0];
+ endcase
+ endcase
+ casez (rst)
+ 1'h1:
+ \i$next = 6'h00;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$6 ) begin end
+ \busy$next = busy;
+ casez ({ busy, \$32 })
+ 2'b?1:
+ \busy$next = 1'h1;
+ 2'b1?:
+ casez ({ \$40 , \$36 })
+ 2'b?1:
+ \busy$next = 1'h0;
+ endcase
+ endcase
+ casez (rst)
+ 1'h1:
+ \busy$next = 1'h0;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$6 ) begin end
+ \data$next = data;
+ casez ({ busy, \$44 })
+ 2'b?1:
+ /* empty */;
+ 2'b1?:
+ casez ({ \$52 , \$48 })
+ 2'b?1:
+ /* empty */;
+ 2'b1?:
+ \data$next = { data[30:0], sdi };
+ endcase
+ endcase
+ casez (rst)
+ 1'h1:
+ \data$next = 32'd520109572;
+ endcase
+ end
+ assign \$27 = \$28 ;
+ assign \$sample$s$sck$sync$1$next = sck;
+ assign \$sample$s$cs$sync$1$next = cs;
+endmodule
+
+module swalense_top(io_in, io_out);
+ wire [1:0] dev_channels;
+ wire dev_clk;
+ wire [7:0] dev_counter;
+ wire dev_cs;
+ wire dev_direction;
+ wire dev_force_x2;
+ wire dev_pwm_signal;
+ wire dev_rst;
+ wire dev_sck;
+ wire dev_sdi;
+ wire dev_tx;
+ input [7:0] io_in;
+ wire [7:0] io_in;
+ output [7:0] io_out;
+ wire [7:0] io_out;
+ dev dev (
+ .channels(dev_channels),
+ .clk(dev_clk),
+ .counter(dev_counter),
+ .cs(dev_cs),
+ .direction(dev_direction),
+ .force_x2(dev_force_x2),
+ .pwm_signal(dev_pwm_signal),
+ .rst(dev_rst),
+ .sck(dev_sck),
+ .sdi(dev_sdi),
+ .tx(dev_tx)
+ );
+ assign io_out = { dev_counter[4:0], dev_direction, dev_pwm_signal, dev_tx };
+ assign { dev_sdi, dev_sck, dev_cs, dev_force_x2, dev_channels } = io_in[7:2];
+ assign dev_rst = io_in[1];
+ assign dev_clk = io_in[0];
+endmodule
+
diff --git a/verilog/rtl/114_luthor2k_top_tto.v b/verilog/rtl/114_luthor2k_top_tto.v
new file mode 100644
index 0000000..5a37f80
--- /dev/null
+++ b/verilog/rtl/114_luthor2k_top_tto.v
@@ -0,0 +1,32 @@
+`default_nettype none
+
+module luthor2k_top_tto
+ #(parameter CLOCK_RATE=9600)
+ (
+ input [7:0] io_in,
+ output [7:0] io_out
+ );
+
+ // INPUTS
+ wire clk_ascii = io_in[0];
+ wire clk_baudot = io_in[1];
+ wire baudot_input = io_in[2];
+
+ // OUTPUTS
+ wire ascii_serial_output;
+ wire baudot_ready_out;
+ wire [4:0] baudot_byte_out;
+
+ assign io_out[0] = ascii_serial_output;
+ assign io_out[1] = baudot_ready_out;
+ //assign io_out[2] =
+ assign io_out[3] = baudot_byte_out[0];
+ assign io_out[4] = baudot_byte_out[1];
+ assign io_out[5] = baudot_byte_out[2];
+ assign io_out[6] = baudot_byte_out[3];
+ assign io_out[7] = baudot_byte_out[4];
+
+ // instatiate converter .function_pin(top_pin)
+ main main(.v65b531(clk_ascii), .v3c4a34(clk_baudot), .vcb44a7(baudot_input), .v7c2fea(ascii_serial_output), .v40cda4(baudot_ready_out), .v4d3fdd(baudot_byte_out));
+
+endmodule
diff --git a/verilog/rtl/114_swalense_top.v b/verilog/rtl/114_swalense_top.v
new file mode 100644
index 0000000..17f77e9
--- /dev/null
+++ b/verilog/rtl/114_swalense_top.v
@@ -0,0 +1,772 @@
+/* Generated by Yosys 0.23+8 (git sha1 48659ee2b, clang 14.0.0 -fPIC -Os) */
+
+module counter(rst, wrap, init_value, max_value, inc, strobe, reset, value, updating_strobe, clk);
+ reg \$auto$verilog_backend.cc:2083:dump_module$1 = 0;
+ wire \$1 ;
+ wire [9:0] \$11 ;
+ wire [8:0] \$12 ;
+ wire [8:0] \$14 ;
+ wire [1:0] \$15 ;
+ wire [9:0] \$18 ;
+ wire [7:0] \$20 ;
+ wire \$3 ;
+ wire \$5 ;
+ wire \$7 ;
+ wire \$9 ;
+ wire can_update;
+ input clk;
+ wire clk;
+ input inc;
+ wire inc;
+ input [7:0] init_value;
+ wire [7:0] init_value;
+ input [7:0] max_value;
+ wire [7:0] max_value;
+ input reset;
+ wire reset;
+ input rst;
+ wire rst;
+ input strobe;
+ wire strobe;
+ output updating_strobe;
+ wire updating_strobe;
+ output [7:0] value;
+ reg [7:0] value = 8'h00;
+ reg [7:0] \value$next ;
+ input wrap;
+ wire wrap;
+ assign \$9 = strobe & \$7 ;
+ assign \$12 = + value;
+ assign \$15 = inc ? 2'h1 : 2'h3;
+ assign \$14 = + $signed(\$15 );
+ assign \$18 = $signed(\$12 ) + $signed(\$14 );
+ assign \$1 = value != max_value;
+ assign \$20 = inc ? 8'h00 : max_value;
+ always @(posedge clk)
+ value <= \value$next ;
+ assign \$3 = | value;
+ assign \$5 = inc ? \$1 : \$3 ;
+ assign \$7 = wrap | can_update;
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
+ \value$next = value;
+ casez ({ updating_strobe, reset })
+ 2'b?1:
+ \value$next = init_value;
+ 2'b1?:
+ (* full_case = 32'd1 *)
+ casez (can_update)
+ 1'h1:
+ \value$next = \$18 [7:0];
+ default:
+ \value$next = \$20 ;
+ endcase
+ endcase
+ casez (rst)
+ 1'h1:
+ \value$next = 8'h00;
+ endcase
+ end
+ assign \$11 = \$18 ;
+ assign updating_strobe = \$9 ;
+ assign can_update = \$5 ;
+endmodule
+
+module decoder(rst, channels, direction, force_x2, debounce, x1_value, strobe_x2, strobe_x4, strobe_x1, clk);
+ reg \$auto$verilog_backend.cc:2083:dump_module$2 = 0;
+ wire \$1 ;
+ wire \$11 ;
+ wire \$13 ;
+ wire \$15 ;
+ wire \$17 ;
+ wire \$19 ;
+ wire \$21 ;
+ wire \$23 ;
+ wire \$25 ;
+ wire \$27 ;
+ wire \$29 ;
+ wire \$3 ;
+ wire [1:0] \$5 ;
+ wire \$7 ;
+ wire \$9 ;
+ input [1:0] channels;
+ wire [1:0] channels;
+ input clk;
+ wire clk;
+ input debounce;
+ wire debounce;
+ wire dir;
+ output direction;
+ reg direction = 1'h0;
+ reg \direction$next ;
+ input force_x2;
+ wire force_x2;
+ reg [1:0] prev_channels = 2'h0;
+ reg [1:0] \prev_channels$next ;
+ input rst;
+ wire rst;
+ output strobe_x1;
+ wire strobe_x1;
+ output strobe_x2;
+ wire strobe_x2;
+ output strobe_x4;
+ reg strobe_x4 = 1'h0;
+ reg \strobe_x4$next ;
+ input [1:0] x1_value;
+ wire [1:0] x1_value;
+ assign \$9 = \$3 | \$7 ;
+ assign \$11 = strobe_x4 & \$9 ;
+ assign \$13 = channels == x1_value;
+ assign \$15 = strobe_x4 & \$13 ;
+ assign \$17 = force_x2 ? strobe_x2 : \$15 ;
+ assign \$1 = channels[0] ^ prev_channels[1];
+ assign \$19 = channels != prev_channels;
+ assign \$21 = dir == direction;
+ assign \$23 = ~ debounce;
+ assign \$25 = \$21 | \$23 ;
+ assign \$27 = channels != prev_channels;
+ assign \$29 = channels != prev_channels;
+ always @(posedge clk)
+ strobe_x4 <= \strobe_x4$next ;
+ always @(posedge clk)
+ prev_channels <= \prev_channels$next ;
+ always @(posedge clk)
+ direction <= \direction$next ;
+ assign \$3 = channels == x1_value;
+ assign \$5 = ~ x1_value;
+ assign \$7 = channels == \$5 ;
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
+ \strobe_x4$next = 1'h0;
+ casez (\$19 )
+ 1'h1:
+ \strobe_x4$next = \$25 ;
+ endcase
+ casez (rst)
+ 1'h1:
+ \strobe_x4$next = 1'h0;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
+ \prev_channels$next = prev_channels;
+ casez (\$27 )
+ 1'h1:
+ \prev_channels$next = channels;
+ endcase
+ casez (rst)
+ 1'h1:
+ \prev_channels$next = channels;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
+ \direction$next = direction;
+ casez (\$29 )
+ 1'h1:
+ \direction$next = dir;
+ endcase
+ casez (rst)
+ 1'h1:
+ \direction$next = 1'h0;
+ endcase
+ end
+ assign strobe_x1 = \$17 ;
+ assign strobe_x2 = \$11 ;
+ assign dir = \$1 ;
+endmodule
+
+module dev(rst, channels, force_x2, cs, sck, sdi, tx, pwm_signal, direction, counter, clk);
+ wire \$2 ;
+ wire \$4 ;
+ wire \$6 ;
+ wire [1:0] \$signal ;
+ input [1:0] channels;
+ wire [1:0] channels;
+ input clk;
+ wire clk;
+ output [7:0] counter;
+ wire [7:0] counter;
+ wire counter_inc;
+ wire [7:0] counter_init_value;
+ wire [7:0] counter_max_value;
+ wire counter_reset;
+ wire counter_strobe;
+ wire counter_updating_strobe;
+ wire [7:0] counter_value;
+ wire counter_wrap;
+ input cs;
+ wire cs;
+ wire decoder_debounce;
+ wire decoder_force_x2;
+ wire decoder_strobe_x1;
+ wire decoder_strobe_x2;
+ wire decoder_strobe_x4;
+ wire [1:0] decoder_x1_value;
+ output direction;
+ wire direction;
+ input force_x2;
+ wire force_x2;
+ wire gearbox_enable;
+ wire gearbox_strobe;
+ wire [7:0] gearbox_timer_cycles;
+ wire [7:0] pwm_duty;
+ wire [7:0] pwm_max_duty;
+ output pwm_signal;
+ wire pwm_signal;
+ input rst;
+ wire rst;
+ input sck;
+ wire sck;
+ input sdi;
+ wire sdi;
+ wire serial_out_strobe;
+ wire [7:0] serial_out_word;
+ wire spi_busy;
+ wire spi_cs;
+ wire [31:0] spi_data;
+ wire spi_force_x2;
+ wire spi_sck;
+ wire spi_sdi;
+ wire spi_strobe;
+ output tx;
+ wire tx;
+ assign \$2 = force_x2 | spi_force_x2;
+ assign \$4 = ~ spi_busy;
+ assign \$6 = \$4 & gearbox_strobe;
+ counter \counter$1 (
+ .clk(clk),
+ .inc(counter_inc),
+ .init_value(counter_init_value),
+ .max_value(counter_max_value),
+ .reset(counter_reset),
+ .rst(rst),
+ .strobe(counter_strobe),
+ .updating_strobe(counter_updating_strobe),
+ .value(counter_value),
+ .wrap(counter_wrap)
+ );
+ decoder decoder (
+ .channels(channels),
+ .clk(clk),
+ .debounce(decoder_debounce),
+ .direction(direction),
+ .force_x2(decoder_force_x2),
+ .rst(rst),
+ .strobe_x1(decoder_strobe_x1),
+ .strobe_x2(decoder_strobe_x2),
+ .strobe_x4(decoder_strobe_x4),
+ .x1_value(decoder_x1_value)
+ );
+ gearbox gearbox (
+ .clk(clk),
+ .enable(gearbox_enable),
+ .rst(rst),
+ .strobe(gearbox_strobe),
+ .strobe_x1(decoder_strobe_x1),
+ .strobe_x2(decoder_strobe_x2),
+ .strobe_x4(decoder_strobe_x4),
+ .timer_cycles(gearbox_timer_cycles)
+ );
+ pwm pwm (
+ .clk(clk),
+ .duty(pwm_duty),
+ .max_duty(pwm_max_duty),
+ .pwm_signal(pwm_signal),
+ .rst(rst)
+ );
+ serial_out serial_out (
+ .clk(clk),
+ .rst(rst),
+ .strobe(serial_out_strobe),
+ .tx(tx),
+ .word(serial_out_word)
+ );
+ spi spi (
+ .busy(spi_busy),
+ .clk(clk),
+ .cs(spi_cs),
+ .data(spi_data),
+ .rst(rst),
+ .sck(spi_sck),
+ .sdi(spi_sdi),
+ .strobe(spi_strobe)
+ );
+ assign serial_out_strobe = counter_updating_strobe;
+ assign serial_out_word = counter_value;
+ assign pwm_max_duty = counter_max_value;
+ assign pwm_duty = counter_value;
+ assign counter = counter_value;
+ assign counter_reset = spi_strobe;
+ assign counter_strobe = \$6 ;
+ assign counter_inc = direction;
+ assign { counter_max_value, counter_init_value, gearbox_timer_cycles, \$signal , spi_force_x2, decoder_x1_value, decoder_debounce, counter_wrap, gearbox_enable } = spi_data;
+ assign spi_sdi = sdi;
+ assign spi_sck = sck;
+ assign spi_cs = cs;
+ assign decoder_force_x2 = \$2 ;
+endmodule
+
+module gearbox(rst, enable, timer_cycles, strobe, strobe_x2, strobe_x4, strobe_x1, clk);
+ reg \$auto$verilog_backend.cc:2083:dump_module$3 = 0;
+ wire [8:0] \$1 ;
+ wire [5:0] \$10 ;
+ wire [5:0] \$11 ;
+ wire \$13 ;
+ wire \$14 ;
+ wire \$17 ;
+ wire [5:0] \$19 ;
+ wire [8:0] \$2 ;
+ wire [5:0] \$20 ;
+ wire [4:0] \$22 ;
+ wire [4:0] \$23 ;
+ wire [1:0] \$25 ;
+ wire \$27 ;
+ wire \$29 ;
+ wire \$31 ;
+ wire \$4 ;
+ wire \$6 ;
+ wire \$8 ;
+ input clk;
+ wire clk;
+ input enable;
+ wire enable;
+ wire [1:0] g;
+ wire [1:0] gear;
+ reg [7:0] period = 8'h7f;
+ reg [7:0] \period$next ;
+ input rst;
+ wire rst;
+ output strobe;
+ reg strobe;
+ input strobe_x1;
+ wire strobe_x1;
+ input strobe_x2;
+ wire strobe_x2;
+ input strobe_x4;
+ wire strobe_x4;
+ reg [4:0] threshold = 5'h00;
+ reg [4:0] \threshold$next ;
+ input [7:0] timer_cycles;
+ wire [7:0] timer_cycles;
+ assign \$11 = threshold - 1'h1;
+ assign \$14 = & threshold;
+ assign \$13 = ~ \$14 ;
+ assign \$17 = strobe_x4 & \$13 ;
+ assign \$20 = threshold + 1'h1;
+ assign \$25 = g[1] ? 2'h2 : g;
+ assign \$2 = period + 1'h1;
+ assign \$29 = enable ? strobe_x2 : strobe_x1;
+ assign \$31 = enable ? strobe_x4 : strobe_x1;
+ always @(posedge clk)
+ period <= \period$next ;
+ always @(posedge clk)
+ threshold <= \threshold$next ;
+ assign \$4 = period == timer_cycles;
+ assign \$6 = period == timer_cycles;
+ assign \$8 = | threshold;
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
+ \period$next = \$2 [7:0];
+ casez (\$4 )
+ 1'h1:
+ \period$next = 8'h00;
+ endcase
+ casez (rst)
+ 1'h1:
+ \period$next = 8'h7f;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
+ \threshold$next = threshold;
+ casez (\$6 )
+ 1'h1:
+ casez (\$8 )
+ 1'h1:
+ \threshold$next = \$11 [4:0];
+ endcase
+ endcase
+ casez (\$17 )
+ 1'h1:
+ \threshold$next = \$20 [4:0];
+ endcase
+ casez (rst)
+ 1'h1:
+ \threshold$next = 5'h00;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
+ (* full_case = 32'd1 *)
+ casez (gear)
+ 2'h0:
+ strobe = \$27 ;
+ 2'h1:
+ strobe = \$29 ;
+ 2'h?:
+ strobe = \$31 ;
+ endcase
+ end
+ assign \$1 = \$2 ;
+ assign \$10 = \$11 ;
+ assign \$19 = \$20 ;
+ assign \$22 = \$23 ;
+ assign gear = \$25 ;
+ assign g = \$23 [1:0];
+ assign \$23 = { 3'h0, threshold[4:3] };
+ assign \$27 = strobe_x1;
+endmodule
+
+module pwm(rst, pwm_signal, duty, max_duty, clk);
+ reg \$auto$verilog_backend.cc:2083:dump_module$4 = 0;
+ wire [8:0] \$1 ;
+ wire \$10 ;
+ wire \$12 ;
+ wire [8:0] \$2 ;
+ wire \$4 ;
+ wire \$6 ;
+ wire \$8 ;
+ input clk;
+ wire clk;
+ reg [7:0] counter = 8'h00;
+ reg [7:0] \counter$next ;
+ input [7:0] duty;
+ wire [7:0] duty;
+ input [7:0] max_duty;
+ wire [7:0] max_duty;
+ output pwm_signal;
+ reg pwm_signal = 1'h0;
+ reg \pwm_signal$next ;
+ input rst;
+ wire rst;
+ assign \$10 = counter == duty;
+ assign \$12 = | duty;
+ always @(posedge clk)
+ counter <= \counter$next ;
+ always @(posedge clk)
+ pwm_signal <= \pwm_signal$next ;
+ assign \$2 = counter + 1'h1;
+ assign \$4 = counter == max_duty;
+ assign \$6 = counter == duty;
+ assign \$8 = counter == max_duty;
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$4 ) begin end
+ \counter$next = \$2 [7:0];
+ casez ({ \$6 , \$4 })
+ 2'b?1:
+ \counter$next = 8'h00;
+ endcase
+ casez (rst)
+ 1'h1:
+ \counter$next = 8'h00;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$4 ) begin end
+ \pwm_signal$next = pwm_signal;
+ casez ({ \$10 , \$8 })
+ 2'b?1:
+ \pwm_signal$next = \$12 ;
+ 2'b1?:
+ \pwm_signal$next = 1'h0;
+ endcase
+ casez (rst)
+ 1'h1:
+ \pwm_signal$next = 1'h0;
+ endcase
+ end
+ assign \$1 = \$2 ;
+endmodule
+
+module serial_out(rst, tx, word, strobe, clk);
+ reg \$auto$verilog_backend.cc:2083:dump_module$5 = 0;
+ wire \$1 ;
+ wire \$10 ;
+ wire [13:0] \$3 ;
+ wire \$5 ;
+ wire [4:0] \$7 ;
+ wire [4:0] \$8 ;
+ input clk;
+ wire clk;
+ reg [13:0] data = 14'h0001;
+ reg [13:0] \data$next ;
+ reg [3:0] i = 4'h0;
+ reg [3:0] \i$next ;
+ input rst;
+ wire rst;
+ reg start = 1'h0;
+ reg \start$next ;
+ input strobe;
+ wire strobe;
+ output tx;
+ wire tx;
+ input [7:0] word;
+ wire [7:0] word;
+ assign \$10 = | i;
+ always @(posedge clk)
+ data <= \data$next ;
+ always @(posedge clk)
+ i <= \i$next ;
+ always @(posedge clk)
+ start <= \start$next ;
+ assign \$1 = | i;
+ assign \$3 = + data[13:1];
+ assign \$5 = | i;
+ assign \$8 = i - 1'h1;
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$5 ) begin end
+ \data$next = data;
+ casez ({ start, \$1 })
+ 2'b?1:
+ \data$next = \$3 ;
+ 2'b1?:
+ \data$next = { 5'h1f, word, 1'h0 };
+ endcase
+ casez (rst)
+ 1'h1:
+ \data$next = 14'h0001;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$5 ) begin end
+ \i$next = i;
+ casez ({ start, \$5 })
+ 2'b?1:
+ \i$next = \$8 [3:0];
+ 2'b1?:
+ \i$next = 4'hd;
+ endcase
+ casez (rst)
+ 1'h1:
+ \i$next = 4'h0;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$5 ) begin end
+ \start$next = start;
+ casez ({ start, \$10 })
+ 2'b?1:
+ /* empty */;
+ 2'b1?:
+ \start$next = 1'h0;
+ endcase
+ casez (strobe)
+ 1'h1:
+ \start$next = 1'h1;
+ endcase
+ casez (rst)
+ 1'h1:
+ \start$next = 1'h0;
+ endcase
+ end
+ assign \$7 = \$8 ;
+ assign tx = data[0];
+endmodule
+
+module spi(rst, cs, sck, sdi, data, busy, strobe, clk);
+ reg \$auto$verilog_backend.cc:2083:dump_module$6 = 0;
+ wire \$1 ;
+ wire \$11 ;
+ wire \$13 ;
+ wire \$15 ;
+ wire \$17 ;
+ wire \$19 ;
+ wire \$21 ;
+ wire \$23 ;
+ wire \$25 ;
+ wire [6:0] \$27 ;
+ wire [6:0] \$28 ;
+ wire \$3 ;
+ wire \$30 ;
+ wire \$32 ;
+ wire \$34 ;
+ wire \$36 ;
+ wire \$38 ;
+ wire \$40 ;
+ wire \$42 ;
+ wire \$44 ;
+ wire \$46 ;
+ wire \$48 ;
+ wire \$5 ;
+ wire \$50 ;
+ wire \$52 ;
+ wire \$7 ;
+ wire \$9 ;
+ (* \amaranth.sample_reg = 32'd1 *)
+ reg \$sample$s$cs$sync$1 = 1'h0;
+ wire \$sample$s$cs$sync$1$next ;
+ (* \amaranth.sample_reg = 32'd1 *)
+ reg \$sample$s$sck$sync$1 = 1'h0;
+ wire \$sample$s$sck$sync$1$next ;
+ output busy;
+ reg busy = 1'h0;
+ reg \busy$next ;
+ input clk;
+ wire clk;
+ input cs;
+ wire cs;
+ output [31:0] data;
+ reg [31:0] data = 32'd520109572;
+ reg [31:0] \data$next ;
+ reg [5:0] i = 6'h00;
+ reg [5:0] \i$next ;
+ input rst;
+ wire rst;
+ input sck;
+ wire sck;
+ input sdi;
+ wire sdi;
+ output strobe;
+ reg strobe = 1'h0;
+ reg \strobe$next ;
+ assign \$9 = ~ \$sample$s$sck$sync$1 ;
+ assign \$11 = \$9 & sck;
+ assign \$13 = i == 6'h20;
+ assign \$15 = ~ cs;
+ assign \$17 = \$sample$s$cs$sync$1 & \$15 ;
+ assign \$1 = ~ cs;
+ assign \$19 = ~ \$sample$s$cs$sync$1 ;
+ assign \$21 = \$19 & cs;
+ assign \$23 = ~ \$sample$s$sck$sync$1 ;
+ assign \$25 = \$23 & sck;
+ assign \$28 = i + 1'h1;
+ assign \$30 = ~ cs;
+ assign \$32 = \$sample$s$cs$sync$1 & \$30 ;
+ assign \$34 = ~ \$sample$s$cs$sync$1 ;
+ assign \$36 = \$34 & cs;
+ assign \$38 = ~ \$sample$s$sck$sync$1 ;
+ assign \$3 = \$sample$s$cs$sync$1 & \$1 ;
+ assign \$40 = \$38 & sck;
+ assign \$42 = ~ cs;
+ assign \$44 = \$sample$s$cs$sync$1 & \$42 ;
+ assign \$46 = ~ \$sample$s$cs$sync$1 ;
+ assign \$48 = \$46 & cs;
+ assign \$50 = ~ \$sample$s$sck$sync$1 ;
+ assign \$52 = \$50 & sck;
+ always @(posedge clk)
+ \$sample$s$cs$sync$1 <= \$sample$s$cs$sync$1$next ;
+ always @(posedge clk)
+ \$sample$s$sck$sync$1 <= \$sample$s$sck$sync$1$next ;
+ always @(posedge clk)
+ strobe <= \strobe$next ;
+ always @(posedge clk)
+ i <= \i$next ;
+ always @(posedge clk)
+ busy <= \busy$next ;
+ always @(posedge clk)
+ data <= \data$next ;
+ assign \$5 = ~ \$sample$s$cs$sync$1 ;
+ assign \$7 = \$5 & cs;
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$6 ) begin end
+ \strobe$next = 1'h0;
+ casez ({ busy, \$3 })
+ 2'b?1:
+ /* empty */;
+ 2'b1?:
+ casez ({ \$11 , \$7 })
+ 2'b?1:
+ \strobe$next = \$13 ;
+ endcase
+ endcase
+ casez (rst)
+ 1'h1:
+ \strobe$next = 1'h0;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$6 ) begin end
+ \i$next = i;
+ casez ({ busy, \$17 })
+ 2'b?1:
+ \i$next = 6'h00;
+ 2'b1?:
+ casez ({ \$25 , \$21 })
+ 2'b?1:
+ /* empty */;
+ 2'b1?:
+ \i$next = \$28 [5:0];
+ endcase
+ endcase
+ casez (rst)
+ 1'h1:
+ \i$next = 6'h00;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$6 ) begin end
+ \busy$next = busy;
+ casez ({ busy, \$32 })
+ 2'b?1:
+ \busy$next = 1'h1;
+ 2'b1?:
+ casez ({ \$40 , \$36 })
+ 2'b?1:
+ \busy$next = 1'h0;
+ endcase
+ endcase
+ casez (rst)
+ 1'h1:
+ \busy$next = 1'h0;
+ endcase
+ end
+ always @* begin
+ if (\$auto$verilog_backend.cc:2083:dump_module$6 ) begin end
+ \data$next = data;
+ casez ({ busy, \$44 })
+ 2'b?1:
+ /* empty */;
+ 2'b1?:
+ casez ({ \$52 , \$48 })
+ 2'b?1:
+ /* empty */;
+ 2'b1?:
+ \data$next = { data[30:0], sdi };
+ endcase
+ endcase
+ casez (rst)
+ 1'h1:
+ \data$next = 32'd520109572;
+ endcase
+ end
+ assign \$27 = \$28 ;
+ assign \$sample$s$sck$sync$1$next = sck;
+ assign \$sample$s$cs$sync$1$next = cs;
+endmodule
+
+module swalense_top(io_in, io_out);
+ wire [1:0] dev_channels;
+ wire dev_clk;
+ wire [7:0] dev_counter;
+ wire dev_cs;
+ wire dev_direction;
+ wire dev_force_x2;
+ wire dev_pwm_signal;
+ wire dev_rst;
+ wire dev_sck;
+ wire dev_sdi;
+ wire dev_tx;
+ input [7:0] io_in;
+ wire [7:0] io_in;
+ output [7:0] io_out;
+ wire [7:0] io_out;
+ dev dev (
+ .channels(dev_channels),
+ .clk(dev_clk),
+ .counter(dev_counter),
+ .cs(dev_cs),
+ .direction(dev_direction),
+ .force_x2(dev_force_x2),
+ .pwm_signal(dev_pwm_signal),
+ .rst(dev_rst),
+ .sck(dev_sck),
+ .sdi(dev_sdi),
+ .tx(dev_tx)
+ );
+ assign io_out = { dev_counter[4:0], dev_direction, dev_pwm_signal, dev_tx };
+ assign { dev_sdi, dev_sck, dev_cs, dev_force_x2, dev_channels } = io_in[7:2];
+ assign dev_rst = io_in[1];
+ assign dev_clk = io_in[0];
+endmodule
+
diff --git a/verilog/rtl/115_luthor2k_top_tto.v b/verilog/rtl/115_luthor2k_top_tto.v
new file mode 100644
index 0000000..5a37f80
--- /dev/null
+++ b/verilog/rtl/115_luthor2k_top_tto.v
@@ -0,0 +1,32 @@
+`default_nettype none
+
+module luthor2k_top_tto
+ #(parameter CLOCK_RATE=9600)
+ (
+ input [7:0] io_in,
+ output [7:0] io_out
+ );
+
+ // INPUTS
+ wire clk_ascii = io_in[0];
+ wire clk_baudot = io_in[1];
+ wire baudot_input = io_in[2];
+
+ // OUTPUTS
+ wire ascii_serial_output;
+ wire baudot_ready_out;
+ wire [4:0] baudot_byte_out;
+
+ assign io_out[0] = ascii_serial_output;
+ assign io_out[1] = baudot_ready_out;
+ //assign io_out[2] =
+ assign io_out[3] = baudot_byte_out[0];
+ assign io_out[4] = baudot_byte_out[1];
+ assign io_out[5] = baudot_byte_out[2];
+ assign io_out[6] = baudot_byte_out[3];
+ assign io_out[7] = baudot_byte_out[4];
+
+ // instatiate converter .function_pin(top_pin)
+ main main(.v65b531(clk_ascii), .v3c4a34(clk_baudot), .vcb44a7(baudot_input), .v7c2fea(ascii_serial_output), .v40cda4(baudot_ready_out), .v4d3fdd(baudot_byte_out));
+
+endmodule
diff --git a/verilog/rtl/116_Asma_Mohsin_conv_enc_core.v b/verilog/rtl/116_Asma_Mohsin_conv_enc_core.v
new file mode 100644
index 0000000..58756c7
--- /dev/null
+++ b/verilog/rtl/116_Asma_Mohsin_conv_enc_core.v
@@ -0,0 +1,42 @@
+module Asma_Mohsin_conv_enc_core(// Inputs
+ input [7:0]io_in,
+// Output
+ output [7:0]io_out
+);
+parameter [4:0] POLY_1 = 5'b10111 ;
+parameter [4:0] POLY_2 = 5'b11001 ;
+// Inputs
+wire clk ;
+wire rst_n ;
+wire data_valid ;
+wire d_in ;
+
+assign clk = io_in[0];
+assign rst_n=io_in[1];
+assign data_valid=io_in[2];
+assign d_in=io_in[3];
+
+// Output
+
+//output [1:0] enc_dout ;
+reg [4:0] shift_reg ;
+reg [1:0] codeword ;
+wire [1:0] enc_dout ;
+// Shift Input Data in 5 bits lenght register
+always @(posedge clk or negedge rst_n)
+begin
+if(~rst_n)
+shift_reg <= 5'd0 ;
+else if(data_valid)
+shift_reg <= {d_in, shift_reg[4:1]} ;
+else
+shift_reg <= 5'd0 ;
+end
+always @(shift_reg)
+begin
+codeword[0] = ^(POLY_2 & shift_reg) ;
+codeword[1] = ^(POLY_1 & shift_reg) ;
+end
+assign io_out = codeword ;
+endmodule
+
diff --git a/verilog/rtl/117_Asma_Mohsin_conv_enc_core.v b/verilog/rtl/117_Asma_Mohsin_conv_enc_core.v
new file mode 100644
index 0000000..e17e50f
--- /dev/null
+++ b/verilog/rtl/117_Asma_Mohsin_conv_enc_core.v
@@ -0,0 +1,42 @@
+module Asma_Mohsin_conv_enc_core(// Inputs
+ input [3:0]io_in,
+// Output
+output [1:0]io_out
+);
+parameter [4:0] POLY_1 = 5'b10111 ;
+parameter [4:0] POLY_2 = 5'b11001 ;
+// Inputs
+wire clk ;
+wire rst_n ;
+wire data_valid ;
+wire d_in ;
+
+assign clk = io_in[0];
+assign rst_n=io_in[1];
+assign data_valid=io_in[2];
+assign d_in=io_in[3];
+
+// Output
+
+//output [1:0] enc_dout ;
+reg [4:0] shift_reg ;
+reg [1:0] codeword ;
+wire [1:0] enc_dout ;
+// Shift Input Data in 5 bits lenght register
+always @(posedge clk or negedge rst_n)
+begin
+if(~rst_n)
+shift_reg <= 5'd0 ;
+else if(data_valid)
+shift_reg <= {d_in, shift_reg[4:1]} ;
+else
+shift_reg <= 5'd0 ;
+end
+always @(shift_reg)
+begin
+codeword[0] = ^(POLY_2 & shift_reg) ;
+codeword[1] = ^(POLY_1 & shift_reg) ;
+end
+assign io_out = codeword ;
+endmodule
+
diff --git a/verilog/rtl/117_stevenmburns_toplevel.v b/verilog/rtl/117_stevenmburns_toplevel.v
new file mode 100644
index 0000000..2549487
--- /dev/null
+++ b/verilog/rtl/117_stevenmburns_toplevel.v
@@ -0,0 +1,16 @@
+module stevenmburns_toplevel(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+
+ScanBinary u0(.clock(io_in[0]),
+ .reset(io_in[1]),
+ .io_ld(io_in[2]),
+ .io_u_bit(io_in[3]),
+ .io_v_bit(io_in[4]),
+ .io_z_bit(io_out[0]),
+ .io_done(io_out[1]));
+
+assign io_out[7:2] = 6'b0;
+
+endmodule
diff --git a/verilog/rtl/119_rglenn_hex_to_7_seg.v b/verilog/rtl/119_rglenn_hex_to_7_seg.v
new file mode 100644
index 0000000..671dc49
--- /dev/null
+++ b/verilog/rtl/119_rglenn_hex_to_7_seg.v
@@ -0,0 +1,25 @@
+`default_nettype none
+
+module rglenn_hex_to_7_seg (
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+
+ wire latch = io_in[0];
+ wire blank = io_in[1];
+ wire [4:0] data = io_in[5:2];
+ wire [6:0] led_out;
+ assign io_out[6:0] = blank ? 7'b0000000 : led_out;
+ assign io_out[7] = io_in[6]; // decimal point
+
+ // external clock is 1000Hz, so need 10 bit counter
+ reg [3:0] data_reg;
+
+ always @(posedge latch) begin
+ data_reg <= data;
+ end
+
+ // instantiate segment display
+ hex2seg7 hex2seg7(.data(data_reg), .segments(led_out));
+
+endmodule
diff --git a/verilog/rtl/120_zymason.sv b/verilog/rtl/120_zymason.sv
new file mode 100644
index 0000000..38cdafe
--- /dev/null
+++ b/verilog/rtl/120_zymason.sv
@@ -0,0 +1,188 @@
+`default_nettype none
+
+// Top-level design module, acting only as a wrapper
+module zymason_tinytop (
+ input logic [7:0] io_in,
+ output logic [7:0] io_out);
+
+ Zymason_Tiny1 p0 (.clock(io_in[0]), .reset(io_in[1]), .RW(io_in[2]),
+ .sel(io_in[3]), .pin_in(io_in[7:4]), .io_out);
+
+endmodule : zymason_tinytop
+
+
+
+// Primary design module
+module Zymason_Tiny1 (
+ input logic clock, reset,
+ input logic RW, sel,
+ input logic [3:0] pin_in,
+ output tri [7:0] io_out);
+ localparam NUM_DIGITS = 12; // The number of total digits that can be stored
+
+ logic [6:0] dig_out[NUM_DIGITS-1:0]; // Unpacked digit output array
+ logic [NUM_DIGITS-1:0] dig_en; // Enable line for each digit
+ logic pos_en, pulse;
+
+
+ // Shift register for selecting current display digit in both modes
+ // Control FSM
+ // Clocking module to generate slow pulses for display cycling in R-mode
+ Zymason_ShiftReg #(NUM_DIGITS) s0 (.clock, .reset, .en(pos_en), .out(dig_en));
+ Zymason_FSM f0 (.clock, .reset, .RW, .sel, .pulse, .pos_en);
+ Zymason_PulseGen p0 (.clock, .reset, .spd({pin_in, sel}), .pulse);
+
+ genvar i;
+ generate
+ for (i=0; i<NUM_DIGITS; i=i+1) begin: STR
+ Zymason_DigStore ds (.clock, .reset, .en(dig_en[i]), .sel, .RW, .pin_in,
+ .dig_out(dig_out[i]));
+ Zymason_Drive dr (.en(dig_en[i]), .val(dig_out[i]), .out(io_out[6:0]));
+ end
+ endgenerate
+
+ // Mode indicator
+ assign io_out[7] = RW;
+
+endmodule : Zymason_Tiny1
+
+
+
+
+module Zymason_Drive (
+ input logic en,
+ input logic [6:0] val,
+ output tri [6:0] out);
+
+ assign out = en ? val : 7'bz;
+
+endmodule : Zymason_Drive
+
+
+
+// Control state machine for Zymason_Tiny1
+module Zymason_FSM (
+ input logic clock, reset,
+ input logic RW, sel, pulse,
+ output logic pos_en);
+
+ // assign st_out = state;
+
+ enum logic [1:0] {INIT, SCAN, WRT0, WRT1} state, nextState;
+
+ // Explicit-style FSM
+ always_ff @(posedge clock, posedge reset) begin
+ if (reset)
+ state <= INIT;
+ else
+ state <= nextState;
+ end
+
+ // Next-state logic
+ always_comb begin
+ case (state)
+ INIT: nextState = RW ? WRT0 : SCAN;
+ SCAN: nextState = RW ? WRT0 : SCAN;
+ WRT0: nextState = sel ? WRT1 : WRT0;
+ WRT1: nextState = RW ? (sel ? WRT1 : WRT0) : SCAN;
+ default: nextState = INIT;
+ endcase
+ end
+
+ // Output logic
+ always_comb begin
+ case (state)
+ INIT: pos_en = 1'b0;
+ SCAN: pos_en = ~RW & pulse;
+ WRT0: pos_en = 1'b0;
+ WRT1: pos_en = RW & ~sel;
+ default: pos_en = 1'b0;
+ endcase
+ end
+
+endmodule : Zymason_FSM
+
+
+
+// Single digit storage instance
+module Zymason_DigStore (
+ input logic clock, reset,
+ input logic en, sel, RW,
+ input logic [3:0] pin_in,
+ output logic [6:0] dig_out);
+
+ // 2 implicit registers with a synchronous reset
+ always_ff @(posedge clock, posedge reset) begin
+ if (reset)
+ dig_out <= 7'd0;
+ else begin
+ if (en & ~sel & RW)
+ dig_out[3:0] <= pin_in;
+ else if (en & sel & RW)
+ dig_out[6:4] <= pin_in[2:0];
+ end
+ end
+
+endmodule : Zymason_DigStore
+
+
+
+// Read-only left-shift register that resets to ...0001
+module Zymason_ShiftReg
+ #(parameter DW = 2)
+ (input logic clock, reset,
+ input logic en,
+ output logic [DW-1:0] out);
+
+ logic [DW:0] long_out;
+ logic tmp;
+
+ assign out = long_out[DW-1:0];
+ assign tmp = long_out[DW-1];
+
+ always_ff @(posedge clock, posedge reset) begin
+ if (reset) begin
+ long_out <= 1;
+ end
+ else if (en) begin
+ long_out <= {long_out, tmp};
+ end
+ end
+
+endmodule : Zymason_ShiftReg
+
+
+
+// Internal clocking pulse, expecting 6.25kHz clock as input
+module Zymason_PulseGen (
+ input logic clock, reset,
+ input logic [4:0] spd,
+ output logic pulse);
+
+ logic [8:0] count;
+ logic [4:0] lowCount;
+
+ logic en_low;
+ logic temp_pulse;
+
+ // Invariant counter to produce pulses at 12.1Hz
+ always_ff @(posedge clock) begin
+ if (reset)
+ count <= 9'd0;
+ else
+ count <= count + 9'd1;
+ end
+
+ // Variable counter to find spd
+ always_ff @(posedge clock) begin
+ if (reset | pulse)
+ lowCount <= 5'd0;
+ else if (en_low & spd[0])
+ lowCount <= lowCount + 5'd1;
+ end
+
+ // pulse is asserted for a single cycle since its counter immediately resets
+ assign pulse = ((lowCount[4:1] == spd[4:1]) & spd[0]) ? en_low : 1'b0;
+ assign en_low = (count == 9'd0) ? 1'b1 : 1'b0;
+
+endmodule : Zymason_PulseGen
\ No newline at end of file
diff --git a/verilog/rtl/122_klei22_ra.v b/verilog/rtl/122_klei22_ra.v
new file mode 100644
index 0000000..914da63
--- /dev/null
+++ b/verilog/rtl/122_klei22_ra.v
@@ -0,0 +1,54 @@
+`default_nettype none
+
+module klei22_ra #(
+ parameter RA_SIZE = 8,
+ parameter BITS_PER_ELEM = 5
+) (
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+
+ wire clk = io_in[0];
+ wire rst = io_in[1];
+ wire i_data_clk = io_in[2];
+ wire start_calc;
+ wire [4:0] i_value = io_in[7:3];
+
+ wire [BITS_PER_ELEM - 1:0] ra_out;
+ assign io_out[BITS_PER_ELEM-1:0] = {3'b000, ra_out[4:0]};
+
+
+ parameter SRL_SIZE = RA_SIZE + 1; // RA_SIZE valid inputs and one stale input
+ parameter TOTAL_SRL_BITS = 5 * SRL_SIZE;
+ wire [TOTAL_SRL_BITS - 1:0] taps;
+
+ shift_register_line #(
+ .TOTAL_TAPS(SRL_SIZE),
+ .BITS_PER_ELEM(BITS_PER_ELEM),
+ .TOTAL_BITS(TOTAL_SRL_BITS)
+ ) srl_1 (
+ .clk(clk),
+ .rst(rst),
+ .i_value(i_value[4:0]),
+ .i_data_clk(i_data_clk),
+ .o_start_calc(start_calc),
+ .o_taps(taps[TOTAL_SRL_BITS-1:0])
+ );
+
+ // rolling sums RA_SIZE elements + 1 stale element
+ parameter RA_NUM_ELEM = RA_SIZE;
+ parameter MAX_BITS = 8; // log_2(31 * 8) = 7.9 ~ 8; where 31 is largest valut for 5 bit elem
+ rolling_average #(
+ .BITS_PER_ELEM(BITS_PER_ELEM),
+ .MAX_BITS(8)
+ ) ra_1 (
+ .clk(clk),
+ .rst(rst),
+ .i_new(taps[4:0]),
+ .i_old(taps[(4 + 5 * 9):(0 + 5 * 8)]),
+ .i_start_calc(start_calc),
+ .o_ra(ra_out[BITS_PER_ELEM-1:0])
+ );
+
+
+endmodule
diff --git a/verilog/rtl/123_w5s8.v b/verilog/rtl/123_w5s8.v
new file mode 100644
index 0000000..2378dd1
--- /dev/null
+++ b/verilog/rtl/123_w5s8.v
@@ -0,0 +1,279 @@
+`default_nettype none
+module afoote_w5s8_tt02_utm_core(
+ input clock,
+ input reset,
+ input mode,
+ input [2:0] encoded_state_in,
+ input [2:0] sym_in,
+ input sym_in_valid,
+ output [2:0] new_sym,
+ output direction,
+ output [2:0] encoded_next_state
+);
+
+reg [7:0] stored_state;
+reg [2:0] symbuf;
+reg symbuf_valid;
+
+wire [7:0] state_in;
+wire [7:0] state;
+wire [7:0] next_state;
+wire [2:0] sym;
+
+always @(posedge clock) begin
+ if (reset) begin
+ stored_state <= 8'h01;
+ end
+ else if (sym_in_valid && symbuf_valid) begin
+ stored_state <= next_state;
+ end
+ else begin
+ stored_state <= stored_state;
+ end
+end
+
+always @(posedge clock) begin
+ if (reset) begin
+ symbuf <= 3'b0;
+ end
+ else if (sym_in_valid) begin
+ symbuf <= sym_in;
+ end
+ else begin
+ symbuf <= symbuf;
+ end
+end
+
+always @(posedge clock) begin
+ if (reset) begin
+ symbuf_valid <= 0;
+ end
+ else if (sym_in_valid) begin
+ symbuf_valid <= 1;
+ end
+ else begin
+ symbuf_valid <= symbuf_valid;
+ end
+end
+
+afoote_w5s8_tt02_decoder_3to8 decode_state_in(
+ .in(encoded_state_in),
+ .out(state_in)
+);
+
+assign state = (mode == 0) ? state_in : stored_state;
+assign sym = (mode == 0) ? sym_in : symbuf;
+
+afoote_w5s8_tt02_direction direction_block(
+ .state(state),
+ .s2(sym[2]),
+ .s1(sym[1]),
+ .s0(sym[0]),
+ .direction(direction)
+);
+
+afoote_w5s8_tt02_next_state next_state_block(
+ .state_in(state),
+ .s2(sym[2]),
+ .s1(sym[1]),
+ .s0(sym[0]),
+ .state_out(next_state));
+
+afoote_w5s8_tt02_new_symbol new_sym_block(
+ .state_in(state),
+ .s2(sym[2]),
+ .s1(sym[1]),
+ .s0(sym[0]),
+ .z2(new_sym[2]),
+ .z1(new_sym[1]),
+ .z0(new_sym[0])
+);
+
+afoote_w5s8_tt02_encoder_8to3 encode_state_out(
+ .in(next_state),
+ .out(encoded_next_state)
+);
+
+endmodule
+
+`default_nettype none
+module afoote_w5s8_tt02_direction(
+ input [7:0] state,
+ input s2,
+ input s1,
+ input s0,
+ // 0 = left, 1 = right
+ output direction
+);
+
+wire a,b,c,d,e,f,g,h;
+
+assign a = state[0];
+assign b = state[1];
+assign c = state[2];
+assign d = state[3];
+assign e = state[4];
+assign f = state[5];
+assign g = state[6];
+assign h = state[7];
+
+assign direction = ((a | e | f) & s1)
+ | (((a & s0) | b | c | (e & s0) | f | g | h) & s2)
+ | ((d | (e & (~s1) & (~s0))) & (~s2))
+ | (g & (~s1));
+endmodule
+
+`default_nettype none
+module afoote_w5s8_tt02_next_state(
+ input [7:0] state_in,
+ input s2,
+ input s1,
+ input s0,
+ output [7:0] state_out
+);
+
+wire a,b,c,d,e,f,g,h;
+
+assign a = state_in[0];
+assign b = state_in[1];
+assign c = state_in[2];
+assign d = state_in[3];
+assign e = state_in[4];
+assign f = state_in[5];
+assign g = state_in[6];
+assign h = state_in[7];
+
+wire sym_0;
+assign sym_0 = (~s2) & (~s1) & (~s0);
+
+// next H
+assign state_out[7] = s2 & ((s0 & (b | c)) | h);
+
+// next G
+assign state_out[6] = (s2 & ( ((b | c) & (~s0)) | g)) | (f & s1);
+
+// next F
+assign state_out[5] = (e & (~s2) & s0) | (f & (~(s2 | s1))) | (s1 & (g | h));
+
+// next E
+assign state_out[4] = (a & s2 & (~s0)) | (d & (~s2) & s0) | (e & (s1 | (s2 & s0)));
+
+// next D
+assign state_out[3] = (b & s1) | (d & s2) | (e & (~s1) & (~s0));
+
+// next C
+assign state_out[2] = (a & (~s2) & s0) | (c & (~(s2 | s1))) | (d & sym_0);
+
+// next B
+assign state_out[1] = (a & sym_0) | (b & (~(s2 | s1))) | (c & s1) | (f & s2);
+
+// next A
+assign state_out[0] = (a & (s1 | (s2 & s0))) | (d & s1) | ((g | h) & (~(s2 | s1)));
+
+endmodule
+
+`default_nettype none
+module afoote_w5s8_tt02_new_symbol(
+ input [7:0] state_in,
+ input s2,
+ input s1,
+ input s0,
+ output z2,
+ output z1,
+ output z0
+);
+
+wire a,b,c,d,e,f,g,h;
+
+assign a = state_in[0];
+assign b = state_in[1];
+assign c = state_in[2];
+assign d = state_in[3];
+assign e = state_in[4];
+assign f = state_in[5];
+assign g = state_in[6];
+assign h = state_in[7];
+
+assign z2 = ((~s2) & b) | (d & s0) | c | (e & (s0 | s1)) | (f & (~(s2 | s1)));
+assign z1 = (a & (~s2)) | (d & (s2 | s1) & (~s0)) | (e & s2 & (~s0));
+assign z0 = (s0 & ((a & s2) | (~a))) | (h & s1);
+
+endmodule
+
+module afoote_w5s8_tt02_decoder_3to8(
+ input [2:0] in,
+ output [7:0] out
+);
+
+assign out[0] = (~in[2]) & (~in[1]) & (~in[0]);
+assign out[1] = (~in[2]) & (~in[1]) & ( in[0]);
+assign out[2] = (~in[2]) & ( in[1]) & (~in[0]);
+assign out[3] = (~in[2]) & ( in[1]) & ( in[0]);
+assign out[4] = ( in[2]) & (~in[1]) & (~in[0]);
+assign out[5] = ( in[2]) & (~in[1]) & ( in[0]);
+assign out[6] = ( in[2]) & ( in[1]) & (~in[0]);
+assign out[7] = ( in[2]) & ( in[1]) & ( in[0]);
+
+endmodule
+
+module afoote_w5s8_tt02_encoder_8to3(
+ input [7:0] in,
+ output [2:0] out
+);
+
+assign out[0] = in[1] | in[3] | in[5] | in[7];
+assign out[1] = in[2] | in[3] | in[6] | in[7];
+assign out[2] = in[4] | in[5] | in[6] | in[7];
+endmodule
+
+`default_nettype none
+module afoote_w5s8_tt02_top(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+
+wire mode;
+wire clock;
+wire reset;
+
+wire direction;
+
+wire sym_valid;
+wire [2:0] sym_in;
+wire [2:0] new_sym;
+
+// 1-hot state in & out
+wire [7:0] state_in;
+wire [7:0] state_out;
+
+// 3-bit dense encoding of state in & out
+wire [2:0] encoded_state_in;
+wire [2:0] encoded_state_out;
+
+assign mode = io_in[7];
+assign clock = io_in[0];
+assign reset = (mode == 0) ? 1'b1 : io_in[1];
+
+assign encoded_state_in = (mode == 0) ? io_in[3:1] : 3'b0;
+assign io_out[7:5] = encoded_state_out;
+
+assign sym_valid = (mode == 0) ? 1'b0 : io_in[2];
+assign sym_in = io_in[6:4];
+assign io_out[4:2] = new_sym;
+
+assign io_out[1] = direction;
+assign io_out[0] = 1'b0;
+
+afoote_w5s8_tt02_utm_core core(
+ .clock(clock),
+ .reset(reset),
+ .mode(mode),
+ .encoded_state_in(encoded_state_in),
+ .sym_in(sym_in),
+ .sym_in_valid(sym_valid),
+ .new_sym(new_sym),
+ .direction(direction),
+ .encoded_next_state(encoded_state_out)
+);
+
+endmodule
diff --git a/verilog/rtl/user_module_341178481588044372.v b/verilog/rtl/user_module_341178481588044372.v
new file mode 100644
index 0000000..19fece8
--- /dev/null
+++ b/verilog/rtl/user_module_341178481588044372.v
@@ -0,0 +1,251 @@
+/* Automatically generated from https://wokwi.com/projects/341178481588044372 */
+
+`default_nettype none
+
+module user_module_341178481588044372(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+ wire net1 = io_in[0];
+ wire net2 = io_in[1];
+ wire net3 = io_in[2];
+ wire net4 = io_in[3];
+ wire net5 = io_in[4];
+ wire net6 = io_in[5];
+ wire net7 = io_in[6];
+ wire net8 = io_in[7];
+ wire net9;
+ wire net10;
+ wire net11;
+ wire net12;
+ wire net13;
+ wire net14;
+ wire net15;
+ wire net16;
+ wire net17 = 1'b0;
+ wire net18 = 1'b1;
+ wire net19 = 1'b1;
+ wire net20;
+ wire net21;
+ wire net22;
+ wire net23;
+ wire net24;
+ wire net25;
+ wire net26;
+ wire net27;
+ wire net28;
+ wire net29;
+ wire net30;
+ wire net31;
+ wire net32;
+ wire net33;
+ wire net34;
+ wire net35;
+ wire net36;
+ wire net37;
+ wire net38;
+ wire net39;
+ wire net40;
+ wire net41;
+ wire net42;
+ wire net43;
+ wire net44;
+ wire net45;
+ wire net46;
+ wire net47;
+ wire net48;
+ wire net49;
+ wire net50;
+ wire net51;
+ wire net52;
+ wire net53;
+ wire net54;
+
+ assign io_out[0] = net9;
+ assign io_out[1] = net10;
+ assign io_out[2] = net11;
+ assign io_out[3] = net12;
+ assign io_out[4] = net13;
+ assign io_out[5] = net14;
+ assign io_out[6] = net15;
+ assign io_out[7] = net16;
+
+ and_cell gate1 (
+ .a (net2),
+ .b (net20),
+ .out (net21)
+ );
+ or_cell gate2 (
+ .a (net21),
+ .b (net22),
+ .out (net23)
+ );
+ xor_cell gate3 (
+
+ );
+ nand_cell gate4 (
+
+ );
+ not_cell gate5 (
+
+ );
+ buffer_cell gate6 (
+
+ );
+ mux_cell mux1 (
+
+ );
+ dff_cell flipflop1 (
+ .d (net24),
+ .clk (net1),
+ .q (net25),
+ .notq (net24)
+ );
+ dff_cell flipflop2 (
+ .d (net26),
+ .clk (net25),
+ .q (net27),
+ .notq (net26)
+ );
+ dff_cell flipflop3 (
+ .d (net28),
+ .clk (net27),
+ .q (net29),
+ .notq (net28)
+ );
+ dff_cell flipflop4 (
+ .d (net30),
+ .clk (net29),
+ .q (net31),
+ .notq (net30)
+ );
+ dff_cell flipflop5 (
+ .d (net32),
+ .clk (net31),
+ .q (net33),
+ .notq (net32)
+ );
+ dff_cell flipflop6 (
+ .d (net34),
+ .clk (net33),
+ .q (net35),
+ .notq (net34)
+ );
+ dff_cell flipflop7 (
+ .d (net36),
+ .clk (net35),
+ .q (net20),
+ .notq (net36)
+ );
+ dff_cell flipflop8 (
+ .d (net37),
+ .clk (net20),
+ .q (net38),
+ .notq (net37)
+ );
+ dff_cell flipflop9 (
+ .d (net39),
+ .clk (net38),
+ .q (net40),
+ .notq (net39)
+ );
+ dff_cell flipflop10 (
+ .d (net41),
+ .clk (net40),
+ .q (net42),
+ .notq (net41)
+ );
+ dff_cell flipflop11 (
+ .d (net43),
+ .clk (net42),
+ .q (net44),
+ .notq (net43)
+ );
+ dff_cell flipflop12 (
+ .d (net45),
+ .clk (net44),
+ .q (net46),
+ .notq (net45)
+ );
+ dff_cell flipflop13 (
+ .d (net47),
+ .clk (net46),
+ .q (net16),
+ .notq (net47)
+ );
+ dff_cell flipflop14 (
+ .d (net8),
+ .clk (net16),
+ .q (net9)
+ );
+ dff_cell flipflop15 (
+ .d (net9),
+ .clk (net16),
+ .q (net10)
+ );
+ dff_cell flipflop16 (
+ .d (net10),
+ .clk (net16),
+ .q (net11)
+ );
+ dff_cell flipflop17 (
+ .d (net11),
+ .clk (net16),
+ .q (net12)
+ );
+ dff_cell flipflop18 (
+ .d (net12),
+ .clk (net16),
+ .q (net13)
+ );
+ dff_cell flipflop19 (
+ .d (net13),
+ .clk (net16),
+ .q (net14)
+ );
+ and_cell gate7 (
+ .a (net3),
+ .b (net38),
+ .out (net22)
+ );
+ and_cell gate8 (
+ .a (net4),
+ .b (net40),
+ .out (net48)
+ );
+ and_cell gate9 (
+ .a (net5),
+ .b (net42),
+ .out (net49)
+ );
+ and_cell gate10 (
+ .a (net6),
+ .b (net44),
+ .out (net50)
+ );
+ and_cell gate11 (
+ .a (net7),
+ .b (net46),
+ .out (net51)
+ );
+ or_cell gate12 (
+ .a (net48),
+ .b (net49),
+ .out (net52)
+ );
+ or_cell gate15 (
+ .a (net50),
+ .b (net51),
+ .out (net53)
+ );
+ or_cell gate16 (
+ .a (net23),
+ .b (net54),
+ .out (net15)
+ );
+ or_cell gate17 (
+ .a (net52),
+ .b (net53),
+ .out (net54)
+ );
+endmodule
diff --git a/verilog/rtl/user_module_341432030163108435.v b/verilog/rtl/user_module_341432030163108435.v
new file mode 100644
index 0000000..367f8ec
--- /dev/null
+++ b/verilog/rtl/user_module_341432030163108435.v
@@ -0,0 +1,180 @@
+/* Automatically generated from https://wokwi.com/projects/341432030163108435 */
+
+`default_nettype none
+
+module user_module_341432030163108435(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+ wire net1 = io_in[0];
+ wire net2 = io_in[1];
+ wire net3 = io_in[2];
+ wire net4 = io_in[3];
+ wire net5 = io_in[4];
+ wire net6 = io_in[5];
+ wire net7 = io_in[6];
+ wire net8 = io_in[7];
+ wire net9;
+ wire net10;
+ wire net11;
+ wire net12;
+ wire net13;
+ wire net14;
+ wire net15 = 1'b1;
+ wire net16 = 1'b1;
+ wire net17;
+ wire net18;
+ wire net19;
+ wire net20;
+ wire net21;
+ wire net22;
+ wire net23;
+ wire net24;
+ wire net25;
+ wire net26;
+ wire net27;
+ wire net28;
+ wire net29;
+ wire net30 = 1'b0;
+ wire net31;
+ wire net32;
+ wire net33;
+ wire net34;
+ wire net35;
+ wire net36;
+ wire net37;
+
+ assign io_out[0] = net9;
+ assign io_out[1] = net10;
+ assign io_out[2] = net11;
+ assign io_out[3] = net12;
+ assign io_out[4] = net13;
+ assign io_out[5] = net14;
+
+ and_cell gate1 (
+ .a (net17),
+ .b (net18),
+ .out (net19)
+ );
+ or_cell gate2 (
+
+ );
+ xor_cell gate3 (
+
+ );
+ nand_cell gate4 (
+
+ );
+ not_cell gate5 (
+ .in (net3),
+ .out (net20)
+ );
+ buffer_cell gate6 (
+
+ );
+ mux_cell mux1 (
+
+ );
+ dff_cell flipflop1 (
+
+ );
+ dff_cell flipflop2 (
+ .d (net21),
+ .clk (net22),
+ .q (net23),
+ .notq (net24)
+ );
+ buffer_cell gate7 (
+ .in (net2),
+ .out (net21)
+ );
+ buffer_cell gate8 (
+ .in (net1),
+ .out (net22)
+ );
+ not_cell gate9 (
+ .in (net4),
+ .out (net25)
+ );
+ not_cell gate10 (
+ .in (net5),
+ .out (net26)
+ );
+ not_cell gate16 (
+ .in (net11),
+ .out (net12)
+ );
+ not_cell gate17 (
+ .in (net6),
+ .out (net27)
+ );
+ not_cell gate18 (
+ .in (net7),
+ .out (net28)
+ );
+ not_cell gate19 (
+ .in (net8),
+ .out (net29)
+ );
+ not_cell gate25 (
+ .in (net13),
+ .out (net14)
+ );
+ buffer_cell gate26 (
+ .in (net23),
+ .out (net9)
+ );
+ buffer_cell gate27 (
+ .in (net24),
+ .out (net10)
+ );
+ not_cell gate11 (
+ .in (net20),
+ .out (net17)
+ );
+ not_cell gate12 (
+ .in (net25),
+ .out (net31)
+ );
+ not_cell gate13 (
+ .in (net26),
+ .out (net18)
+ );
+ and_cell gate14 (
+ .a (net31),
+ .b (net26),
+ .out (net32)
+ );
+ or_cell gate15 (
+ .a (net19),
+ .b (net32),
+ .out (net11)
+ );
+ and_cell gate20 (
+ .a (net33),
+ .b (net34),
+ .out (net35)
+ );
+ not_cell gate21 (
+ .in (net27),
+ .out (net33)
+ );
+ not_cell gate22 (
+ .in (net28),
+ .out (net36)
+ );
+ not_cell gate23 (
+ .in (net29),
+ .out (net34)
+ );
+ and_cell gate24 (
+ .a (net36),
+ .b (net29),
+ .out (net37)
+ );
+ or_cell gate28 (
+ .a (net35),
+ .b (net37),
+ .out (net13)
+ );
+endmodule
diff --git a/verilog/rtl/user_module_341546888233747026.v b/verilog/rtl/user_module_341546888233747026.v
new file mode 100644
index 0000000..373692e
--- /dev/null
+++ b/verilog/rtl/user_module_341546888233747026.v
@@ -0,0 +1,468 @@
+/* Automatically generated from https://wokwi.com/projects/341546888233747026 */
+
+`default_nettype none
+
+module user_module_341546888233747026(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+ wire net1 = io_in[0];
+ wire net2 = io_in[1];
+ wire net3 = io_in[2];
+ wire net4 = io_in[3];
+ wire net5 = io_in[4];
+ wire net6 = io_in[5];
+ wire net7 = io_in[6];
+ wire net8 = io_in[7];
+ wire net9;
+ wire net10;
+ wire net11;
+ wire net12;
+ wire net13;
+ wire net14;
+ wire net15;
+ wire net16;
+ wire net17 = 1'b1;
+ wire net18 = 1'b1;
+ wire net19 = 1'b0;
+ wire net20;
+ wire net21;
+ wire net22;
+ wire net23;
+ wire net24;
+ wire net25;
+ wire net26;
+ wire net27;
+ wire net28;
+ wire net29;
+ wire net30;
+ wire net31;
+ wire net32;
+ wire net33;
+ wire net34;
+ wire net35;
+ wire net36;
+ wire net37;
+ wire net38;
+ wire net39;
+ wire net40;
+ wire net41;
+ wire net42;
+ wire net43;
+ wire net44;
+ wire net45;
+ wire net46;
+ wire net47;
+ wire net48;
+ wire net49;
+ wire net50;
+ wire net51;
+ wire net52;
+ wire net53;
+ wire net54;
+ wire net55;
+ wire net56;
+ wire net57;
+ wire net58;
+ wire net59;
+ wire net60;
+ wire net61;
+ wire net62;
+ wire net63;
+ wire net64 = 1'b0;
+ wire net65;
+ wire net66;
+ wire net67;
+ wire net68;
+ wire net69;
+ wire net70;
+ wire net71;
+ wire net72;
+ wire net73;
+ wire net74;
+ wire net75;
+ wire net76;
+ wire net77;
+ wire net78;
+ wire net79;
+ wire net80;
+ wire net81;
+ wire net82;
+ wire net83;
+ wire net84;
+
+ assign io_out[0] = net9;
+ assign io_out[1] = net10;
+ assign io_out[2] = net11;
+ assign io_out[3] = net12;
+ assign io_out[4] = net13;
+ assign io_out[5] = net14;
+ assign io_out[6] = net15;
+ assign io_out[7] = net16;
+
+ or_cell gate2 (
+
+ );
+ xor_cell gate3 (
+
+ );
+ nand_cell gate4 (
+
+ );
+ not_cell gate5 (
+
+ );
+ buffer_cell gate6 (
+
+ );
+ mux_cell mux4 (
+
+ );
+ not_cell gate17 (
+ .in (net20),
+ .out (net21)
+ );
+ buffer_cell gate18 (
+ .in (net20),
+ .out (net22)
+ );
+ not_cell gate19 (
+ .in (net23),
+ .out (net24)
+ );
+ buffer_cell gate20 (
+ .in (net23),
+ .out (net25)
+ );
+ not_cell gate21 (
+ .in (net26),
+ .out (net27)
+ );
+ buffer_cell gate22 (
+ .in (net26),
+ .out (net28)
+ );
+ not_cell gate23 (
+ .in (net29)
+ );
+ buffer_cell gate24 (
+ .in (net29),
+ .out (net30)
+ );
+ and_cell gate25 (
+ .a (net27),
+ .b (net21),
+ .out (net31)
+ );
+ and_cell gate26 (
+ .a (net25),
+ .b (net21),
+ .out (net32)
+ );
+ or_cell gate27 (
+ .a (net31),
+ .b (net32),
+ .out (net13)
+ );
+ or_cell gate28 (
+ .a (net31),
+ .b (net25),
+ .out (net33)
+ );
+ or_cell gate29 (
+ .a (net30),
+ .b (net34),
+ .out (net35)
+ );
+ or_cell gate30 (
+ .a (net33),
+ .b (net35),
+ .out (net9)
+ );
+ and_cell gate31 (
+ .a (net28),
+ .b (net22),
+ .out (net34)
+ );
+ or_cell gate32 (
+ .a (net36),
+ .b (net37),
+ .out (net10)
+ );
+ or_cell gate33 (
+ .a (net27),
+ .b (net38),
+ .out (net37)
+ );
+ and_cell gate34 (
+ .a (net25),
+ .b (net22),
+ .out (net38)
+ );
+ and_cell gate35 (
+ .a (net24),
+ .b (net21),
+ .out (net36)
+ );
+ or_cell gate36 (
+ .a (net24),
+ .b (net39),
+ .out (net11)
+ );
+ or_cell gate37 (
+ .a (net28),
+ .b (net22),
+ .out (net39)
+ );
+ or_cell gate38 (
+ .a (net31),
+ .b (net40),
+ .out (net41)
+ );
+ and_cell gate39 (
+ .a (net27),
+ .b (net25),
+ .out (net40)
+ );
+ or_cell gate40 (
+ .a (net30),
+ .b (net42),
+ .out (net43)
+ );
+ or_cell gate41 (
+ .a (net44),
+ .b (net45),
+ .out (net42)
+ );
+ or_cell gate42 (
+ .a (net41),
+ .b (net43),
+ .out (net12)
+ );
+ and_cell gate43 (
+ .a (net28),
+ .b (net46),
+ .out (net45)
+ );
+ and_cell gate44 (
+ .a (net25),
+ .b (net21),
+ .out (net44)
+ );
+ and_cell gate45 (
+ .a (net24),
+ .b (net22),
+ .out (net46)
+ );
+ or_cell gate46 (
+ .a (net47),
+ .b (net48),
+ .out (net14)
+ );
+ or_cell gate47 (
+ .a (net49),
+ .b (net50),
+ .out (net47)
+ );
+ or_cell gate48 (
+ .a (net30),
+ .b (net51),
+ .out (net48)
+ );
+ and_cell gate49 (
+ .a (net24),
+ .b (net21),
+ .out (net49)
+ );
+ and_cell gate50 (
+ .a (net28),
+ .b (net24),
+ .out (net50)
+ );
+ and_cell gate51 (
+ .a (net28),
+ .b (net21),
+ .out (net51)
+ );
+ or_cell gate52 (
+ .a (net52),
+ .b (net53),
+ .out (net15)
+ );
+ or_cell gate53 (
+ .a (net54),
+ .b (net55),
+ .out (net52)
+ );
+ or_cell gate54 (
+ .a (net30),
+ .b (net56),
+ .out (net53)
+ );
+ and_cell gate55 (
+ .a (net27),
+ .b (net25),
+ .out (net54)
+ );
+ and_cell gate56 (
+ .a (net28),
+ .b (net24),
+ .out (net55)
+ );
+ and_cell gate57 (
+ .a (net28),
+ .b (net21),
+ .out (net56)
+ );
+ and_cell gate58 (
+
+ );
+ xor_cell gate1 (
+ .a (net57),
+ .b (net58),
+ .out (net59)
+ );
+ xor_cell gate7 (
+ .a (net59),
+ .b (net60),
+ .out (net20)
+ );
+ or_cell gate10 (
+ .a (net61),
+ .b (net62),
+ .out (net63)
+ );
+ and_cell gate11 (
+ .a (net60),
+ .b (net59),
+ .out (net61)
+ );
+ and_cell gate12 (
+ .a (net58),
+ .b (net57),
+ .out (net62)
+ );
+ buffer_cell gate8 (
+ .in (net1),
+ .out (net57)
+ );
+ buffer_cell gate9 (
+ .in (net64),
+ .out (net60)
+ );
+ buffer_cell gate13 (
+ .in (net5),
+ .out (net58)
+ );
+ xor_cell gate14 (
+ .a (net65),
+ .b (net66),
+ .out (net67)
+ );
+ xor_cell gate15 (
+ .a (net67),
+ .b (net68),
+ .out (net23)
+ );
+ or_cell gate16 (
+ .a (net69),
+ .b (net70),
+ .out (net71)
+ );
+ and_cell gate59 (
+ .a (net68),
+ .b (net67),
+ .out (net69)
+ );
+ and_cell gate60 (
+ .a (net66),
+ .b (net65),
+ .out (net70)
+ );
+ buffer_cell gate61 (
+ .in (net2),
+ .out (net65)
+ );
+ buffer_cell gate62 (
+ .in (net63),
+ .out (net68)
+ );
+ buffer_cell gate63 (
+ .in (net6),
+ .out (net66)
+ );
+ xor_cell gate64 (
+ .a (net72),
+ .b (net73),
+ .out (net74)
+ );
+ xor_cell gate65 (
+ .a (net74),
+ .b (net75),
+ .out (net26)
+ );
+ or_cell gate66 (
+ .a (net76),
+ .b (net77),
+ .out (net78)
+ );
+ and_cell gate67 (
+ .a (net75),
+ .b (net74),
+ .out (net76)
+ );
+ and_cell gate68 (
+ .a (net73),
+ .b (net72),
+ .out (net77)
+ );
+ buffer_cell gate69 (
+ .in (net3),
+ .out (net72)
+ );
+ buffer_cell gate70 (
+ .in (net71),
+ .out (net75)
+ );
+ buffer_cell gate71 (
+ .in (net7),
+ .out (net73)
+ );
+ xor_cell gate72 (
+ .a (net79),
+ .b (net80),
+ .out (net81)
+ );
+ xor_cell gate73 (
+ .a (net81),
+ .b (net82),
+ .out (net29)
+ );
+ or_cell gate74 (
+ .a (net83),
+ .b (net84),
+ .out (net16)
+ );
+ and_cell gate75 (
+ .a (net82),
+ .b (net81),
+ .out (net83)
+ );
+ and_cell gate76 (
+ .a (net80),
+ .b (net79),
+ .out (net84)
+ );
+ buffer_cell gate77 (
+ .in (net4),
+ .out (net79)
+ );
+ buffer_cell gate78 (
+ .in (net78),
+ .out (net82)
+ );
+ buffer_cell gate79 (
+ .in (net8),
+ .out (net80)
+ );
+endmodule
diff --git a/verilog/rtl/user_module_341614346808328788.v b/verilog/rtl/user_module_341614346808328788.v
new file mode 100644
index 0000000..67baf70
--- /dev/null
+++ b/verilog/rtl/user_module_341614346808328788.v
@@ -0,0 +1,165 @@
+/* Automatically generated from https://wokwi.com/projects/341614346808328788 */
+
+`default_nettype none
+
+module user_module_341614346808328788(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+ wire net1 = io_in[1];
+ wire net2 = io_in[2];
+ wire net3 = io_in[3];
+ wire net4 = io_in[4];
+ wire net5 = io_in[5];
+ wire net6;
+ wire net7;
+ wire net8;
+ wire net9;
+ wire net10;
+ wire net11 = 1'b0;
+ wire net12 = 1'b1;
+ wire net13;
+ wire net14;
+ wire net15;
+ wire net16;
+ wire net17;
+ wire net18;
+ wire net19;
+ wire net20;
+ wire net21;
+ wire net22;
+ wire net23;
+ wire net24;
+ wire net25;
+ wire net26;
+ wire net27;
+ wire net28;
+ wire net29 = 1'b0;
+ wire net30;
+ wire net31;
+ wire net32;
+
+ assign io_out[0] = net6;
+ assign io_out[1] = net7;
+ assign io_out[2] = net7;
+ assign io_out[3] = net6;
+ assign io_out[4] = net8;
+ assign io_out[5] = net8;
+ assign io_out[6] = net9;
+ assign io_out[7] = net10;
+
+ or_cell gate2 (
+ .a (net13),
+ .b (net3),
+ .out (net14)
+ );
+ not_cell gate7 (
+ .in (net1),
+ .out (net13)
+ );
+ or_cell gate8 (
+ .a (net14),
+ .b (net4),
+ .out (net15)
+ );
+ not_cell gate9 (
+ .in (net15),
+ .out (net8)
+ );
+ and_cell gate10 (
+ .a (net13),
+ .b (net16),
+ .out (net17)
+ );
+ not_cell gate11 (
+ .in (net3),
+ .out (net16)
+ );
+ or_cell gate12 (
+ .a (net17),
+ .b (net18),
+ .out (net19)
+ );
+ or_cell gate13 (
+ .a (net20),
+ .b (net21),
+ .out (net22)
+ );
+ or_cell gate14 (
+ .a (net19),
+ .b (net22),
+ .out (net23)
+ );
+ and_cell gate15 (
+ .a (net1),
+ .b (net3),
+ .out (net18)
+ );
+ not_cell gate16 (
+ .in (net2),
+ .out (net24)
+ );
+ and_cell gate17 (
+ .a (net24),
+ .b (net25),
+ .out (net20)
+ );
+ not_cell gate18 (
+ .in (net4),
+ .out (net25)
+ );
+ and_cell gate19 (
+ .a (net1),
+ .b (net2),
+ .out (net21)
+ );
+ not_cell gate20 (
+ .in (net23),
+ .out (net7)
+ );
+ nand_cell gate21 (
+ .a (net15),
+ .b (net23),
+ .out (net6)
+ );
+ and_cell gate22 (
+ .a (net1),
+ .b (net2),
+ .out (net26)
+ );
+ and_cell gate23 (
+ .a (net3),
+ .b (net4),
+ .out (net27)
+ );
+ and_cell gate24 (
+ .a (net26),
+ .b (net27),
+ .out (net28)
+ );
+ and_cell gate3 (
+ .a (net1),
+ .b (net30),
+ .out (net31)
+ );
+ and_cell gate1 (
+ .a (net5),
+ .b (net32),
+ .out (net9)
+ );
+ and_cell gate4 (
+ .a (net3),
+ .b (net4),
+ .out (net30)
+ );
+ or_cell gate5 (
+ .a (net28),
+ .b (net9),
+ .out (net10)
+ );
+ and_cell gate6 (
+ .a (net31),
+ .b (net24),
+ .out (net32)
+ );
+endmodule
diff --git a/verilog/rtl/user_module_341631511790879314.v b/verilog/rtl/user_module_341631511790879314.v
new file mode 100644
index 0000000..f6ddd92
--- /dev/null
+++ b/verilog/rtl/user_module_341631511790879314.v
@@ -0,0 +1,281 @@
+/* Automatically generated from https://wokwi.com/projects/341631511790879314 */
+
+`default_nettype none
+
+module user_module_341631511790879314(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+ wire net1 = io_in[0];
+ wire net2 = io_in[1];
+ wire net3 = io_in[2];
+ wire net4 = io_in[3];
+ wire net5 = io_in[4];
+ wire net6 = io_in[5];
+ wire net7 = io_in[6];
+ wire net8 = io_in[7];
+ wire net9;
+ wire net10;
+ wire net11;
+ wire net12;
+ wire net13;
+ wire net14;
+ wire net15;
+ wire net16;
+ wire net17 = 1'b0;
+ wire net18 = 1'b1;
+ wire net19 = 1'b1;
+ wire net20;
+ wire net21;
+ wire net22 = 1'b1;
+ wire net23;
+ wire net24;
+ wire net25 = 1'b1;
+ wire net26;
+ wire net27;
+ wire net28 = 1'b0;
+ wire net29;
+ wire net30;
+ wire net31;
+ wire net32;
+ wire net33;
+ wire net34;
+ wire net35;
+ wire net36;
+ wire net37;
+ wire net38;
+ wire net39;
+ wire net40;
+ wire net41 = 1'b0;
+ wire net42;
+ wire net43 = 1'b1;
+ wire net44;
+ wire net45;
+ wire net46 = 1'b0;
+ wire net47;
+ wire net48;
+ wire net49 = 1'b1;
+ wire net50;
+ wire net51 = 1'b1;
+ wire net52 = 1'b1;
+ wire net53 = 1'b1;
+ wire net54 = 1'b1;
+ wire net55 = 1'b1;
+ wire net56 = 1'b0;
+ wire net57 = 1'b0;
+ wire net58 = 1'b0;
+ wire net59 = 1'b0;
+ wire net60 = 1'b0;
+ wire net61 = 1'b0;
+ wire net62 = 1'b0;
+ wire net63 = 1'b0;
+ wire net64 = 1'b0;
+ wire net65 = 1'b0;
+ wire net66 = 1'b0;
+ wire net67 = 1'b0;
+ wire net68 = 1'b0;
+ wire net69 = 1'b0;
+ wire net70 = 1'b0;
+ wire net71 = 1'b0;
+ wire net72 = 1'b0;
+
+ assign io_out[0] = net9;
+ assign io_out[1] = net10;
+ assign io_out[2] = net11;
+ assign io_out[3] = net12;
+ assign io_out[4] = net13;
+ assign io_out[5] = net14;
+ assign io_out[6] = net15;
+ assign io_out[7] = net16;
+
+ and_cell gate1 (
+
+ );
+ or_cell gate2 (
+
+ );
+ xor_cell gate3 (
+
+ );
+ nand_cell gate4 (
+
+ );
+ not_cell gate5 (
+
+ );
+ buffer_cell gate6 (
+
+ );
+ mux_cell mux1 (
+
+ );
+ dff_cell flipflop2 (
+ .d (net20),
+ .clk (net1),
+ .q (net9),
+ .notq (net11)
+ );
+ mux_cell mux3 (
+ .a (net21),
+ .b (net22),
+ .sel (net7),
+ .out (net20)
+ );
+ dff_cell flipflop3 (
+ .d (net23),
+ .clk (net1),
+ .q (net21)
+ );
+ mux_cell mux4 (
+ .a (net24),
+ .b (net25),
+ .sel (net7),
+ .out (net23)
+ );
+ dff_cell flipflop4 (
+ .d (net26),
+ .clk (net1),
+ .q (net24)
+ );
+ mux_cell mux5 (
+ .a (net27),
+ .b (net28),
+ .sel (net7),
+ .out (net26)
+ );
+ dff_cell flipflop5 (
+ .d (net29),
+ .clk (net1),
+ .q (net27)
+ );
+ mux_cell mux6 (
+ .a (net30),
+ .b (net2),
+ .sel (net7),
+ .out (net29)
+ );
+ dff_cell flipflop6 (
+ .d (net31),
+ .clk (net1),
+ .q (net30)
+ );
+ mux_cell mux7 (
+ .a (net32),
+ .b (net3),
+ .sel (net7),
+ .out (net31)
+ );
+ dff_cell flipflop1 (
+ .d (net33),
+ .clk (net1),
+ .q (net32)
+ );
+ mux_cell mux2 (
+ .a (net34),
+ .b (net4),
+ .sel (net7),
+ .out (net33)
+ );
+ dff_cell flipflop7 (
+ .d (net35),
+ .clk (net1),
+ .q (net34)
+ );
+ mux_cell mux8 (
+ .a (net36),
+ .b (net5),
+ .sel (net7),
+ .out (net35)
+ );
+ dff_cell flipflop8 (
+ .d (net37),
+ .clk (net1),
+ .q (net36)
+ );
+ mux_cell mux9 (
+ .a (net38),
+ .b (net6),
+ .sel (net7),
+ .out (net37)
+ );
+ dff_cell flipflop9 (
+ .d (net39),
+ .clk (net1),
+ .q (net38)
+ );
+ mux_cell mux10 (
+ .a (net40),
+ .b (net41),
+ .sel (net7),
+ .out (net39)
+ );
+ dff_cell flipflop10 (
+ .d (net42),
+ .clk (net1),
+ .q (net40)
+ );
+ mux_cell mux11 (
+ .a (net13),
+ .b (net43),
+ .sel (net7),
+ .out (net42)
+ );
+ dff_cell flipflop11 (
+ .d (net44),
+ .clk (net1),
+ .q (net13),
+ .notq (net14)
+ );
+ mux_cell mux12 (
+ .a (net45),
+ .b (net46),
+ .sel (net7),
+ .out (net44)
+ );
+ dff_cell flipflop12 (
+ .d (net47),
+ .clk (net1),
+ .q (net45)
+ );
+ mux_cell mux13 (
+ .a (net48),
+ .b (net49),
+ .sel (net7),
+ .out (net47)
+ );
+ dff_cell flipflop13 (
+ .d (net50),
+ .clk (net1),
+ .q (net48)
+ );
+ mux_cell mux14 (
+ .a (net9),
+ .b (net51),
+ .sel (net7),
+ .out (net50)
+ );
+ mux_cell mux15 (
+ .a (net52),
+ .b (net9),
+ .sel (net8),
+ .out (net10)
+ );
+ mux_cell mux16 (
+ .a (net53),
+ .b (net11),
+ .sel (net8),
+ .out (net12)
+ );
+ mux_cell mux17 (
+ .a (net54),
+ .b (net11),
+ .sel (net8),
+ .out (net15)
+ );
+ mux_cell mux18 (
+ .a (net55),
+ .b (net12),
+ .sel (net8),
+ .out (net16)
+ );
+endmodule
diff --git a/verilog/rtl/user_module_348255968419643987.v b/verilog/rtl/user_module_348255968419643987.v
index 33e75d4..655919e 100644
--- a/verilog/rtl/user_module_348255968419643987.v
+++ b/verilog/rtl/user_module_348255968419643987.v
@@ -15,37 +15,37 @@
wire net7 = io_in[6];
wire net8 = io_in[7];
wire net9;
- wire net10 = 1'b1;
+ wire net10;
wire net11;
wire net12;
- wire net13;
- wire net14 = 1'b0;
+ wire net13 = 1'b1;
+ wire net14;
wire net15;
wire net16;
- wire net17;
- wire net18 = 1'b0;
+ wire net17 = 1'b0;
+ wire net18;
wire net19;
- wire net20;
+ wire net20 = 1'b0;
wire net21;
wire net22;
- wire net23 = 1'b0;
+ wire net23;
wire net24;
- wire net25;
+ wire net25 = 1'b0;
wire net26;
wire net27;
- wire net28 = 1'b0;
+ wire net28;
wire net29;
- wire net30;
+ wire net30 = 1'b0;
wire net31;
wire net32;
- wire net33 = 1'b0;
+ wire net33;
wire net34;
- wire net35;
+ wire net35 = 1'b0;
wire net36;
wire net37;
- wire net38 = 1'b0;
+ wire net38;
wire net39;
- wire net40;
+ wire net40 = 1'b0;
wire net41;
wire net42;
wire net43;
@@ -81,341 +81,360 @@
wire net73;
wire net74;
wire net75;
- wire net76 = 1'b0;
+ wire net76;
wire net77;
- wire net78;
+ wire net78 = 1'b0;
wire net79;
wire net80;
wire net81;
wire net82;
wire net83;
- wire net84 = 1'b0;
+ wire net84;
+ wire net85;
+ wire net86 = 1'b0;
+ wire net87;
+ wire net88;
assign io_out[0] = net9;
+ assign io_out[1] = net10;
+ assign io_out[2] = net11;
+ assign io_out[3] = net12;
and_cell gate1 (
- .a (net11),
- .b (net12),
- .out (net13)
- );
- mux_cell mux2 (
- .a (net12),
- .b (net14),
- .sel (net15),
+ .a (net14),
+ .b (net15),
.out (net16)
);
+ mux_cell mux2 (
+ .a (net15),
+ .b (net17),
+ .sel (net9),
+ .out (net18)
+ );
dff_cell flipflop2 (
- .d (net16),
+ .d (net18),
.clk (net1),
- .q (net17),
- .notq (net12)
+ .q (net19),
+ .notq (net15)
);
mux_cell mux3 (
- .a (net11),
- .b (net18),
- .sel (net15),
- .out (net19)
+ .a (net14),
+ .b (net20),
+ .sel (net9),
+ .out (net21)
);
dff_cell flipflop3 (
- .d (net19),
- .clk (net20),
- .q (net21),
- .notq (net11)
+ .d (net21),
+ .clk (net22),
+ .q (net23),
+ .notq (net14)
);
mux_cell mux4 (
- .a (net22),
- .b (net23),
- .sel (net15),
- .out (net24)
+ .a (net24),
+ .b (net25),
+ .sel (net9),
+ .out (net26)
);
dff_cell flipflop4 (
- .d (net24),
- .clk (net25),
- .q (net26),
- .notq (net22)
+ .d (net26),
+ .clk (net27),
+ .q (net28),
+ .notq (net24)
);
mux_cell mux5 (
- .a (net27),
- .b (net28),
- .sel (net15),
- .out (net29)
+ .a (net29),
+ .b (net30),
+ .sel (net9),
+ .out (net31)
);
dff_cell flipflop5 (
- .d (net29),
- .clk (net30),
- .q (net31),
- .notq (net27)
+ .d (net31),
+ .clk (net32),
+ .q (net33),
+ .notq (net29)
);
mux_cell mux6 (
- .a (net32),
- .b (net33),
- .sel (net15),
- .out (net34)
+ .a (net34),
+ .b (net35),
+ .sel (net9),
+ .out (net36)
);
dff_cell flipflop6 (
- .d (net34),
- .clk (net35),
- .q (net36),
- .notq (net32)
+ .d (net36),
+ .clk (net37),
+ .q (net38),
+ .notq (net34)
);
mux_cell mux7 (
- .a (net37),
- .b (net38),
- .sel (net15),
- .out (net39)
+ .a (net39),
+ .b (net40),
+ .sel (net9),
+ .out (net41)
);
dff_cell flipflop7 (
- .d (net39),
- .clk (net40),
- .q (net41),
- .notq (net37)
+ .d (net41),
+ .clk (net42),
+ .q (net43),
+ .notq (net39)
);
mux_cell mux8 (
- .a (net32),
+ .a (net34),
.b (net1),
- .sel (net15),
- .out (net40)
- );
- mux_cell mux9 (
- .a (net27),
- .b (net1),
- .sel (net15),
- .out (net35)
- );
- mux_cell mux10 (
- .a (net22),
- .b (net1),
- .sel (net15),
- .out (net30)
- );
- mux_cell mux11 (
- .a (net11),
- .b (net1),
- .sel (net15),
- .out (net25)
- );
- mux_cell mux12 (
- .a (net12),
- .b (net1),
- .sel (net15),
- .out (net20)
- );
- and_cell gate7 (
- .a (net22),
- .b (net13),
+ .sel (net9),
.out (net42)
);
- and_cell gate8 (
- .a (net27),
- .b (net42),
- .out (net43)
+ mux_cell mux9 (
+ .a (net29),
+ .b (net1),
+ .sel (net9),
+ .out (net37)
);
- and_cell gate9 (
- .a (net36),
- .b (net43),
+ mux_cell mux10 (
+ .a (net24),
+ .b (net1),
+ .sel (net9),
+ .out (net32)
+ );
+ mux_cell mux11 (
+ .a (net14),
+ .b (net1),
+ .sel (net9),
+ .out (net27)
+ );
+ mux_cell mux12 (
+ .a (net15),
+ .b (net1),
+ .sel (net9),
+ .out (net22)
+ );
+ and_cell gate7 (
+ .a (net24),
+ .b (net16),
.out (net44)
);
- and_cell gate10 (
- .a (net41),
+ and_cell gate8 (
+ .a (net29),
.b (net44),
.out (net45)
);
- and_cell gate11 (
- .a (net21),
- .b (net17),
+ and_cell gate9 (
+ .a (net38),
+ .b (net45),
.out (net46)
);
- and_cell gate12 (
- .a (net22),
+ and_cell gate10 (
+ .a (net43),
.b (net46),
.out (net47)
);
- and_cell gate13 (
- .a (net31),
- .b (net47),
+ and_cell gate11 (
+ .a (net23),
+ .b (net19),
.out (net48)
);
- and_cell gate14 (
- .a (net32),
+ and_cell gate12 (
+ .a (net24),
.b (net48),
.out (net49)
);
- and_cell gate15 (
- .a (net41),
+ and_cell gate13 (
+ .a (net33),
.b (net49),
.out (net50)
);
- and_cell gate16 (
- .a (net21),
- .b (net12),
+ and_cell gate14 (
+ .a (net34),
+ .b (net50),
.out (net51)
);
- and_cell gate17 (
- .a (net26),
+ and_cell gate15 (
+ .a (net43),
.b (net51),
.out (net52)
);
- and_cell gate18 (
- .a (net27),
- .b (net52),
+ and_cell gate16 (
+ .a (net23),
+ .b (net15),
.out (net53)
);
- and_cell gate19 (
- .a (net32),
+ and_cell gate17 (
+ .a (net28),
.b (net53),
.out (net54)
);
- and_cell gate20 (
- .a (net41),
+ and_cell gate18 (
+ .a (net29),
.b (net54),
.out (net55)
);
- and_cell gate21 (
- .a (net11),
- .b (net12),
+ and_cell gate19 (
+ .a (net34),
+ .b (net55),
.out (net56)
);
- and_cell gate22 (
- .a (net26),
+ and_cell gate20 (
+ .a (net43),
.b (net56),
.out (net57)
);
- and_cell gate23 (
- .a (net27),
- .b (net57),
+ and_cell gate21 (
+ .a (net14),
+ .b (net15),
.out (net58)
);
- and_cell gate24 (
- .a (net32),
+ and_cell gate22 (
+ .a (net28),
.b (net58),
.out (net59)
);
- and_cell gate25 (
- .a (net41),
+ and_cell gate23 (
+ .a (net29),
.b (net59),
.out (net60)
);
- and_cell gate26 (
- .a (net11),
- .b (net12),
+ and_cell gate24 (
+ .a (net34),
+ .b (net60),
.out (net61)
);
- and_cell gate27 (
- .a (net22),
+ and_cell gate25 (
+ .a (net43),
.b (net61),
.out (net62)
);
- and_cell gate28 (
- .a (net27),
- .b (net62),
+ and_cell gate26 (
+ .a (net14),
+ .b (net15),
.out (net63)
);
- and_cell gate29 (
- .a (net32),
+ and_cell gate27 (
+ .a (net24),
.b (net63),
.out (net64)
);
- and_cell gate30 (
- .a (net41),
+ and_cell gate28 (
+ .a (net29),
.b (net64),
.out (net65)
);
- and_cell gate31 (
- .a (net21),
- .b (net17),
+ and_cell gate29 (
+ .a (net34),
+ .b (net65),
.out (net66)
);
- and_cell gate32 (
- .a (net26),
+ and_cell gate30 (
+ .a (net43),
.b (net66),
.out (net67)
);
- and_cell gate33 (
- .a (net31),
- .b (net67),
+ and_cell gate31 (
+ .a (net23),
+ .b (net19),
.out (net68)
);
- and_cell gate34 (
- .a (net36),
+ and_cell gate32 (
+ .a (net28),
.b (net68),
.out (net69)
);
- and_cell gate35 (
- .a (net37),
+ and_cell gate33 (
+ .a (net33),
.b (net69),
.out (net70)
);
- and_cell gate36 (
- .a (net11),
- .b (net12),
+ and_cell gate34 (
+ .a (net38),
+ .b (net70),
.out (net71)
);
- and_cell gate37 (
- .a (net22),
+ and_cell gate35 (
+ .a (net39),
.b (net71),
.out (net72)
);
- and_cell gate38 (
- .a (net31),
- .b (net72),
+ and_cell gate36 (
+ .a (net14),
+ .b (net15),
.out (net73)
);
- and_cell gate39 (
- .a (net36),
+ and_cell gate37 (
+ .a (net24),
.b (net73),
.out (net74)
);
- and_cell gate40 (
- .a (net37),
+ and_cell gate38 (
+ .a (net33),
.b (net74),
.out (net75)
);
- mux_cell mux13 (
- .a (net76),
- .b (net45),
- .sel (net2),
+ and_cell gate39 (
+ .a (net38),
+ .b (net75),
+ .out (net76)
+ );
+ and_cell gate40 (
+ .a (net39),
+ .b (net76),
.out (net77)
);
- mux_cell mux14 (
- .a (net77),
- .b (net50),
- .sel (net3),
- .out (net78)
- );
- mux_cell mux15 (
+ mux_cell mux13 (
.a (net78),
- .b (net55),
- .sel (net4),
+ .b (net47),
+ .sel (net2),
.out (net79)
);
- mux_cell mux16 (
+ mux_cell mux14 (
.a (net79),
- .b (net60),
- .sel (net5),
+ .b (net52),
+ .sel (net3),
.out (net80)
);
- mux_cell mux17 (
+ mux_cell mux15 (
.a (net80),
- .b (net65),
- .sel (net6),
+ .b (net57),
+ .sel (net4),
.out (net81)
);
- mux_cell mux18 (
+ mux_cell mux16 (
.a (net81),
- .b (net70),
- .sel (net7),
+ .b (net62),
+ .sel (net5),
.out (net82)
);
- mux_cell mux19 (
+ mux_cell mux17 (
.a (net82),
- .b (net75),
+ .b (net67),
+ .sel (net6),
+ .out (net83)
+ );
+ mux_cell mux18 (
+ .a (net83),
+ .b (net72),
+ .sel (net7),
+ .out (net84)
+ );
+ mux_cell mux19 (
+ .a (net84),
+ .b (net77),
.sel (net8),
- .out (net15)
+ .out (net9)
);
dff_cell flipflop8 (
- .d (net83),
- .clk (net15),
- .q (net9),
- .notq (net83)
+ .d (net85),
+ .clk (net9),
+ .q (net10),
+ .notq (net85)
+ );
+ dff_cell flipflop1 (
+ .d (net87),
+ .clk (net10),
+ .q (net11),
+ .notq (net87)
+ );
+ dff_cell flipflop9 (
+ .d (net88),
+ .clk (net11),
+ .q (net12),
+ .notq (net88)
);
endmodule
diff --git a/verilog/rtl/user_module_348540666182107731.v b/verilog/rtl/user_module_348540666182107731.v
index c1c863b..1eda4ea 100644
--- a/verilog/rtl/user_module_348540666182107731.v
+++ b/verilog/rtl/user_module_348540666182107731.v
@@ -21,9 +21,13 @@
wire net13;
wire net14;
wire net15;
- wire net16 = 1'b0;
- wire net17 = 1'b1;
+ wire net16;
+ wire net17 = 1'b0;
wire net18 = 1'b1;
+ wire net19 = 1'b1;
+ wire net20;
+ wire net21;
+ wire net22;
assign io_out[0] = net9;
assign io_out[1] = net10;
@@ -32,7 +36,7 @@
assign io_out[4] = net13;
assign io_out[5] = net14;
assign io_out[6] = net15;
- assign io_out[7] = net1;
+ assign io_out[7] = net16;
and_cell gate1 (
@@ -41,9 +45,7 @@
);
xor_cell gate3 (
- .a (net2),
- .b (net8),
- .out (net15)
+
);
nand_cell gate4 (
.a (net6),
@@ -81,4 +83,28 @@
.b (net7),
.out (net14)
);
+ and_cell gate8 (
+ .a (net2),
+ .b (net8),
+ .out (net20)
+ );
+ or_cell gate9 (
+ .a (net2),
+ .b (net8),
+ .out (net21)
+ );
+ and_cell gate10 (
+ .a (net21),
+ .b (net15),
+ .out (net22)
+ );
+ or_cell gate11 (
+ .a (net20),
+ .b (net22),
+ .out (net15)
+ );
+ not_cell gate12 (
+ .in (net1),
+ .out (net16)
+ );
endmodule
diff --git a/verilog/rtl/user_module_349209305274122835.v b/verilog/rtl/user_module_349209305274122835.v
new file mode 100644
index 0000000..d11a3d5
--- /dev/null
+++ b/verilog/rtl/user_module_349209305274122835.v
@@ -0,0 +1,86 @@
+/* Automatically generated from https://wokwi.com/projects/349209305274122835 */
+
+`default_nettype none
+
+module user_module_349209305274122835(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+ wire net1 = io_in[1];
+ wire net2 = io_in[2];
+ wire net3 = io_in[3];
+ wire net4 = io_in[4];
+ wire net5 = io_in[5];
+ wire net6 = io_in[6];
+ wire net7 = io_in[7];
+ wire net8;
+ wire net9;
+ wire net10;
+ wire net11;
+ wire net12;
+ wire net13;
+ wire net14;
+ wire net15 = 1'b0;
+ wire net16 = 1'b1;
+ wire net17 = 1'b1;
+
+ assign io_out[0] = net1;
+ assign io_out[1] = net8;
+ assign io_out[2] = net9;
+ assign io_out[3] = net10;
+ assign io_out[4] = net11;
+ assign io_out[5] = net12;
+ assign io_out[6] = net13;
+ assign io_out[7] = net14;
+
+ and_cell gate1 (
+ .a (net1),
+ .b (net1),
+ .out (net8)
+ );
+ or_cell gate2 (
+
+ );
+ xor_cell gate3 (
+
+ );
+ nand_cell gate4 (
+
+ );
+ buffer_cell gate6 (
+
+ );
+ mux_cell mux1 (
+
+ );
+ dff_cell flipflop1 (
+ .d (net2),
+ .clk (net8),
+ .q (net9)
+ );
+ dff_cell flipflop2 (
+ .d (net3),
+ .clk (net8),
+ .q (net10)
+ );
+ dff_cell flipflop3 (
+ .d (net4),
+ .clk (net8),
+ .q (net11)
+ );
+ dff_cell flipflop4 (
+ .d (net5),
+ .clk (net8),
+ .q (net12)
+ );
+ dff_cell flipflop5 (
+ .d (net6),
+ .clk (net8),
+ .q (net13)
+ );
+ dff_cell flipflop6 (
+ .d (net7),
+ .clk (net8),
+ .q (net14)
+ );
+endmodule
diff --git a/verilog/rtl/user_module_349886696875098706.v b/verilog/rtl/user_module_349886696875098706.v
new file mode 100644
index 0000000..be9fcb3
--- /dev/null
+++ b/verilog/rtl/user_module_349886696875098706.v
@@ -0,0 +1,91 @@
+/* Automatically generated from https://wokwi.com/projects/349886696875098706 */
+
+`default_nettype none
+
+module user_module_349886696875098706(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+ wire net1 = io_in[0];
+ wire net2;
+ wire net3;
+ wire net4;
+ wire net5;
+ wire net6 = 1'b1;
+ wire net7;
+ wire net8 = 1'b0;
+ wire net9 = 1'b0;
+ wire net10 = 1'b1;
+ wire net11 = 1'b1;
+ wire net12;
+ wire net13;
+ wire net14;
+ wire net15 = 1'b0;
+ wire net16 = 1'b0;
+
+ assign io_out[0] = net2;
+ assign io_out[1] = net3;
+ assign io_out[2] = net3;
+ assign io_out[3] = net4;
+ assign io_out[4] = net5;
+ assign io_out[5] = net6;
+ assign io_out[6] = net7;
+ assign io_out[7] = net8;
+
+ and_cell gate1 (
+
+ );
+ or_cell gate2 (
+
+ );
+ xor_cell gate3 (
+
+ );
+ nand_cell gate4 (
+
+ );
+ not_cell gate5 (
+
+ );
+ buffer_cell gate6 (
+
+ );
+ mux_cell mux1 (
+
+ );
+ dff_cell flipflop1 (
+
+ );
+ dff_cell flipflop2 (
+ .d (net12),
+ .clk (net1),
+ .q (net3),
+ .notq (net13)
+ );
+ dff_cell flipflop3 (
+ .d (net13),
+ .clk (net1),
+ .q (net12),
+ .notq (net14)
+ );
+ nand_cell gate7 (
+ .a (net13),
+ .b (net12),
+ .out (net2)
+ );
+ nand_cell gate8 (
+ .a (net3),
+ .b (net12),
+ .out (net4)
+ );
+ nand_cell gate9 (
+ .a (net3),
+ .b (net14),
+ .out (net5)
+ );
+ nand_cell gate10 (
+ .a (net13),
+ .b (net14),
+ .out (net7)
+ );
+endmodule
diff --git a/verilog/rtl/user_module_349901899339661908.v b/verilog/rtl/user_module_349901899339661908.v
new file mode 100644
index 0000000..744a496
--- /dev/null
+++ b/verilog/rtl/user_module_349901899339661908.v
@@ -0,0 +1,1669 @@
+/* Automatically generated from https://wokwi.com/projects/349901899339661908 */
+
+`default_nettype none
+
+module user_module_349901899339661908(
+ input [7:0] io_in,
+ output [7:0] io_out
+);
+ wire net1 = io_in[0];
+ wire net2 = io_in[2];
+ wire net3 = io_in[3];
+ wire net4 = io_in[4];
+ wire net5 = io_in[5];
+ wire net6 = io_in[6];
+ wire net7 = io_in[7];
+ wire net8;
+ wire net9;
+ wire net10;
+ wire net11;
+ wire net12;
+ wire net13;
+ wire net14;
+ wire net15;
+ wire net16 = 1'b1;
+ wire net17 = 1'b1;
+ wire net18 = 1'b1;
+ wire net19;
+ wire net20;
+ wire net21;
+ wire net22;
+ wire net23;
+ wire net24;
+ wire net25;
+ wire net26;
+ wire net27;
+ wire net28;
+ wire net29;
+ wire net30;
+ wire net31;
+ wire net32;
+ wire net33;
+ wire net34;
+ wire net35;
+ wire net36;
+ wire net37;
+ wire net38;
+ wire net39;
+ wire net40;
+ wire net41;
+ wire net42;
+ wire net43;
+ wire net44;
+ wire net45;
+ wire net46;
+ wire net47;
+ wire net48;
+ wire net49;
+ wire net50;
+ wire net51;
+ wire net52;
+ wire net53;
+ wire net54;
+ wire net55;
+ wire net56;
+ wire net57;
+ wire net58;
+ wire net59;
+ wire net60;
+ wire net61;
+ wire net62;
+ wire net63;
+ wire net64;
+ wire net65;
+ wire net66;
+ wire net67;
+ wire net68;
+ wire net69;
+ wire net70;
+ wire net71;
+ wire net72;
+ wire net73;
+ wire net74;
+ wire net75;
+ wire net76;
+ wire net77;
+ wire net78;
+ wire net79;
+ wire net80;
+ wire net81;
+ wire net82;
+ wire net83;
+ wire net84;
+ wire net85;
+ wire net86;
+ wire net87;
+ wire net88;
+ wire net89;
+ wire net90;
+ wire net91;
+ wire net92;
+ wire net93;
+ wire net94;
+ wire net95;
+ wire net96;
+ wire net97;
+ wire net98 = 1'b1;
+ wire net99;
+ wire net100;
+ wire net101;
+ wire net102;
+ wire net103;
+ wire net104;
+ wire net105;
+ wire net106;
+ wire net107;
+ wire net108;
+ wire net109;
+ wire net110;
+ wire net111;
+ wire net112;
+ wire net113;
+ wire net114;
+ wire net115;
+ wire net116;
+ wire net117;
+ wire net118;
+ wire net119;
+ wire net120;
+ wire net121;
+ wire net122;
+ wire net123;
+ wire net124;
+ wire net125;
+ wire net126;
+ wire net127;
+ wire net128;
+ wire net129;
+ wire net130;
+ wire net131;
+ wire net132;
+ wire net133;
+ wire net134;
+ wire net135;
+ wire net136;
+ wire net137;
+ wire net138;
+ wire net139;
+ wire net140;
+ wire net141;
+ wire net142;
+ wire net143;
+ wire net144;
+ wire net145;
+ wire net146;
+ wire net147;
+ wire net148;
+ wire net149;
+ wire net150;
+ wire net151;
+ wire net152;
+ wire net153;
+ wire net154;
+ wire net155;
+ wire net156;
+ wire net157;
+ wire net158;
+ wire net159;
+ wire net160;
+ wire net161;
+ wire net162;
+ wire net163;
+ wire net164;
+ wire net165;
+ wire net166;
+ wire net167;
+ wire net168;
+ wire net169;
+ wire net170;
+ wire net171;
+ wire net172;
+ wire net173;
+ wire net174;
+ wire net175;
+ wire net176;
+ wire net177;
+ wire net178;
+ wire net179;
+ wire net180;
+ wire net181;
+ wire net182;
+ wire net183;
+ wire net184;
+ wire net185;
+ wire net186;
+ wire net187;
+ wire net188;
+ wire net189;
+ wire net190;
+ wire net191;
+ wire net192;
+ wire net193;
+ wire net194;
+ wire net195;
+ wire net196;
+ wire net197;
+ wire net198;
+ wire net199;
+ wire net200;
+ wire net201;
+ wire net202;
+ wire net203;
+ wire net204;
+ wire net205;
+ wire net206;
+ wire net207;
+ wire net208;
+ wire net209;
+ wire net210;
+ wire net211;
+ wire net212;
+ wire net213;
+ wire net214;
+ wire net215;
+ wire net216;
+ wire net217;
+ wire net218;
+ wire net219;
+ wire net220;
+ wire net221;
+ wire net222;
+ wire net223;
+ wire net224;
+ wire net225;
+ wire net226;
+ wire net227;
+ wire net228;
+ wire net229;
+ wire net230;
+ wire net231;
+ wire net232;
+ wire net233;
+ wire net234;
+ wire net235;
+ wire net236;
+ wire net237;
+ wire net238;
+ wire net239;
+ wire net240;
+ wire net241;
+ wire net242;
+ wire net243;
+ wire net244;
+ wire net245;
+ wire net246;
+ wire net247;
+ wire net248;
+ wire net249;
+ wire net250;
+ wire net251;
+ wire net252;
+ wire net253;
+ wire net254;
+ wire net255;
+ wire net256;
+ wire net257;
+ wire net258;
+ wire net259;
+ wire net260;
+ wire net261;
+ wire net262;
+ wire net263;
+ wire net264;
+ wire net265;
+ wire net266;
+ wire net267;
+ wire net268;
+ wire net269;
+ wire net270;
+ wire net271;
+ wire net272;
+ wire net273;
+ wire net274;
+ wire net275;
+ wire net276 = 1'b0;
+ wire net277;
+ wire net278;
+ wire net279;
+ wire net280;
+ wire net281;
+ wire net282;
+ wire net283;
+ wire net284;
+ wire net285;
+ wire net286;
+ wire net287;
+ wire net288;
+ wire net289;
+ wire net290;
+ wire net291;
+ wire net292;
+ wire net293;
+
+ assign io_out[0] = net8;
+ assign io_out[1] = net9;
+ assign io_out[2] = net10;
+ assign io_out[3] = net11;
+ assign io_out[4] = net12;
+ assign io_out[5] = net13;
+ assign io_out[6] = net14;
+ assign io_out[7] = net15;
+
+ and_cell gate1 (
+
+ );
+ or_cell gate2 (
+
+ );
+ xor_cell gate3 (
+
+ );
+ nand_cell gate4 (
+
+ );
+ not_cell gate5 (
+
+ );
+ buffer_cell gate6 (
+
+ );
+ mux_cell mux1 (
+
+ );
+ dff_cell flipflop1 (
+
+ );
+ dff_cell flipflop2 (
+ .d (net19),
+ .clk (net1),
+ .q (net20),
+ .notq (net21)
+ );
+ and_cell gate7 (
+ .a (net21),
+ .b (net18),
+ .out (net22)
+ );
+ and_cell gate8 (
+ .a (net23),
+ .b (net20),
+ .out (net24)
+ );
+ or_cell gate9 (
+ .a (net22),
+ .b (net24),
+ .out (net25)
+ );
+ not_cell gate10 (
+ .in (net18),
+ .out (net23)
+ );
+ dff_cell flipflop3 (
+ .d (net26),
+ .clk (net1),
+ .q (net27),
+ .notq (net28)
+ );
+ and_cell gate11 (
+ .a (net28),
+ .b (net29),
+ .out (net30)
+ );
+ and_cell gate12 (
+ .a (net31),
+ .b (net27),
+ .out (net32)
+ );
+ or_cell gate13 (
+ .a (net30),
+ .b (net32),
+ .out (net33)
+ );
+ not_cell gate14 (
+ .in (net29),
+ .out (net31)
+ );
+ and_cell gate15 (
+ .a (net34),
+ .b (net20),
+ .out (net35)
+ );
+ and_cell gate16 (
+ .a (net7),
+ .b (net21),
+ .out (net36)
+ );
+ or_cell gate17 (
+ .a (net35),
+ .b (net36),
+ .out (net29)
+ );
+ not_cell gate18 (
+ .in (net7),
+ .out (net34)
+ );
+ dff_cell flipflop4 (
+ .d (net37),
+ .clk (net1),
+ .q (net38),
+ .notq (net39)
+ );
+ and_cell gate19 (
+ .a (net39),
+ .b (net40),
+ .out (net41)
+ );
+ and_cell gate20 (
+ .a (net42),
+ .b (net38),
+ .out (net43)
+ );
+ or_cell gate21 (
+ .a (net41),
+ .b (net43),
+ .out (net44)
+ );
+ not_cell gate22 (
+ .in (net40),
+ .out (net42)
+ );
+ and_cell gate23 (
+ .a (net35),
+ .b (net27),
+ .out (net45)
+ );
+ and_cell gate24 (
+ .a (net28),
+ .b (net36),
+ .out (net46)
+ );
+ or_cell gate25 (
+ .a (net45),
+ .b (net46),
+ .out (net40)
+ );
+ dff_cell flipflop5 (
+ .d (net47),
+ .clk (net1),
+ .q (net48),
+ .notq (net49)
+ );
+ and_cell gate26 (
+ .a (net49),
+ .b (net50),
+ .out (net51)
+ );
+ and_cell gate27 (
+ .a (net52),
+ .b (net48),
+ .out (net53)
+ );
+ or_cell gate28 (
+ .a (net51),
+ .b (net53),
+ .out (net54)
+ );
+ not_cell gate29 (
+ .in (net50),
+ .out (net52)
+ );
+ and_cell gate30 (
+ .a (net45),
+ .b (net38),
+ .out (net55)
+ );
+ and_cell gate31 (
+ .a (net39),
+ .b (net46),
+ .out (net56)
+ );
+ or_cell gate32 (
+ .a (net55),
+ .b (net56),
+ .out (net50)
+ );
+ dff_cell flipflop6 (
+ .d (net57),
+ .clk (net1),
+ .q (net58),
+ .notq (net59)
+ );
+ and_cell gate33 (
+ .a (net59),
+ .b (net60),
+ .out (net61)
+ );
+ and_cell gate34 (
+ .a (net62),
+ .b (net58),
+ .out (net63)
+ );
+ or_cell gate35 (
+ .a (net61),
+ .b (net63),
+ .out (net64)
+ );
+ not_cell gate36 (
+ .in (net60),
+ .out (net62)
+ );
+ and_cell gate37 (
+ .a (net55),
+ .b (net48),
+ .out (net65)
+ );
+ and_cell gate38 (
+ .a (net49),
+ .b (net56),
+ .out (net66)
+ );
+ or_cell gate39 (
+ .a (net65),
+ .b (net66),
+ .out (net60)
+ );
+ dff_cell flipflop7 (
+ .d (net67),
+ .clk (net1),
+ .q (net68),
+ .notq (net69)
+ );
+ and_cell gate40 (
+ .a (net69),
+ .b (net70),
+ .out (net71)
+ );
+ and_cell gate41 (
+ .a (net72),
+ .b (net68),
+ .out (net73)
+ );
+ or_cell gate42 (
+ .a (net71),
+ .b (net73),
+ .out (net74)
+ );
+ not_cell gate43 (
+ .in (net70),
+ .out (net72)
+ );
+ and_cell gate44 (
+ .a (net65),
+ .b (net58),
+ .out (net75)
+ );
+ and_cell gate45 (
+ .a (net59),
+ .b (net66),
+ .out (net76)
+ );
+ or_cell gate46 (
+ .a (net75),
+ .b (net76),
+ .out (net70)
+ );
+ dff_cell flipflop8 (
+ .d (net77),
+ .clk (net1),
+ .q (net78),
+ .notq (net79)
+ );
+ and_cell gate47 (
+ .a (net79),
+ .b (net80),
+ .out (net81)
+ );
+ and_cell gate48 (
+ .a (net82),
+ .b (net78),
+ .out (net83)
+ );
+ or_cell gate49 (
+ .a (net81),
+ .b (net83),
+ .out (net84)
+ );
+ not_cell gate50 (
+ .in (net80),
+ .out (net82)
+ );
+ and_cell gate51 (
+ .a (net75),
+ .b (net68),
+ .out (net85)
+ );
+ and_cell gate52 (
+ .a (net69),
+ .b (net76),
+ .out (net86)
+ );
+ or_cell gate53 (
+ .a (net85),
+ .b (net86),
+ .out (net80)
+ );
+ dff_cell flipflop9 (
+ .d (net87),
+ .clk (net1),
+ .q (net88),
+ .notq (net89)
+ );
+ and_cell gate54 (
+ .a (net89),
+ .b (net90),
+ .out (net91)
+ );
+ and_cell gate55 (
+ .a (net92),
+ .b (net88),
+ .out (net93)
+ );
+ or_cell gate56 (
+ .a (net91),
+ .b (net93),
+ .out (net94)
+ );
+ not_cell gate57 (
+ .in (net90),
+ .out (net92)
+ );
+ and_cell gate58 (
+ .a (net85),
+ .b (net78),
+ .out (net95)
+ );
+ and_cell gate59 (
+ .a (net79),
+ .b (net86),
+ .out (net96)
+ );
+ or_cell gate60 (
+ .a (net95),
+ .b (net96),
+ .out (net90)
+ );
+ not_cell gate114 (
+ .in (net7),
+ .out (net97)
+ );
+ dff_cell flipflop10 (
+ .d (net99),
+ .clk (net1),
+ .q (net100),
+ .notq (net101)
+ );
+ and_cell gate61 (
+ .a (net101),
+ .b (net98),
+ .out (net102)
+ );
+ and_cell gate62 (
+ .a (net103),
+ .b (net100),
+ .out (net104)
+ );
+ or_cell gate63 (
+ .a (net102),
+ .b (net104),
+ .out (net105)
+ );
+ not_cell gate64 (
+ .in (net98),
+ .out (net103)
+ );
+ dff_cell flipflop11 (
+ .d (net106),
+ .clk (net1),
+ .q (net107),
+ .notq (net108)
+ );
+ and_cell gate65 (
+ .a (net108),
+ .b (net109),
+ .out (net110)
+ );
+ and_cell gate66 (
+ .a (net111),
+ .b (net107),
+ .out (net112)
+ );
+ or_cell gate67 (
+ .a (net110),
+ .b (net112),
+ .out (net113)
+ );
+ not_cell gate68 (
+ .in (net109),
+ .out (net111)
+ );
+ and_cell gate69 (
+ .a (net97),
+ .b (net100),
+ .out (net114)
+ );
+ and_cell gate70 (
+ .a (net7),
+ .b (net101),
+ .out (net115)
+ );
+ or_cell gate71 (
+ .a (net114),
+ .b (net115),
+ .out (net109)
+ );
+ dff_cell flipflop12 (
+ .d (net116),
+ .clk (net1),
+ .q (net117),
+ .notq (net118)
+ );
+ and_cell gate72 (
+ .a (net118),
+ .b (net119),
+ .out (net120)
+ );
+ and_cell gate73 (
+ .a (net121),
+ .b (net117),
+ .out (net122)
+ );
+ or_cell gate74 (
+ .a (net120),
+ .b (net122),
+ .out (net123)
+ );
+ not_cell gate75 (
+ .in (net119),
+ .out (net121)
+ );
+ and_cell gate76 (
+ .a (net114),
+ .b (net107),
+ .out (net124)
+ );
+ and_cell gate77 (
+ .a (net108),
+ .b (net115),
+ .out (net125)
+ );
+ or_cell gate78 (
+ .a (net124),
+ .b (net125),
+ .out (net119)
+ );
+ dff_cell flipflop13 (
+ .d (net126),
+ .clk (net1),
+ .q (net127),
+ .notq (net128)
+ );
+ and_cell gate79 (
+ .a (net128),
+ .b (net129),
+ .out (net130)
+ );
+ and_cell gate80 (
+ .a (net131),
+ .b (net127),
+ .out (net132)
+ );
+ or_cell gate81 (
+ .a (net130),
+ .b (net132),
+ .out (net133)
+ );
+ not_cell gate82 (
+ .in (net129),
+ .out (net131)
+ );
+ and_cell gate83 (
+ .a (net124),
+ .b (net117),
+ .out (net134)
+ );
+ and_cell gate84 (
+ .a (net118),
+ .b (net125),
+ .out (net135)
+ );
+ or_cell gate85 (
+ .a (net134),
+ .b (net135),
+ .out (net129)
+ );
+ dff_cell flipflop14 (
+ .d (net136),
+ .clk (net1),
+ .q (net137),
+ .notq (net138)
+ );
+ and_cell gate86 (
+ .a (net138),
+ .b (net139),
+ .out (net140)
+ );
+ and_cell gate87 (
+ .a (net141),
+ .b (net137),
+ .out (net142)
+ );
+ or_cell gate88 (
+ .a (net140),
+ .b (net142),
+ .out (net143)
+ );
+ not_cell gate89 (
+ .in (net139),
+ .out (net141)
+ );
+ and_cell gate90 (
+ .a (net134),
+ .b (net127),
+ .out (net144)
+ );
+ and_cell gate91 (
+ .a (net128),
+ .b (net135),
+ .out (net145)
+ );
+ or_cell gate92 (
+ .a (net144),
+ .b (net145),
+ .out (net139)
+ );
+ dff_cell flipflop15 (
+ .d (net146),
+ .clk (net1),
+ .q (net147),
+ .notq (net148)
+ );
+ and_cell gate93 (
+ .a (net148),
+ .b (net149),
+ .out (net150)
+ );
+ and_cell gate94 (
+ .a (net151),
+ .b (net147),
+ .out (net152)
+ );
+ or_cell gate95 (
+ .a (net150),
+ .b (net152),
+ .out (net153)
+ );
+ not_cell gate96 (
+ .in (net149),
+ .out (net151)
+ );
+ and_cell gate97 (
+ .a (net144),
+ .b (net137),
+ .out (net154)
+ );
+ and_cell gate98 (
+ .a (net138),
+ .b (net145),
+ .out (net155)
+ );
+ or_cell gate99 (
+ .a (net154),
+ .b (net155),
+ .out (net149)
+ );
+ dff_cell flipflop16 (
+ .d (net156),
+ .clk (net1),
+ .q (net157),
+ .notq (net158)
+ );
+ and_cell gate100 (
+ .a (net158),
+ .b (net159),
+ .out (net160)
+ );
+ and_cell gate101 (
+ .a (net161),
+ .b (net157),
+ .out (net162)
+ );
+ or_cell gate102 (
+ .a (net160),
+ .b (net162),
+ .out (net163)
+ );
+ not_cell gate103 (
+ .in (net159),
+ .out (net161)
+ );
+ and_cell gate104 (
+ .a (net154),
+ .b (net147),
+ .out (net164)
+ );
+ and_cell gate105 (
+ .a (net148),
+ .b (net155),
+ .out (net165)
+ );
+ or_cell gate106 (
+ .a (net164),
+ .b (net165),
+ .out (net159)
+ );
+ dff_cell flipflop17 (
+ .d (net166),
+ .clk (net1),
+ .q (net167),
+ .notq (net168)
+ );
+ and_cell gate107 (
+ .a (net168),
+ .b (net169),
+ .out (net170)
+ );
+ and_cell gate108 (
+ .a (net171),
+ .b (net167),
+ .out (net172)
+ );
+ or_cell gate109 (
+ .a (net170),
+ .b (net172),
+ .out (net173)
+ );
+ not_cell gate110 (
+ .in (net169),
+ .out (net171)
+ );
+ and_cell gate111 (
+ .a (net164),
+ .b (net157),
+ .out (net174)
+ );
+ and_cell gate112 (
+ .a (net158),
+ .b (net165),
+ .out (net175)
+ );
+ or_cell gate113 (
+ .a (net174),
+ .b (net175),
+ .out (net169)
+ );
+ not_cell gate117 (
+ .in (net6),
+ .out (net176)
+ );
+ not_cell gate118 (
+
+ );
+ not_cell gate130 (
+
+ );
+ not_cell gate131 (
+
+ );
+ buffer_cell gate132 (
+ .in (net177),
+ .out (net178)
+ );
+ buffer_cell gate133 (
+ .in (net179),
+ .out (net180)
+ );
+ buffer_cell gate134 (
+ .in (net181),
+ .out (net182)
+ );
+ buffer_cell gate135 (
+ .in (net183),
+ .out (net184)
+ );
+ not_cell gate136 (
+ .in (net182),
+ .out (net185)
+ );
+ not_cell gate137 (
+ .in (net184),
+ .out (net186)
+ );
+ not_cell gate138 (
+ .in (net180),
+ .out (net187)
+ );
+ not_cell gate139 (
+ .in (net178),
+ .out (net188)
+ );
+ and_cell gate140 (
+ .a (net182),
+ .b (net189),
+ .out (net190)
+ );
+ and_cell gate141 (
+ .a (net188),
+ .b (net180),
+ .out (net189)
+ );
+ or_cell gate142 (
+ .a (net191),
+ .b (net192),
+ .out (net8)
+ );
+ and_cell gate143 (
+ .a (net178),
+ .b (net185),
+ .out (net193)
+ );
+ and_cell gate144 (
+ .a (net186),
+ .b (net194),
+ .out (net195)
+ );
+ and_cell gate145 (
+ .a (net187),
+ .b (net178),
+ .out (net194)
+ );
+ and_cell gate146 (
+ .a (net184),
+ .b (net188),
+ .out (net196)
+ );
+ and_cell gate147 (
+ .a (net180),
+ .b (net184),
+ .out (net197)
+ );
+ or_cell gate148 (
+ .a (net198),
+ .b (net197),
+ .out (net199)
+ );
+ or_cell gate149 (
+ .a (net196),
+ .b (net190),
+ .out (net200)
+ );
+ or_cell gate150 (
+ .a (net195),
+ .b (net193),
+ .out (net192)
+ );
+ or_cell gate151 (
+ .a (net199),
+ .b (net200),
+ .out (net191)
+ );
+ and_cell gate152 (
+ .a (net178),
+ .b (net201),
+ .out (net202)
+ );
+ and_cell gate153 (
+ .a (net186),
+ .b (net182),
+ .out (net201)
+ );
+ and_cell gate154 (
+ .a (net187),
+ .b (net185),
+ .out (net198)
+ );
+ and_cell gate155 (
+ .a (net188),
+ .b (net203),
+ .out (net204)
+ );
+ and_cell gate156 (
+ .a (net186),
+ .b (net185),
+ .out (net203)
+ );
+ and_cell gate157 (
+ .a (net188),
+ .b (net184),
+ .out (net205)
+ );
+ and_cell gate158 (
+ .a (net205),
+ .b (net182),
+ .out (net206)
+ );
+ and_cell gate159 (
+ .a (net188),
+ .b (net187),
+ .out (net207)
+ );
+ or_cell gate160 (
+ .a (net202),
+ .b (net207),
+ .out (net208)
+ );
+ or_cell gate161 (
+ .a (net206),
+ .b (net204),
+ .out (net209)
+ );
+ or_cell gate162 (
+ .a (net208),
+ .b (net209),
+ .out (net210)
+ );
+ or_cell gate163 (
+ .a (net210),
+ .b (net198),
+ .out (net9)
+ );
+ and_cell gate164 (
+ .a (net178),
+ .b (net187),
+ .out (net211)
+ );
+ and_cell gate165 (
+ .a (net188),
+ .b (net180),
+ .out (net212)
+ );
+ and_cell gate166 (
+ .a (net188),
+ .b (net186),
+ .out (net213)
+ );
+ and_cell gate167 (
+ .a (net188),
+ .b (net182),
+ .out (net214)
+ );
+ and_cell gate168 (
+ .a (net182),
+ .b (net186),
+ .out (net215)
+ );
+ or_cell gate169 (
+ .a (net211),
+ .b (net212),
+ .out (net216)
+ );
+ or_cell gate170 (
+ .a (net213),
+ .b (net214),
+ .out (net217)
+ );
+ or_cell gate171 (
+ .a (net216),
+ .b (net217),
+ .out (net218)
+ );
+ or_cell gate172 (
+ .a (net218),
+ .b (net215),
+ .out (net10)
+ );
+ and_cell gate173 (
+ .a (net180),
+ .b (net186),
+ .out (net219)
+ );
+ and_cell gate174 (
+ .a (net188),
+ .b (net184),
+ .out (net220)
+ );
+ and_cell gate175 (
+ .a (net178),
+ .b (net180),
+ .out (net221)
+ );
+ and_cell gate176 (
+ .a (net219),
+ .b (net182),
+ .out (net222)
+ );
+ and_cell gate177 (
+ .a (net220),
+ .b (net185),
+ .out (net223)
+ );
+ and_cell gate178 (
+ .a (net221),
+ .b (net185),
+ .out (net224)
+ );
+ and_cell gate179 (
+ .a (net187),
+ .b (net186),
+ .out (net225)
+ );
+ and_cell gate180 (
+ .a (net187),
+ .b (net184),
+ .out (net226)
+ );
+ and_cell gate181 (
+ .a (net225),
+ .b (net185),
+ .out (net227)
+ );
+ and_cell gate182 (
+ .a (net226),
+ .b (net182),
+ .out (net228)
+ );
+ or_cell gate183 (
+ .a (net224),
+ .b (net223),
+ .out (net229)
+ );
+ or_cell gate184 (
+ .a (net222),
+ .b (net228),
+ .out (net230)
+ );
+ or_cell gate185 (
+ .a (net229),
+ .b (net230),
+ .out (net231)
+ );
+ or_cell gate186 (
+ .a (net231),
+ .b (net227),
+ .out (net11)
+ );
+ and_cell gate187 (
+ .a (net178),
+ .b (net184),
+ .out (net232)
+ );
+ and_cell gate188 (
+ .a (net178),
+ .b (net180),
+ .out (net233)
+ );
+ and_cell gate189 (
+ .a (net184),
+ .b (net185),
+ .out (net234)
+ );
+ or_cell gate190 (
+ .a (net233),
+ .b (net232),
+ .out (net235)
+ );
+ or_cell gate191 (
+ .a (net198),
+ .b (net234),
+ .out (net236)
+ );
+ or_cell gate192 (
+ .a (net235),
+ .b (net236),
+ .out (net12)
+ );
+ and_cell gate193 (
+ .a (net178),
+ .b (net187),
+ .out (net237)
+ );
+ and_cell gate194 (
+ .a (net213),
+ .b (net180),
+ .out (net238)
+ );
+ and_cell gate195 (
+ .a (net180),
+ .b (net185),
+ .out (net239)
+ );
+ or_cell gate196 (
+ .a (net237),
+ .b (net232),
+ .out (net240)
+ );
+ or_cell gate197 (
+ .a (net238),
+ .b (net239),
+ .out (net241)
+ );
+ or_cell gate198 (
+ .a (net240),
+ .b (net241),
+ .out (net242)
+ );
+ or_cell gate199 (
+ .a (net242),
+ .b (net203),
+ .out (net13)
+ );
+ and_cell gate200 (
+ .a (net237),
+ .b (net243),
+ .out (net15)
+ );
+ and_cell gate201 (
+ .a (net178),
+ .b (net182),
+ .out (net244)
+ );
+ or_cell gate202 (
+ .a (net237),
+ .b (net238),
+ .out (net245)
+ );
+ or_cell gate203 (
+ .a (net244),
+ .b (net246),
+ .out (net247)
+ );
+ and_cell gate204 (
+ .a (net187),
+ .b (net184),
+ .out (net246)
+ );
+ or_cell gate205 (
+ .a (net245),
+ .b (net247),
+ .out (net248)
+ );
+ or_cell gate206 (
+ .a (net234),
+ .b (net248),
+ .out (net14)
+ );
+ and_cell gate207 (
+ .a (net184),
+ .b (net182),
+ .out (net243)
+ );
+ mux_cell mux5 (
+ .a (net20),
+ .b (net100),
+ .sel (net249),
+ .out (net250)
+ );
+ mux_cell mux6 (
+ .a (net48),
+ .b (net127),
+ .sel (net249),
+ .out (net251)
+ );
+ mux_cell mux7 (
+ .a (net38),
+ .b (net117),
+ .sel (net249),
+ .out (net252)
+ );
+ mux_cell mux8 (
+ .a (net27),
+ .b (net107),
+ .sel (net249),
+ .out (net253)
+ );
+ mux_cell mux9 (
+ .a (net58),
+ .b (net137),
+ .sel (net249),
+ .out (net254)
+ );
+ mux_cell mux10 (
+ .a (net88),
+ .b (net167),
+ .sel (net249),
+ .out (net255)
+ );
+ mux_cell mux11 (
+ .a (net78),
+ .b (net157),
+ .sel (net249),
+ .out (net256)
+ );
+ mux_cell mux12 (
+ .a (net68),
+ .b (net147),
+ .sel (net249),
+ .out (net257)
+ );
+ not_cell not1 (
+ .in (net5),
+ .out (net249)
+ );
+ mux_cell mux2 (
+ .a (net252),
+ .b (net256),
+ .sel (net4),
+ .out (net179)
+ );
+ mux_cell mux3 (
+ .a (net253),
+ .b (net257),
+ .sel (net4),
+ .out (net183)
+ );
+ mux_cell mux4 (
+ .a (net250),
+ .b (net254),
+ .sel (net4),
+ .out (net181)
+ );
+ mux_cell mux13 (
+ .a (net251),
+ .b (net255),
+ .sel (net4),
+ .out (net177)
+ );
+ not_cell not2 (
+ .in (net3),
+ .out (net258)
+ );
+ and_cell and1 (
+ .a (net258),
+ .b (net25),
+ .out (net259)
+ );
+ and_cell and2 (
+ .a (net258),
+ .b (net33),
+ .out (net260)
+ );
+ and_cell and3 (
+ .a (net258),
+ .b (net44),
+ .out (net261)
+ );
+ and_cell and4 (
+ .a (net258),
+ .b (net54),
+ .out (net262)
+ );
+ and_cell and5 (
+ .a (net258),
+ .b (net64),
+ .out (net263)
+ );
+ and_cell and6 (
+ .a (net258),
+ .b (net74),
+ .out (net264)
+ );
+ and_cell and7 (
+ .a (net258),
+ .b (net84),
+ .out (net265)
+ );
+ and_cell and8 (
+ .a (net258),
+ .b (net94),
+ .out (net266)
+ );
+ not_cell not3 (
+ .in (net3),
+ .out (net267)
+ );
+ and_cell and9 (
+ .a (net267),
+ .b (net105),
+ .out (net268)
+ );
+ and_cell and10 (
+ .a (net267),
+ .b (net113),
+ .out (net269)
+ );
+ and_cell and11 (
+ .a (net267),
+ .b (net123),
+ .out (net270)
+ );
+ and_cell and12 (
+ .a (net267),
+ .b (net133),
+ .out (net271)
+ );
+ and_cell and13 (
+ .a (net267),
+ .b (net143),
+ .out (net272)
+ );
+ and_cell and14 (
+ .a (net267),
+ .b (net153),
+ .out (net273)
+ );
+ and_cell and15 (
+ .a (net267),
+ .b (net163),
+ .out (net274)
+ );
+ and_cell and16 (
+ .a (net267),
+ .b (net173),
+ .out (net275)
+ );
+ mux_cell mux14 (
+ .a (net20),
+ .b (net259),
+ .sel (net277),
+ .out (net19)
+ );
+ and_cell and17 (
+ .a (net2),
+ .b (net6),
+ .out (net277)
+ );
+ mux_cell mux15 (
+ .a (net27),
+ .b (net260),
+ .sel (net278),
+ .out (net26)
+ );
+ buffer_cell gate115 (
+ .in (net277),
+ .out (net278)
+ );
+ mux_cell mux16 (
+ .a (net38),
+ .b (net261),
+ .sel (net279),
+ .out (net37)
+ );
+ buffer_cell gate119 (
+ .in (net278),
+ .out (net279)
+ );
+ mux_cell mux17 (
+ .a (net48),
+ .b (net262),
+ .sel (net280),
+ .out (net47)
+ );
+ buffer_cell gate120 (
+ .in (net279),
+ .out (net280)
+ );
+ mux_cell mux18 (
+ .a (net58),
+ .b (net263),
+ .sel (net281),
+ .out (net57)
+ );
+ buffer_cell gate121 (
+ .in (net280),
+ .out (net281)
+ );
+ mux_cell mux19 (
+ .a (net68),
+ .b (net264),
+ .sel (net282),
+ .out (net67)
+ );
+ buffer_cell gate122 (
+ .in (net281),
+ .out (net282)
+ );
+ mux_cell mux20 (
+ .a (net78),
+ .b (net265),
+ .sel (net283),
+ .out (net77)
+ );
+ buffer_cell gate123 (
+ .in (net282),
+ .out (net283)
+ );
+ mux_cell mux21 (
+ .a (net88),
+ .b (net266),
+ .sel (net284),
+ .out (net87)
+ );
+ buffer_cell gate124 (
+ .in (net283),
+ .out (net284)
+ );
+ mux_cell mux22 (
+ .a (net100),
+ .b (net268),
+ .sel (net285),
+ .out (net99)
+ );
+ buffer_cell gate125 (
+ .in (net286),
+ .out (net285)
+ );
+ and_cell and18 (
+ .a (net2),
+ .b (net176),
+ .out (net286)
+ );
+ mux_cell mux23 (
+ .a (net107),
+ .b (net269),
+ .sel (net287),
+ .out (net106)
+ );
+ buffer_cell gate116 (
+ .in (net285),
+ .out (net287)
+ );
+ mux_cell mux24 (
+ .a (net117),
+ .b (net270),
+ .sel (net288),
+ .out (net116)
+ );
+ buffer_cell gate126 (
+ .in (net287),
+ .out (net288)
+ );
+ mux_cell mux25 (
+ .a (net127),
+ .b (net271),
+ .sel (net289),
+ .out (net126)
+ );
+ buffer_cell gate127 (
+ .in (net288),
+ .out (net289)
+ );
+ mux_cell mux26 (
+ .a (net137),
+ .b (net272),
+ .sel (net290),
+ .out (net136)
+ );
+ buffer_cell gate128 (
+ .in (net289),
+ .out (net290)
+ );
+ mux_cell mux27 (
+ .a (net147),
+ .b (net273),
+ .sel (net291),
+ .out (net146)
+ );
+ buffer_cell gate129 (
+ .in (net290),
+ .out (net291)
+ );
+ mux_cell mux28 (
+ .a (net157),
+ .b (net274),
+ .sel (net292),
+ .out (net156)
+ );
+ buffer_cell gate208 (
+ .in (net291),
+ .out (net292)
+ );
+ mux_cell mux29 (
+ .a (net167),
+ .b (net275),
+ .sel (net293),
+ .out (net166)
+ );
+ buffer_cell gate209 (
+ .in (net292),
+ .out (net293)
+ );
+endmodule
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index e085da5..96fcb72 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -923,7 +923,7 @@
.module_data_out (sw_036_module_data_out)
);
- jar_illegal_logic jar_illegal_logic_036 (
+ jar_pi jar_pi_036 (
.io_in (sw_036_module_data_in),
.io_out (sw_036_module_data_out)
);
@@ -1473,12 +1473,12 @@
.module_data_out (sw_061_module_data_out)
);
- user_module_349405063877231188 user_module_349405063877231188_061 (
+ user_module_349901899339661908 user_module_349901899339661908_061 (
.io_in (sw_061_module_data_in),
.io_out (sw_061_module_data_out)
);
- // [062] https://github.com/NYIT-CNS/cns002-tt02-submission2
+ // [062] https://github.com/shaos/tt02-submission-shaos
wire sw_062_clk_out, sw_062_data_out, sw_062_scan_out, sw_062_latch_out;
wire [7:0] sw_062_module_data_in;
wire [7:0] sw_062_module_data_out;
@@ -1495,12 +1495,12 @@
.module_data_out (sw_062_module_data_out)
);
- user_module_348961139276644947 user_module_348961139276644947_062 (
+ user_module_348540666182107731 user_module_348540666182107731_062 (
.io_in (sw_062_module_data_in),
.io_out (sw_062_module_data_out)
);
- // [063] https://github.com/shaos/tt02-submission-shaos
+ // [063] https://github.com/toybuilder/tt02-learn-tinytapeout
wire sw_063_clk_out, sw_063_data_out, sw_063_scan_out, sw_063_latch_out;
wire [7:0] sw_063_module_data_in;
wire [7:0] sw_063_module_data_out;
@@ -1517,12 +1517,12 @@
.module_data_out (sw_063_module_data_out)
);
- user_module_348540666182107731 user_module_348540666182107731_063 (
+ user_module_341490465660469844 user_module_341490465660469844_063 (
.io_in (sw_063_module_data_in),
.io_out (sw_063_module_data_out)
);
- // [064] https://github.com/toybuilder/tt02-learn-tinytapeout
+ // [064] https://github.com/drburke3/tt02-nano-neuron
wire sw_064_clk_out, sw_064_data_out, sw_064_scan_out, sw_064_latch_out;
wire [7:0] sw_064_module_data_in;
wire [7:0] sw_064_module_data_out;
@@ -1539,12 +1539,12 @@
.module_data_out (sw_064_module_data_out)
);
- user_module_341490465660469844 user_module_341490465660469844_064 (
+ user_module_349047610915422802 user_module_349047610915422802_064 (
.io_in (sw_064_module_data_in),
.io_out (sw_064_module_data_out)
);
- // [065] https://github.com/drburke3/tt02-nano-neuron
+ // [065] https://github.com/UDXS/sqrt-tt02
wire sw_065_clk_out, sw_065_data_out, sw_065_scan_out, sw_065_latch_out;
wire [7:0] sw_065_module_data_in;
wire [7:0] sw_065_module_data_out;
@@ -1561,12 +1561,12 @@
.module_data_out (sw_065_module_data_out)
);
- user_module_349047610915422802 user_module_349047610915422802_065 (
+ udxs_sqrt_top udxs_sqrt_top_065 (
.io_in (sw_065_module_data_in),
.io_out (sw_065_module_data_out)
);
- // [066] https://github.com/UDXS/sqrt-tt02
+ // [066] https://github.com/argunda/tt02-breathing-led
wire sw_066_clk_out, sw_066_data_out, sw_066_scan_out, sw_066_latch_out;
wire [7:0] sw_066_module_data_in;
wire [7:0] sw_066_module_data_out;
@@ -1583,12 +1583,12 @@
.module_data_out (sw_066_module_data_out)
);
- udxs_sqrt_top udxs_sqrt_top_066 (
+ pwm_gen pwm_gen_066 (
.io_in (sw_066_module_data_in),
.io_out (sw_066_module_data_out)
);
- // [067] https://github.com/argunda/tt02-breathing-led
+ // [067] https://github.com/daniestevez/tt02-gold-fibonacci
wire sw_067_clk_out, sw_067_data_out, sw_067_scan_out, sw_067_latch_out;
wire [7:0] sw_067_module_data_in;
wire [7:0] sw_067_module_data_out;
@@ -1605,12 +1605,12 @@
.module_data_out (sw_067_module_data_out)
);
- pwm_gen pwm_gen_067 (
+ user_module_341164910646919762 user_module_341164910646919762_067 (
.io_in (sw_067_module_data_in),
.io_out (sw_067_module_data_out)
);
- // [068] https://github.com/daniestevez/tt02-gold-fibonacci
+ // [068] https://github.com/r4d10n/tt02-HELLo-3orLd-7seg
wire sw_068_clk_out, sw_068_data_out, sw_068_scan_out, sw_068_latch_out;
wire [7:0] sw_068_module_data_in;
wire [7:0] sw_068_module_data_out;
@@ -1627,12 +1627,12 @@
.module_data_out (sw_068_module_data_out)
);
- user_module_341164910646919762 user_module_341164910646919762_068 (
+ user_module_341609034095264340 user_module_341609034095264340_068 (
.io_in (sw_068_module_data_in),
.io_out (sw_068_module_data_out)
);
- // [069] https://github.com/r4d10n/tt02-HELLo-3orLd-7seg
+ // [069] https://github.com/navray/tt02-square-root
wire sw_069_clk_out, sw_069_data_out, sw_069_scan_out, sw_069_latch_out;
wire [7:0] sw_069_module_data_in;
wire [7:0] sw_069_module_data_out;
@@ -1649,12 +1649,12 @@
.module_data_out (sw_069_module_data_out)
);
- user_module_341609034095264340 user_module_341609034095264340_069 (
+ navray_top navray_top_069 (
.io_in (sw_069_module_data_in),
.io_out (sw_069_module_data_out)
);
- // [070] https://github.com/navray/tt02-square-root
+ // [070] https://github.com/shaos-net/tt02-submission-shaos2
wire sw_070_clk_out, sw_070_data_out, sw_070_scan_out, sw_070_latch_out;
wire [7:0] sw_070_module_data_in;
wire [7:0] sw_070_module_data_out;
@@ -1671,12 +1671,12 @@
.module_data_out (sw_070_module_data_out)
);
- navray_top navray_top_070 (
+ user_module_349011320806310484 user_module_349011320806310484_070 (
.io_in (sw_070_module_data_in),
.io_out (sw_070_module_data_out)
);
- // [071] https://github.com/shaos-net/tt02-submission-shaos2
+ // [071] https://github.com/krasin/tt02-verilog-spi-7-channel-pwm-driver
wire sw_071_clk_out, sw_071_data_out, sw_071_scan_out, sw_071_latch_out;
wire [7:0] sw_071_module_data_in;
wire [7:0] sw_071_module_data_out;
@@ -1693,12 +1693,12 @@
.module_data_out (sw_071_module_data_out)
);
- user_module_349011320806310484 user_module_349011320806310484_071 (
+ krasin_tt02_verilog_spi_7_channel_pwm_driver krasin_tt02_verilog_spi_7_channel_pwm_driver_071 (
.io_in (sw_071_module_data_in),
.io_out (sw_071_module_data_out)
);
- // [072] https://github.com/krasin/tt02-verilog-spi-7-channel-pwm-driver
+ // [072] https://github.com/brouhaha/tt02-hex-sr
wire sw_072_clk_out, sw_072_data_out, sw_072_scan_out, sw_072_latch_out;
wire [7:0] sw_072_module_data_in;
wire [7:0] sw_072_module_data_out;
@@ -1715,12 +1715,12 @@
.module_data_out (sw_072_module_data_out)
);
- krasin_tt02_verilog_spi_7_channel_pwm_driver krasin_tt02_verilog_spi_7_channel_pwm_driver_072 (
+ hex_sr hex_sr_072 (
.io_in (sw_072_module_data_in),
.io_out (sw_072_module_data_out)
);
- // [073] https://github.com/brouhaha/tt02-hex-sr
+ // [073] https://github.com/ericsmi/tt02-verilog-ring-osc-demo
wire sw_073_clk_out, sw_073_data_out, sw_073_scan_out, sw_073_latch_out;
wire [7:0] sw_073_module_data_in;
wire [7:0] sw_073_module_data_out;
@@ -1737,12 +1737,12 @@
.module_data_out (sw_073_module_data_out)
);
- hex_sr hex_sr_073 (
+ ericsmi_speed_test ericsmi_speed_test_073 (
.io_in (sw_073_module_data_in),
.io_out (sw_073_module_data_out)
);
- // [074] https://github.com/ericsmi/tt02-verilog-ring-osc-demo
+ // [074] https://github.com/AidanMedcalf/tt02-pid
wire sw_074_clk_out, sw_074_data_out, sw_074_scan_out, sw_074_latch_out;
wire [7:0] sw_074_module_data_in;
wire [7:0] sw_074_module_data_out;
@@ -1759,12 +1759,12 @@
.module_data_out (sw_074_module_data_out)
);
- ericsmi_speed_test ericsmi_speed_test_074 (
+ AidanMedcalf_pid_controller AidanMedcalf_pid_controller_074 (
.io_in (sw_074_module_data_in),
.io_out (sw_074_module_data_out)
);
- // [075] https://github.com/AidanMedcalf/tt02-pid
+ // [075] https://github.com/cpldcpu/tt02-TrainLED
wire sw_075_clk_out, sw_075_data_out, sw_075_scan_out, sw_075_latch_out;
wire [7:0] sw_075_module_data_in;
wire [7:0] sw_075_module_data_out;
@@ -1781,12 +1781,12 @@
.module_data_out (sw_075_module_data_out)
);
- AidanMedcalf_pid_controller AidanMedcalf_pid_controller_075 (
+ cpldcpu_TrainLED2top cpldcpu_TrainLED2top_075 (
.io_in (sw_075_module_data_in),
.io_out (sw_075_module_data_out)
);
- // [076] https://github.com/cpldcpu/tt02-TrainLED
+ // [076] https://github.com/cpldcpu/tt02-mcpu5plus
wire sw_076_clk_out, sw_076_data_out, sw_076_scan_out, sw_076_latch_out;
wire [7:0] sw_076_module_data_in;
wire [7:0] sw_076_module_data_out;
@@ -1803,12 +1803,12 @@
.module_data_out (sw_076_module_data_out)
);
- cpldcpu_TrainLED2top cpldcpu_TrainLED2top_076 (
+ cpldcpu_MCPU5plus cpldcpu_MCPU5plus_076 (
.io_in (sw_076_module_data_in),
.io_out (sw_076_module_data_out)
);
- // [077] https://github.com/cpldcpu/tt02-mcpu5plus
+ // [077] https://github.com/MoonbaseOtago/tt-cpu
wire sw_077_clk_out, sw_077_data_out, sw_077_scan_out, sw_077_latch_out;
wire [7:0] sw_077_module_data_in;
wire [7:0] sw_077_module_data_out;
@@ -1825,12 +1825,12 @@
.module_data_out (sw_077_module_data_out)
);
- cpldcpu_MCPU5plus cpldcpu_MCPU5plus_077 (
+ moonbase_cpu_4bit moonbase_cpu_4bit_077 (
.io_in (sw_077_module_data_in),
.io_out (sw_077_module_data_out)
);
- // [078] https://github.com/MoonbaseOtago/tt-cpu
+ // [078] https://github.com/davidsiaw/tt02-davidsiaw-stackcalc
wire sw_078_clk_out, sw_078_data_out, sw_078_scan_out, sw_078_latch_out;
wire [7:0] sw_078_module_data_in;
wire [7:0] sw_078_module_data_out;
@@ -1847,12 +1847,12 @@
.module_data_out (sw_078_module_data_out)
);
- moonbase_cpu_4bit moonbase_cpu_4bit_078 (
+ davidsiaw_stackcalc davidsiaw_stackcalc_078 (
.io_in (sw_078_module_data_in),
.io_out (sw_078_module_data_out)
);
- // [079] https://github.com/davidsiaw/tt02-davidsiaw-stackcalc
+ // [079] https://github.com/mole99/tt02-1bit-alu
wire sw_079_clk_out, sw_079_data_out, sw_079_scan_out, sw_079_latch_out;
wire [7:0] sw_079_module_data_in;
wire [7:0] sw_079_module_data_out;
@@ -1869,12 +1869,12 @@
.module_data_out (sw_079_module_data_out)
);
- davidsiaw_stackcalc davidsiaw_stackcalc_079 (
+ user_module_340318610245288530 user_module_340318610245288530_079 (
.io_in (sw_079_module_data_in),
.io_out (sw_079_module_data_out)
);
- // [080] https://github.com/mole99/tt02-1bit-alu
+ // [080] https://github.com/steieio/tt02-sfsm-wokwi
wire sw_080_clk_out, sw_080_data_out, sw_080_scan_out, sw_080_latch_out;
wire [7:0] sw_080_module_data_in;
wire [7:0] sw_080_module_data_out;
@@ -1891,12 +1891,12 @@
.module_data_out (sw_080_module_data_out)
);
- user_module_340318610245288530 user_module_340318610245288530_080 (
+ user_module_349228308755382868 user_module_349228308755382868_080 (
.io_in (sw_080_module_data_in),
.io_out (sw_080_module_data_out)
);
- // [081] https://github.com/steieio/tt02-sfsm-wokwi
+ // [081] https://github.com/youngpines/tt02-youngpines-submission
wire sw_081_clk_out, sw_081_data_out, sw_081_scan_out, sw_081_latch_out;
wire [7:0] sw_081_module_data_in;
wire [7:0] sw_081_module_data_out;
@@ -1913,12 +1913,12 @@
.module_data_out (sw_081_module_data_out)
);
- user_module_349228308755382868 user_module_349228308755382868_081 (
+ user_module_341571228858843732 user_module_341571228858843732_081 (
.io_in (sw_081_module_data_in),
.io_out (sw_081_module_data_out)
);
- // [082] https://github.com/youngpines/tt02-youngpines-submission
+ // [082] https://github.com/timvgso/tinatapeworm
wire sw_082_clk_out, sw_082_data_out, sw_082_scan_out, sw_082_latch_out;
wire [7:0] sw_082_module_data_in;
wire [7:0] sw_082_module_data_out;
@@ -1935,12 +1935,12 @@
.module_data_out (sw_082_module_data_out)
);
- user_module_341571228858843732 user_module_341571228858843732_082 (
+ user_module_348381622440034899 user_module_348381622440034899_082 (
.io_in (sw_082_module_data_in),
.io_out (sw_082_module_data_out)
);
- // [083] https://github.com/timvgso/tinatapeworm
+ // [083] https://github.com/OneRNG/tt-cpu8
wire sw_083_clk_out, sw_083_data_out, sw_083_scan_out, sw_083_latch_out;
wire [7:0] sw_083_module_data_in;
wire [7:0] sw_083_module_data_out;
@@ -1957,12 +1957,12 @@
.module_data_out (sw_083_module_data_out)
);
- user_module_348381622440034899 user_module_348381622440034899_083 (
+ moonbase_cpu_8bit moonbase_cpu_8bit_083 (
.io_in (sw_083_module_data_in),
.io_out (sw_083_module_data_out)
);
- // [084] https://github.com/OneRNG/tt-cpu8
+ // [084] https://github.com/tcptomato/tt02-submission-template
wire sw_084_clk_out, sw_084_data_out, sw_084_scan_out, sw_084_latch_out;
wire [7:0] sw_084_module_data_in;
wire [7:0] sw_084_module_data_out;
@@ -1979,12 +1979,12 @@
.module_data_out (sw_084_module_data_out)
);
- moonbase_cpu_8bit moonbase_cpu_8bit_084 (
+ user_module_341178154799333971 user_module_341178154799333971_084 (
.io_in (sw_084_module_data_in),
.io_out (sw_084_module_data_out)
);
- // [085] https://github.com/tcptomato/tt02-submission-template
+ // [085] https://github.com/jglim/tt02-bcd-7seg
wire sw_085_clk_out, sw_085_data_out, sw_085_scan_out, sw_085_latch_out;
wire [7:0] sw_085_module_data_in;
wire [7:0] sw_085_module_data_out;
@@ -2001,12 +2001,12 @@
.module_data_out (sw_085_module_data_out)
);
- user_module_341178154799333971 user_module_341178154799333971_085 (
+ user_module_349546262775726676 user_module_349546262775726676_085 (
.io_in (sw_085_module_data_in),
.io_out (sw_085_module_data_out)
);
- // [086] https://github.com/jglim/tt02-bcd-7seg
+ // [086] https://github.com/ARamsey118/tiny_tapeout_freq_counter
wire sw_086_clk_out, sw_086_data_out, sw_086_scan_out, sw_086_latch_out;
wire [7:0] sw_086_module_data_in;
wire [7:0] sw_086_module_data_out;
@@ -2023,12 +2023,12 @@
.module_data_out (sw_086_module_data_out)
);
- user_module_349546262775726676 user_module_349546262775726676_086 (
+ aramsey118_freq_counter aramsey118_freq_counter_086 (
.io_in (sw_086_module_data_in),
.io_out (sw_086_module_data_out)
);
- // [087] https://github.com/ARamsey118/tiny_tapeout_freq_counter
+ // [087] https://github.com/splinedrive/thunderbird_taillight_1965
wire sw_087_clk_out, sw_087_data_out, sw_087_scan_out, sw_087_latch_out;
wire [7:0] sw_087_module_data_in;
wire [7:0] sw_087_module_data_out;
@@ -2045,12 +2045,12 @@
.module_data_out (sw_087_module_data_out)
);
- aramsey118_freq_counter aramsey118_freq_counter_087 (
+ thunderbird_taillight_ctrl thunderbird_taillight_ctrl_087 (
.io_in (sw_087_module_data_in),
.io_out (sw_087_module_data_out)
);
- // [088] https://github.com/splinedrive/thunderbird_taillight_1965
+ // [088] https://github.com/gatecat/tt02-fpga-respin
wire sw_088_clk_out, sw_088_data_out, sw_088_scan_out, sw_088_latch_out;
wire [7:0] sw_088_module_data_in;
wire [7:0] sw_088_module_data_out;
@@ -2067,12 +2067,12 @@
.module_data_out (sw_088_module_data_out)
);
- thunderbird_taillight_ctrl thunderbird_taillight_ctrl_088 (
+ gatecat_fpga_top gatecat_fpga_top_088 (
.io_in (sw_088_module_data_in),
.io_out (sw_088_module_data_out)
);
- // [089] https://github.com/gatecat/tt02-fpga-respin
+ // [089] https://github.com/mmolteni-secpat/tinytapeout02_chi2shares
wire sw_089_clk_out, sw_089_data_out, sw_089_scan_out, sw_089_latch_out;
wire [7:0] sw_089_module_data_in;
wire [7:0] sw_089_module_data_out;
@@ -2089,12 +2089,12 @@
.module_data_out (sw_089_module_data_out)
);
- gatecat_fpga_top gatecat_fpga_top_089 (
+ user_module_341589685194195540 user_module_341589685194195540_089 (
.io_in (sw_089_module_data_in),
.io_out (sw_089_module_data_out)
);
- // [090] https://github.com/mmolteni-secpat/tinytapeout02_chi2shares
+ // [090] https://github.com/mmolteni-secpat/tinytapeout02_chi3shares
wire sw_090_clk_out, sw_090_data_out, sw_090_scan_out, sw_090_latch_out;
wire [7:0] sw_090_module_data_in;
wire [7:0] sw_090_module_data_out;
@@ -2111,12 +2111,12 @@
.module_data_out (sw_090_module_data_out)
);
- user_module_341589685194195540 user_module_341589685194195540_090 (
+ user_module_341608574336631379 user_module_341608574336631379_090 (
.io_in (sw_090_module_data_in),
.io_out (sw_090_module_data_out)
);
- // [091] https://github.com/mmolteni-secpat/tinytapeout02_chi3shares
+ // [091] https://github.com/Wren6991/tt02-whisk-serial-processor
wire sw_091_clk_out, sw_091_data_out, sw_091_scan_out, sw_091_latch_out;
wire [7:0] sw_091_module_data_in;
wire [7:0] sw_091_module_data_out;
@@ -2133,12 +2133,12 @@
.module_data_out (sw_091_module_data_out)
);
- user_module_341608574336631379 user_module_341608574336631379_091 (
+ wren6991_whisk_tt2_io_wrapper wren6991_whisk_tt2_io_wrapper_091 (
.io_in (sw_091_module_data_in),
.io_out (sw_091_module_data_out)
);
- // [092] https://github.com/Wren6991/tt02-whisk-serial-processor
+ // [092] https://github.com/aiunderstand/tt02-4bit-tristate-loadable-counter
wire sw_092_clk_out, sw_092_data_out, sw_092_scan_out, sw_092_latch_out;
wire [7:0] sw_092_module_data_in;
wire [7:0] sw_092_module_data_out;
@@ -2155,12 +2155,12 @@
.module_data_out (sw_092_module_data_out)
);
- wren6991_whisk_tt2_io_wrapper wren6991_whisk_tt2_io_wrapper_092 (
+ user_module_341423712597181012 user_module_341423712597181012_092 (
.io_in (sw_092_module_data_in),
.io_out (sw_092_module_data_out)
);
- // [093] https://github.com/aiunderstand/tt02-4bit-tristate-loadable-counter
+ // [093] https://github.com/aiunderstand/tt02-async-binary-ternary-convert-compare
wire sw_093_clk_out, sw_093_data_out, sw_093_scan_out, sw_093_latch_out;
wire [7:0] sw_093_module_data_in;
wire [7:0] sw_093_module_data_out;
@@ -2177,12 +2177,12 @@
.module_data_out (sw_093_module_data_out)
);
- user_module_341423712597181012 user_module_341423712597181012_093 (
+ user_module_341277789473735250 user_module_341277789473735250_093 (
.io_in (sw_093_module_data_in),
.io_out (sw_093_module_data_out)
);
- // [094] https://github.com/aiunderstand/tt02-async-binary-ternary-convert-compare
+ // [094] https://github.com/RobertRiachi/tt02-dot-product
wire sw_094_clk_out, sw_094_data_out, sw_094_scan_out, sw_094_latch_out;
wire [7:0] sw_094_module_data_in;
wire [7:0] sw_094_module_data_out;
@@ -2199,12 +2199,12 @@
.module_data_out (sw_094_module_data_out)
);
- user_module_341277789473735250 user_module_341277789473735250_094 (
+ user_module_348787952842703444 user_module_348787952842703444_094 (
.io_in (sw_094_module_data_in),
.io_out (sw_094_module_data_out)
);
- // [095] https://github.com/RobertRiachi/tt02-dot-product
+ // [095] https://github.com/regymm/tt02-verilog-mcpi
wire sw_095_clk_out, sw_095_data_out, sw_095_scan_out, sw_095_latch_out;
wire [7:0] sw_095_module_data_in;
wire [7:0] sw_095_module_data_out;
@@ -2221,12 +2221,12 @@
.module_data_out (sw_095_module_data_out)
);
- user_module_348787952842703444 user_module_348787952842703444_095 (
+ regymm_mcpi regymm_mcpi_095 (
.io_in (sw_095_module_data_in),
.io_out (sw_095_module_data_out)
);
- // [096] https://github.com/regymm/tt02-verilog-mcpi
+ // [096] https://github.com/regymm/tt02-verilog-funnyblinky
wire sw_096_clk_out, sw_096_data_out, sw_096_scan_out, sw_096_latch_out;
wire [7:0] sw_096_module_data_in;
wire [7:0] sw_096_module_data_out;
@@ -2243,12 +2243,12 @@
.module_data_out (sw_096_module_data_out)
);
- regymm_mcpi regymm_mcpi_096 (
+ regymm_funnyblinky regymm_funnyblinky_096 (
.io_in (sw_096_module_data_in),
.io_out (sw_096_module_data_out)
);
- // [097] https://github.com/regymm/tt02-verilog-funnyblinky
+ // [097] https://github.com/adamgreig/tt02-gpa-ca-prn
wire sw_097_clk_out, sw_097_data_out, sw_097_scan_out, sw_097_latch_out;
wire [7:0] sw_097_module_data_in;
wire [7:0] sw_097_module_data_out;
@@ -2265,12 +2265,12 @@
.module_data_out (sw_097_module_data_out)
);
- regymm_funnyblinky regymm_funnyblinky_097 (
+ adamgreig_tt02_gps_ca_prn adamgreig_tt02_gps_ca_prn_097 (
.io_in (sw_097_module_data_in),
.io_out (sw_097_module_data_out)
);
- // [098] https://github.com/adamgreig/tt02-gpa-ca-prn
+ // [098] https://github.com/adamgreig/tt02-adc-dac
wire sw_098_clk_out, sw_098_data_out, sw_098_scan_out, sw_098_latch_out;
wire [7:0] sw_098_module_data_in;
wire [7:0] sw_098_module_data_out;
@@ -2287,12 +2287,12 @@
.module_data_out (sw_098_module_data_out)
);
- adamgreig_tt02_gps_ca_prn adamgreig_tt02_gps_ca_prn_098 (
+ adamgreig_tt02_adc_dac adamgreig_tt02_adc_dac_098 (
.io_in (sw_098_module_data_in),
.io_out (sw_098_module_data_out)
);
- // [099] https://github.com/adamgreig/tt02-adc-dac
+ // [099] https://github.com/jglim/tt02-bcd-hex7seg-hdl
wire sw_099_clk_out, sw_099_data_out, sw_099_scan_out, sw_099_latch_out;
wire [7:0] sw_099_module_data_in;
wire [7:0] sw_099_module_data_out;
@@ -2309,12 +2309,12 @@
.module_data_out (sw_099_module_data_out)
);
- adamgreig_tt02_adc_dac adamgreig_tt02_adc_dac_099 (
+ jglim_7seg jglim_7seg_099 (
.io_in (sw_099_module_data_in),
.io_out (sw_099_module_data_out)
);
- // [100] https://github.com/jglim/tt02-bcd-hex7seg-hdl
+ // [100] https://github.com/burtyb/tt02-srld
wire sw_100_clk_out, sw_100_data_out, sw_100_scan_out, sw_100_latch_out;
wire [7:0] sw_100_module_data_in;
wire [7:0] sw_100_module_data_out;
@@ -2331,12 +2331,12 @@
.module_data_out (sw_100_module_data_out)
);
- jglim_7seg jglim_7seg_100 (
+ user_module_349790606404354643 user_module_349790606404354643_100 (
.io_in (sw_100_module_data_in),
.io_out (sw_100_module_data_out)
);
- // [101] https://github.com/burtyb/tt02-srld
+ // [101] https://github.com/azzeloof/tt02-counter
wire sw_101_clk_out, sw_101_data_out, sw_101_scan_out, sw_101_latch_out;
wire [7:0] sw_101_module_data_in;
wire [7:0] sw_101_module_data_out;
@@ -2353,12 +2353,12 @@
.module_data_out (sw_101_module_data_out)
);
- user_module_349790606404354643 user_module_349790606404354643_101 (
+ user_module_341279123277087315 user_module_341279123277087315_101 (
.io_in (sw_101_module_data_in),
.io_out (sw_101_module_data_out)
);
- // [102] https://github.com/azzeloof/tt02-counter
+ // [102] https://github.com/shan1293/tt02-2bitCPU
wire sw_102_clk_out, sw_102_data_out, sw_102_scan_out, sw_102_latch_out;
wire [7:0] sw_102_module_data_in;
wire [7:0] sw_102_module_data_out;
@@ -2375,12 +2375,12 @@
.module_data_out (sw_102_module_data_out)
);
- user_module_341279123277087315 user_module_341279123277087315_102 (
+ shan1293_2bitalu shan1293_2bitalu_102 (
.io_in (sw_102_module_data_in),
.io_out (sw_102_module_data_out)
);
- // [103] https://github.com/shan1293/tt02-2bitCPU
+ // [103] https://github.com/Josvth/tt02-convolutional-encoder
wire sw_103_clk_out, sw_103_data_out, sw_103_scan_out, sw_103_latch_out;
wire [7:0] sw_103_module_data_in;
wire [7:0] sw_103_module_data_out;
@@ -2397,12 +2397,12 @@
.module_data_out (sw_103_module_data_out)
);
- shan1293_2bitalu shan1293_2bitalu_103 (
+ user_module_349729432862196307 user_module_349729432862196307_103 (
.io_in (sw_103_module_data_in),
.io_out (sw_103_module_data_out)
);
- // [104] https://github.com/Josvth/tt02-convolutional-encoder
+ // [104] https://github.com/gatecat/tt02-pic
wire sw_104_clk_out, sw_104_data_out, sw_104_scan_out, sw_104_latch_out;
wire [7:0] sw_104_module_data_in;
wire [7:0] sw_104_module_data_out;
@@ -2419,12 +2419,12 @@
.module_data_out (sw_104_module_data_out)
);
- user_module_349729432862196307 user_module_349729432862196307_104 (
+ tiny_kinda_pic tiny_kinda_pic_104 (
.io_in (sw_104_module_data_in),
.io_out (sw_104_module_data_out)
);
- // [105] https://github.com/TinyTapeout/tt02-test-invert
+ // [105] https://github.com/browndeer/rv8u
wire sw_105_clk_out, sw_105_data_out, sw_105_scan_out, sw_105_latch_out;
wire [7:0] sw_105_module_data_in;
wire [7:0] sw_105_module_data_out;
@@ -2441,12 +2441,12 @@
.module_data_out (sw_105_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_105 (
+ browndeer_rv8u browndeer_rv8u_105 (
.io_in (sw_105_module_data_in),
.io_out (sw_105_module_data_out)
);
- // [106] https://github.com/TinyTapeout/tt02-test-invert
+ // [106] https://github.com/Sirawit7205/tt02-2G97-2G98
wire sw_106_clk_out, sw_106_data_out, sw_106_scan_out, sw_106_latch_out;
wire [7:0] sw_106_module_data_in;
wire [7:0] sw_106_module_data_out;
@@ -2463,12 +2463,12 @@
.module_data_out (sw_106_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_106 (
+ user_module_341432030163108435 user_module_341432030163108435_106 (
.io_in (sw_106_module_data_in),
.io_out (sw_106_module_data_out)
);
- // [107] https://github.com/TinyTapeout/tt02-test-invert
+ // [107] https://github.com/gatecat/tt02-melody-gen
wire sw_107_clk_out, sw_107_data_out, sw_107_scan_out, sw_107_latch_out;
wire [7:0] sw_107_module_data_in;
wire [7:0] sw_107_module_data_out;
@@ -2485,12 +2485,12 @@
.module_data_out (sw_107_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_107 (
+ prog_melody_gen prog_melody_gen_107 (
.io_in (sw_107_module_data_in),
.io_out (sw_107_module_data_out)
);
- // [108] https://github.com/TinyTapeout/tt02-test-invert
+ // [108] https://github.com/vaishnavachath/tt02-submission-rotary-encoder-counter
wire sw_108_clk_out, sw_108_data_out, sw_108_scan_out, sw_108_latch_out;
wire [7:0] sw_108_module_data_in;
wire [7:0] sw_108_module_data_out;
@@ -2507,12 +2507,12 @@
.module_data_out (sw_108_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_108 (
+ vaishnavachath_rotary_toplevel vaishnavachath_rotary_toplevel_108 (
.io_in (sw_108_module_data_in),
.io_out (sw_108_module_data_out)
);
- // [109] https://github.com/TinyTapeout/tt02-test-invert
+ // [109] https://github.com/maehw/tt02-wokwi-wolf-goat-cabbage
wire sw_109_clk_out, sw_109_data_out, sw_109_scan_out, sw_109_latch_out;
wire [7:0] sw_109_module_data_in;
wire [7:0] sw_109_module_data_out;
@@ -2529,12 +2529,12 @@
.module_data_out (sw_109_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_109 (
+ user_module_341614346808328788 user_module_341614346808328788_109 (
.io_in (sw_109_module_data_in),
.io_out (sw_109_module_data_out)
);
- // [110] https://github.com/TinyTapeout/tt02-test-invert
+ // [110] https://github.com/maehw/tt02-wokwi-lowspeed-tiny-uart
wire sw_110_clk_out, sw_110_data_out, sw_110_scan_out, sw_110_latch_out;
wire [7:0] sw_110_module_data_in;
wire [7:0] sw_110_module_data_out;
@@ -2551,12 +2551,12 @@
.module_data_out (sw_110_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_110 (
+ user_module_341631511790879314 user_module_341631511790879314_110 (
.io_in (sw_110_module_data_in),
.io_out (sw_110_module_data_out)
);
- // [111] https://github.com/TinyTapeout/tt02-test-invert
+ // [111] https://github.com/wimdams/tt02-rotary-encoder
wire sw_111_clk_out, sw_111_data_out, sw_111_scan_out, sw_111_latch_out;
wire [7:0] sw_111_module_data_in;
wire [7:0] sw_111_module_data_out;
@@ -2573,12 +2573,12 @@
.module_data_out (sw_111_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_111 (
+ rotary_encoder rotary_encoder_111 (
.io_in (sw_111_module_data_in),
.io_out (sw_111_module_data_out)
);
- // [112] https://github.com/TinyTapeout/tt02-test-invert
+ // [112] https://github.com/ChrisPVille/tt02-FROG4bitCPU
wire sw_112_clk_out, sw_112_data_out, sw_112_scan_out, sw_112_latch_out;
wire [7:0] sw_112_module_data_in;
wire [7:0] sw_112_module_data_out;
@@ -2595,12 +2595,12 @@
.module_data_out (sw_112_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_112 (
+ frog frog_112 (
.io_in (sw_112_module_data_in),
.io_out (sw_112_module_data_out)
);
- // [113] https://github.com/TinyTapeout/tt02-test-invert
+ // [113] https://github.com/swalense/tt02-graycode_counter
wire sw_113_clk_out, sw_113_data_out, sw_113_scan_out, sw_113_latch_out;
wire [7:0] sw_113_module_data_in;
wire [7:0] sw_113_module_data_out;
@@ -2617,12 +2617,12 @@
.module_data_out (sw_113_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_113 (
+ swalense_top swalense_top_113 (
.io_in (sw_113_module_data_in),
.io_out (sw_113_module_data_out)
);
- // [114] https://github.com/TinyTapeout/tt02-test-invert
+ // [114] https://github.com/Luthor2k/tt02-baudot
wire sw_114_clk_out, sw_114_data_out, sw_114_scan_out, sw_114_latch_out;
wire [7:0] sw_114_module_data_in;
wire [7:0] sw_114_module_data_out;
@@ -2639,12 +2639,12 @@
.module_data_out (sw_114_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_114 (
+ luthor2k_top_tto luthor2k_top_tto_114 (
.io_in (sw_114_module_data_in),
.io_out (sw_114_module_data_out)
);
- // [115] https://github.com/TinyTapeout/tt02-test-invert
+ // [115] https://github.com/ctag/tt02-submission-ctag
wire sw_115_clk_out, sw_115_data_out, sw_115_scan_out, sw_115_latch_out;
wire [7:0] sw_115_module_data_in;
wire [7:0] sw_115_module_data_out;
@@ -2661,12 +2661,12 @@
.module_data_out (sw_115_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_115 (
+ user_module_349886696875098706 user_module_349886696875098706_115 (
.io_in (sw_115_module_data_in),
.io_out (sw_115_module_data_out)
);
- // [116] https://github.com/TinyTapeout/tt02-test-invert
+ // [116] https://github.com/AsmaMohsin1507/tt02-channel-coding
wire sw_116_clk_out, sw_116_data_out, sw_116_scan_out, sw_116_latch_out;
wire [7:0] sw_116_module_data_in;
wire [7:0] sw_116_module_data_out;
@@ -2683,12 +2683,12 @@
.module_data_out (sw_116_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_116 (
+ Asma_Mohsin_conv_enc_core Asma_Mohsin_conv_enc_core_116 (
.io_in (sw_116_module_data_in),
.io_out (sw_116_module_data_out)
);
- // [117] https://github.com/TinyTapeout/tt02-test-invert
+ // [117] https://github.com/stevenmburns/tt02-scannable-gcd
wire sw_117_clk_out, sw_117_data_out, sw_117_scan_out, sw_117_latch_out;
wire [7:0] sw_117_module_data_in;
wire [7:0] sw_117_module_data_out;
@@ -2705,12 +2705,12 @@
.module_data_out (sw_117_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_117 (
+ stevenmburns_toplevel stevenmburns_toplevel_117 (
.io_in (sw_117_module_data_in),
.io_out (sw_117_module_data_out)
);
- // [118] https://github.com/TinyTapeout/tt02-test-invert
+ // [118] https://github.com/cy384/tt02-submission-template
wire sw_118_clk_out, sw_118_data_out, sw_118_scan_out, sw_118_latch_out;
wire [7:0] sw_118_module_data_in;
wire [7:0] sw_118_module_data_out;
@@ -2727,12 +2727,12 @@
.module_data_out (sw_118_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_118 (
+ user_module_341546888233747026 user_module_341546888233747026_118 (
.io_in (sw_118_module_data_in),
.io_out (sw_118_module_data_out)
);
- // [119] https://github.com/TinyTapeout/tt02-test-invert
+ // [119] https://github.com/rglenn/tt02-rglenn-hex-to-7-seg
wire sw_119_clk_out, sw_119_data_out, sw_119_scan_out, sw_119_latch_out;
wire [7:0] sw_119_module_data_in;
wire [7:0] sw_119_module_data_out;
@@ -2749,12 +2749,12 @@
.module_data_out (sw_119_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_119 (
+ rglenn_hex_to_7_seg rglenn_hex_to_7_seg_119 (
.io_in (sw_119_module_data_in),
.io_out (sw_119_module_data_out)
);
- // [120] https://github.com/TinyTapeout/tt02-test-invert
+ // [120] https://github.com/zymason/tt02-zymason
wire sw_120_clk_out, sw_120_data_out, sw_120_scan_out, sw_120_latch_out;
wire [7:0] sw_120_module_data_in;
wire [7:0] sw_120_module_data_out;
@@ -2771,12 +2771,12 @@
.module_data_out (sw_120_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_120 (
+ zymason_tinytop zymason_tinytop_120 (
.io_in (sw_120_module_data_in),
.io_out (sw_120_module_data_out)
);
- // [121] https://github.com/TinyTapeout/tt02-test-invert
+ // [121] https://github.com/DaveyPocket/chaser_tt2
wire sw_121_clk_out, sw_121_data_out, sw_121_scan_out, sw_121_latch_out;
wire [7:0] sw_121_module_data_in;
wire [7:0] sw_121_module_data_out;
@@ -2793,12 +2793,12 @@
.module_data_out (sw_121_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_121 (
+ user_module_341178481588044372 user_module_341178481588044372_121 (
.io_in (sw_121_module_data_in),
.io_out (sw_121_module_data_out)
);
- // [122] https://github.com/TinyTapeout/tt02-test-invert
+ // [122] https://github.com/klei22/Rolling-Average
wire sw_122_clk_out, sw_122_data_out, sw_122_scan_out, sw_122_latch_out;
wire [7:0] sw_122_module_data_in;
wire [7:0] sw_122_module_data_out;
@@ -2815,12 +2815,12 @@
.module_data_out (sw_122_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_122 (
+ klei22_ra klei22_ra_122 (
.io_in (sw_122_module_data_in),
.io_out (sw_122_module_data_out)
);
- // [123] https://github.com/TinyTapeout/tt02-test-invert
+ // [123] https://github.com/andars/tt02-universal-turing-machine-w5s8
wire sw_123_clk_out, sw_123_data_out, sw_123_scan_out, sw_123_latch_out;
wire [7:0] sw_123_module_data_in;
wire [7:0] sw_123_module_data_out;
@@ -2837,7 +2837,7 @@
.module_data_out (sw_123_module_data_out)
);
- user_module_341535056611770964 user_module_341535056611770964_123 (
+ afoote_w5s8_tt02_top afoote_w5s8_tt02_top_123 (
.io_in (sw_123_module_data_in),
.io_out (sw_123_module_data_out)
);