verilog/rtl/100_adc_dac.v

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module adamgreig_tt02_adc_dac(io_in, io_out);
  reg \$auto$verilog_backend.cc:2083:dump_module$1  = 0;
  wire adc_comp;
  wire [11:0] adc_data;
  wire adc_out;
  wire [11:0] adc_uart_data;
  wire adc_uart_ready;
  wire adc_uart_tx_o;
  wire adc_uart_valid;
  wire clk;
  wire [7:0] dac_data;
  wire dac_out;
  wire [7:0] dac_uart_data;
  wire dac_uart_rx_i;
  input [7:0] io_in;
  wire [7:0] io_in;
  output [7:0] io_out;
  wire [7:0] io_out;
  reg [9:0] ready_sr = 10'h000;
  reg [9:0] \ready_sr$next ;
  wire rst;
  always @(posedge clk)
    ready_sr <= \ready_sr$next ;
  adc adc (
    .clk(clk),
    .comp(adc_comp),
    .data(adc_data),
    .out(adc_out),
    .rst(rst)
  );
  adc_uart adc_uart (
    .clk(clk),
    .data(adc_uart_data),
    .ready(adc_uart_ready),
    .rst(rst),
    .tx_o(adc_uart_tx_o),
    .valid(adc_uart_valid)
  );
  \dac$1  dac (
    .clk(clk),
    .data(dac_data),
    .out(dac_out),
    .rst(rst)
  );
  dac_uart dac_uart (
    .clk(clk),
    .data(dac_uart_data),
    .rst(rst),
    .rx_i(dac_uart_rx_i)
  );
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
    \ready_sr$next  = { ready_sr[8:0], adc_uart_ready };
    casez (rst)
      1'h1:
          \ready_sr$next  = 10'h000;
    endcase
  end
  assign dac_uart_rx_i = io_in[3];
  assign dac_data = dac_uart_data;
  assign adc_uart_valid = ready_sr[9];
  assign adc_uart_data = adc_data;
  assign io_out[2] = dac_out;
  assign io_out[1] = adc_uart_tx_o;
  assign io_out[0] = adc_out;
  assign io_out[7:3] = 5'h00;
  assign adc_comp = io_in[2];
  assign rst = io_in[1];
  assign clk = io_in[0];
endmodule

module adc(rst, comp, out, data, clk);
  reg \$auto$verilog_backend.cc:2083:dump_module$2  = 0;
  wire [12:0] \$1 ;
  wire [12:0] \$2 ;
  wire [12:0] \$4 ;
  wire [12:0] \$5 ;
  input clk;
  wire clk;
  input comp;
  wire comp;
  wire [11:0] dac_data;
  wire dac_out;
  output [11:0] data;
  reg [11:0] data = 12'h000;
  reg [11:0] \data$next ;
  output out;
  wire out;
  input rst;
  wire rst;
  assign \$2  = data - 1'h1;
  assign \$5  = data + 1'h1;
  always @(posedge clk)
    data <= \data$next ;
  dac dac (
    .clk(clk),
    .data(dac_data),
    .out(dac_out),
    .rst(rst)
  );
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
    (* full_case = 32'd1 *)
    casez (comp)
      1'h1:
          \data$next  = \$2 [11:0];
      default:
          \data$next  = \$5 [11:0];
    endcase
    casez (rst)
      1'h1:
          \data$next  = 12'h000;
    endcase
  end
  assign \$1  = \$2 ;
  assign \$4  = \$5 ;
  assign dac_data = data;
  assign out = dac_out;
endmodule

module adc_uart(rst, tx_o, data, ready, valid, clk);
  reg \$auto$verilog_backend.cc:2083:dump_module$3  = 0;
  wire \$1 ;
  wire [8:0] \$10 ;
  wire [7:0] \$3 ;
  wire [6:0] \$4 ;
  wire [8:0] \$7 ;
  wire [7:0] \$8 ;
  input clk;
  wire clk;
  input [11:0] data;
  wire [11:0] data;
  reg [11:0] data_reg = 12'h000;
  reg [11:0] \data_reg$next ;
  reg [2:0] fsm_state = 3'h0;
  reg [2:0] \fsm_state$next ;
  reg [3:0] nibble;
  output ready;
  reg ready;
  input rst;
  wire rst;
  output tx_o;
  wire tx_o;
  reg [7:0] uart_data;
  wire uart_ready;
  wire uart_tx_o;
  reg uart_valid;
  input valid;
  wire valid;
  assign \$10  = \$8  - 4'ha;
  always @(posedge clk)
    data_reg <= \data_reg$next ;
  always @(posedge clk)
    fsm_state <= \fsm_state$next ;
  assign \$1  = nibble < 4'ha;
  assign \$4  = nibble + 6'h30;
  assign \$3  = + \$4 ;
  assign \$8  = nibble + 7'h41;
  uart uart (
    .clk(clk),
    .data(uart_data),
    .ready(uart_ready),
    .rst(rst),
    .tx_o(uart_tx_o),
    .valid(uart_valid)
  );
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
    (* full_case = 32'd1 *)
    casez (\$1 )
      1'h1:
          uart_data = \$3 ;
      default:
          uart_data = \$10 [7:0];
    endcase
    casez (fsm_state)
      3'h0:
          /* empty */;
      3'h1:
          /* empty */;
      3'h2:
          /* empty */;
      3'h3:
          /* empty */;
      3'h4:
          uart_data = 8'h0a;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
    ready = 1'h0;
    casez (fsm_state)
      3'h0:
          ready = uart_ready;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
    \data_reg$next  = data_reg;
    casez (fsm_state)
      3'h0:
          \data_reg$next  = data;
    endcase
    casez (rst)
      1'h1:
          \data_reg$next  = 12'h000;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
    \fsm_state$next  = fsm_state;
    casez (fsm_state)
      3'h0:
          casez (valid)
            1'h1:
                \fsm_state$next  = 3'h1;
          endcase
      3'h1:
          casez (uart_ready)
            1'h1:
                \fsm_state$next  = 3'h2;
          endcase
      3'h2:
          casez (uart_ready)
            1'h1:
                \fsm_state$next  = 3'h3;
          endcase
      3'h3:
          casez (uart_ready)
            1'h1:
                \fsm_state$next  = 3'h4;
          endcase
      3'h4:
          casez (uart_ready)
            1'h1:
                \fsm_state$next  = 3'h0;
          endcase
    endcase
    casez (rst)
      1'h1:
          \fsm_state$next  = 3'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
    nibble = 4'h0;
    casez (fsm_state)
      3'h0:
          /* empty */;
      3'h1:
          nibble = data_reg[11:8];
      3'h2:
          nibble = data_reg[7:4];
      3'h3:
          nibble = data_reg[3:0];
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
    uart_valid = 1'h0;
    casez (fsm_state)
      3'h0:
          /* empty */;
      3'h1:
          uart_valid = 1'h1;
      3'h2:
          uart_valid = 1'h1;
      3'h3:
          uart_valid = 1'h1;
      3'h4:
          uart_valid = 1'h1;
    endcase
  end
  assign \$7  = \$10 ;
  assign tx_o = uart_tx_o;
endmodule

module dac(rst, out, data, clk);
  reg \$auto$verilog_backend.cc:2083:dump_module$4  = 0;
  wire [12:0] \$1 ;
  reg [12:0] acc = 13'h0000;
  reg [12:0] \acc$next ;
  input clk;
  wire clk;
  input [11:0] data;
  wire [11:0] data;
  output out;
  wire out;
  input rst;
  wire rst;
  assign \$1  = acc[11:0] + data;
  always @(posedge clk)
    acc <= \acc$next ;
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$4 ) begin end
    \acc$next  = \$1 ;
    casez (rst)
      1'h1:
          \acc$next  = 13'h0000;
    endcase
  end
  assign out = acc[12];
endmodule

module \dac$1 (rst, out, data, clk);
  reg \$auto$verilog_backend.cc:2083:dump_module$5  = 0;
  wire [8:0] \$1 ;
  reg [8:0] acc = 9'h000;
  reg [8:0] \acc$next ;
  input clk;
  wire clk;
  input [7:0] data;
  wire [7:0] data;
  output out;
  wire out;
  input rst;
  wire rst;
  assign \$1  = acc[7:0] + data;
  always @(posedge clk)
    acc <= \acc$next ;
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$5 ) begin end
    \acc$next  = \$1 ;
    casez (rst)
      1'h1:
          \acc$next  = 9'h000;
    endcase
  end
  assign out = acc[8];
endmodule

module dac_uart(rst, data, rx_i, clk);
  reg \$auto$verilog_backend.cc:2083:dump_module$6  = 0;
  wire \$1 ;
  wire \$10 ;
  wire [4:0] \$12 ;
  wire [4:0] \$13 ;
  wire \$15 ;
  wire \$17 ;
  wire \$19 ;
  wire \$21 ;
  wire \$23 ;
  wire \$25 ;
  wire \$27 ;
  wire [4:0] \$3 ;
  wire [4:0] \$4 ;
  wire \$6 ;
  wire \$8 ;
  reg [3:0] bit_idx = 4'h0;
  reg [3:0] \bit_idx$next ;
  input clk;
  wire clk;
  reg [3:0] ctr = 4'h0;
  reg [3:0] \ctr$next ;
  output [7:0] data;
  reg [7:0] data = 8'h00;
  reg [7:0] \data$next ;
  reg fsm_state = 1'h0;
  reg \fsm_state$next ;
  input rst;
  wire rst;
  input rx_i;
  wire rx_i;
  reg [7:0] sr = 8'h00;
  reg [7:0] \sr$next ;
  reg valid = 1'h0;
  reg \valid$next ;
  assign \$10  = ~ rx_i;
  assign \$13  = ctr - 1'h1;
  assign \$15  = ! ctr;
  assign \$17  = ~ rx_i;
  assign \$1  = ! ctr;
  assign \$19  = ! ctr;
  assign \$21  = bit_idx == 4'h8;
  assign \$23  = ! ctr;
  assign \$25  = ! ctr;
  assign \$27  = bit_idx == 4'h8;
  always @(posedge clk)
    bit_idx <= \bit_idx$next ;
  always @(posedge clk)
    valid <= \valid$next ;
  always @(posedge clk)
    ctr <= \ctr$next ;
  always @(posedge clk)
    fsm_state <= \fsm_state$next ;
  always @(posedge clk)
    sr <= \sr$next ;
  always @(posedge clk)
    data <= \data$next ;
  assign \$4  = bit_idx + 1'h1;
  assign \$6  = ! ctr;
  assign \$8  = bit_idx == 4'h8;
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$6 ) begin end
    \bit_idx$next  = bit_idx;
    (* full_case = 32'd1 *)
    casez (fsm_state)
      1'h0:
          \bit_idx$next  = 4'h0;
      1'h1:
          casez (\$1 )
            1'h1:
                \bit_idx$next  = \$4 [3:0];
          endcase
    endcase
    casez (rst)
      1'h1:
          \bit_idx$next  = 4'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$6 ) begin end
    \valid$next  = valid;
    (* full_case = 32'd1 *)
    casez (fsm_state)
      1'h0:
          \valid$next  = 1'h0;
      1'h1:
          casez (\$6 )
            1'h1:
                casez (\$8 )
                  1'h1:
                      \valid$next  = 1'h1;
                endcase
          endcase
    endcase
    casez (rst)
      1'h1:
          \valid$next  = 1'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$6 ) begin end
    \ctr$next  = ctr;
    (* full_case = 32'd1 *)
    casez (fsm_state)
      1'h0:
          casez (\$10 )
            1'h1:
                \ctr$next  = 4'he;
          endcase
      1'h1:
        begin
          \ctr$next  = \$13 [3:0];
          casez (\$15 )
            1'h1:
                \ctr$next  = 4'h9;
          endcase
        end
    endcase
    casez (rst)
      1'h1:
          \ctr$next  = 4'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$6 ) begin end
    \fsm_state$next  = fsm_state;
    (* full_case = 32'd1 *)
    casez (fsm_state)
      1'h0:
          casez (\$17 )
            1'h1:
                \fsm_state$next  = 1'h1;
          endcase
      1'h1:
          casez (\$19 )
            1'h1:
                casez (\$21 )
                  1'h1:
                      \fsm_state$next  = 1'h0;
                endcase
          endcase
    endcase
    casez (rst)
      1'h1:
          \fsm_state$next  = 1'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$6 ) begin end
    \sr$next  = sr;
    (* full_case = 32'd1 *)
    casez (fsm_state)
      1'h0:
          /* empty */;
      1'h1:
          casez (\$23 )
            1'h1:
                \sr$next  = { rx_i, sr[7:1] };
          endcase
    endcase
    casez (rst)
      1'h1:
          \sr$next  = 8'h00;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$6 ) begin end
    \data$next  = data;
    (* full_case = 32'd1 *)
    casez (fsm_state)
      1'h0:
          /* empty */;
      1'h1:
          casez (\$25 )
            1'h1:
                casez (\$27 )
                  1'h1:
                      \data$next  = sr;
                endcase
          endcase
    endcase
    casez (rst)
      1'h1:
          \data$next  = 8'h00;
    endcase
  end
  assign \$3  = \$4 ;
  assign \$12  = \$13 ;
endmodule

module uart(rst, tx_o, data, ready, valid, clk);
  reg \$auto$verilog_backend.cc:2083:dump_module$7  = 0;
  wire \$1 ;
  wire \$3 ;
  wire \$5 ;
  wire [4:0] \$7 ;
  wire [4:0] \$8 ;
  input clk;
  wire clk;
  input [7:0] data;
  wire [7:0] data;
  output ready;
  reg ready;
  input rst;
  wire rst;
  reg [3:0] tx_cnt = 4'h0;
  reg [3:0] \tx_cnt$next ;
  output tx_o;
  wire tx_o;
  reg [9:0] tx_reg = 10'h001;
  reg [9:0] \tx_reg$next ;
  input valid;
  wire valid;
  always @(posedge clk)
    tx_reg <= \tx_reg$next ;
  always @(posedge clk)
    tx_cnt <= \tx_cnt$next ;
  assign \$1  = ! tx_cnt;
  assign \$3  = ! tx_cnt;
  assign \$5  = ! tx_cnt;
  assign \$8  = tx_cnt - 1'h1;
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$7 ) begin end
    (* full_case = 32'd1 *)
    casez (\$1 )
      1'h1:
          ready = 1'h1;
      default:
          ready = 1'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$7 ) begin end
    \tx_reg$next  = tx_reg;
    (* full_case = 32'd1 *)
    casez (\$3 )
      1'h1:
          casez (valid)
            1'h1:
                \tx_reg$next  = { 1'h1, data, 1'h0 };
          endcase
      default:
          \tx_reg$next  = { 1'h1, tx_reg[9:1] };
    endcase
    casez (rst)
      1'h1:
          \tx_reg$next  = 10'h001;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$7 ) begin end
    \tx_cnt$next  = tx_cnt;
    (* full_case = 32'd1 *)
    casez (\$5 )
      1'h1:
          casez (valid)
            1'h1:
                \tx_cnt$next  = 4'ha;
          endcase
      default:
          \tx_cnt$next  = \$8 [3:0];
    endcase
    casez (rst)
      1'h1:
          \tx_cnt$next  = 4'h0;
    endcase
  end
  assign \$7  = \$8 ;
  assign tx_o = tx_reg[0];
endmodule