| /****************************************************************************** |
| ** Logisim-evolution goes FPGA automatic generated Verilog code ** |
| ** https://github.com/logisim-evolution/ ** |
| ** ** |
| ** Component : eq_0 ** |
| ** ** |
| *****************************************************************************/ |
| |
| module eq_0( D0, |
| D1, |
| D2, |
| D3, |
| is_zero ); |
| |
| /******************************************************************************* |
| ** The inputs are defined here ** |
| *******************************************************************************/ |
| input D0; |
| input D1; |
| input D2; |
| input D3; |
| |
| /******************************************************************************* |
| ** The outputs are defined here ** |
| *******************************************************************************/ |
| output is_zero; |
| |
| /******************************************************************************* |
| ** The wires are defined here ** |
| *******************************************************************************/ |
| wire s_logisimNet0; |
| wire s_logisimNet1; |
| wire s_logisimNet2; |
| wire s_logisimNet3; |
| wire s_logisimNet4; |
| wire s_logisimNet5; |
| wire s_logisimNet6; |
| |
| /******************************************************************************* |
| ** The module functionality is described here ** |
| *******************************************************************************/ |
| |
| /******************************************************************************* |
| ** Here all input connections are defined ** |
| *******************************************************************************/ |
| assign s_logisimNet1 = D0; |
| assign s_logisimNet2 = D1; |
| assign s_logisimNet3 = D2; |
| assign s_logisimNet4 = D3; |
| |
| /******************************************************************************* |
| ** Here all output connections are defined ** |
| *******************************************************************************/ |
| assign is_zero = s_logisimNet6; |
| |
| /******************************************************************************* |
| ** Here all normal components are defined ** |
| *******************************************************************************/ |
| OR_GATE #(.BubblesMask(2'b00)) |
| GATES_1 (.input1(s_logisimNet1), |
| .input2(s_logisimNet2), |
| .result(s_logisimNet0)); |
| |
| OR_GATE #(.BubblesMask(2'b00)) |
| GATES_2 (.input1(s_logisimNet3), |
| .input2(s_logisimNet4), |
| .result(s_logisimNet5)); |
| |
| NOR_GATE #(.BubblesMask(2'b00)) |
| GATES_3 (.input1(s_logisimNet0), |
| .input2(s_logisimNet5), |
| .result(s_logisimNet6)); |
| |
| |
| endmodule |