blob: 48ac45686bf7de07a8c792bf79d770dd1e4f8a34 [file] [log] [blame]
module top(
input wire [7:0] io_in,
output wire [7:0] io_out
);
wire rdy = 1;
wire vld;
user_module counter0(io_in[0], io_in[1], rdy, io_out, vld);
endmodule