add scanchain config to the repo
diff --git a/openlane/scan_controller/config.tcl b/openlane/scan_controller/config.tcl
index 24a2d50..8a4a09a 100644
--- a/openlane/scan_controller/config.tcl
+++ b/openlane/scan_controller/config.tcl
@@ -8,7 +8,7 @@
set ::env(RUN_KLAYOUT_XOR) 0
set ::env(RUN_KLAYOUT_DRC) 0
-# add your source files here
+# caravel defines for number of IO, needed for internal drives of oen_b
set ::env(VERILOG_FILES) "\
$script_dir/../../caravel/verilog/rtl/defines.v \
$script_dir/../../verilog/rtl/scan_controller/scan_controller.v"
@@ -27,7 +27,7 @@
set ::env(SYNTH_PARAMETERS) "NUM_DESIGNS=250"
-# clock period is ns - 100MHz
+# clock period is ns - 200MHz
set ::env(CLOCK_PERIOD) "5"
set ::env(CLOCK_PORT) "clk"
diff --git a/openlane/scanchain/base.sdc b/openlane/scanchain/base.sdc
new file mode 100644
index 0000000..eadeece
--- /dev/null
+++ b/openlane/scanchain/base.sdc
@@ -0,0 +1,39 @@
+# Create a clock for the scan chain @ 200 MHz
+create_clock -name clk_scan_in -period 5 [get_ports {clk_in}]
+create_generated_clock -name clk_scan_out -source clk_in -combinational [get_ports {clk_out}]
+
+# Scan chain input 0.5 ns setup time, 0.5 ns hold time
+set_input_delay -min 0.5 -clock [get_clocks clk_scan_in] [get_ports {data_in}]
+set_input_delay -max 0.5 -clock [get_clocks clk_scan_in] [get_ports {data_in}]
+
+# Scan chain output 1.5 ns setup time, 1.5 ns hold time
+set_output_delay -min -1.5 -clock [get_clocks clk_scan_out] [get_ports {data_out}]
+set_output_delay -max 1.5 -clock [get_clocks clk_scan_out] [get_ports {data_out}]
+
+# Misc
+set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
+
+if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL)] } {
+ set ::env(SYNTH_CLK_DRIVING_CELL) $::env(SYNTH_DRIVING_CELL)
+}
+
+if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL_PIN)] } {
+ set ::env(SYNTH_CLK_DRIVING_CELL_PIN) $::env(SYNTH_DRIVING_CELL_PIN)
+}
+
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [get_ports {data_in scan_select_in latch_enable_in}]
+set_driving_cell -lib_cell $::env(SYNTH_CLK_DRIVING_CELL) -pin $::env(SYNTH_CLK_DRIVING_CELL_PIN) [get_ports {clk_in}]
+
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
+
+puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINITY)"
+set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {clk_sys clk_scan_in clk_scan_out}]
+
+puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
+set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {clk_sys clk_scan_in clk_scan_out}]
+
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 100}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
diff --git a/openlane/scanchain/config.tcl b/openlane/scanchain/config.tcl
new file mode 100644
index 0000000..64df2c5
--- /dev/null
+++ b/openlane/scanchain/config.tcl
@@ -0,0 +1,57 @@
+# User config
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) scanchain
+
+# save some time
+set ::env(RUN_KLAYOUT_XOR) 0
+set ::env(RUN_KLAYOUT_DRC) 0
+
+# don't put clock buffers on the outputs
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
+
+# allow use of specific sky130 cells
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+
+# read all verilog files
+set ::env(VERILOG_FILES) "$script_dir/../../verilog/rtl/scanchain/scanchain.v"
+
+# put all the io pins on the right, and scan chain on the left
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+# reduce wasted space
+set ::env(TOP_MARGIN_MULT) 2
+set ::env(BOTTOM_MARGIN_MULT) 2
+
+# absolute die size
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 30 120"
+set ::env(FP_CORE_UTIL) 45
+set ::env(PL_BASIC_PLACEMENT) {1}
+
+set ::env(FP_IO_HLENGTH) 2
+
+# use alternative efabless decap cells to solve LI density issue
+set ::env(DECAP_CELL) "\
+ sky130_fd_sc_hd__decap_3 \
+ sky130_fd_sc_hd__decap_4 \
+ sky130_fd_sc_hd__decap_6 \
+ sky130_fd_sc_hd__decap_8 \
+ sky130_ef_sc_hd__decap_12"
+
+# clock
+set ::env(CLOCK_PERIOD) "5"
+set ::env(CLOCK_PORT) ""
+
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+
+set ::env(SYNTH_CLOCK_UNCERTAINITY) 0.20
+set ::env(SYNTH_CLOCK_TRANSITION) 0.15
+
+# don't use power rings or met5
+set ::env(DESIGN_IS_CORE) 0
+set ::env(RT_MAX_LAYER) {met4}
+
+# connect to first digital rails
+set ::env(VDD_NETS) [list {vccd1}]
+set ::env(GND_NETS) [list {vssd1}]
diff --git a/openlane/scanchain/pin_order.cfg b/openlane/scanchain/pin_order.cfg
new file mode 100644
index 0000000..1a75f54
--- /dev/null
+++ b/openlane/scanchain/pin_order.cfg
@@ -0,0 +1,17 @@
+#N
+
+#S
+
+#E
+module_data_in.*
+module_data_out.*
+
+#W
+clk_in
+data_in
+scan_select_in
+latch_enable_in
+latch_enable_out
+scan_select_out
+data_out
+clk_out
