| -v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v |
| -v $(USER_PROJECT_VERILOG)/rtl/scan_controller/scan_controller.v |
| -v $(USER_PROJECT_VERILOG)/rtl/scanchain/scanchain.v |
| -v $(USER_PROJECT_VERILOG)/rtl/cells.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_341535056611770964.v |
| -v $(USER_PROJECT_VERILOG)/rtl/001_simon.v |
| -v $(USER_PROJECT_VERILOG)/rtl/002_tomkeddie_top_tto.v |
| -v $(USER_PROJECT_VERILOG)/rtl/003_matrix.v |
| -v $(USER_PROJECT_VERILOG)/rtl/004_sequencer.v |
| -v $(USER_PROJECT_VERILOG)/rtl/005_top.v |
| -v $(USER_PROJECT_VERILOG)/rtl/006_s4ga.v |
| -v $(USER_PROJECT_VERILOG)/rtl/007_alu_top.v |
| -v $(USER_PROJECT_VERILOG)/rtl/008_mccoy.v |
| -v $(USER_PROJECT_VERILOG)/rtl/009_binary_clock.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_347787021138264660.v |
| -v $(USER_PROJECT_VERILOG)/rtl/011_sram_top.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_347690870424732244.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_347592305412145748.v |
| -v $(USER_PROJECT_VERILOG)/rtl/014_logisimTopLevelShell.v |
| -v $(USER_PROJECT_VERILOG)/rtl/015_tiny_fft.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_346553315158393428.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_347894637149553236.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_346916357828248146.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_347594509754827347.v |
| -v $(USER_PROJECT_VERILOG)/rtl/020_top.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_347688030570545747.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_342981109408072274.v |
| -v $(USER_PROJECT_VERILOG)/rtl/023_asic_multiplier_wrapper.v |
| -v $(USER_PROJECT_VERILOG)/rtl/024_logisimTopLevelShell.v |
| -v $(USER_PROJECT_VERILOG)/rtl/025_tomkeddie_top_tto_a.v |
| -v $(USER_PROJECT_VERILOG)/rtl/026_ledmatrix.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_348195845106041428.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_348121131386929746.v |
| -v $(USER_PROJECT_VERILOG)/rtl/029_yubex_egg_timer.v |
| -v $(USER_PROJECT_VERILOG)/rtl/030_potato1.v |
| -v $(USER_PROJECT_VERILOG)/rtl/031_zoechip.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_348255968419643987.v |
| -v $(USER_PROJECT_VERILOG)/rtl/033_mbikovitsky_top.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_348260124451668562.v |
| -v $(USER_PROJECT_VERILOG)/rtl/035_top.v |
| -v $(USER_PROJECT_VERILOG)/rtl/036_illegal_logic.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_348242239268323922.v |
| -v $(USER_PROJECT_VERILOG)/rtl/038_wrapper.v |
| -v $(USER_PROJECT_VERILOG)/rtl/039_moyes0.v |
| -v $(USER_PROJECT_VERILOG)/rtl/040_yupferris_bitslam.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_341620484740219475.v |
| -v $(USER_PROJECT_VERILOG)/rtl/042_top.v |
| -v $(USER_PROJECT_VERILOG)/rtl/043_rc5_top.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_341614374571475540.v |
| -v $(USER_PROJECT_VERILOG)/rtl/045_player.v |
| -v $(USER_PROJECT_VERILOG)/rtl/046_counter.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_341541108650607187.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_341516949939814994.v |
| -v $(USER_PROJECT_VERILOG)/rtl/049_logisimTopLevelShell.v |
| -v $(USER_PROJECT_VERILOG)/rtl/050_logisimTopLevelShell.v |
| -v $(USER_PROJECT_VERILOG)/rtl/051_top.v |
| -v $(USER_PROJECT_VERILOG)/rtl/052_counter.v |
| -v $(USER_PROJECT_VERILOG)/rtl/053_counter.v |
| -v $(USER_PROJECT_VERILOG)/rtl/054_player.v |
| -v $(USER_PROJECT_VERILOG)/rtl/055_jleightcap_top.v |
| -v $(USER_PROJECT_VERILOG)/rtl/056_toplevel.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_347619669052490324.v |
| -v $(USER_PROJECT_VERILOG)/rtl/058_pwm.v |
| -v $(USER_PROJECT_VERILOG)/rtl/059_user_module_nickoe.v |
| -v $(USER_PROJECT_VERILOG)/rtl/060_fp8.v |
| -v $(USER_PROJECT_VERILOG)/rtl/061_toplevel.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_348953272198890067.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_348961139276644947.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_348540666182107731.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_341490465660469844.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_349047610915422802.v |
| -v $(USER_PROJECT_VERILOG)/rtl/067_sqrt.v |
| -v $(USER_PROJECT_VERILOG)/rtl/068_pwm_gen.v |
| -v $(USER_PROJECT_VERILOG)/rtl/069_user_module_341164910646919762.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_341609034095264340.v |
| -v $(USER_PROJECT_VERILOG)/rtl/071_navray_top.sv |
| -v $(USER_PROJECT_VERILOG)/rtl/user_module_349011320806310484.v |
| -v $(USER_PROJECT_VERILOG)/rtl/073_pwm.v |
| -v $(USER_PROJECT_VERILOG)/rtl/074_hex_sr.v |