update design number to 250
diff --git a/INFO.md b/INFO.md
index 296b0be..d488ae4 100644
--- a/INFO.md
+++ b/INFO.md
@@ -2,7 +2,7 @@
## Scan chain
-All 498 designs are joined together in a long chain similiar to JTAG. We provide the inputs and outputs of that chain (see pinout below) externally, to the Caravel logic analyser, and to an internal scan chain driver.
+All 250 designs are joined together in a long chain similiar to JTAG. We provide the inputs and outputs of that chain (see pinout below) externally, to the Caravel logic analyser, and to an internal scan chain driver.
The default is to use an external driver, this is in case anything goes wrong with the Caravel logic analyser or the internal driver.
@@ -44,10 +44,10 @@
* 100MHz input clock
* 8 ins & 8 outs
* 2 clock cycles to push one bit through the scan chain (scan clock is half input clock rate)
-* 500 designs
+* 250 designs
* scan controller can do a read/write cycle in one refresh
-So the max refresh rate is 100MHz / (8 * 2 * 500) = 12500Hz.
+So the max refresh rate is 100MHz / (8 * 2 * 250) = 25000Hz.
## Clock divider
diff --git a/README.md b/README.md
index df468b5..c57acc9 100644
--- a/README.md
+++ b/README.md
@@ -123,3 +123,7 @@
| 98 | Adam Greig | GPS C/A PRN Generator | HDL | https://github.com/adamgreig/tt02-gpa-ca-prn |
| 99 | Adam Greig | Sigma-Delta ADC/DAC | HDL | https://github.com/adamgreig/tt02-adc-dac |
| 100 | JinGen Lim | BCD to Hex 7-Segment Decoder | HDL | https://github.com/jglim/tt02-bcd-hex7seg-hdl |
+| 101 | Chris Burton | SRLD | [Wokwi](https://wokwi.com/projects/349790606404354643) | https://github.com/burtyb/tt02-srld |
+| 102 | Adam Zeloof | Counter | [Wokwi](https://wokwi.com/projects/341279123277087315) | https://github.com/azzeloof/tt02-counter |
+| 103 | shan | 2bitALU | HDL | https://github.com/shan1293/tt02-2bitCPU |
+| 104 | Jos van 't Hof | A (7, 1/2) Convolutional Encoder | [Wokwi](https://wokwi.com/projects/349729432862196307) | https://github.com/Josvth/tt02-convolutional-encoder |
diff --git a/VERIFICATION.md b/VERIFICATION.md
index 651fc3a..cc7dd5c 100644
--- a/VERIFICATION.md
+++ b/VERIFICATION.md
@@ -10,7 +10,7 @@
You will need the GitHub tokens setup as described in [INFO](INFO.md#instructions-to-build-gds).
-The default of 498 projects takes a very long time to simulate, so I advise overriding the configuration:
+The default of 250 projects takes a very long time to simulate, so I advise overriding the configuration:
# fetch the test projects
./configure.py --test --clone-all
@@ -35,7 +35,7 @@
The Gate Level simulation requires scan_controller and user_project_wrapper to be re-hardened to get the correct gate level netlists:
-* Edit openlane/scan_controller/config.tcl and change NUM_DESIGNS=498 to NUM_DESIGNS=20.
+* Edit openlane/scan_controller/config.tcl and change NUM_DESIGNS=250 to NUM_DESIGNS=20.
* Then from the top level directory:
make scan_controller
