88373511294cb21efb513c918f6fa7e0189a6f1a - third_party/shuttle/sky130/mpw-008/slot-009

commit	88373511294cb21efb513c918f6fa7e0189a6f1a	[log] [tgz]
author	Soumil Jain <soumil@capella.ucsd.edu>	Tue Sep 20 11:49:18 2022 -0700
committer	Soumil Jain <soumil@capella.ucsd.edu>	Tue Sep 20 11:49:18 2022 -0700
tree	e36a24b7d4f5ed515aed48f038b1f910c5452e1d
parent	2cdf3861d883c000d682da80d89aeabb3f79ada0 [diff]

added schematics

xschem/.user_analog_project_wrapper.sch.swp[Added - diff]
xschem/.user_analog_project_wrapper.spice.swp[Added - diff]
xschem/.user_analog_project_wrapper.sym.swp[Added - diff]
xschem/1T1R.sch[Added - diff]
xschem/1T1R.sym[Added - diff]
xschem/1T1R_16x16.sch[Added - diff]
xschem/1T1R_16x16.sym[Added - diff]
xschem/1T1R_2x2.sch[Added - diff]
xschem/1T1R_2x2.sym[Added - diff]
xschem/WL_driver.sch[Added - diff]
xschem/WL_driver.sym[Added - diff]
xschem/WL_drivers_16x1.sch[Added - diff]
xschem/WL_drivers_16x1.sym[Added - diff]
xschem/analog_wrapper_tb.sch[Deleted - diff]
xschem/analog_wrapper_tb.spice[Deleted - diff]
xschem/and.sch[Added - diff]
xschem/and.sym[Added - diff]
xschem/and2_4.sym[Added - diff]
xschem/and4_4.sym[Added - diff]
xschem/and_level_up_shifter_x4.sch[Added - diff]
xschem/and_level_up_shifter_x4.sym[Added - diff]
xschem/and_pair.sch[Added - diff]
xschem/and_pair.sym[Added - diff]
xschem/buf_4.sym[Added - diff]
xschem/col_driver_big.sch[Added - diff]
xschem/col_driver_big.sym[Added - diff]
xschem/col_driver_x50.sch[Added - diff]
xschem/col_driver_x50.sym[Added - diff]
xschem/col_drivers_1x16.sch[Added - diff]
xschem/col_drivers_1x16.sym[Added - diff]
xschem/comp_out_sel.sch[Added - diff]
xschem/comp_out_sel.sym[Added - diff]
xschem/comparator.sch[Added - diff]
xschem/comparator.sym[Added - diff]
xschem/core.sch[Added - diff]
xschem/core.sym[Added - diff]
xschem/current_test.spice[Deleted - diff]
xschem/decoder2to4_x6.sch[Added - diff]
xschem/decoder2to4_x6.sym[Added - diff]
xschem/decoder_3to8_top.sch[Added - diff]
xschem/decoder_3to8_top.sym[Added - diff]
xschem/dfxtp_1.sym[Added - diff]
xschem/example_por.sch[Deleted - diff]
xschem/example_por.sym[Deleted - diff]
xschem/example_por_tb.sch[Deleted - diff]
xschem/example_por_tb.spice[Deleted - diff]
xschem/example_por_tb.spice.orig[Deleted - diff]
xschem/inv_16.sym[Added - diff]
xschem/inv_2.sym[Added - diff]
xschem/inv_8.sym[Added - diff]
xschem/inv_x6.sch[Added - diff]
xschem/inv_x6.sym[Added - diff]
xschem/level_up_shifter_2x.sch[Added - diff]
xschem/level_up_shifter_2x.sym[Added - diff]
xschem/level_up_shifter_x4.sch[Added - diff]
xschem/level_up_shifter_x4.sym[Added - diff]
xschem/mimcap_stacked_57x50.sch[Added - diff]
xschem/mimcap_stacked_57x50.sym[Added - diff]
xschem/nand2_x6.sch[Added - diff]
xschem/nand2_x6.sym[Added - diff]
xschem/reram.sym[Added - diff]
xschem/row_driver_x30.sch[Added - diff]
xschem/row_driver_x30.sym[Added - diff]
xschem/row_drivers_16x1.sch[Added - diff]
xschem/row_drivers_16x1.sym[Added - diff]
xschem/test.data[Deleted - diff]
xschem/threshold_test_tb.spice[Deleted - diff]
xschem/user_analog_project_wrapper.sch[diff]
xschem/user_analog_project_wrapper.spice[diff]
xschem/user_analog_project_wrapper.sym[diff]

70 files changed

tree: e36a24b7d4f5ed515aed48f038b1f910c5452e1d

README.md

ReRAM 16x16 array characterisation, including forming, incremental set and reset, and parallel analog read for vector-matrix multiplication. All characterisation is fully digitally controlled over the logic analyser.