DRC fixing.

doitcode/sram.py

diff --git a/doitcode/sram.py b/doitcode/sram.py
index 24bac9b..e89f7ab 100644
--- a/doitcode/sram.py
+++ b/doitcode/sram.py
@@ -196,7 +196,6 @@
         dpsram_bb = dpsram_lay.boundary
         assert dpsram_bb is not None
 
-
         # Make three rows of to place standard cells in
         #
         dbound = 4.0

gds/user_analog_project_wrapper.gds.gz

diff --git a/gds/user_analog_project_wrapper.gds.gz b/gds/user_analog_project_wrapper.gds.gz
index e410f8a..352b5df 100644
--- a/gds/user_analog_project_wrapper.gds.gz
+++ b/gds/user_analog_project_wrapper.gds.gz
Binary files differ