Fixing spurious via placement
This hopefully fixes the XOR precheck error.
diff --git a/doitcode/sram.py b/doitcode/sram.py
index bbb861c..9b33ebd 100644
--- a/doitcode/sram.py
+++ b/doitcode/sram.py
@@ -203,9 +203,9 @@
left=left, bottom=(top + 10.0), right=toppin_bb.right, top=(top+20.0),
)
layouter.add_wire(net=net, wire=m3, shape=shape)
- shape = _geo.Rect.from_rect(rect=toppin_bb, top=_frm.boundary.top, bottom=(top + 10.0))
+ shape = _geo.Rect.from_rect(rect=toppin_bb, bottom=(top + 10.0))
layouter.add_wire(net=net, wire=m3, shape=shape)
- # layouter.add_wire(net=net, wire=m3, pin=m3pin, shape=toppin_bb)
+ layouter.add_wire(net=net, wire=m3, pin=m3pin, shape=toppin_bb)
# vdd
spec = io_sig2spec["vdd"]
@@ -237,9 +237,9 @@
left=toppin_bb.left, bottom=(top + 10.0), right=right, top=(top+20.0),
)
layouter.add_wire(net=net, wire=m3, shape=shape)
- shape = _geo.Rect.from_rect(rect=toppin_bb, top=_frm.boundary.top, bottom=(top + 10.0))
+ shape = _geo.Rect.from_rect(rect=toppin_bb, bottom=(top + 10.0))
layouter.add_wire(net=net, wire=m3, shape=shape)
- # layouter.add_wire(net=net, wire=m3, pin=m3pin, shape=toppin_bb)
+ layouter.add_wire(net=net, wire=m3, pin=m3pin, shape=toppin_bb)
# a
col = 0
@@ -281,11 +281,9 @@
shape = _geo.Rect.from_rect(rect=via_m2bb, bottom=via2_m2bb.bottom)
layouter.add_wire(net=net, wire=m2, shape=shape)
- shape = _geo.Rect.from_rect(
- rect=toppin_bb, left=_frm.boundary.left, right=via2_m3bb.right,
- )
+ shape = _geo.Rect.from_rect(rect=toppin_bb, right=via2_m3bb.right)
layouter.add_wire(net=net, wire=m3, shape=shape)
- # layouter.add_wire(net=net, wire=m3, pin=m3pin, shape=toppin_bb)
+ layouter.add_wire(net=net, wire=m3, pin=m3pin, shape=toppin_bb)
# The rest of the pin on m2
for sram_signame in (
@@ -299,7 +297,7 @@
sram_m2pinbb = sram_lay.bounds(mask=m2pin.mask, net=net, depth=1)
toppin_bb = _frm.toppins[spec.toppin_name]
- _via2_lay = layouter.add_wire(
+ _via2_lay = layouter.wire_layout(
net=net, wire=via2, rows=6, columns=6,
)
_via2_m2bb = _via2_lay.bounds(mask=m2.mask)
@@ -315,15 +313,11 @@
shape = _geo.Rect.from_rect(rect=sram_m2pinbb, bottom=via2_m2bb.bottom)
layouter.add_wire(net=net, wire=m2, shape=shape)
if toppin_bb.center.x > sram_m2pinbb.center.x:
- shape = _geo.Rect.from_rect(
- rect=toppin_bb, left=via2_m3bb.left, right=_frm.boundary.right,
- )
+ shape = _geo.Rect.from_rect(rect=toppin_bb, left=via2_m3bb.left)
else:
- shape = _geo.Rect.from_rect(
- rect=toppin_bb, left=_frm.boundary.left, right=via2_m3bb.right,
- )
+ shape = _geo.Rect.from_rect(rect=toppin_bb, right=via2_m3bb.right)
layouter.add_wire(net=net, wire=m3, shape=shape)
- # layouter.add_wire(net=net, wire=m3, pin=m3pin, shape=toppin_bb)
+ layouter.add_wire(net=net, wire=m3, pin=m3pin, shape=toppin_bb)
# boundary
layout.boundary = _frm.boundary
diff --git a/gds/user_analog_project_wrapper.gds.gz b/gds/user_analog_project_wrapper.gds.gz
index 93d8ebe..0a228d0 100644
--- a/gds/user_analog_project_wrapper.gds.gz
+++ b/gds/user_analog_project_wrapper.gds.gz
Binary files differ
