signoff/build/gpio_defaults.out

Step 1:  Create new cells for new GPIO default vectors.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_1803.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_1803.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_1803.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_1803.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_0801.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_0801.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/mpw-8/u5504_mehdi/nanofabrication_project_using_openfasoc_mpw8/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Step 2:  Modify top-level layouts to use the specified defaults.
Done.