commit | 36fe51bd3b4effada1b7b9d0d1a4e9f690e2e4fe | [log] [tgz] |
---|---|---|
author | roman3017 <rbacik@hotmail.com> | Sun Dec 25 21:07:57 2022 -0800 |
committer | roman3017 <rbacik@hotmail.com> | Sun Dec 25 21:09:48 2022 -0800 |
tree | da382c2031e59edb703557b540c4a9b20b771853 | |
parent | a0e54bab590780989a1a1731440658522d96beff [diff] |
add tag repo to ci action on dispatch
Full speed USB2 to 115200 bauds UART module for TTL logic at 3V3. It requires 48MHz clock from user_clock2.
See verilog/rtl/fpga folder for FPGA tests.
mkdir -p dependencies export OPENLANE_ROOT=$(pwd)/dependencies/openlane_src export PDK_ROOT=$(pwd)/dependencies/pdks export PDK=sky130A make setup make user_proj_example klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_proj_example.gds make user_project_wrapper klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_project_wrapper.gds make verify make SIM=GL verify #make extract-parasitics make create-spef-mapping #make caravel-sta rm -rf ~/mpw_precheck/ make precheck make run-precheck #make compress