add uart to fpga_top test
diff --git a/verilog/rtl/fpga/Makefile b/verilog/rtl/fpga/Makefile
index 555204e..03bfe8a 100644
--- a/verilog/rtl/fpga/Makefile
+++ b/verilog/rtl/fpga/Makefile
@@ -16,15 +16,18 @@
../usb_cdc/usb_cdc/usb_cdc.v \
../usb_cdc/examples/common/hdl/prescaler.v \
../usb_cdc/examples/common/hdl/fifo_if.v \
+../verilog-uart/rtl/uart_rx.v \
+../verilog-uart/rtl/uart_tx.v \
+../verilog-uart/rtl/uart.v \
../usb_cdc/examples/TinyFPGA-BX/hdl/soc/app.v
PIN_DEF = fpga_pins.pcf
# TinyFPGA-BX
FPGA_SIZE = 8k
-FPGA_TYPE = hx
+FPGA_TYPE = lp
FPGA_PACK = cm81
-all: sint
+all: sint time
sim: $(NAME)_tb.vcd
gtkwave $< $(<:.vcd=.gtkw) &
@@ -52,7 +55,7 @@
./$(@:.vcd=.out)
.v.json:
- yosys -p "synth_ice40 -json $@" $^
+ yosys -p "$(foreach file,$^,read_verilog $(file);)" -p "synth_ice40 -json $@" $^
.json.asc:
nextpnr-ice40 --$(FPGA_TYPE)$(FPGA_SIZE) --package $(FPGA_PACK) --pcf-allow-unconstrained --pcf $(PIN_DEF) --json $< --asc $@
diff --git a/verilog/rtl/fpga/README.md b/verilog/rtl/fpga/README.md
index a3bb582..3fc86c5 100644
--- a/verilog/rtl/fpga/README.md
+++ b/verilog/rtl/fpga/README.md
@@ -4,11 +4,28 @@
## USB
+See echo of slightly modified input.
+
```sh
cd ../usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/
tinyprog -l
-make all PROJ=soc
-make prog PROJ=soc
+make PROJ=soc clean all
+make PROJ=soc prog
+tinyprog -b
+
minicom -D /dev/ttyACM0
```
+## USB2TTL
+
+Attach another USB2TTL to pins 4,5 and see characters being passed between.
+
+```sh
+tinyprog -l
+make clean all
+make prog
+tinyprog -b
+
+minicom -D /dev/ttyACM0
+minicom -D /dev/ttyUSB0
+```
diff --git a/verilog/rtl/fpga/fpga_pins.pcf b/verilog/rtl/fpga/fpga_pins.pcf
index 3674bae..afa9d4d 100644
--- a/verilog/rtl/fpga/fpga_pins.pcf
+++ b/verilog/rtl/fpga/fpga_pins.pcf
@@ -5,5 +5,7 @@
set_io usb_pu A3
set_io usb_n A4
set_io usb_p B4
+set_io uart_rx C2
+set_io uart_tx D2
set_io led B3
set_io clk B2
diff --git a/verilog/rtl/fpga/fpga_top.v b/verilog/rtl/fpga/fpga_top.v
index 67da9e0..d704edd 100644
--- a/verilog/rtl/fpga/fpga_top.v
+++ b/verilog/rtl/fpga/fpga_top.v
@@ -1,8 +1,9 @@
-module soc
- (
+module fpga_top (
input clk, // 16MHz Clock
output led, // User LED ON=1, OFF=0
+ input uart_rx, // uart in
+ output uart_tx, // uart out
inout usb_p, // USB+
inout usb_n, // USB-
output usb_pu // USB 1.5kOhm Pullup EN
@@ -32,37 +33,40 @@
// if FEEDBACK_PATH = SIMPLE:
// clk_freq = (ref_freq * (DIVF + 1)) / (2**DIVQ * (DIVR + 1));
- SB_PLL40_CORE #(.DIVR(4'd0),
- .DIVF(DIVF),
- .DIVQ(3'd4),
- .FILTER_RANGE(3'b001),
- .FEEDBACK_PATH("SIMPLE"),
- .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
- .FDA_FEEDBACK(4'b0000),
- .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
- .FDA_RELATIVE(4'b0000),
- .SHIFTREG_DIV_MODE(2'b00),
- .PLLOUT_SELECT("GENCLK"),
- .ENABLE_ICEGATE(1'b0))
- u_pll (.REFERENCECLK(clk), // 16MHz
- .PLLOUTCORE(),
- .PLLOUTGLOBAL(clk_pll), // 48MHz
- .EXTFEEDBACK(1'b0),
- .DYNAMICDELAY(8'd0),
- .LOCK(lock),
- .BYPASS(1'b0),
- .RESETB(1'b1),
- .SDI(1'b0),
- .SDO(),
- .SCLK(1'b0),
- .LATCHINPUTVALUE(1'b1));
+ SB_PLL40_CORE #(
+ .DIVR(4'd0),
+ .DIVF(DIVF),
+ .DIVQ(3'd4),
+ .FILTER_RANGE(3'b001),
+ .FEEDBACK_PATH("SIMPLE"),
+ .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
+ .FDA_FEEDBACK(4'b0000),
+ .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
+ .FDA_RELATIVE(4'b0000),
+ .SHIFTREG_DIV_MODE(2'b00),
+ .PLLOUT_SELECT("GENCLK"),
+ .ENABLE_ICEGATE(1'b0))
+ u_pll (
+ .REFERENCECLK(clk), // 16MHz
+ .PLLOUTCORE(),
+ .PLLOUTGLOBAL(clk_pll), // 48MHz
+ .EXTFEEDBACK(1'b0),
+ .DYNAMICDELAY(8'd0),
+ .LOCK(lock),
+ .BYPASS(1'b0),
+ .RESETB(1'b1),
+ .SDI(1'b0),
+ .SDO(),
+ .SCLK(1'b0),
+ .LATCHINPUTVALUE(1'b1));
- prescaler u_prescaler (.clk_i(clk),
- .rstn_i(lock),
- .clk_div16_o(clk_1mhz),
- .clk_div8_o(clk_2mhz),
- .clk_div4_o(clk_4mhz),
- .clk_div2_o(clk_8mhz));
+ prescaler u_prescaler (
+ .clk_i(clk),
+ .rstn_i(lock),
+ .clk_div16_o(clk_1mhz),
+ .clk_div8_o(clk_2mhz),
+ .clk_div4_o(clk_4mhz),
+ .clk_div2_o(clk_8mhz));
reg [1:0] rstn_sync;
@@ -97,80 +101,108 @@
end
assign led = ~dp_pu | ~up_cnt[20];
+/*
+ app u_app (
+ .clk_i(clk_2mhz),
+ .rstn_i(rstn),
+ .sleep_o(sleep),
+ .out_data_i(out_data),
+ .out_valid_i(out_valid),
+ .in_ready_i(in_ready),
+ .out_ready_o(out_ready),
+ .in_data_o(in_data),
+ .in_valid_o(in_valid));
+//*/
+//*
+ uart u_uart (
+ .clk(clk_2mhz),
+ .rst(~rstn),
+ .s_axis_tdata(out_data),
+ .s_axis_tvalid(out_valid),
+ .s_axis_tready(out_ready),
+ .m_axis_tdata(in_data),
+ .m_axis_tvalid(in_valid),
+ .m_axis_tready(in_ready),
+ .rxd(uart_rx),
+ .txd(uart_tx),
+ //.tx_busy(),
+ //.rx_busy(),
+ //.rx_overrun_error(),
+ //.rx_frame_error(),
+ .prescale(16'h0002) //2000000÷(115200*8)=2.17
+ );
+//*/
+ usb_cdc #(
+ .VENDORID(16'h1D50),
+ .PRODUCTID(16'h6130),
+ .IN_BULK_MAXPACKETSIZE('d8),
+ .OUT_BULK_MAXPACKETSIZE('d8),
+ .BIT_SAMPLES(BIT_SAMPLES),
+ .USE_APP_CLK(1),
+ .APP_CLK_RATIO(BIT_SAMPLES*12/2)) // BIT_SAMPLES * 12MHz / 2MHz
+ u_usb_cdc (
+ .frame_o(),
+ .configured_o(),
+ .app_clk_i(clk_2mhz),
+ .clk_i(clk_pll),
+ .rstn_i(rstn),
+ .out_ready_i(out_ready),
+ .in_data_i(in_data),
+ .in_valid_i(in_valid),
+ .dp_rx_i(dp_rx),
+ .dn_rx_i(dn_rx),
+ .out_data_o(out_data),
+ .out_valid_o(out_valid),
+ .in_ready_o(in_ready),
+ .dp_pu_o(dp_pu),
+ .tx_en_o(tx_en),
+ .dp_tx_o(dp_tx),
+ .dn_tx_o(dn_tx));
- app u_app (.clk_i(clk_2mhz),
- .rstn_i(rstn),
- .sleep_o(sleep),
- .out_data_i(out_data),
- .out_valid_i(out_valid),
- .in_ready_i(in_ready),
- .out_ready_o(out_ready),
- .in_data_o(in_data),
- .in_valid_o(in_valid));
+ SB_IO #(
+ .PIN_TYPE(6'b101001),
+ .PULLUP(1'b0))
+ u_usb_p (
+ .PACKAGE_PIN(usb_p),
+ .OUTPUT_ENABLE(tx_en),
+ .D_OUT_0(dp_tx),
+ .D_IN_0(dp_rx),
+ .D_OUT_1(1'b0),
+ .D_IN_1(),
+ .CLOCK_ENABLE(1'b0),
+ .LATCH_INPUT_VALUE(1'b0),
+ .INPUT_CLK(1'b0),
+ .OUTPUT_CLK(1'b0));
- usb_cdc #(.VENDORID(16'h1D50),
- .PRODUCTID(16'h6130),
- .IN_BULK_MAXPACKETSIZE('d8),
- .OUT_BULK_MAXPACKETSIZE('d8),
- .BIT_SAMPLES(BIT_SAMPLES),
- .USE_APP_CLK(1),
- .APP_CLK_RATIO(BIT_SAMPLES*12/2)) // BIT_SAMPLES * 12MHz / 2MHz
- u_usb_cdc (.frame_o(),
- .configured_o(),
- .app_clk_i(clk_2mhz),
- .clk_i(clk_pll),
- .rstn_i(rstn),
- .out_ready_i(out_ready),
- .in_data_i(in_data),
- .in_valid_i(in_valid),
- .dp_rx_i(dp_rx),
- .dn_rx_i(dn_rx),
- .out_data_o(out_data),
- .out_valid_o(out_valid),
- .in_ready_o(in_ready),
- .dp_pu_o(dp_pu),
- .tx_en_o(tx_en),
- .dp_tx_o(dp_tx),
- .dn_tx_o(dn_tx));
-
- SB_IO #(.PIN_TYPE(6'b101001),
- .PULLUP(1'b0))
- u_usb_p (.PACKAGE_PIN(usb_p),
- .OUTPUT_ENABLE(tx_en),
- .D_OUT_0(dp_tx),
- .D_IN_0(dp_rx),
- .D_OUT_1(1'b0),
- .D_IN_1(),
- .CLOCK_ENABLE(1'b0),
- .LATCH_INPUT_VALUE(1'b0),
- .INPUT_CLK(1'b0),
- .OUTPUT_CLK(1'b0));
-
- SB_IO #(.PIN_TYPE(6'b101001),
- .PULLUP(1'b0))
- u_usb_n (.PACKAGE_PIN(usb_n),
- .OUTPUT_ENABLE(tx_en),
- .D_OUT_0(dn_tx),
- .D_IN_0(dn_rx),
- .D_OUT_1(1'b0),
- .D_IN_1(),
- .CLOCK_ENABLE(1'b0),
- .LATCH_INPUT_VALUE(1'b0),
- .INPUT_CLK(1'b0),
- .OUTPUT_CLK(1'b0));
+ SB_IO #(
+ .PIN_TYPE(6'b101001),
+ .PULLUP(1'b0))
+ u_usb_n (
+ .PACKAGE_PIN(usb_n),
+ .OUTPUT_ENABLE(tx_en),
+ .D_OUT_0(dn_tx),
+ .D_IN_0(dn_rx),
+ .D_OUT_1(1'b0),
+ .D_IN_1(),
+ .CLOCK_ENABLE(1'b0),
+ .LATCH_INPUT_VALUE(1'b0),
+ .INPUT_CLK(1'b0),
+ .OUTPUT_CLK(1'b0));
// drive usb_pu to 3.3V or to high impedance
- SB_IO #(.PIN_TYPE(6'b101001),
- .PULLUP(1'b0))
- u_usb_pu (.PACKAGE_PIN(usb_pu),
- .OUTPUT_ENABLE(dp_pu),
- .D_OUT_0(1'b1),
- .D_IN_0(),
- .D_OUT_1(1'b0),
- .D_IN_1(),
- .CLOCK_ENABLE(1'b0),
- .LATCH_INPUT_VALUE(1'b0),
- .INPUT_CLK(1'b0),
- .OUTPUT_CLK(1'b0));
+ SB_IO #(
+ .PIN_TYPE(6'b101001),
+ .PULLUP(1'b0))
+ u_usb_pu (
+ .PACKAGE_PIN(usb_pu),
+ .OUTPUT_ENABLE(dp_pu),
+ .D_OUT_0(1'b1),
+ .D_IN_0(),
+ .D_OUT_1(1'b0),
+ .D_IN_1(),
+ .CLOCK_ENABLE(1'b0),
+ .LATCH_INPUT_VALUE(1'b0),
+ .INPUT_CLK(1'b0),
+ .OUTPUT_CLK(1'b0));
endmodule
