commit | dd99eecb6d59cd607841ce9f5c1ff9daaece02b6 | [log] [tgz] |
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author | roman3017 <rbacik@hotmail.com> | Thu Dec 29 19:03:41 2022 -0800 |
committer | roman3017 <rbacik@hotmail.com> | Thu Dec 29 19:03:41 2022 -0800 |
tree | e16e111751d30a532fbf48754cd45a4442816cb4 | |
parent | 080e49aba0dd2603ca7957045655ec9e34f38517 [diff] |
ci retry when make gds fails
Full speed USB2 to 115200 bauds UART module for TTL logic at 3V3. It requires 48MHz clock from user_clock2.
See verilog/rtl/fpga folder for FPGA tests.
mkdir -p dependencies export OPENLANE_ROOT=$(pwd)/dependencies/openlane_src export PDK_ROOT=$(pwd)/dependencies/pdks export PDK=sky130A make setup make user_proj_example klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_proj_example.gds make user_project_wrapper klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_project_wrapper.gds make verify make SIM=GL verify #make extract-parasitics make create-spef-mapping #make caravel-sta rm -rf ~/mpw_precheck/ make precheck make run-precheck #make compress