commit | d1966acd236bd76621fd208754cd2ef3c45ba33a | [log] [tgz] |
---|---|---|
author | roman3017 <rbacik@hotmail.com> | Sat Dec 24 21:24:30 2022 -0800 |
committer | roman3017 <rbacik@hotmail.com> | Sat Dec 24 21:24:30 2022 -0800 |
tree | 015e5a94c8dfa7b2bc2922d17f47504af0afde7a | |
parent | fa4325bdf335b0b87e759ff8579d26a7b643f00f [diff] |
update gds
Full speed USB2 to 115200 bauds UART module for TTL logic at 3V3. It requires 48MHz clock from user_clock2.
See verilog/rtl/fpga folder for FPGA tests.
mkdir -p dependencies export OPENLANE_ROOT=$(pwd)/dependencies/openlane_src export PDK_ROOT=$(pwd)/dependencies/pdks export PDK=sky130A make setup make user_proj_example klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_proj_example.gds make user_project_wrapper klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_project_wrapper.gds make verify make SIM=GL verify #make extract-parasitics make create-spef-mapping #make caravel-sta rm -rf ~/mpw_precheck/ make precheck make run-precheck #make compress