| commit | a0e54bab590780989a1a1731440658522d96beff | [log] [tgz] |
|---|---|---|
| author | roman3017 <rbacik@hotmail.com> | Mon Dec 26 04:23:02 2022 +0000 |
| committer | roman3017 <rbacik@hotmail.com> | Mon Dec 26 04:23:02 2022 +0000 |
| tree | 0cee9fbbc2a44c60e9220f38967d11a9e1b335b3 | |
| parent | 6655e86e94b3c27074959894a177f981282b7cb1 [diff] |
action: update build
Full speed USB2 to 115200 bauds UART module for TTL logic at 3V3. It requires 48MHz clock from user_clock2.
See verilog/rtl/fpga folder for FPGA tests.
mkdir -p dependencies export OPENLANE_ROOT=$(pwd)/dependencies/openlane_src export PDK_ROOT=$(pwd)/dependencies/pdks export PDK=sky130A make setup make user_proj_example klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_proj_example.gds make user_project_wrapper klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_project_wrapper.gds make verify make SIM=GL verify #make extract-parasitics make create-spef-mapping #make caravel-sta rm -rf ~/mpw_precheck/ make precheck make run-precheck #make compress