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foss-eda-tools/third_party/shuttle/sky130/mpw-008/slot-006/HEAD/./verilog/rtl
tree: 072b36319a30778e95ff73c471b3f636ac822e52 [path history] [tgz]
  1. fpga/
  2. usb_cdc
  3. verilog-uart
  4. 0001-usb_cdc-fix-make-targets.patch
  5. defines.v
  6. usb2uart.v
  7. user_defines.v
  8. user_proj_example.v
  9. user_project_wrapper.v
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