move user pins from 33:37 to 16:20
diff --git a/verilog/dv/usb2uart/usb2uart_tb.v b/verilog/dv/usb2uart/usb2uart_tb.v
index 44c969f..22d9fab 100644
--- a/verilog/dv/usb2uart/usb2uart_tb.v
+++ b/verilog/dv/usb2uart/usb2uart_tb.v
@@ -41,15 +41,16 @@
wire [37:0] mprj_io;
reg user_uart_rx;
+
/*
wire mgmt_uart_tx;
assign mgmt_uart_tx = mprj_io[6];
- //assign mprj_io[34] = mprj_io[6];
*/
+
+ pullup(mprj_io[3]);
assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
- // Signals Assignment
- assign mprj_io[34] = user_uart_rx;
+ assign mprj_io[19] = user_uart_rx;
always #(c_CLOCK_PERIOD_NS/2) clock <= (clock === 1'b0);
@@ -155,9 +156,9 @@
$dumpfile("usb2uart.vcd");
$dumpvars(0, usb2uart_tb);
`ifdef GL
- $monitor( "io_in[34]: 0x%x", uut.mprj.mprj.io_in[34] );
+ $monitor( "uart_rx_inst.rxd_reg: 0x%x", uut.mprj.mprj.\usb2uart.u_uart.uart_rx_inst.rxd_reg );
`else
- $monitor( "usb2uart.in_data: 0x%x", uut.mprj.mprj.usb2uart.in_data );
+ $monitor( "uart_rx_inst.rxd_reg: 0x%x", uut.mprj.mprj.usb2uart.u_uart.uart_rx_inst.rxd_reg );
`endif
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (50) begin
@@ -200,8 +201,8 @@
endtask
initial begin
- // Exercise Rx
- j=0;
+ // Verify Rx data from uart to usb is correct
+ j=0; k=0;
for (i=0; i<8; i=i+1) begin
UART_WRITE_RX_AND_RCV(i);
`ifdef GL
@@ -215,7 +216,7 @@
uut.mprj.mprj.\usb2uart.u_uart.uart_rx_inst.m_axis_tdata_reg[1] ,
uut.mprj.mprj.\usb2uart.u_uart.uart_rx_inst.m_axis_tdata_reg[0] };
`else
- k = uut.mprj.mprj.usb2uart.in_data;
+ k[7:0] = uut.mprj.mprj.usb2uart.u_uart.uart_rx_inst.m_axis_tdata_reg ;
`endif
if (k == i)
@@ -232,11 +233,11 @@
// Reset Operation
initial begin
- CSB <= 1'b1;
RSTB <= 1'b0;
+ CSB <= 1'b1;
#2000;
RSTB <= 1'b1; // Release reset
- #1_300_000;
+ #300000;
CSB <= 1'b0; // Stop driving CSB
end
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
deleted file mode 100644
index e2dc64e..0000000
--- a/verilog/rtl/uprj_netlists.v
+++ /dev/null
@@ -1,42 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-// Include caravel global defines for the number of the user project IO pads
-`include "defines.v"
-`define USE_POWER_PINS
-
-`ifdef GL
- // Assume default net type to be wire because GL netlists don't have the wire definitions
- `default_nettype wire
- `include "gl/user_project_wrapper.v"
- `include "gl/user_proj_example.v"
-`else
- `include "user_project_wrapper.v"
- `include "user_proj_example.v"
- `include "usb2uart.v"
- `include "usb_cdc/usb_cdc/phy_tx.v",
- `include "usb_cdc/usb_cdc/phy_rx.v",
- `include "usb_cdc/usb_cdc/sie.v",
- `include "usb_cdc/usb_cdc/ctrl_endp.v",
- `include "usb_cdc/usb_cdc/in_fifo.v",
- `include "usb_cdc/usb_cdc/out_fifo.v",
- `include "usb_cdc/usb_cdc/bulk_endp.v",
- `include "usb_cdc/usb_cdc/usb_cdc.v",
- `include "usb_cdc/examples/common/hdl/prescaler.v",
- `include "usb_cdc/examples/common/hdl/fifo_if.v",
- `include "verilog-uart/rtl/uart_rx.v",
- `include "verilog-uart/rtl/uart_tx.v",
- `include "verilog-uart/rtl/uart.v"
-`endif
\ No newline at end of file
diff --git a/verilog/rtl/usb2uart.v b/verilog/rtl/usb2uart.v
index c9bb686..7ee6554 100644
--- a/verilog/rtl/usb2uart.v
+++ b/verilog/rtl/usb2uart.v
@@ -20,6 +20,10 @@
wire [7:0] out_data;
wire out_valid;
+ //115200 bauds from 48MHz clock
+ //.prescale(((48*1000000)+(115200*8)-1)/(115200*8))
+ reg [15:0] prescale = 16'h0035;
+
assign clk = clk48;
uart # (
@@ -40,8 +44,7 @@
.m_axis_tready(in_ready),
.rxd(uart_rx),
- //115200 bauds from 48MHz clock
- .prescale(((48*1000000)+(115200*8)-1)/(115200*8))
+ .prescale(prescale)
);
wire dp_pu;
diff --git a/verilog/rtl/user_defines.v b/verilog/rtl/user_defines.v
index fe9bcbc..c93c274 100644
--- a/verilog/rtl/user_defines.v
+++ b/verilog/rtl/user_defines.v
@@ -61,20 +61,19 @@
`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
`define USER_CONFIG_GPIO_12_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
`define USER_CONFIG_GPIO_13_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
-
-// Configurations of GPIO 14 to 24 are used on caravel but not caravan.
`define USER_CONFIG_GPIO_14_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
`define USER_CONFIG_GPIO_15_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
-`define USER_CONFIG_GPIO_16_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
-`define USER_CONFIG_GPIO_17_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
-`define USER_CONFIG_GPIO_18_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
-`define USER_CONFIG_GPIO_19_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
-`define USER_CONFIG_GPIO_20_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+/* user pins */
+`define USER_CONFIG_GPIO_16_INIT `GPIO_MODE_USER_STD_OUTPUT
+`define USER_CONFIG_GPIO_17_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_18_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_19_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_20_INIT `GPIO_MODE_USER_STD_OUTPUT
+/*************/
`define USER_CONFIG_GPIO_21_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
`define USER_CONFIG_GPIO_22_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
`define USER_CONFIG_GPIO_23_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
`define USER_CONFIG_GPIO_24_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
-
`define USER_CONFIG_GPIO_25_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
`define USER_CONFIG_GPIO_26_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
`define USER_CONFIG_GPIO_27_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
@@ -83,12 +82,10 @@
`define USER_CONFIG_GPIO_30_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
`define USER_CONFIG_GPIO_31_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
`define USER_CONFIG_GPIO_32_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
-
-// User GPIO 33 to 37
-`define USER_CONFIG_GPIO_33_INIT `GPIO_MODE_USER_STD_OUTPUT
-`define USER_CONFIG_GPIO_34_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
-`define USER_CONFIG_GPIO_35_INIT `GPIO_MODE_USER_STD_OUTPUT
-`define USER_CONFIG_GPIO_36_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
-`define USER_CONFIG_GPIO_37_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_33_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_34_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_35_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_36_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_37_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
`endif // __USER_DEFINES_H
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 41524a4..6f6a14c 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -61,9 +61,9 @@
input [127:0] la_oenb,
// IOs
- input [`MPRJ_IO_PADS-1:0] io_in,
- output [`MPRJ_IO_PADS-1:0] io_out,
- output [`MPRJ_IO_PADS-1:0] io_oeb,
+ input [37:0] io_in,
+ output [37:0] io_out,
+ output [37:0] io_oeb,
// User clock
input user_clock2,
@@ -89,8 +89,8 @@
assign la_data_out = 128'h00000000000000000000000000000000;
// IO
- assign io_out[`MPRJ_IO_PADS-6:0] = {(`MPRJ_IO_PADS-5){1'b0}};
- assign io_oeb[`MPRJ_IO_PADS-6:0] = {(`MPRJ_IO_PADS-5){1'b1}};
+ assign io_oeb[15:0] = 16'hffff;
+ assign io_oeb[37:21] = 17'h1ffff;
// IRQ
assign irq = 3'b000;
@@ -98,27 +98,29 @@
assign clk = user_clock2;
assign rst = wb_rst_i;
- // io_out[33] output uart_tx
- assign io_oeb[`MPRJ_IO_PADS-5] = 1'b0;
- assign io_out[`MPRJ_IO_PADS-5] = uart_tx;
+ // io_out[16] output usb_pu
+ assign io_oeb[16] = 1'b0;
+ assign io_out[16] = usb_pu;
- // io_out[34] input uart_rx
- assign io_oeb[`MPRJ_IO_PADS-4] = 1'b1;
- assign uart_rx = io_in[`MPRJ_IO_PADS-4];
+ // io_out[17] inout usb_n
+ assign io_oeb[17] = ~usb_tx_en;
+ //assign io_out[17] = usb_tx_en ? usb_n;
+ assign io_out[17] = usb_n;
+ assign usb_n = io_in[17];
- // io_out[35] output usb_pu
- assign io_oeb[`MPRJ_IO_PADS-3] = 1'b0;
- assign io_out[`MPRJ_IO_PADS-3] = usb_pu;
+ // io_out[18] inout usb_p
+ assign io_oeb[18] = ~usb_tx_en;
+ //assign io_out[18] = usb_tx_en ? usb_p;
+ assign io_out[18] = usb_p;
+ assign usb_p = io_in[18];
- // io_out[36] inout usb_n
- assign io_oeb[`MPRJ_IO_PADS-2] = ~usb_tx_en;
- assign io_out[`MPRJ_IO_PADS-2] = /* usb_tx_en ? */ usb_n;
- assign usb_n = io_in[`MPRJ_IO_PADS-2];
+ // io_out[19] input uart_rx
+ assign io_oeb[19] = 1'b1;
+ assign uart_rx = io_in[19];
- // io_out[37] inout usb_p
- assign io_oeb[`MPRJ_IO_PADS-1] = ~usb_tx_en;
- assign io_out[`MPRJ_IO_PADS-1] = /* usb_tx_en ? */ usb_p;
- assign usb_p = io_in[`MPRJ_IO_PADS-1];
+ // io_out[20] output uart_tx
+ assign io_oeb[20] = 1'b0;
+ assign io_out[20] = uart_tx;
usb2uart usb2uart (
.clk48(clk),
