Google Git
Sign in
foss-eda-tools / third_party / shuttle / sky130 / mpw-008 / slot-006 / 6655e86e94b3c27074959894a177f981282b7cb1
commit6655e86e94b3c27074959894a177f981282b7cb1[log] [tgz]
authorroman3017 <rbacik@hotmail.com>Sun Dec 25 17:35:57 2022 -0800
committerroman3017 <rbacik@hotmail.com>Sun Dec 25 17:35:57 2022 -0800
treeab6f761bbe7443edb5f9dfecacbacea9e94405a4
parent7092e29fa9accbbdb1e01b3d538bdd83ac75ce22 [diff]
add update gds to ci
2 files changed
tree: ab6f761bbe7443edb5f9dfecacbacea9e94405a4
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spi/
  11. verilog/
  12. .gitignore
  13. .gitmodules
  14. LICENSE
  15. Makefile
  16. README.md
README.md

MPW shuttle

USB2UART

Full speed USB2 to 115200 bauds UART module for TTL logic at 3V3. It requires 48MHz clock from user_clock2.

See verilog/rtl/fpga folder for FPGA tests.

mkdir -p dependencies
export OPENLANE_ROOT=$(pwd)/dependencies/openlane_src
export PDK_ROOT=$(pwd)/dependencies/pdks
export PDK=sky130A
make setup

make user_proj_example
klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_proj_example.gds

make user_project_wrapper
klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_project_wrapper.gds

make verify
make SIM=GL verify
#make extract-parasitics
make create-spef-mapping
#make caravel-sta
rm -rf ~/mpw_precheck/
make precheck
make run-precheck
#make compress

References

  • MPW-8 Shuttle projects (project 1758)
  • USB IP taken from ulixxe
  • UART IP taken from alexforencich
  • Harness Harness specification
  • OpenLane OpenLane documentation
  • Board Test board
  • PLL PLL registers calculator
  • QSG Quick start guide
  • README A sample project documentation